Ring gate transistor and manufacturing method thereof

Abstract

The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to suppress parasitic channel electric leakage and improve the working performance of the gate-all-around transistor. The ring gate transistor comprises a semiconductor substrate, an active structure, a gate stack structure, an inner side wall and a dielectric isolation structure. The active structure is disposed on the semiconductor substrate. The active structure comprises a source region, a drain region and a channel region located between the source region and the drain region, and the two ends, in the length direction, of the channel region make contact with the source region and the drain region respectively. The gate stack structure surrounds the periphery of the channel region. The inner side walls are arranged between the gate stack structure and the source region and between the gate stack structure and the drain region. And the dielectric isolation structure is arranged below the active structure and is used for isolating the semiconductor substrate from the source region, the drain region and part of the gate stack structure. At least the part, located below the channel region, in the dielectric isolation structure is integrally continuous with the inner side wall located at the bottom layer. The manufacturing method of the gate-all-around transistor is used for manufacturing the gate-all-around transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gate-all-around transistor and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, the ring-gate transistor has emerged. Because the gate stack structure of the ring-gate transistor is not only formed on the top and sidewalls of the channel region, but also on the bottom of the channel region, compared with the planar transistor and the fin field effect transistor, the ring-gate transistor has a stronger gate control capability, which is conducive to suppressing the short channel effect.

[0003] However, the quality of the all-around gate transistor formed by the existing manufacturing method for suppressing parasitic channel leakage is poor, which is not conducive to improving the electrical performance of the all-around gate transistor. Summary of the invention

[0004] The object of the present invention is to provide a ring-gate transistor and a manufacturing method thereof, which are used to suppress parasitic channel leakage and help improve the working performance of the ring-gate transistor.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a ring-gate transistor, which includes: a semiconductor substrate, an active structure, a gate stack structure, an inner sidewall and a dielectric isolation structure. The active structure is arranged on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region, and the two ends of the channel region along the length direction are respectively in contact with the source region and the drain region. The gate stack structure surrounds the periphery of the channel region. The inner sidewall is arranged between the gate stack structure and the source region and the drain region respectively. The dielectric isolation structure is arranged below the active structure, and the dielectric isolation structure is used to isolate the semiconductor substrate from the source region, the drain region and part of the gate stack structure respectively. At least the portion of the dielectric isolation structure located below the channel region is continuous with the inner sidewall located at the bottom layer.

[0006] In the case of adopting the above technical solution, the ring-gate transistor provided by the present invention includes an inner sidewall located between the source region and the gate stack structure, and between the drain region and the gate stack structure, so as to limit the length of the gate stack structure, improve the yield of the ring-gate transistor, and reduce the parasitic capacitance between the source region and the gate stack structure, and between the drain region and the gate stack structure. Secondly, the ring-gate transistor provided by the present invention also includes a dielectric isolation structure. The dielectric isolation structure is arranged below the active structure. Specifically, the dielectric isolation structure is arranged between the semiconductor substrate and the source region, the drain region and part of the gate stack structure respectively. Because the dielectric isolation structure is a non-conductive structure, the dielectric isolation structure can separate the semiconductor substrate from the source region, the drain region and part of the gate stack structure respectively, and prevent the source region and the drain region from being turned on through the semiconductor material located below the gate stack structure when a suitable voltage is applied to the gate stack structure, that is, to prevent parasitic channel leakage, so that the ring-gate transistor has good electrical performance. In addition, the source region and the drain region can also be isolated from the semiconductor substrate by the dielectric isolation structure to prevent source and drain leakage and improve the radiation resistance of the ring-gate transistor.

[0007] In addition, at least the portion of the dielectric isolation structure located below the channel region is continuous with the inner sidewall located at the bottom layer, that is, the inner sidewall and at least part of the dielectric isolation structure can be manufactured simultaneously based on the same dielectric material, which is conducive to simplifying the manufacturing process of the ring-gate transistor and improving the manufacturing efficiency of the ring-gate transistor while ensuring that the ring-gate transistor has good electrical performance. In addition, as long as the first sacrificial layer preformed between the second sacrificial layer and the semiconductor substrate is removed, a first dielectric filling area for filling the dielectric isolation structure can be formed, without the need to use ion implantation and precisely control the implantation parameters to only dope the top silicon layer or the middle and lower parts of the fin structure as in the existing manufacturing method, which leads to greater manufacturing difficulty, and is conducive to improving the yield of the ring-gate transistor.

[0008] In one example, the channel region includes multiple layers of nanostructures spaced apart in a thickness direction of the semiconductor substrate. The gate-all-around transistor includes multiple layers of inner sidewalls. Among all layers of inner sidewalls included in the gate-all-around transistor, the thickness of the inner sidewalls located at the bottom layer is less than the thickness of the inner sidewalls of the remaining layers. The thickness direction of the inner sidewalls is parallel to the length direction of the gate stack structure.

[0009] In one example, the material of the portion of the dielectric isolation structure located between the semiconductor substrate and the source region and the drain region includes a high thermal conductivity material.

[0010] In one example, a connection between a side of the inner sidewall of the bottom layer close to the gate stack structure and the dielectric isolation structure has an arc-shaped transition.

[0011] In one example, the material of the inner sidewall includes at least one of SiN, SiO2 and SiON.

[0012] In one example, along the thickness direction of the semiconductor substrate, the height of the dielectric isolation structure is greater than or equal to the height of the inner sidewall.

[0013] In a second aspect, the present invention provides a method for manufacturing a ring-gate transistor, the method for manufacturing a ring-gate transistor comprising: first, providing a semiconductor substrate. Next, forming an active structure, a dielectric isolation structure and an inner sidewall on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region, and the two ends of the channel region along the length direction are respectively in contact with the source region and the drain region. The dielectric isolation structure is arranged below the active structure. Next, a gate stack structure surrounding the periphery of the channel region is formed. The inner sidewall is arranged between the gate stack structure and the source region and the drain region respectively. The dielectric isolation structure is used to isolate the semiconductor substrate from the source region, the drain region and part of the gate stack structure respectively. At least the portion of the dielectric isolation structure located below the channel region is continuous with the inner sidewall located at the bottom layer.

[0014] In one example, an active structure, a dielectric isolation structure and an inner sidewall are formed on a semiconductor substrate, including: forming a fin structure on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes a first sacrificial layer and at least one stack located on the first sacrificial layer. Each stack includes a second sacrificial layer and a channel layer located on the second sacrificial layer. The materials of the first sacrificial layer, the second sacrificial layer and the channel layer are different from each other. Next, a mask structure is formed across the fin structure. Next, the portion of the stack exposed outside the mask structure is removed. Next, the first sacrificial layer is removed to form a first dielectric filling region; and along the length direction of the fin structure, the edge portions on both sides of the remaining second sacrificial layer are removed to form a second dielectric filling region. Next, a dielectric isolation structure is formed in the first dielectric filling region, and an inner sidewall is formed in the second dielectric filling region. Next, a source region and a drain region are formed on both sides of the remaining stack, respectively. Next, at least a portion of the mask structure is removed; and the remaining second sacrificial layer is removed so that the remaining channel layer forms a channel region.

[0015] In an example, the mask structure includes a sacrificial gate and gate spacers at least located on two sides of the sacrificial gate along a length direction.

[0016] In one example, the materials of the first sacrificial layer and the second sacrificial layer both include germanium silicon, and the germanium content in the material of the first sacrificial layer is greater than the germanium content in the material of the second sacrificial layer.

[0017] In one example, the fin structure includes a plurality of stacked layers, wherein a germanium content in a material of a second sacrificial layer at a bottom layer is less than a germanium content in a material of a second sacrificial layer at a remaining layer.

[0018] In one example, while forming the inner sidewall in the second dielectric-filled region, a dielectric isolation structure is formed in the first dielectric-filled region.

[0019] In one example, while forming the inner sidewall in the second dielectric filling region, a portion of the dielectric isolation structure located below the channel region is formed. Next, a deposition and etching process is used to form a portion of the dielectric isolation structure located below the source region and the drain region.

[0020] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0022] Figure 1 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 1 ;

[0023] Figure 2 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 2 ;

[0024] Figure 3 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 3 ;

[0025] Figure 4 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 4 ;

[0026] Figure 5 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 5 ;

[0027] Figure 6 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 6 ;

[0028] Figure 7 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 7 ;

[0029] Figure 8 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 8 ;

[0030] Fig. 9 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 9 ;

[0031] Fig.10 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 ;

[0032] Fig.11 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 one;

[0033] Fig.12 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 two;

[0034] Fig.13 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 three;

[0035] Fig.14 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 Four;

[0036] Fig.15 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 five;

[0037] Fig.16 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 six;

[0038] Fig.17 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 seven;

[0039] Fig.18 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 eight;

[0040] Fig.19 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 Nine.

[0041] Figure numerals: 11 is a semiconductor substrate, 12 is a source region, 13 is a drain region, 14 is a channel region, 15 is a gate stack structure, 16 is an inner sidewall, 17 is a dielectric isolation structure, 18 is a shallow trench isolation structure, 19 is a gate sidewall, 20 is an interlayer dielectric layer, 21 is a fin structure, 22 is a first sacrificial layer, 23 is a channel layer, 24 is a second sacrificial layer, 25 is a mask structure, 26 is a first dielectric filling region, and 27 is a second dielectric filling region. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0043] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0044] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0046] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0047] With the development of semiconductor technology, the ring-gate transistor has emerged. Compared with the fin field effect transistor, the gate-all-around transistor has a gate stack structure formed not only on the top and sidewalls of the channel, but also on the bottom of the channel, which can enhance the gate control ability of the ring-gate transistor, suppress the short channel effect, and make the ring-gate transistor have higher working performance.

[0048] However, the gate-all-around transistor has a parasitic channel leakage problem during actual operation. To solve this problem, those skilled in the art mainly use the following two methods to improve it:

[0049] The first type uses a semiconductor substrate with a buried oxide layer, such as a silicon-on-insulator substrate. The parasitic channel leakage is mainly suppressed by injecting doping into the top silicon layer before the stacked material layer of the epitaxial sacrificial layer / channel layer.

[0050] Second, an anti-punch-through injection process is used to inject impurity ions into the middle and lower part of the formed fin structure to suppress parasitic channel leakage. Specifically, in the process of manufacturing the ring-gate transistor, after the fin structure and the shallow trench isolation structure are formed on the substrate, the anti-punch-through injection process is used to inject impurity ions of a conductivity type opposite to that of the impurities doped in the source region and the drain region into at least the fin structure to form a barrier layer in the middle and lower part of the fin structure, thereby using the highly doped barrier layer to suppress the parasitic channel.

[0051] However, in the semiconductor substrate with buried oxide layer such as silicon on insulator used in the first method, the thickness and uniformity of the top silicon layer are difficult to be guaranteed. Specifically, in the process of manufacturing the semiconductor layer substrate on insulator, the thickness of the top silicon layer itself varies after thinning or epitaxy. Different thicknesses have strict requirements on the concentration of impurity injection, and the thickness of the top silicon layer is usually small (about 20nm), resulting in a higher control accuracy of impurity injection into the thinner top silicon layer, that is, it is more difficult to suppress parasitic channel leakage. In the second method, the process fluctuation (for example: injection depth, source and drain etching depth, etc.) of the anti-punch-through injection process has a greater impact, resulting in poor effect of suppressing parasitic channel leakage. In addition, when the width of the channel region included in the ring gate transistor is large, the fin structure formed on the substrate also has a wider width. Based on this, when the anti-punch-through injection process is used to inject ion impurities into the fin structure, it is difficult for the ion impurities to enter the central area of ​​the fin structure along its width direction, that is, the central area of ​​the fin structure along its width direction does not fully form a barrier layer. In this case, after an appropriate voltage is loaded on the gate stack structure of the ring-gate transistor, the source and drain regions can not only be connected through the channel, but also the central area has a parasitic channel leakage problem, thereby reducing the electrical performance of the ring-gate transistor.

[0052] In order to solve the above technical problems, an embodiment of the present invention provides a ring-gate transistor and a manufacturing method thereof. Among them, in the ring-gate transistor provided by the embodiment of the present invention, a dielectric isolation structure is arranged below the active structure, which is used to isolate the semiconductor substrate from the source region, the drain region and part of the gate stack structure respectively to prevent parasitic channel leakage. In addition, at least the portion of the dielectric isolation structure located below the channel region is continuous with the inner sidewall located at the bottom layer to simplify the manufacturing process of the ring-gate transistor and improve the manufacturing efficiency of the ring-gate transistor.

[0053] Specifically, the first aspect is Figures 16 to 19 As shown, the ring-gate transistor of the embodiment of the present invention includes: a semiconductor substrate 11, an active structure, a gate stack structure 15, an inner sidewall 16 and a dielectric isolation structure 17. The active structure is arranged on the semiconductor substrate 11. The active structure includes a source region 12, a drain region 13, and a channel region 14 located between the source region 12 and the drain region 13, and the two ends of the channel region 14 along the length direction are respectively in contact with the source region 12 and the drain region 13. The gate stack structure 15 surrounds the outer periphery of the channel region 14. The inner sidewall 16 is arranged between the gate stack structure 15 and the source region 12 and the drain region 13 respectively. The dielectric isolation structure 17 is arranged below the active structure, and the dielectric isolation structure 17 is used to isolate the semiconductor substrate 11 from the source region 12, the drain region 13 and part of the gate stack structure 15 respectively. At least the portion of the dielectric isolation structure 17 located below the channel region 14 is continuous with the inner sidewall 16 located at the bottom layer.

[0054] When the above technical solution is adopted, Figures 16 to 19 As shown, the ring-gate transistor provided by the embodiment of the present invention includes an inner sidewall 16 located between the source region 12 and the gate stack structure 15, and between the drain region 13 and the gate stack structure 15, so as to limit the length of the gate stack structure 15, improve the yield of the ring-gate transistor, and reduce the parasitic capacitance between the source region 12 and the gate stack structure 15, and between the drain region 13 and the gate stack structure 15. Secondly, the ring-gate transistor provided by the embodiment of the present invention also includes a dielectric isolation structure 17. The dielectric isolation structure 17 is arranged below the active structure. Specifically, the dielectric isolation structure 17 is arranged between the semiconductor substrate 11 and the source region 12, the drain region 13 and a portion of the gate stack structure 15, respectively. Since the dielectric isolation structure 17 is a non-conductive structure, the dielectric isolation structure 17 can separate the semiconductor substrate 11 from the source region 12, the drain region 13 and part of the gate stack structure 15, respectively, to prevent the source region 12 and the drain region 13 from being turned on through the semiconductor material located below the gate stack structure 15 when a suitable voltage is applied to the gate stack structure 15, that is, to prevent parasitic channel leakage, so that the ring-gate transistor has good electrical properties. In addition, the source region 12 and the drain region 13 can also be isolated from the semiconductor substrate 11 by the dielectric isolation structure 17 to prevent source-drain leakage and improve the radiation resistance of the ring-gate transistor. In addition, if Figures 1 to 19As shown, at least the portion of the dielectric isolation structure 17 located below the channel region 14 is continuous with the inner sidewall 16 located at the bottom layer, that is, the inner sidewall 16 and at least part of the dielectric isolation structure 17 can be manufactured simultaneously based on the same dielectric material, which is conducive to simplifying the manufacturing process of the ring-gate transistor and improving the manufacturing efficiency of the ring-gate transistor while ensuring that the ring-gate transistor has good electrical properties. In addition, as long as the first sacrificial layer 22 pre-formed between the second sacrificial layer 24 and the semiconductor substrate 11 is removed, a first dielectric filling area 26 for filling the dielectric isolation structure 17 can be formed, without the need to use ion implantation and precisely control the implantation parameters to only dope the top silicon layer or the middle and lower parts of the fin structure as in the existing manufacturing method, which leads to greater manufacturing difficulty, and is conducive to improving the yield of the ring-gate transistor.

[0055] In the actual application process, the specific structure of the above-mentioned semiconductor substrate can be set according to the actual application scenario, and is not specifically limited here. For example, the semiconductor substrate provided in the embodiment of the present invention can be a semiconductor substrate such as silicon, silicon germanium, germanium, etc. without any structure formed. Alternatively, the semiconductor substrate can also be a semiconductor substrate formed with some structures. For example: when the ring-gate transistor provided in the embodiment of the present invention is a transistor of the second layer or higher layer in the semiconductor device, the semiconductor substrate includes a semiconductor structure located below the ring-gate transistor, etc.

[0056] For the above active structure, from the structural point of view, the source region and the drain region included in the active structure are spaced apart in a direction parallel to the surface of the semiconductor substrate. The channel region is located between the source region and the drain region. Secondly, the channel region can include only one layer of nanostructures, and in this case, the ring-gate transistor only includes a single layer of inner sidewalls. Or, as Figures 16 to 19 As shown, the channel region 14 may also include multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate 11, and in this case, the gate-all-around transistor includes multiple layers of inner sidewalls 16. Among them, the nanostructures at the bottom layer in the channel region 14 are spaced apart from the dielectric isolation structure 17. The number of layers of nanostructures included in the channel region 14, the spacing between the nanostructures and the dielectric isolation structure 17, and the spacing between different layers of nanostructures can be set according to actual needs and are not specifically limited here.

[0057] From the material aspect, the material of the source region, drain region and channel region included in the active structure may include any semiconductor material such as silicon, silicon germanium or germanium, as long as it can be applied to the ring-gate transistor provided in the embodiment of the present invention. Secondly, in the case where the channel region includes a multi-layer nanostructure, the materials of different layers of nanostructures may be the same or different.

[0058] Among them, in the channel region, when the materials of different layers of nanostructures are the same, the critical thickness limit of manufacturing nanostructures can be reduced, and the difficulty of etching process for releasing nanostructures can be reduced, which is conducive to improving the yield of ring-gate transistors. In addition, it can be understood that in the ring-gate transistor, the source electrode electrically connected to the source region is formed at the top of the source region, and the drain electrode electrically connected to the drain region is formed at the top of the drain region, so along the thickness direction close to the semiconductor substrate, the spacing between each layer of nanostructure and the source and drain is greater than the spacing between the other nanostructure located above itself and the source and drain. Correspondingly, when the ring-gate transistor is in the on state, the transmission path of the source and drain through the nanostructure located at the upper part is shorter, and the transmission path of the two through the nanostructure located at the lower part is longer. Because the transmission path is proportional to the on-resistance, the on-resistance of each layer of nanostructure is greater than the on-resistance of another nanostructure located above itself. Under the influence of the on-resistance, the conduction uniformity between the nanostructures of each layer is poor, which leads to the deterioration of the driving performance of the ring-gate transistor. Based on this, when the materials of different layers of nanostructures are different, the carrier mobility of at least one layer of nanostructure material can be set to be greater than the carrier mobility of the nanostructure material located in the layer above itself, so that the nanostructure located in the lower layer has a higher conduction characteristic, which is conducive to improving the conduction uniformity between different layers of nanostructures. As for when the materials of different layers of nanostructures are different, the specific material type of each layer of nanostructure can be determined according to the actual application scenario, and is not specifically limited here.

[0059] For the gate stack structure, the gate stack structure may include a gate dielectric layer and a gate. The gate dielectric layer surrounds the periphery of each layer of the nanostructure and covers the portion of the semiconductor substrate corresponding to the gate formation area. The gate is located on the gate dielectric layer. The material of the gate dielectric layer may be an insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the gate may be a conductive material such as TiN, TaN or TiSiN.

[0060] As for the inner sidewall, the inner sidewall is arranged between the gate stack structure and the source region and the drain region respectively. The material of the inner sidewall may include any low dielectric constant insulating dielectric material such as SiN, SiO2, SiON and SiCO.

[0061] As for the thickness of the inner sidewall, it can be determined according to the length requirement of the gate stack structure in the actual application scenario, and no specific limitation is made here. Figures 16 to 19 As shown, the thicknesses of the inner sidewall spacers 16 of different layers may be the same or different. The thickness direction of the inner sidewall spacers 16 is parallel to the length direction of the gate stack structure 15 .

[0062] Among them, Fig.16 and Fig.17As shown, when the thickness of the inner side walls 16 of different layers are the same, it is not necessary to set different materials for the second sacrificial layers 24 of different layers in order to obtain inner side walls 16 of different thicknesses. While reducing the critical thickness limit of epitaxy, it is beneficial to improve the crystal quality of the channel layer and the conductive performance of the channel region 14; it can also reduce the difficulty of releasing the second dielectric filling area 27 and improve the yield of semiconductor devices.

[0063] like Fig.18 and Fig.19 As shown, when the thickness of the inner sidewalls 16 of different layers is different, optionally, among the inner sidewalls 16 of all layers included in the ring-gate transistor, the thickness of the inner sidewall 16 located at the bottom layer can be set to be smaller than the thickness of the inner sidewalls 16 of the remaining layers, so as to increase the contact area between the nanostructure located at the bottom layer and the gate stack structure 15, and improve the control ability of the gate stack structure 15 over the nanostructure located at the bottom layer, thereby improving the conduction characteristics of the nanostructure located at the bottom layer, and the conduction uniformity between the nanostructures of different layers. Specifically, only the thickness of the inner sidewall 16 located at the bottom layer can be smaller than the thickness of the inner sidewalls 16 of the remaining layers, or the thickness of the inner sidewalls 16 of different layers can be gradually reduced in the direction close to the semiconductor substrate 11. Secondly, the thickness difference of the inner sidewalls 16 of different layers can be determined according to the requirements for the conduction characteristics of the nanostructures of different layers in the actual application scenario, and is not specifically limited here.

[0064] For the dielectric isolation structure, the dielectric isolation structure is arranged below the active structure. Fig.17 As shown, only the portion of the dielectric isolation structure 17 located below the channel region 14 may be continuous with the inner sidewall 16 located at the bottom layer. Fig.16 , Fig.18 and Fig.19 As shown, each part of the dielectric isolation structure 17 may be integrally connected to the inner sidewall 16 at the bottom layer, so as to further simplify the manufacturing process of the ring-gate transistor and improve the manufacturing efficiency of the ring-gate transistor.

[0065] From the material aspect, the material of the dielectric isolation structure can be determined according to its own manufacturing method and actual needs. Fig.17As shown, when only the portion of the dielectric isolation structure 17 located below the channel region 14 is continuous with the inner sidewall 16 located at the bottom layer, the portion of the dielectric isolation structure 17 located below the channel region 14 is made of the same material as the inner sidewall 16; at this time, the material of the portion of the dielectric isolation structure 17 located below the source region 12 and the drain region 13 can be the same as or different from the material of the inner sidewall 16. Among them, when the material of the portion of the dielectric isolation structure 17 located below the source region 12 and the drain region 13 is different from the material of the inner sidewall 16, the type of material of the portion of the dielectric isolation structure 17 located below the source region 12 and the drain region 13 can be set according to actual needs, as long as the source region 12 and the drain region 13 can be isolated from the semiconductor substrate 11 respectively. Exemplarily, the material of the portion of the dielectric isolation structure 17 located between the semiconductor substrate 11 and the source region 12 and the drain region 13 can include a high thermal conductivity material (such as diamond, silicon carbide or boron nitride, etc.), which reduces the thermal resistance of the all-around gate transistor, thereby reducing the loss of the all-around gate transistor.

[0066] Or, if Fig.16 , Fig.18 and Fig.19 As shown, when each part of the dielectric isolation structure 17 is integrally continuous with the inner side wall 16 located at the bottom layer, the material of each part of the dielectric isolation structure 17 is the same as that of the inner side wall 16 .

[0067] Of course, the material of the portion where the dielectric isolation structure is integrally connected to the inner wall of the bottom layer may also include the above-mentioned high thermal conductivity material.

[0068] In terms of appearance, Figures 16 to 18 As shown, the connection between the inner sidewall 16 of the bottom layer close to the gate stack structure 15 and the dielectric isolation structure 17 can be a straight line transition, and the angle between the inner sidewall 16 of the bottom layer close to the gate stack structure 15 and the dielectric isolation structure 17 can be greater than or equal to 90°. Fig.19 As shown, the connection between the inner side wall 16 of the bottom layer close to the gate stack structure 15 and the dielectric isolation structure 17 may also have an arc transition. In this case, the morphology of the gate stack structure 15 at the connection is relatively smooth, which is beneficial to prevent electric field concentration and improve the working performance of the ring-gate transistor.

[0069] In terms of size, the thickness of the dielectric isolation structure can be determined based on the anti-leakage requirements between the semiconductor substrate and the source region, drain region and gate stack structure in the actual application scenario, as well as the actual manufacturing process of the dielectric isolation structure, and is not specifically limited here.

[0070] Optional, such as Figures 16 to 19As shown, along the thickness direction of the semiconductor substrate 11, the height of the dielectric isolation structure 17 can be greater than or equal to the height of the inner side wall 16, so as to ensure that the dielectric isolation structure 17 has good insulation properties, while facilitating the formation of a second dielectric filling area for filling the inner side wall 16, so as to have a larger contact area between the etchant and the first sacrificial layer, so that the etchant has a higher etching rate for the first sacrificial layer, thereby completely releasing the first dielectric filling area for filling the inner side wall 16 and improving the yield of the ring-gate transistor.

[0071] In one example, if Figures 16 to 19 As shown, the above-mentioned ring-gate transistor may also include gate sidewalls 19 located on both sides of the gate stack structure 15 along its own length direction. Along the length direction of the gate stack structure 15, the gate sidewalls 19 span the edge regions on both sides of the channel region 14 to isolate the gate stack structure 15 from other conductive structures, thereby ensuring that the ring-gate transistor has stable electrical characteristics.

[0072] In some cases, such as Fig. 9 ,as well as Figures 16 to 19 As shown, the ring-gate transistor provided by the embodiment of the present invention may also include a shallow trench isolation structure 18 and / or an interlayer dielectric layer 20. The above-mentioned shallow trench isolation structure 18 is located on the semiconductor substrate 11, and is used to isolate different active areas of the semiconductor substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 18 can be set according to actual conditions. The above-mentioned interlayer dielectric layer 20 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 15, which is used to protect the source area 12 and the drain area 13 from being affected by operations such as etching and cleaning when removing the sacrificial gate.

[0073] The material of at least one of the gate sidewall, the shallow trench isolation structure and the interlayer dielectric layer may be an insulating material such as SiN, Si3N4, SiO2 or SiCO.

[0074] In a second aspect, an embodiment of the present invention provides a method for manufacturing a gate-all-around transistor. Figures 1 to 19 The manufacturing process is described by a stereoscopic view or a cross-sectional view of the operation shown. Specifically, the manufacturing method of the ring-gate transistor includes the following steps:

[0075] First, a semiconductor substrate is provided. Next, Figures 1 to 15 As shown, an active structure, a dielectric isolation structure 17 and an inner sidewall 16 are formed on a semiconductor substrate 11. The active structure includes a source region 12, a drain region 13, and a channel region 14 located between the source region 12 and the drain region 13. The two ends of the channel region 14 along the length direction are respectively in contact with the source region 12 and the drain region 13. The dielectric isolation structure 17 is arranged below the active structure. Next, as shown in FIG. Figures 16 to 19As shown, a gate stack structure 15 is formed around the periphery of the channel region 14. An inner sidewall 16 is disposed between the gate stack structure 15 and the source region 12 and the drain region 13, respectively. The dielectric isolation structure 17 is used to isolate the semiconductor substrate 11 from the source region 12, the drain region 13 and part of the gate stack structure 15, respectively. At least the portion of the dielectric isolation structure 17 located below the channel region 14 is continuous with the inner sidewall 16 located at the bottom layer.

[0076] Among them, the structures, materials and specifications of the semiconductor substrate, active structure, dielectric isolation structure, inner sidewall and gate stack structure can be referred to in the previous text and will not be repeated here.

[0077] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0078] In an actual manufacturing process, illustratively, the above-mentioned steps of forming an active structure, a dielectric isolation structure and an inner sidewall on a semiconductor substrate may include:

[0079] like Figures 1 to 3 As shown, a fin structure 21 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 21 includes a first sacrificial layer 22 and at least one stacked layer located on the first sacrificial layer 22. Each stacked layer includes a second sacrificial layer 24 and a channel layer 23 located on the second sacrificial layer 24. The materials of the first sacrificial layer 22, the second sacrificial layer 24 and the channel layer 23 are different from each other.

[0080] Among them, the channel layer in each of the above-mentioned stacked layers is used to manufacture the corresponding layer of nanostructure included in the channel region of the ring-gate transistor, so the number of layers of the stacked layers included in the fin structure can be determined according to the number of layers of the nanostructure included in the channel region, and the material and thickness of the channel layer in the stacked layers can be determined according to the material and thickness of the nanostructure included in the channel region. In addition, the second sacrificial layer in the stacked layers is used to release and form a space to fill the inner sidewall and the gate stack structure in the subsequent release, so the thickness of the second sacrificial layer can be determined with reference to the height of the inner sidewall and the thickness of the gate stack structure mentioned above.

[0081] As for the first sacrificial layer, it is used to form a first dielectric filling region for filling the dielectric isolation structure after subsequent release. Therefore, the thickness of the first sacrificial layer can be determined according to the thickness of the dielectric isolation structure, which is not specifically limited here.

[0082] As for the materials of the first sacrificial layer and the second sacrificial layer, the materials of the two layers may include any two semiconductor materials that are different from the materials of the channel layer and are different from each other, as long as they can be applied to the method for manufacturing the ring-gate transistor provided in the embodiment of the present invention.

[0083] Exemplarily, in the case where the materials of the first sacrificial layer and the second sacrificial layer both include germanium silicon, the germanium content in the material of the first sacrificial layer is greater than the germanium content in the material of the second sacrificial layer, so that the etching rate of the etchant on the first sacrificial layer is greater than the etching rate of the etchant on the second sacrificial layer. As for the size of the germanium content in the materials of the first sacrificial layer and the second sacrificial layer, and the difference in germanium content between the two, it can be determined based on the thickness of the first sacrificial layer and the second sacrificial layer, and the thickness of the inner side wall, and is not specifically limited here. For example: the germanium content in the material of the second sacrificial layer can be 20% to 30%, and the germanium content in the material of the first sacrificial layer can be 50%. For example: the difference in germanium content in the materials of the first sacrificial layer and the second sacrificial layer can be greater than or equal to 20%.

[0084] In addition, when the fin structure includes multiple layers, the materials of different second sacrificial layers can be the same or different. The difference between different second sacrificial layers can be determined according to the thickness difference of the inner sidewalls of different layers in the manufactured all-around gate transistor, which is not specifically limited here.

[0085] For example, in the case where the fin structure includes a multi-layer stack, the germanium content in the material of the second sacrificial layer located at the bottom layer may be less than the germanium content in the material of the second sacrificial layer of the remaining layers. For example, the germanium content in the material of the second sacrificial layer located at the bottom layer may be 20%, and the germanium content in the material of the second sacrificial layer of the remaining layers may be 30%.

[0086] In the actual manufacturing process, Figure 1 As shown, epitaxy or other processes can be used to form a first sacrificial layer 22, a second sacrificial layer 24 and a channel layer 23 on the semiconductor substrate 11 according to the relative position relationship of each film layer in the fin structure. Then, as shown in FIG. Figure 2 As shown, photolithography and etching processes may be used to at least etch the first sacrificial layer 22, the second sacrificial layer 24, the channel layer 23 and a portion of the semiconductor substrate 11 to form a fin. Figure 3 As shown, a shallow trench isolation structure 18 is formed on the semiconductor substrate 11 by using processes such as deposition and etching. The material of the shallow trench isolation structure 18 can refer to the above. Secondly, the top height of the shallow trench isolation structure 18 is less than or equal to the bottom height of the first sacrificial layer 22, and the part of the fin exposed outside the shallow trench isolation structure 18 is a fin-shaped structure 21.

[0087] Next, if Figure 4 As shown, a mask structure 25 is formed across the fin structure 21 .

[0088] In the actual manufacturing process, a deposition process can be used to form a mask material covering the semiconductor substrate. Then, processes such as photolithography and etching are used to selectively etch the mask material to form the above-mentioned mask structure. As for the material of the mask structure, it can be set according to actual needs, as long as it can play a protective role in the subsequent mask.

[0089] Exemplarily, the mask structure may include a sacrificial gate. The material of the sacrificial gate may include a material that is easy to remove, such as polysilicon. Secondly, the mask structure may also include a gate oxide layer, and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include materials such as silicon oxide. In addition, the mask structure may also include a sacrificial gate, and gate sidewalls located at least on both sides of the sacrificial gate along the length direction. The material of the gate sidewall can be referred to in the above text and will not be repeated here.

[0090] Next, if Figure 5 As shown, a dry etching process or a wet etching process may be used to remove the portion of the stack exposed outside the mask structure 25 .

[0091] Next, if Figures 5 to 8 As shown, the first sacrificial layer is removed by dry etching or wet etching to form a first dielectric filling region 26; and the edge portions of the remaining second sacrificial layer 24 are removed along the length direction of the fin structure to form a second dielectric filling region 27. The width of the edge portions of the remaining second sacrificial layer 24 can be determined according to the thickness of the inner sidewall, which is not specifically limited here.

[0092] Next, if Figures 9 to 12 As shown, deposition and etching processes may be used to form a dielectric isolation structure 17 in the first dielectric filling region and to form an inner sidewall 16 in the second dielectric filling region.

[0093] Specifically, in the actual application process, such as Fig.12 As shown, the dielectric isolation structure 17 may be formed in the first dielectric filling region 26 while the inner sidewall 16 is formed in the second dielectric filling region 27 , so as to further simplify the manufacturing process of the all-around gate transistor and improve the manufacturing efficiency of the all-around gate transistor.

[0094] Or, if Fig.10 As shown, it is also possible to form the inner sidewall 16 in the second dielectric filling region 27 while only forming the portion of the dielectric isolation structure 17 located below the channel region 14. Fig.11As shown, deposition and etching processes are used to form the dielectric isolation structure 17 located below the source region 12 and the drain region 13. On the premise that the source region 12 and the drain region 13 can be isolated from the semiconductor substrate 11 by the dielectric isolation structure 17, the materials of different regions of the dielectric isolation structure 17 can be set separately according to different actual needs, thereby improving the applicability of the manufacturing method provided in the embodiment of the present invention in different application scenarios.

[0095] Next, if Fig.13 As shown, epitaxial growth or other processes may be used to form a source region 12 and a drain region 13 on both sides of the remaining stack.

[0096] Next, if Fig.14 As shown, deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 20 on the semiconductor substrate 11. The top of the interlayer dielectric layer 20 is flush with the top of the mask structure 25. The material of the interlayer dielectric layer 20 can be referred to above and will not be repeated here.

[0097] Next, if Fig.15 As shown, a dry etching process or a wet etching process may be used to remove at least a portion of the mask structure; and the remaining second sacrificial layer may be removed, so that the remaining channel layer forms a channel region 14 .

[0098] Specifically, whether to completely remove the mask structure can be determined according to the specific structure of the mask structure. For example, when the mask structure only includes a gate oxide layer and a sacrificial gate, the mask structure needs to be completely removed. For another example, when the mask structure includes a sacrificial gate and a gate sidewall, only the sacrificial gate needs to be removed, that is, only part of the mask structure needs to be removed.

[0099] Next, if Figures 16 to 19 As shown, atomic layer deposition and other processes may be used to form a gate stack structure 15 surrounding the outer periphery of the channel region 14. The specific structure and material of the gate stack structure 15 can be referred to above and will not be repeated here.

[0100] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0101] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A gate-all-around transistor, characterized in that: include: Semiconductor substrate, An active structure is arranged on the semiconductor substrate; the active structure comprises a source region, a drain region, and a channel region located between the source region and the drain region, and two ends of the channel region along the length direction are respectively in contact with the source region and the drain region; A gate stack structure surrounding the periphery of the channel region; An inner sidewall is arranged between the gate stack structure and the source region and the drain region respectively; A dielectric isolation structure, disposed below the active structure, the dielectric isolation structure being used to isolate the semiconductor substrate from the source region, the drain region and a portion of the gate stack structure; At least a portion of the dielectric isolation structure located below the channel region is integrally continuous with the inner sidewall located at the bottom layer.

2. The gate-all-around transistor according to claim 1, characterized in that: The channel region includes multiple layers of nanostructures spaced apart in the thickness direction of the semiconductor substrate; the ring-gate transistor includes multiple layers of inner sidewalls; Among the inner sidewalls of all layers included in the ring-gate transistor, the thickness of the inner sidewalls located at the bottom layer is less than the thickness of the inner sidewalls of the remaining layers; the thickness direction of the inner sidewalls is parallel to the length direction of the gate stack structure.

3. The gate-all-around transistor according to claim 1, wherein: The material of the portion of the dielectric isolation structure located between the semiconductor substrate and the source region and the drain region respectively comprises a high thermal conductivity material.

4. The gate-all-around transistor according to claim 1, wherein: A connection between a side of the inner sidewall located at the bottom layer close to the gate stack structure and the dielectric isolation structure has an arc-shaped transition; And / or, the material of the inner sidewall includes at least one of SiN, SiO2 and SiON.

5. The gate-all-around transistor according to claim 1, wherein: Along the thickness direction of the semiconductor substrate, the height of the dielectric isolation structure is greater than or equal to the height of the inner sidewall.

6. A method for manufacturing a gate-all-around transistor, characterized in that: include: Providing a semiconductor substrate; An active structure, a dielectric isolation structure and an inner sidewall are formed on the semiconductor substrate; the active structure comprises a source region, a drain region, and a channel region located between the source region and the drain region, and two ends of the channel region along the length direction are respectively in contact with the source region and the drain region; the dielectric isolation structure is arranged below the active structure; A gate stack structure is formed around the periphery of the channel region; the inner sidewall is arranged between the gate stack structure and the source region and the drain region respectively; The dielectric isolation structure is used to isolate the semiconductor substrate from the source region, the drain region and part of the gate stack structure respectively; At least a portion of the dielectric isolation structure located below the channel region is integrally continuous with the inner sidewall located at the bottom layer.

7. The method for manufacturing a gate-all-around transistor according to claim 6, wherein: The active structure, dielectric isolation structure and inner sidewall are formed on the semiconductor substrate, comprising: A fin structure is formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, the fin structure includes a first sacrificial layer and at least one stacked layer located on the first sacrificial layer; each of the stacked layers includes a second sacrificial layer and a channel layer located on the second sacrificial layer; the materials of the first sacrificial layer, the second sacrificial layer and the channel layer are different from each other; forming a mask structure spanning over the fin-shaped structure; removing the portion of the stack exposed outside the mask structure; The first sacrificial layer is removed to form a first dielectric filling region; and along the length direction of the fin-shaped structure, the edge portions on both sides of the remaining second sacrificial layer are removed to form a second dielectric filling region; forming the dielectric isolation structure in the first dielectric filling area, and forming the inner sidewall in the second dielectric filling area; forming the source region and the drain region on both sides of the remaining stacked layers respectively; At least a portion of the mask structure is removed; and the remaining second sacrificial layer is removed, so that the remaining channel layer forms the channel region.

8. The method for manufacturing a gate-all-around transistor according to claim 7, characterized in that: The mask structure includes a sacrificial gate and gate sidewalls at least located on two sides of the sacrificial gate along the length direction.

9. The method for manufacturing a gate-all-around transistor according to claim 7, wherein: The materials of the first sacrificial layer and the second sacrificial layer both include germanium silicon, and the germanium content in the material of the first sacrificial layer is greater than the germanium content in the material of the second sacrificial layer; And / or, the fin structure includes a plurality of the stacked layers; the germanium content in the material of the second sacrificial layer at the bottom layer is less than the germanium content in the materials of the second sacrificial layers in the remaining layers.

10. The method for manufacturing a gate-all-around transistor according to claim 7, wherein: While forming the inner sidewall in the second medium filling area, forming the medium isolation structure in the first medium filling area; or, while forming the inner sidewall in the second dielectric filling region, forming a portion of the dielectric isolation structure located below the channel region; Next, a deposition and etching process is used to form a portion of the dielectric isolation structure located below the source region and the drain region.

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