A silicon carbide PiN with tunable fin-type JTE structure and its preparation method

Abstract

This invention discloses a silicon carbide (PiN) with a tunable fin-type JTE structure and its fabrication method. The PiN includes a substrate, a drift layer on the substrate, a positive doped region and a negative doped region formed by doping the drift layer, a fin-type JTE structure formed by etching the drift layer between the positive and negative doped regions, a terminal oxide layer surrounding the fin-type JTE structure on three sides, a terminal metal layer covering the surface of the terminal oxide layer, a positive metal layer on the positive doped region, and a negative metal layer on the negative doped region. The tunable fin-type JTE structure provided by this invention allows for the formation of a terminal electric field distribution suitable for different operating environments by adjusting the terminal control signal and terminal charge, thereby improving terminal efficiency.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a tunable fin-type JTE (Junction Termination Extension) structure silicon carbide PiN (Positive-intrinsic-Negative, P-type semiconductor-impurity-N-type semiconductor) and its preparation method. Background Technology

[0002] Due to the superior physical properties of SiC (silicon carbide) material, SiC devices have attracted widespread attention and research. These high-temperature, high-power silicon carbide electronic devices possess advantages such as high input impedance, fast switching speed, high operating frequency, and resistance to high temperature and high pressure, and have been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] During the fabrication of SiC devices, electric field concentration inevitably occurs at the junction edges. Therefore, existing SiC power devices require termination structures to protect these edges. The termination structure significantly impacts the performance of SiC power devices, necessitating a high-performance SiC power device that also incorporates a termination structure. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a silicon carbide PiN with a tunable fin-type JTE structure and its preparation method.

[0005] The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a silicon carbide PiN with a tunable fin-type JTE structure, comprising:

[0007] Substrate;

[0008] A drift layer is located on the substrate;

[0009] The drift layer is doped to form a positive doped region and a negative doped region;

[0010] A fin-type JTE structure is formed by etching the drift layer between the positive doped region and the negative doped region.

[0011] The terminal oxide layer surrounds the fin-type JTE structure on three sides;

[0012] A terminal metal layer covering the surface of the terminal oxide layer;

[0013] A positive electrode metal layer located above the positive electrode doped region;

[0014] The negative electrode metal layer located above the negative electrode doped region.

[0015] Optionally, the substrate includes a silicon carbide substrate.

[0016] Optionally, the drift layer includes a silicon carbide drift layer.

[0017] Optionally, the terminal oxide layer includes a silicon dioxide terminal oxide layer.

[0018] Optionally, the terminal metal layer includes an aluminum terminal metal layer.

[0019] Optionally, the positive electrode metal layer includes an aluminum positive electrode metal layer; the negative electrode metal layer includes an aluminum negative electrode metal layer.

[0020] Secondly, the present invention provides a method for preparing silicon carbide PiN with a tunable fin-type JTE structure, the method comprising:

[0021] A substrate is selected and a drift layer is formed on the substrate;

[0022] Ion implantation is performed on the drift layer to form positive and negative doped regions, respectively;

[0023] The drift layer between the positive electrode doped region and the negative electrode doped region is etched to form a fin-type JTE structure.

[0024] A terminal oxide layer is deposited around the fin-type JTE structure on three sides;

[0025] A terminal metal layer is deposited on the surface of the terminal oxide layer;

[0026] A positive electrode metal layer is deposited on the positive electrode doped region;

[0027] A negative electrode metal layer is deposited on the negative electrode doped region.

[0028] Optionally, ion implantation is performed on the drift layer to form positive and negative doped regions, including:

[0029] A positive electrode region is selected on the surface of the drift layer;

[0030] A first barrier layer is formed on the surface of the drift layer other than the positive electrode region;

[0031] Ion implantation is performed on the positive electrode region to form the positive electrode doped region;

[0032] The first barrier layer is etched away;

[0033] A negative electrode region is selected on the surface of the drift layer; the negative electrode region and the positive electrode region are spaced apart by a certain distance.

[0034] A second barrier layer is formed on the surface of the drift layer other than the negative electrode region;

[0035] Ion implantation is performed on the negative electrode region to form the negative electrode doped region;

[0036] The second barrier layer is etched away.

[0037] Optionally, etching the drift layer between the positive doped region and the negative doped region to form a fin-type JTE structure includes:

[0038] A third barrier layer is formed on the surfaces of the positive electrode doped region and the negative electrode doped region;

[0039] The drift layer between the positive doped region and the negative doped region is etched to form the fin-type JTE structure.

[0040] The third barrier layer is etched away.

[0041] The present invention provides a silicon carbide PiN with an adjustable fin-type JTE structure, comprising a substrate, a drift layer on the substrate, a positive electrode doped region and a negative electrode doped region formed by doping the drift layer, a fin-type JTE structure formed by etching the drift layer between the positive electrode doped region and the negative electrode doped region, a terminal oxide layer surrounding the fin-type JTE structure on three sides, a terminal metal layer covering the surface of the terminal oxide layer, a positive electrode metal layer located on the positive electrode doped region, and a negative electrode metal layer located on the negative electrode doped region.

[0042] Because the terminal oxide layer in this design is a three-sided finned JTE structure, terminal charges can be provided from three directions via the terminal control signal provided by the terminal metal layer, thereby adjusting the terminal electric field distribution. Furthermore, the presence of the finned JTE structure enhances the controllability of the terminal charge and terminal control signal. By adjusting the terminal control signal and terminal charge, a terminal electric field distribution suitable for different operating environments can be formed, thereby improving terminal efficiency.

[0043] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0044] Figure 1 A cross-sectional view of a silicon carbide PiN with an adjustable fin-type JTE structure provided in an embodiment of the present invention;

[0045] Figure 2 A schematic flowchart illustrating a method for preparing silicon carbide PiN with a tunable fin-type JTE structure, provided in an embodiment of the present invention.

[0046] Figure 3This is a schematic diagram illustrating the preparation process of a silicon carbide PiN with an adjustable fin-type JTE structure, as provided in an embodiment of the present invention. Detailed Implementation

[0047] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0048] To provide a high-performance SiC power device with a termination structure, this invention provides a silicon carbide (PiN) with a tunable fin-type JTE structure, see [link to relevant documentation]. Figure 1 , Figure 1 This is a cross-sectional view of a silicon carbide PiN with an adjustable fin-type JTE structure provided in an embodiment of the present invention. The silicon carbide PiN comprises:

[0049] Substrate 10, drift layer 20 on substrate 10, positive electrode doped region 30 and negative electrode doped region 40 formed by doping drift layer 20, fin-type JTE structure formed by etching drift layer 20 between positive electrode doped region 30 and negative electrode doped region 40, terminal oxide layer 50 surrounding fin-type JTE structure on three sides, terminal metal layer 60 covering the surface of terminal oxide layer 50, positive electrode metal layer 70 on positive electrode doped region 30 and negative electrode metal layer 80 on negative electrode doped region 40.

[0050] In this embodiment, the substrate 10 serves as the base for the semiconductor chip, providing a process platform for the subsequent formation of the semiconductor structure. The substrate 10 can be grown using different methods, and no limitation is made here.

[0051] In this embodiment, a drift layer 20 can be deposited on the substrate 10 using methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0052] The positive electrode doped region 30 is formed by introducing trivalent elements such as boron or gallium. The negative electrode doped region 40 is formed by introducing pentavalent elements such as phosphorus or arsenic.

[0053] In this embodiment, the fin-type JTE structure is formed by etching the drift layer 20 between the positive electrode doped region 30 and the negative electrode doped region 40.

[0054] Specifically, a photolithography machine can be used to expose and develop the drift layer 20 between the positive electrode doped region 30 and the negative electrode doped region 40 to form the photolithographic pattern to be etched. Then, the photolithographic pattern is etched to finally obtain the fin-type JTE structure.

[0055] In this embodiment, the terminal oxide layer 50 surrounds the fin-type JTE structure from three sides in the front, top and back directions. Therefore, the terminal oxide layer 50 can provide terminal charge from three directions and regulate the terminal electric field distribution.

[0056] The terminal metal layer 60, i.e. the terminal electrode, is deposited on the surface of the terminal oxide layer 50, and provides the terminal control signal through the terminal electrode.

[0057] In this embodiment, the positive electrode metal layer 70 and the negative electrode metal layer 80 are used to establish electrical connections and extract electrical signals. Specifically, the positive electrode metal layer 70 is connected to a positive electrode voltage to form an electrical connection on the surface of the positive electrode doped region 30. The negative electrode metal layer 80 is connected to a negative electrode voltage to form an electrical connection on the surface of the negative electrode doped region 40.

[0058] In this embodiment, a silicon carbide (PiN) with an adjustable fin-type JTE structure is provided. The terminal oxide layer 50 is a three-sided surrounding fin-type JTE structure. Therefore, terminal charges can be provided from three directions via the terminal control signal provided by the terminal metal layer 60, thereby adjusting the terminal electric field distribution. Furthermore, the presence of the fin-type JTE structure enhances the controllability of the terminal charge and the terminal control signal. By adjusting the terminal control signal and the terminal charge, a terminal electric field distribution suitable for different operating environments can be formed, thereby improving terminal efficiency.

[0059] In this embodiment of the invention, the substrate 10 can be a silicon carbide, germanium, or silicon germanide substrate. Since silicon carbide material has good stability, heat dissipation, and corrosion resistance, it is preferably a silicon carbide substrate for the substrate 10 in this embodiment. Simultaneously, because silicon carbide material also has good conductivity, the drift layer 20 is preferably a silicon carbide drift layer, and the corresponding positive electrode doped region 30 is a silicon carbide positive electrode doped region, and the negative electrode doped region 40 is a silicon carbide negative electrode doped region.

[0060] In this embodiment of the invention, the terminal oxide layer 50 is preferably a silicon dioxide terminal oxide layer. Silicon dioxide has excellent insulating properties and good thermal stability, maintaining stable insulating properties even at high temperatures, which helps to improve the operating temperature range of semiconductor devices. Simultaneously, silicon dioxide has good chemical stability and anti-friction properties, reducing the risk of device damage. Furthermore, silicon dioxide is a common inorganic material with low cost, is easy to prepare and process, and helps to reduce manufacturing costs.

[0061] In this embodiment of the invention, the terminal metal layer 60 is preferably an aluminum terminal metal layer, the positive electrode metal layer 70 is preferably an aluminum positive electrode metal layer, and the negative electrode metal layer 80 is preferably an aluminum negative electrode metal layer. Aluminum is a high-quality conductive material that provides excellent current transmission. Furthermore, aluminum possesses good chemical and physical stability, making semiconductor devices more stable and reliable. Simultaneously, aluminum's high thermal conductivity effectively dissipates heat, helping to reduce the temperature of semiconductor devices. In addition, aluminum is a common and relatively inexpensive metal, which can reduce the manufacturing cost of semiconductor devices.

[0062] This invention also provides a method for preparing silicon carbide PiN with a tunable fin-type JTE structure. See [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic flowchart illustrating a method for preparing silicon carbide PiN with a tunable fin-type JTE structure, provided by an embodiment of the present invention. The method includes the following steps:

[0063] Step S201: Select substrate 10 and form drift layer 20 on substrate 10.

[0064] See Figure 3 (a) in the middle, Figure 3 This is a schematic diagram illustrating the fabrication process of a silicon carbide PiN with a tunable fin-type JTE structure, provided in an embodiment of the present invention. In this embodiment, the substrate 10 is preferably a silicon carbide substrate, and the drift layer 20 is preferably a silicon carbide drift layer.

[0065] In step S202, ion implantation is performed on the drift layer 20 to form the positive electrode doped region 30 and the negative electrode doped region 40, respectively.

[0066] See Figure 3 In (b), ion implantation refers to the implantation of charged ions with a certain energy into the drift layer 20. Ion implantation allows for more precise control of the amount of impurities incorporated. In this embodiment, ion implantation can be a single implantation or multiple implantations.

[0067] Step S203: Etch the drift layer 20 between the positive electrode doped region 30 and the negative electrode doped region 40 to form a fin-type JTE structure.

[0068] Etching is a semiconductor manufacturing process that removes unwanted portions of the drift layer 20 between the positive doped region 30 and the negative doped region 40. See also... Figure 3 In (c), a fin-type JTE structure is formed by etching the drift layer 20 between the positive electrode doped region 30 and the negative electrode doped region 40.

[0069] Step S204: Deposit terminal oxide layer 50 on three sides of the surrounding fin-type JTE structure.

[0070] See Figure 3 In embodiment (d), terminal oxide layers 50 are deposited around the upper, front, and rear surfaces of the fin-type JTE structure.

[0071] Common oxidation methods include dry oxidation and wet oxidation. To ensure both a short oxidation time and high oxidation quality, this embodiment employs a method of first wet oxidation followed by dry oxidation to form the terminal oxide layer 50. Wet oxidation is used first to increase the rate of formation of the terminal oxide layer 50, while dry oxidation is used later to ensure the quality of the terminal oxide layer 50.

[0072] Step S205: Deposit a terminal metal layer 60 on the surface of the terminal oxide layer 50.

[0073] See Figure 3 In step (e), after cleaning the surface of the terminal oxide layer 50, a terminal metal layer 60 is formed on the surface of the terminal oxide layer 50. Specifically, this can be achieved using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques.

[0074] Step S206: Deposit a positive electrode metal layer 70 on the positive electrode doped region 30.

[0075] See Figure 3 In step (f), a positive electrode metal layer 70 is deposited on the surface of the positive electrode doped region 30 on the left side. For the specific deposition process, please refer to step S205.

[0076] Step S207: Deposit a negative electrode metal layer 80 on the negative electrode doped region 40.

[0077] See Figure 3 In step (f), a negative electrode metal layer 80 is deposited on the surface of the negative electrode doped region 40 on the right side. For the specific deposition process, please refer to step S205.

[0078] In this embodiment, the method for fabricating the tunable fin-type JTE structure of silicon carbide PiN involves selecting a substrate 10 and forming a drift layer 20 on top of the substrate 10. Ion implantation is then performed on the drift layer 20 to form a positive electrode doped region 30 and a negative electrode doped region 40. The drift layer 20 between the positive electrode doped region 30 and the negative electrode doped region 40 is then etched to form a fin-type JTE structure. A terminal oxide layer 50 is deposited around the fin-type JTE structure on three sides. A terminal metal layer 60 is deposited on the surface of the terminal oxide layer 50. A positive electrode metal layer 70 is deposited on the positive electrode doped region 30, and a negative electrode metal layer 80 is deposited on the negative electrode doped region 40.

[0079] Because the terminal oxide layer 50 is a three-sided finned JTE structure, terminal charges can be provided from three directions via the terminal control signal provided by the terminal metal layer 60, thereby adjusting the terminal electric field distribution. Furthermore, the presence of the finned JTE structure enhances the controllability of the terminal charge and terminal control signal. By adjusting the terminal control signal and terminal charge, a terminal electric field distribution suitable for different operating environments can be formed, thereby improving terminal efficiency.

[0080] In this embodiment of the invention, ion implantation is performed on the drift layer 20 to form a positive electrode doped region 30 and a negative electrode doped region 40, respectively, including:

[0081] (1) Select a positive electrode region on the surface of the drift layer 20.

[0082] See Figure 3 In (b), the left side is selected as the positive pole region.

[0083] (2) After forming a first barrier layer on the surface of the drift layer 20 other than the positive electrode region, ion implantation is performed on the positive electrode region to form a positive electrode doped region 30.

[0084] The positive electrode doped region 30 is formed by introducing trivalent elements, such as boron or gallium. The first barrier layer can be a silicon dioxide barrier layer.

[0085] (3) After forming the positive electrode doped region 30, the first barrier layer is etched away.

[0086] (4) Select a negative electrode region on the surface of the drift layer 20; wherein the negative electrode region and the positive electrode region are separated by a certain distance.

[0087] See Figure 3 In (b), the right side is selected as the negative region.

[0088] (5) After forming a second barrier layer on the surface of the drift layer 20 other than the negative electrode region, ion implantation is performed on the negative electrode region to form a negative electrode doped region 40.

[0089] (6) After forming the negative electrode doped region 40, the second barrier layer is etched away. The second barrier layer can be a silicon dioxide barrier layer.

[0090] In this embodiment of the invention, the step of etching the drift layer 20 between the positive electrode doped region 30 and the negative electrode doped region 40 to form a fin-type JTE structure can be as follows: An oxide barrier layer is generated on the surface of the drift layer 20, the positive electrode doped region 30, and the negative electrode doped region 40. Then, a third barrier layer is formed on the oxide barrier layer generated on the surface of the positive electrode doped region 30 and the negative electrode doped region 40. The third barrier layer can be formed by coating with photoresist. The third barrier layer is exposed and developed using a photolithography machine. Then, the third barrier layer is used as an etching barrier layer for the oxide barrier layer on the surface of the drift layer 20 between the positive electrode doped region 30 and the negative electrode doped region 40 to etch the oxide barrier layer, forming the photolithographic pattern to be etched. The third barrier layer is removed, and then the photolithographic pattern of the oxide barrier layer on the surface of the drift layer 20 between the positive electrode doped region 30 and the negative electrode doped region 40 is etched to remove the drift layer 20 to a certain depth, forming the fin-type JTE structure. The oxide barrier layer can be a silicon dioxide barrier layer.

[0091] Etching removes areas not covered by the third barrier layer and removes a certain depth of drift layer 20, forming a fin-type JTE structure. (See [reference]) Figure 3 In step (c), the oxide barrier layer is finally etched away.

[0092] In addition, after etching, the residue produced by etching can be removed by cleaning.

[0093] In this embodiment of the invention, the step of depositing a terminal oxide layer 50 around the fin-type JTE structure on three sides specifically includes: forming a fourth barrier layer on the surface other than the fin-type JTE structure, and depositing the terminal oxide layer 50 around the fin-type JTE structure on three sides from the front, top, and rear directions. See [link to previous section]. Figure 3 Then, (d) is etched away, and the fourth barrier layer is removed. The fourth barrier layer can be a silicon dioxide barrier layer.

[0094] In this embodiment of the invention, the step of depositing a terminal metal layer 60 on the surface of the terminal oxide layer 50 specifically involves forming a fifth barrier layer on the surface other than the terminal oxide layer 50, and depositing a terminal metal layer 60 on the surface of the terminal oxide layer 50. See [link to previous section]. Figure 3 Then, (e) is etched away, and the fifth barrier layer is removed. The fifth barrier layer can be a silicon dioxide barrier layer.

[0095] In this embodiment of the invention, the specific steps for depositing a positive electrode metal layer 70 on the positive electrode doped region 30 are as follows: after forming a sixth barrier layer on the surface other than the positive electrode doped region 30, a positive electrode metal layer 70 is deposited on the positive electrode doped region 30. See [link to previous instructions]. Figure 3 (f) is then etched away, removing the sixth barrier layer. The specific steps for depositing the negative electrode metal layer 80 on the negative electrode doped region 40 are as follows: after forming the seventh barrier layer on the surface other than the negative electrode doped region 40, the negative electrode metal layer 80 is deposited on the negative electrode doped region 40. See [link to relevant documentation]. Figure 3 Then, the seventh barrier layer is etched away. Both the sixth and seventh barrier layers are silicon dioxide barrier layers.

[0096] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0097] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0098] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0099] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0100] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0101] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A silicon carbide PiN with an adjustable fin-type JTE structure, characterized in that, include: Substrate; A drift layer is located on the substrate; The drift layer is doped to form a positive doped region and a negative doped region; A fin-type JTE structure is formed by etching the drift layer between the positive doped region and the negative doped region. The terminal oxide layer surrounds the fin-type JTE structure on three sides; A terminal metal layer covering the surface of the terminal oxide layer; A positive electrode metal layer located above the positive electrode doped region; The negative electrode metal layer located above the negative electrode doped region.

2. The silicon carbide PiN with an adjustable fin-type JTE structure according to claim 1, characterized in that, The substrate includes a silicon carbide substrate.

3. The silicon carbide PiN with an adjustable fin-type JTE structure according to claim 1, characterized in that, The drift layer includes a silicon carbide drift layer.

4. The silicon carbide PiN with an adjustable fin-type JTE structure according to claim 1, characterized in that, The terminal oxide layer includes a silicon dioxide terminal oxide layer.

5. The silicon carbide PiN with an adjustable fin-type JTE structure according to claim 1, characterized in that, The terminal metal layer includes an aluminum terminal metal layer.

6. The silicon carbide PiN with an adjustable fin-type JTE structure according to claim 1, characterized in that, The positive electrode metal layer includes an aluminum positive electrode metal layer; the negative electrode metal layer includes an aluminum negative electrode metal layer.

7. A method for preparing silicon carbide PiN with a tunable fin-type JTE structure, characterized in that, The method includes: A substrate is selected and a drift layer is formed on the substrate; Ion implantation is performed on the drift layer to form positive and negative doped regions, respectively; The drift layer between the positive electrode doped region and the negative electrode doped region is etched to form a fin-type JTE structure. A terminal oxide layer is deposited around the fin-type JTE structure on three sides; A terminal metal layer is deposited on the surface of the terminal oxide layer; A positive electrode metal layer is deposited on the positive electrode doped region; A negative electrode metal layer is deposited on the negative electrode doped region.

8. The preparation method according to claim 7, characterized in that, Ion implantation is performed on the drift layer to form positive and negative doped regions, including: A positive electrode region is selected on the surface of the drift layer; A first barrier layer is formed on the surface of the drift layer other than the positive electrode region; Ion implantation is performed on the positive electrode region to form the positive electrode doped region; The first barrier layer is etched away; A negative electrode region is selected on the surface of the drift layer; the negative electrode region and the positive electrode region are spaced apart by a certain distance. A second barrier layer is formed on the surface of the drift layer other than the negative electrode region; Ion implantation is performed on the negative electrode region to form the negative electrode doped region; The second barrier layer is etched away.

9. The preparation method according to claim 7, characterized in that, The etching of the drift layer between the positive doped region and the negative doped region to form a fin-type JTE structure includes: A third barrier layer is formed on the surface of the positive electrode doped region and the negative electrode doped region; The drift layer between the positive doped region and the negative doped region is etched to form the fin-type JTE structure. The third barrier layer is etched away.

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