Power device and preparation method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a power device and a preparation method, a power module, a power conversion circuit and a vehicle. The power device comprises: a semiconductor body, the semiconductor body comprises a first surface and a second surface arranged oppositely, the semiconductor body further comprises a well region, a first region and a plurality of buried layers, the well region and the buried layer have the same conductivity type; a gate groove is further arranged on the first surface, the semiconductor body further comprises a first insulating layer, the first insulating layer is located in the gate groove; the gate is located in the gate groove and is located on the side of the first insulating layer away from the second surface; a plurality of buried layers are located on the side of the gate away from the first surface and are arranged along a first direction, the plurality of buried layers comprise a first buried layer at least covering the bottom of the gate groove, and a second buried layer penetrated by the gate groove and located on both sides of the gate groove; a drain electrode, the drain electrode is located on the second surface; a source electrode, the source electrode is located on the first surface. The present invention can reduce the specific on-resistance of the device and enhance the withstand voltage performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Among common power devices, trench metal oxide semiconductor field effect transistor (trench MOSFET) has the advantages of high current density and small cell pitch. The current mainstream solutions of trench MOSFET are: Figure 1 This is a schematic diagram of the structure of a power device in the prior art. Figure 1 The double-trench Trench MOSFET has a source trench structure 01, and the source trench structure 01 is in contact with the source 90, which will result in a larger chip area, a larger specific on-resistance of the chip, and poor device performance. Summary of the invention

[0003] The present invention provides a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, which can reduce the specific on-resistance of the device and enhance the voltage resistance performance of the device.

[0004] According to one aspect of the present invention, there is provided a power device, comprising:

[0005] A semiconductor body, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body further comprises a well region, a first region and a plurality of buried layers, wherein the well region and the buried layers have the same conductivity type; the first region is arranged on the first surface, and the well region is located on a side of the first region away from the first surface; a gate trench is further arranged on the first surface, and the gate trench extends from the first surface into the semiconductor body; the semiconductor body further comprises a first insulating layer, and the first insulating layer is located in the gate trench;

[0006] A gate, the gate is located in the gate trench and is located on a side of the first insulating layer away from the second surface;

[0007] The plurality of buried layers are located on a side of the gate away from the first surface and are arranged along a first direction, the plurality of buried layers include a first buried layer at least covering the bottom of the gate trench, and a second buried layer penetrated by the gate trench and located on both sides of the gate trench, and the first direction is a direction from the first surface to the second surface;

[0008] A drain electrode, the drain electrode is located on the second surface;

[0009] The source electrode is located on the first surface.

[0010] Optionally, a plurality of buried layers are arranged in contact or spaced apart along the first direction.

[0011] Optionally, the gate trench extends from the first surface into the first buried layer, and the first buried layer covers the bottom and at least a portion of the sidewall of the gate trench.

[0012] Optionally, the semiconductor body includes a substrate and an epitaxial structure, and the epitaxial structure is located on a side of the substrate away from the second surface;

[0013] The epitaxial structure includes a first epitaxial layer and a second epitaxial layer, wherein the second epitaxial layer is located on a side of the first epitaxial layer away from a substrate; a second buried layer extends from an edge of the second sub-epitaxial layer away from a substrate to the second sub-epitaxial layer, wherein the first epitaxial layer includes a first buried layer, and the second epitaxial layer includes a second buried layer.

[0014] Optionally, the second epitaxial layer includes at least one second sub-epitaxial layer, and the number of the second sub-epitaxial layers is greater than or equal to the number of the second buried layers.

[0015] Optionally, the thicknesses of the multiple buried layers along the first direction are the same, or the thicknesses of the multiple buried layers along the first direction decrease one by one, or the thicknesses of the multiple buried layers along the first direction increase one by one.

[0016] Optionally, along the first direction, the widths of multiple buried layers along the second direction are the same, or, along the first direction, the widths of multiple buried layers along the second direction decrease one by one, or, along the first direction, the widths of multiple buried layers along the second direction increase one by one; the second direction intersects the first direction.

[0017] Optionally, the depth of the gate trench along the first direction is 2 μm-12 μm;

[0018] The thickness of any one of the plurality of buried layers along the first direction is 0.2 μm-3 μm;

[0019] The width of any one of the plurality of buried layers along the second direction is 0.5 μm-5 μm.

[0020] According to another aspect of the present invention, a power module is provided, comprising a substrate and a power device according to any embodiment of the present invention, wherein the substrate is used for carrying the power device.

[0021] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0022] The power conversion circuit comprises a circuit board and at least one power device according to any embodiment of the present invention, and the power device is electrically connected to the circuit board.

[0023] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit being used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input into the load.

[0024] According to another aspect of the present invention, there is provided a method for preparing a power device, comprising:

[0025] A semiconductor body is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region, a first region and a plurality of buried layers, the well region and the buried layers have the same conductivity type; the first region is arranged on the first surface, the well region is located on a side of the first region away from the first surface; a gate trench is further arranged on the first surface, the gate trench extends from the first surface into the semiconductor body; the semiconductor body further comprises a first insulating layer, the first insulating layer is located in the gate trench;

[0026] A gate is formed in the gate trench; the gate is located on a side of the first insulating layer away from the second surface; a plurality of buried layers are located on a side of the gate away from the first surface and are arranged along a first direction, the plurality of buried layers include a first buried layer at least covering the bottom of the gate trench, and a second buried layer penetrated by the gate trench and located on both sides of the gate trench, and the first direction is a direction from the first surface to the second surface;

[0027] forming a drain electrode on the second surface;

[0028] A source electrode is formed on the first surface.

[0029] Optionally, a semiconductor body is provided, comprising:

[0030] providing a substrate;

[0031] An epitaxial structure is formed on the side of the substrate away from the second surface; the epitaxial structure includes a first epitaxial layer and a second epitaxial layer, the second epitaxial layer is located on the side of the first epitaxial layer away from the substrate; the first epitaxial layer includes a first buried layer, and the second epitaxial layer includes a second buried layer.

[0032] The power device provided by the technical solution of the embodiment of the present invention includes: a semiconductor body, the semiconductor body includes a first surface and a second surface arranged oppositely, the semiconductor body also includes a well region, a first region and a plurality of buried layers, the well region and the buried layers have the same conductivity type; the first region is arranged on the first surface, the well region is located on the side of the first region away from the first surface; the first surface is also provided with a gate groove, the gate groove extends from the first surface to the semiconductor body; the semiconductor body also includes a first insulating layer, the first insulating layer is located in the gate groove. A gate, the gate is located in the gate groove and is located on the side of the first insulating layer away from the second surface; a plurality of buried layers are located on the side of the gate away from the first surface and are arranged along a first direction, the plurality of buried layers include a first buried layer at least covering the bottom of the gate groove, and a second buried layer penetrated by the gate groove and located on both sides of the gate groove, the first direction is the direction from the first surface to the second surface; a drain, the drain is located on the second surface; a source, the source is located on the first surface. In the embodiment of the present invention, by flexibly setting the buried layer at the bottom and sidewall of the gate trench, the buried layer can be flexibly distributed, the voltage resistance of the device can be enhanced, and the device can be prevented from being punched through; there is no need to set a source trench structure at the source to occupy the area of ​​the semiconductor body to reduce the peak electric field at the bottom of the trench-type gate; thereby reducing the device's specific on-resistance and improving the device's performance; and by flexibly setting the buried layer at the bottom and sidewall of the gate trench, the buried layer can be flexibly distributed, the voltage resistance of the device can be enhanced, and the device can be prevented from being punched through.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 It is a structural schematic diagram of a power device in the prior art.

[0036] Figure 2 It is a schematic diagram of the structure of a power device provided in Embodiment 1 of the present invention.

[0037] Figure 3 It is a structural schematic diagram of another power device provided in the first embodiment of the present invention.

[0038] Figure 4It is a structural schematic diagram of another power device provided in the first embodiment of the present invention.

[0039] Figure 5 It is a structural schematic diagram of another power device provided in the first embodiment of the present invention.

[0040] Figure 6 It is a structural schematic diagram of another power device provided in the first embodiment of the present invention.

[0041] Figure 7 It is a flow chart of a method for preparing a power device provided in the second embodiment of the present invention.

[0042] Figure 8 yes Figure 7 A detailed flow chart included in S110.

[0043] Figure 9-11 It is a schematic diagram of an intermediate structure of a power device provided in the second embodiment of the present invention.

[0044] Fig.12 It is a schematic diagram of the intermediate structure of another power device provided in the second embodiment of the present invention.

[0045] Fig.13 It is a schematic diagram of the intermediate structure of another power device provided in the second embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0048] Embodiment 1

[0049] An embodiment of the present invention provides a power device. Figure 2 is a schematic diagram of the structure of a power device provided in Embodiment 1 of the present invention, Figure 3 is a schematic diagram of the structure of another power device provided in the first embodiment of the present invention, Figure 4 is a schematic diagram of the structure of another power device provided in the first embodiment of the present invention, referring to Figure 2-Figure 4 , power devices include:

[0050] A semiconductor body, the semiconductor body includes a first surface 02 and a second surface 03 arranged opposite to each other, the semiconductor body also includes a well region 30, a first region 40 and a plurality of buried layers 51, the well region 30 and the buried layer 51 have the same conductivity type; the first region 40 is arranged on the first surface 02, and the well region 30 is located on a side of the first region 40 away from the first surface 02; the first surface 02 is also provided with a gate trench 60, and the gate trench 60 extends from the first surface 02 to the semiconductor body; the semiconductor body also includes a first insulating layer 71, and the first insulating layer 71 is located in the gate trench 60.

[0051] A gate 73, the gate 73 is located in the gate groove 60 and is located on the side of the first insulating layer 71 away from the second surface 03; a plurality of buried layers 51 are located on the side of the gate 73 away from the first surface 02 and are arranged along a first direction Y, the plurality of buried layers 51 include a first buried layer 501 at least covering the bottom of the gate groove 60, and a second buried layer 502 penetrated by the gate groove 60 and located on both sides of the gate groove 60, the first direction Y is the direction from the first surface 02 to the second surface 03; a drain 80, the drain 80 is located on the second surface 03; a source 90, the source 90 is located on the first surface 02.

[0052] The power device may be a trench metal oxide field effect transistor (MOSFET) device. If the device is an N-type device, the conductivity type of the first region 40 is N-type, and the conductivity type of the well region 30 and the buried layer 51 is P-type; if the device is a P-type device, the conductivity type of the first region 40 is P-type, and the conductivity type of the well region 30 and the buried layer 51 is N-type. The semiconductor body may also include a substrate 10 and an epitaxial structure 20 formed on one side of the substrate 10. The material of the substrate and the semiconductor epitaxial layer may be SiC. The power device in the embodiment of the present invention may be a SiC MOSFET device. The semiconductor body includes a first surface 02 and a second surface 03 that are arranged opposite to each other. When the semiconductor body includes a substrate 10 and an epitaxial structure 20, the first surface 02 may be a surface of the epitaxial structure 20 away from the substrate, and the second surface 03 may be a surface of the substrate 10 away from the epitaxial structure 20.

[0053] When the power device is an N-type device, the first region 40 can be an N+ region, and the N+ region can be formed by injecting N-type ions at the position of the first region 40. The N-type ions can be phosphorus (P) ions or nitrogen (N) ions; the well region 30 can be a P-type well region (PW region), and the PW region can be formed by injecting P-type ions at the position of the well region 30. The P-type ions can be aluminum (Al) ions or boron (B) ions; the buried layer 51 can be a P+ region, and the P+ region can be formed by injecting P-type ions at the position of the buried layer 51.

[0054] The first insulating layer 71 and the second insulating layer 72 are located between the gate 73 and the gate trench 60, and are used to insulate the semiconductor body and the gate 73; the first insulating layer 71 can play a supporting role to avoid reliability risks of the device; the second insulating layer 72 can be used as a gate oxide layer; the gate 73 can be a polysilicon layer. Exemplarily, the device structure in the embodiment of the present invention may include multiple gates, each gate corresponds to multiple buried layers 51, and the width of the buried layer 51 in the second direction X is greater than the width of the gate trench 60 in the second direction X; there is no need to set a source trench structure at the source to occupy the area of ​​the semiconductor body to reduce the peak electric field at the bottom of the trench-type gate; and setting multiple gates 73 can form multiple conductive channels, increase the number of channels, thereby increasing the current density, reducing the specific on-resistance of the device, and improving the performance of the device. The vertical projection of the buried layer 51 in the second direction X of the insulating layer does not overlap with the vertical projection of the gate 73 in the second direction X of the insulating layer, which can avoid excessive on-resistance of the device and affect the performance of the device. In the first direction X, the more the number of buried layers 51, the stronger the pressure bearing capacity.

[0055] The power device provided by the technical solution of the embodiment of the present invention includes: a semiconductor body, the semiconductor body includes a first surface 02 and a second surface 03 arranged opposite to each other, the semiconductor body also includes a well region 30, a first region 40 and a plurality of buried layers 51, the well region 30 and the buried layer 51 have the same conductivity type; the first region 40 is arranged on the first surface 02, and the well region 30 is located on a side of the first region 40 away from the first surface 02; the first surface 02 is also provided with a gate trench 60, and the gate trench 60 extends from the first surface 02 to the semiconductor body; the semiconductor body also includes a first insulating layer 71, and the first insulating layer 71 is located in the gate trench 60. A gate 73, the gate 73 is located in the gate groove 60 and is located on the side of the first insulating layer 71 away from the second surface 03; a plurality of buried layers 51 are located on the side of the gate 73 away from the first surface 02 and are arranged along a first direction Y, the plurality of buried layers 51 include a first buried layer 51 at least covering the bottom of the gate groove 60, and a second buried layer 52 penetrated by the gate groove 60 and located on both sides of the gate groove 60, the first direction Y is the direction from the first surface 02 to the second surface 03; a drain 80, the drain 80 is located on the second surface 03; a source 90, the source 90 is located on the first surface 02. In the embodiment of the present invention, by flexibly setting the buried layer 51 at the bottom and sidewall of the gate trench 60, the buried layer 51 can be flexibly distributed, the voltage resistance of the device can be enhanced, and the device can be prevented from being punched through; there is no need to set a source trench structure at the source to occupy the area of ​​the semiconductor body to reduce the peak electric field at the bottom of the trench-type gate; thereby reducing the device's specific on-resistance and improving the device's performance; and by flexibly setting the buried layer at the bottom and sidewall of the gate trench, the buried layer can be flexibly distributed, the voltage resistance of the device can be enhanced, and the device can be prevented from being punched through.

[0056] Based on the above embodiment, optionally, refer to Figure 2-Figure 4 , multiple buried layers 51 are arranged in contact or spaced apart along the first direction Y.

[0057] Among them, reference Figure 3 , when the semiconductor body includes a plurality of buried layers 51, the plurality of buried layers 51 are arranged along the first direction Y and contact each other; or, referring to Figure 2 and Figure 4 When the semiconductor body includes a plurality of buried layers 51, the plurality of buried layers 51 are arranged along a first direction Y and are spaced apart; the first direction Y is a direction from the first surface 02 to the second surface 03. The semiconductor body further includes a second region 102, which is disposed on the first surface 02 and is located between adjacent gate trenches 60; the second region 102 has the same conductivity type as the well region 30.

[0058] Based on the above embodiment, optionally, refer to Figure 2The gate trench 60 extends from the first surface 02 into the first buried layer 501 , and the first buried layer 501 covers the bottom and at least a portion of the sidewall of the gate trench 60 .

[0059] The first buried layer 501 is the buried layer farthest from the first surface 02 among the multiple buried layers 51. The first buried layer 501 covers the bottom and at least part of the sidewall of the insulating layer, so that the buried layer 501 can withstand voltage drop, improve the voltage resistance of the device, and avoid device breakdown.

[0060] Based on the above embodiment, optionally, refer to Figure 2-Figure 4 The semiconductor body includes a substrate 10 and an epitaxial structure 20, the epitaxial structure 20 is located on the side of the substrate 10 away from the second surface 03; the epitaxial structure 20 includes a first epitaxial layer 21 and a second epitaxial layer 22, the second epitaxial layer 22 is located on the side of the first epitaxial layer 21 away from the substrate 10; the first epitaxial layer 21 includes a first buried layer 501, and the second epitaxial layer 22 includes a second buried layer 502.

[0061] Based on the above embodiment, optionally, refer to Figure 2-Figure 4 The second epitaxial layer 22 includes at least one second sub-epitaxial layer 221, and the second buried layer 502 extends from the edge of the second sub-epitaxial layer 221 away from the substrate side 10 to the second sub-epitaxial layer 221, and the number of the second sub-epitaxial layers 221 is greater than or equal to the number of the second buried layers 502.

[0062] Among them, when the power device is an N-type device, the substrate 10 is an N+ substrate, for example, it can be an N+ silicon carbide substrate; the epitaxial structure 20 is an N-epitaxial structure, for example, it can be an N-silicon carbide epitaxial structure; the second region 102 has the same conductivity type as the well region 30, and the second region 102 can be formed by injecting P-type ions at the position of the second region 102, and the P-type ions can be aluminum (Al) ions or boron (B) ions; the second region 102 runs through the first region 40 to the well region 30, and can be grounded when the reverse device is turned off, thereby protecting the device.

[0063] Specifically, in the multiple buried layers 51 corresponding to a gate 73, the second epitaxial layer 22 includes at least one second sub-epitaxial layer 221, and the number of the second sub-epitaxial layers 221 is greater than or equal to the number of the second buried layers 502. The epitaxial structure 20 is formed by multiple epitaxy, and the number of the second epitaxial layers 22 can be determined according to the number of buried layers 51. Exemplarily, when forming multiple buried layers 51 arranged along the first direction Y, the number of the second epitaxial layers 22 is the same as the number of the multiple buried layers 51 arranged along the first direction Y. Each gate corresponds to multiple buried layers 51, and the first buried layers 501 formed corresponding to multiple gates 73 can be formed simultaneously in the same epitaxial layer, and multiple buried layers 51 arranged along the second direction X can be formed in the second epitaxial layer 22, so as to realize the flexible distribution of the buried layers 51, enhance the voltage resistance of the device, and avoid device breakdown.

[0064] Exemplarily, the semiconductor body includes a substrate 10 and an epitaxial structure 20, and the epitaxial structure 20 includes at least three epitaxial layers. Figure 2 , Figure 2 It may include a plurality of gates 73, and the epitaxial structure 20 includes three epitaxial layers. A first epitaxial layer 21 may be formed on one side of the substrate 10, and ion implantation is performed on the first epitaxial layer 21 to form a plurality of first buried layers 501 spaced apart. At this time, each first buried layer 501 corresponds to a gate, and the width of the first buried layer 501 in the second direction X is greater than the width of the gate trench 60 in the second direction X; a second epitaxial layer is then formed, and ion implantation is performed on the first second sub-epitaxial layer 221 to form a plurality of second buried layers 502 spaced apart; a second second sub-epitaxial layer 221 is then formed, and a gate trench 60 and a gate are subsequently formed by etching, the gate trench 60 extends from the first surface 02 to the first buried layer 501 adjacent to the second surface 03, a first buried layer 501 covers the bottom of the first insulating layer 71, and a second buried layer 502 contacts the side of the first insulating layer 71, and the plurality of buried layers 51 can withstand voltage drop, thereby improving the voltage resistance of the device and preventing the device from breakdown.

[0065] refer to Figure 3 , Figure 3The epitaxial structure 20 may include a plurality of gates 73. The epitaxial structure 20 may include a plurality of epitaxial layers. A first epitaxial layer 21 may be formed on one side of the substrate 10, and ion implantation may be performed on the first epitaxial layer 21 to form a plurality of first buried layers 501. At this time, each first buried layer 501 corresponds to a gate 73, and the width of the buried layer 51 in the second direction X is greater than the width of the gate trench 60 in the second direction X. The epitaxial layer formation and ion implantation process are repeated, and each gate 73 corresponds to a plurality of buried layers 51 arranged along the first direction Y. Then, the last epitaxial layer is formed. Except for the epitaxial layers formed for the first and last time, in the first buried layer 501, The thickness of the epitaxial layer formed secondary and thereafter is the same as the thickness of the ion implantation, so that the multiple buried layers 51 are in contact with each other along the first direction Y, and then a gate groove 60 and a gate are formed by etching. The gate groove 60 extends from the first surface 02 to the first buried layer 501 adjacent to the second surface 03. The first buried layer 501 adjacent to the second surface 03 is the outermost buried layer 51 away from the first surface 02 among the multiple buried layers 51. The multiple buried layers 51 are in contact with each other and cover the bottom surface and part of the side surface of the first insulating layer 71, so that the buried layer 51 can withstand the voltage drop, thereby improving the voltage resistance of the device and avoiding device breakdown.

[0066] refer to Figure 4 , Figure 4 The epitaxial structure 20 may include multiple gates. The epitaxial structure 20 may include multiple epitaxial layers. A first epitaxial layer 21 may be formed on one side of the substrate 10. Ion implantation may be performed on the first epitaxial layer 21 to form multiple first buried layers 501. At this time, each first buried layer 501 corresponds to a gate 73. The epitaxial layer formation and ion implantation process may be repeated. Each gate 73 corresponds to multiple buried layers 51 arranged along the first direction Y. Then, the last epitaxial layer may be formed. The thickness of the epitaxial layer formed for the second time and thereafter is greater than the thickness of the ion implantation. Thus, the multiple buried layers 501 may be formed. 1 are arranged at intervals along the first direction Y, and subsequently a gate trench 60 and a gate are formed by etching. The gate trench 60 extends from the first surface 02 to the first buried layer 501 adjacent to the second surface 03. The first buried layer 501 adjacent to the second surface 03 is the outermost buried layer 51 away from the first surface 02 among the multiple buried layers 51. The first buried layer 501 covers the bottom of the first insulating layer 71, and the multiple second buried layers 502 are in contact with the side of the first insulating layer 71, so that the buried layer 51 can withstand the voltage drop, thereby improving the voltage resistance of the device and avoiding the breakdown of the device.

[0067] Based on the above embodiment, optionally, refer to Figure 4 , along the first direction Y, the thicknesses of the plurality of buried layers 51 along the first direction Y are the same, or, Figure 5 is a schematic diagram of the structure of another power device provided in the first embodiment of the present invention, referring to Figure 5Along the first direction Y, the thickness of the multiple buried layers 51 along the first direction Y gradually decreases, or, along the first direction Y, the thickness of the multiple buried layers 51 along the first direction Y gradually increases.

[0068] Among them, the thicker the buried layer 51 is, the smaller the on-resistance is and the stronger the pressure-bearing capacity of the device is. The thickness of the buried layer 51 can be set according to needs, and the thickness change can be a uniform change or an uneven change. The embodiments of the present invention do not make specific limitations, and can achieve flexible distribution of the buried layer 51, enhance the pressure-bearing capacity of the device, and avoid device breakdown.

[0069] Based on the above embodiment, optionally, refer to Figure 4 , along the first direction Y, the widths of the plurality of buried layers 51 along the second direction X are the same, or, along the first direction Y, the widths of the plurality of buried layers 51 along the second direction X gradually decrease, or, Figure 6 is a schematic diagram of the structure of another power device provided in the first embodiment of the present invention, referring to Figure 6 Along the first direction Y, the widths of the multiple buried layers 51 along the second direction X gradually increase; the second direction X intersects the first direction Y.

[0070] Among them, the smaller the width of the buried layer 51 along the first direction Y, the smaller the on-resistance and the stronger the pressure-bearing capacity of the device; the width of the buried layer 51 can be set according to needs, and the width change can be a uniform change or an uneven change. The embodiments of the present invention do not make specific limitations, and can achieve flexible distribution of the buried layer 51, enhance the pressure-bearing capacity of the device, and avoid device breakdown.

[0071] Based on the above embodiment, optionally, refer to Figure 2-Figure 4 The power device further includes: an interlayer dielectric layer 101, which is located on a side of the first surface 02 away from the second surface 03, and covers the gate 73; a second insulating layer 72, which is located in the gate trench 60, covers the surface of the first insulating layer 71 adjacent to the gate 73 and a portion of the sidewall of the gate trench 60, and is used to isolate the gate 73 from the semiconductor body; a source 90 is located on a side of the interlayer dielectric layer 101 away from the second surface 03, and covers the interlayer dielectric layer 101 and a portion of the first surface 02.

[0072] The material of the interlayer dielectric layer 101 may be silicon dioxide, and the interlayer dielectric layer 101 may play a role of insulation isolation. The first insulating layer 71 covers the bottom and part of the sidewall of the gate trench 60, and the second insulating layer 72 may cover the surface of the first insulating layer 71 adjacent to the first surface 02 and the sidewall of the gate trench 60 not covered by the first insulating layer 71.

[0073] Specifically, the material of the first insulating layer 71 can be an insulating material such as silicon carbide (SiN), oxide (Oxide) and polycrystalline silicon (Poly). The first insulating layer 71 can be deposited in the gate groove 60, and the area for the second insulating layer 72 and the gate 73 is reserved by back etching. The first insulating layer 71 fills part of the gate groove 60, so that the first insulating layer 71 is in contact with the buried layer 51, and the second insulating layer 72 and the gate 73 are not in contact with the buried layer 51; the first insulating layer 71 can play a supporting role to avoid reliability risks of the device; the second insulating layer 72 can cover the side of the first insulating layer 71 adjacent to the first surface 02, and the side wall of part of the gate groove 60. The second insulating layer 72 does not fill the gate trench 60. The second insulating layer 72 is a thin layer formed by an oxidation process and can be used as a gate oxide layer. Subsequently, a gate 73 is formed on the side of the second insulating layer 72 away from the second surface 03.

[0074] Based on the above embodiment, optionally, refer to Figure 2-Figure 4 The depth of the gate trench 60 along the first direction Y is 2 μm-12 μm; the thickness of the multiple buried layers 51 along the first direction Y is 0.2 μm-3 μm; the width of the multiple buried layers 51 along the second direction X is 0.5 μm-5 μm.

[0075] in, Figure 2-Figure 4 A plurality of gate trenches 60 are formed in the device. The depth of the gate trenches 60 along the first direction Y is 2μm-12μm, which can be used to form a deep trench structure, so that the buried layer 51 has less influence on the on-resistance. The distance between adjacent gate trenches 60 is 0.5μm-6μm, which can facilitate the formation of a conductive channel between adjacent gate trenches 60 and reduce the specific on-resistance of the device. The thickness of the buried layer along the first direction Y is 0.2μm-3μm, and the width of the buried layer 51 along the second direction X is 0.5μm-5μm, both of which can make the on-resistance of the device smaller and the pressure-bearing capacity stronger.

[0076] Based on the above embodiment, optionally, the material of the semiconductor body includes silicon carbide; and the material of the first insulating layer includes at least one of silicon nitride, oxide, and polysilicon.

[0077] The material of the semiconductor body includes silicon carbide; the material of the first insulating layer includes any one of silicon nitride, oxide, and polysilicon, and the process is mature and the preparation is simple.

[0078] An embodiment of the present invention further provides a power module based on the above embodiment, comprising a substrate and the power device described in any embodiment of the present invention, wherein the substrate is used to carry the power device.

[0079] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0080] An embodiment of the present invention further provides a power conversion circuit based on the above embodiments, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and the power device described in any embodiment of the present invention, and the power device is electrically connected to the circuit board.

[0081] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0082] An embodiment of the present invention further provides a vehicle based on the above embodiments, including a load and the power conversion circuit described in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0083] The vehicle provided by the technical solution of the embodiment of the present invention and the power device described in any embodiment of the present invention have the same beneficial effects.

[0084] Embodiment 2

[0085] The embodiment of the present invention provides a method for preparing a power device based on the above embodiment. The method for preparing a power device provided by the embodiment of the present invention is used to prepare the power device described in any embodiment of the present invention. Figure 7 is a flow chart of a method for preparing a power device provided in the second embodiment of the present invention, with reference to Figure 7 , the preparation method comprises:

[0086] S110. Provide a semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a well region, a first region and a plurality of buried layers, the well region and the buried layers have the same conductivity type; the first region is arranged on the first surface, the well region is located on a side of the first region away from the first surface; the first surface is also provided with a gate trench, the gate trench extends from the first surface into the semiconductor body; the semiconductor body also includes a first insulating layer, the first insulating layer is located in the gate trench.

[0087] S120, forming a gate in the gate groove; the gate is located on the side of the first insulating layer away from the second surface; multiple buried layers are located on the side of the gate away from the first surface and are arranged along a first direction, the multiple buried layers include a first buried layer that at least covers the bottom of the gate groove, and a second buried layer that is penetrated by the gate groove and located on both sides of the gate groove, and the first direction is the direction from the first surface to the second surface.

[0088] S130, forming a drain on the second surface.

[0089] The drain electrode may be formed by a conventional metal electrode forming method.

[0090] S140, forming a source on the first surface.

[0091] The source electrode may be formed by a conventional metal electrode forming method.

[0092] The method for preparing a power device provided by the technical solution of the embodiment of the present invention can achieve flexible distribution of the buried layer, enhance the voltage resistance of the device, and avoid device breakdown by flexibly setting the buried layer at the bottom and side walls of the gate groove; there is no need to set a source groove structure at the source to occupy the area of ​​the semiconductor body to reduce the peak electric field at the bottom of the trench-type gate; thereby reducing the device's specific on-resistance and improving the device's performance; and by flexibly setting the buried layer at the bottom and side walls of the gate groove, it can achieve flexible distribution of the buried layer, enhance the voltage resistance of the device, and avoid device breakdown.

[0093] Based on the above embodiment, optionally, Figure 8 yes Figure 7 A detailed flow chart included in S110, Figure 9-11 is a schematic diagram of an intermediate structure of a power device provided in the second embodiment of the present invention, with reference to Figure 8-Figure 11 , S110, providing a semiconductor body, including:

[0094] S111, forming a plurality of buried layers;

[0095] Among them, reference Fig. 9 , a plurality of buried layers 51 arranged along the first direction Y can be formed through multiple epitaxial growth and ion implantation processes.

[0096] S112, forming a first region on the first surface.

[0097] Among them, reference Fig.10 , the first region 40 is formed by an ion implantation process. If the device is an N-type device, N-type ions may be implanted into the first surface 02 to form the first region 40 .

[0098] S113, forming a well region on a side of the first region away from the first surface; the well region has the same conductivity type as the buried layer.

[0099] Among them, reference Fig.10 , a well region 30 is formed by an ion implantation process; if the device is an N-type device, P-type ions can be implanted on a side of the first region 40 away from the first surface 02 to form the well region 30; after the well region is formed, it also includes: forming a second region 102 on the first surface 02, and P-type ions can be implanted on the first surface 02 to form the second region 102.

[0100] S114, forming a gate trench on the first surface; the gate trench extends from the first surface into the semiconductor body.

[0101] Among them, reference Fig.11 , a gate trench 60 is formed on the first surface 02 by a trench etching process. If the gate trench 60 includes a plurality of buried layers 51 arranged along the first direction Y, the gate trench 60 penetrates the first region 40 and the well region 30, as well as a plurality of buried layers 51 adjacent to the first surface 02, and the plurality of buried layers 51 adjacent to the first surface 02 do not include the outermost buried layer 51 away from the first surface 02; each gate trench 60 extends from the first surface 02 to the buried layer 51 adjacent to the second surface 03, and the buried layer adjacent to the second surface 03 is the outermost buried layer 51 away from the first surface 02.

[0102] S115 , forming a first insulating layer in the gate trench.

[0103] in, Fig.12 is a schematic diagram of an intermediate structure of another power device provided in the second embodiment of the present invention, with reference to Fig.12 The entire first insulating layer 71 is formed by chemical vapor deposition (CVD), and then formed by an etching back process. Fig.12 The structure of the first insulating layer 71 in FIG.

[0104] Based on the above embodiment, optionally, S111, forming a plurality of buried layers, includes:

[0105] S1111. Provide a substrate.

[0106] S1112. Form an epitaxial structure on a side of the substrate away from the second surface; the epitaxial structure includes a first epitaxial layer and a second epitaxial layer, the second epitaxial layer is located on a side of the first epitaxial layer away from the substrate; the first epitaxial layer includes a first buried layer, and the second epitaxial layer includes a second buried layer.

[0107] Among them, reference Fig. 9 , a buried layer 51 is formed in the second epitaxial layer 22 by ion implantation. The second epitaxial layer 22 includes at least one second sub-epitaxial layer 221 , and the number of the second sub-epitaxial layers 221 is greater than or equal to the number of the second buried layers 502 .

[0108] Exemplary, reference Fig. 9 , Fig. 9The present invention comprises five buried layers 51 arranged along a first direction Y, wherein the five buried layers 51 are arranged at intervals, and the thickness of the epitaxial layers is greater than the thickness of the buried layers 51. After forming a plurality of first buried layers 501 in the first epitaxial layer 21, a first second sub-epitaxial layer 221 is formed on a side of the first epitaxial layer 21 away from the substrate 10, and a plurality of second buried layers 502 are formed in the first second sub-epitaxial layer 221; a second second sub-epitaxial layer 221 is formed on a side of the first second sub-epitaxial layer 221 away from the substrate 10, A plurality of second buried layers 502 are formed in the second second sub-epitaxial layer 221; a third second sub-epitaxial layer 221 is formed on the side of the second second sub-epitaxial layer 221 away from the substrate 10, and a plurality of second buried layers 502 are formed in the third second sub-epitaxial layer 221; a fourth second sub-epitaxial layer 221 is formed on the side of the third second sub-epitaxial layer 221 away from the substrate 10, and a plurality of buried layers 51 are formed in the fourth second sub-epitaxial layer 221; and finally, the last second sub-epitaxial layer 221 is formed.

[0109] Based on the above embodiment, optionally, after S115, forming the first insulating layer in the gate trench, the method further includes: forming a second insulating layer in the gate trench.

[0110] in, Fig.13 is a schematic diagram of an intermediate structure of another power device provided in the second embodiment of the present invention, with reference to Fig.13 , a second insulating layer 72 is formed in the gate trench 60; the second insulating layer 72 covers the side of the first insulating layer 71 adjacent to the first surface and a portion of the sidewall of the gate trench 60, and the second insulating layer 72 is formed on the side of the first insulating layer 71 away from the second surface 03 through an oxidation process.

[0111] On the basis of the above embodiment, optionally, S120, forming a gate in the gate trench includes: forming a gate on a side of the second insulating layer 72 away from the second surface.

[0112] The gate may be formed on a side of the second insulating layer away from the second surface by a conventional deposition process.

[0113] Based on the above embodiment, optionally, after forming the gate in the gate trench, the method further includes:

[0114] An interlayer dielectric layer is formed on a side of the first surface away from the second surface; the interlayer dielectric layer covers the gate.

[0115] A source electrode is formed on the first surface, comprising:

[0116] A source electrode is formed on a side of the interlayer dielectric layer away from the second surface, and the source electrode covers the interlayer dielectric layer and a portion of the first surface.

[0117] An interlayer dielectric layer (ILD) is formed by depositing an insulating material to isolate the gate and the source; then the source and the drain are formed.

[0118] The method for preparing a power device provided in an embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0119] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0120] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A power device, characterized in that: include: A semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region, a first region and a plurality of buried layers, the well region and the buried layers having the same conductivity type; the first region being arranged on the first surface, the well region being located on a side of the first region away from the first surface; the first surface being further provided with a gate trench, the gate trench extending from the first surface into the semiconductor body; the semiconductor body further comprising a first insulating layer, the first insulating layer being located in the gate trench; a gate, the gate being located in the gate trench and on a side of the first insulating layer away from the second surface; The multiple buried layers are located on a side of the gate away from the first surface and arranged along a first direction, the multiple buried layers include a first buried layer at least covering the bottom of the gate trench, and a second buried layer penetrated by the gate trench and located on both sides of the gate trench, and the first direction is a direction from the first surface to the second surface; a drain electrode, the drain electrode being located on the second surface; A source electrode is located on the first surface.

2. The power device according to claim 1, characterized in that: The plurality of buried layers are arranged in contact or spaced apart arrangement along the first direction.

3. The power device according to claim 2, characterized in that: The gate trench extends from the first surface into the first buried layer, and the first buried layer covers the bottom and at least a portion of the sidewall of the gate trench.

4. The power device according to claim 2, characterized in that: The semiconductor body comprises a substrate and an epitaxial structure, wherein the epitaxial structure is located on a side of the substrate away from the second surface; The epitaxial structure includes a first epitaxial layer and a second epitaxial layer, wherein the second epitaxial layer is located on a side of the first epitaxial layer away from a substrate; the first epitaxial layer includes a first buried layer, and the second epitaxial layer includes the second buried layer.

5. The power device according to claim 4, characterized in that: The second epitaxial layer includes at least one second sub-epitaxial layer, the second buried layer extends from an edge of the second sub-epitaxial layer away from the substrate into the second sub-epitaxial layer, and the number of the second sub-epitaxial layers is greater than or equal to the number of the second buried layers.

6. The power device according to claim 1, characterized in that: The thicknesses of the multiple buried layers along the first direction are the same, or the thicknesses of the multiple buried layers along the first direction decrease one by one, or the thicknesses of the multiple buried layers along the first direction increase one by one.

7. The power device according to claim 6, characterized in that: Along the first direction, the widths of the multiple buried layers along the second direction are the same, or, along the first direction, the widths of the multiple buried layers along the second direction decrease one by one, or, along the first direction, the widths of the multiple buried layers along the second direction increase one by one; the second direction intersects with the first direction.

8. The power device according to claim 7, characterized in that: The depth of the gate trench along the first direction is 2 μm-12 μm; The thickness of any one of the plurality of buried layers along the first direction is 0.2 μm-3 μm; A width of any one of the plurality of buried layers along the second direction is 0.5 μm-5 μm.

9. A power module, characterized in that: It comprises a substrate and at least one power device according to any one of claims 1 to 8, wherein the substrate is used to support the power device.

10. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one power device according to any one of claims 1 to 8, wherein the power device is electrically connected to the circuit board.

11. A vehicle, characterized in that: It includes a load and a power conversion circuit as claimed in claim 10, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

12. A method for preparing a power device, characterized in that: include: A semiconductor body is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region, a first region and a plurality of buried layers, the well region and the buried layers have the same conductivity type; the first region is arranged on the first surface, the well region is located on a side of the first region away from the first surface; the first surface is further provided with a gate trench, the gate trench extends from the first surface into the semiconductor body; the semiconductor body further comprises a first insulating layer, the first insulating layer is located in the gate trench; A gate is formed in the gate trench; the gate is located on a side of the first insulating layer away from the second surface; the multiple buried layers are located on a side of the gate away from the first surface and are arranged along a first direction, the multiple buried layers include a first buried layer at least covering the bottom of the gate trench, and a second buried layer penetrated by the gate trench and located on both sides of the gate trench, and the first direction is the direction from the first surface to the second surface; forming a drain electrode on the second surface; A source electrode is formed on the first surface.

13. The preparation method according to claim 12, characterized in that: The semiconductor body is provided, comprising: providing a substrate; An epitaxial structure is formed on the side of the substrate away from the second surface; the epitaxial structure includes a first epitaxial layer and a second epitaxial layer, the second epitaxial layer is located on the side of the first epitaxial layer away from the substrate; the first epitaxial layer includes a first buried layer, and the second epitaxial layer includes the second buried layer.

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