A LDMOS device structure and preparation method thereof
By using thin film conductive layer as field plates in LDMOS devices, the problem of difficulty in balancing resistance value and volume in field plates is solved, and the process steps are simplified to adapt to the aperture requirements of different sizes, and efficient device design is achieved.
Patent Information
- Application Number
- CN202411905439.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-04-08
AI Technical Summary
The field plate of LDMOS devices is difficult to balance the relationship between resistance and volume, and the processing technology is complicated by the requirements of different sizes of apertures.
A thin film conductive layer is used as the field plate of the LDMOS device. The thin film conductive layer is located on the side surface of the SAB barrier layer facing away from the semiconductor substrate layer, connecting the field plate to lead out the conductive column, and is coated by the device dielectric layer.
By serving as the field plate, the process steps are simplified, the balance between the field plate size and resistance value is achieved, the problem of conductive column occupies volume and adapting to the pore size requirements of different sizes.
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Figure CN119789484A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of MOS devices, and in particular to an LDMOS device and a preparation method thereof. Background Art
[0002] With the continuous development of semiconductor technology, the application of power devices is becoming more and more extensive, among which LDMOS (Laterally Diffused Metal Oxide Semiconductor) is widely used in wireless communication, broadcasting and television, radar, medical and industrial fields. In LDMOS devices, the trade-off between on-resistance and breakdown voltage is the focus of device design. With the increasing application of LDMOS, higher requirements are put forward for the performance of LDMOS such as voltage resistance and output power, such as requiring it to have a higher breakdown voltage.
[0003] Field plate technology is a common technical method for improving the withstand voltage of LDMOS devices. A field plate is set above the drift region of the substrate, and an electric field is applied to the drift region to increase the voltage of several strings. One common field plate is to use semiconductor material or metal material to form a column structure of metal or semiconductor material as a field plate on the side of the barrier layer at the corresponding position above the drift region of the substrate facing away from the substrate. This method usually requires that after the dielectric layer of the upper structure of the substrate is formed, the dielectric layer is punched to form a field plate. On the one hand, the column structure as a field plate needs to cover the drift region as much as possible and requires a suitable resistance value, so the diameter is large in size, resulting in a large volume occupied by the field plate part, and balancing the resistance and volume of the field plate becomes a cumbersome problem. On the other hand, there are usually more than one size of LDMOS devices in the entire semiconductor structure, and then there are also multiple sizes of field plates, and the corresponding field plate fills multiple holes. Since the same layer structure is usually prepared synchronously, it is difficult to form holes of different sizes in one step, and multiple steps are required to complete, resulting in cumbersome process steps.
[0004] Therefore, a solution is needed to solve the problem that the field plate of the LDMOS device is difficult to balance the relationship between resistance and volume, and the processing process is complicated due to the requirements of different aperture sizes. Summary of the invention
[0005] Therefore, the present invention provides an LDMOS device and a method for preparing the same, so as to solve the problem that the field plate of the LDMOS device is difficult to balance the relationship between resistance and volume, and the processing process is complicated due to the requirements of apertures of different sizes.
[0006] In one aspect of the present invention: the present invention provides an LDMOS device, comprising: a semiconductor substrate layer; a gate structure, located on the surface of the semiconductor substrate layer; a SAB barrier layer, the SAB barrier layer at least covers a portion of the surface of the gate structure, and extends to one side along the side of the gate structure to the surface of the semiconductor substrate layer, and further extends on the surface of the semiconductor substrate layer; a device dielectric layer, covering the gate structure and the SAB barrier layer; a field plate lead-out conductive layer located on the surface of the device dielectric layer on the side facing away from the semiconductor substrate layer, and a field plate lead-out conductive column extending from the field plate lead-out conductive layer to the SAB barrier layer and penetrating the device dielectric layer; and further comprising: a thin film conductive layer, serving as a field plate of the LDMOS device; the thin film conductive layer is located on the surface of the SAB barrier layer on the side facing away from the semiconductor substrate layer, and is connected to the field plate lead-out conductive column, and is covered by the device dielectric layer; the area of the SAB barrier layer covered by the thin film conductive layer is larger than the area of the projection of the field plate lead-out conductive column on the SAB barrier layer.
[0007] The LDMOS device provided by the present invention has a thin film conductive layer arranged on the surface of the SAB barrier layer facing away from the semiconductor substrate layer, which can be used as a field plate of the device to provide an electric field to increase the breakdown voltage of the drift region. Compared with using a conductive column as a field plate, the thin film conductive layer can be used as a field plate. Since it can be directly formed as a thin film layer on the surface of the SAB barrier layer during production, any pattern can be formed using a metal etching process. No matter how many shapes are required, the size can be completed in one etching step, and the process steps are simple. At the same time, the thin film conductive layer is used as a field plate, so that the balance between the size of the field plate and the resistance value does not need to be limited by the height of the conductive column, and can be relatively freely selected and balanced between a larger spreading coverage area and a lower thickness, making the design balance easier, and without occupying a larger device volume. In addition, the thickness of the thin film conductive layer can also be designed and adjusted as needed to meet other design requirements. And the corresponding field plate conductive column can be set to a smaller size, and there is no need to occupy a larger device volume.
[0008] Optionally, the thin film conductive layer at least covers a portion of the SAB barrier layer located on the surface of the semiconductor substrate layer. Using the thin film conductive layer as a field plate, the field plate coverage can be controlled to a portion of the SAB barrier layer located on the surface of the semiconductor substrate layer by graphical means, which is simple to implement.
[0009] Optionally, the thin film conductive layer completely covers the surface of the SAB barrier layer facing away from the semiconductor substrate layer. Using the thin film conductive layer as a field plate allows the thin film conductive layer and the SAB barrier layer to be patterned together during the manufacturing process, and the remaining portion is directly used as a field plate to cover the entire surface of the SAB barrier layer, which simplifies the processing technology.
[0010] Optionally, the LDMOS device also includes: a source and a drain, the source and the drain are located in the semiconductor substrate layer, and one side surface of the source and the drain exposes the surface of the semiconductor substrate layer; a gate structure is located between the source and the drain; the gate structure includes a gate conductive layer and side walls on both sides of the gate conductive layer; the SAB barrier layer covers at least part of the gate conductive layer, extends toward the drain side, extends along the side wall to the surface of the semiconductor substrate layer, and continues to extend to the side edge of the drain; a gate lead-out conductive column is located at a portion of the gate conductive layer surface not covered by the SAB barrier layer, penetrates the device dielectric layer, and is connected to the gate lead-out conductive layer on the surface of the device dielectric layer; a source lead-out conductive column is located on the source surface, penetrates the device dielectric layer, and is connected to the source lead-out conductive layer on the surface of the device dielectric layer; a drain lead-out conductive column is located on the drain surface, penetrates the device dielectric layer, and is connected to the drain lead-out conductive layer on the surface of the device dielectric layer.
[0011] In another aspect of the present invention, the present invention also provides a method for forming an LDMOS device, comprising the following steps: providing a semiconductor substrate layer; forming a gate structure on the surface of the semiconductor substrate layer; forming a SAB barrier layer, the SAB barrier layer at least covering a portion of the surface of the gate structure, and extending to one side along the side of the gate structure to the surface of the semiconductor substrate layer, and further extending on the surface of the semiconductor substrate layer; forming a device dielectric layer, the device dielectric layer covering the gate structure and the SAB barrier layer; forming a field plate lead-out conductive layer on the surface of the device dielectric layer on the side facing away from the semiconductor substrate layer; forming a field plate lead-out conductive column in the device dielectric layer, the field plate lead-out conductive column extending from the field plate lead-out conductive layer to the SAB barrier layer and penetrating the device dielectric layer; further comprising: forming a thin film conductive layer as a field plate of the LDMOS device; the thin film conductive layer is formed on the surface of the SAB barrier layer on the side facing away from the semiconductor substrate layer; the formed thin film conductive layer is covered by the device dielectric layer, and in the step of forming the field plate lead-out conductive column, the field plate lead-out conductive column is connected; the area of the thin film conductive layer covering the SAB barrier layer is larger than the area of the projection of the field plate lead-out conductive column on the SAB barrier layer.
[0012] The method for forming an LDMOS device provided by the present invention forms a thin film conductive layer on the surface of the SAB barrier layer facing away from the semiconductor substrate layer as a field plate of the device, providing an electric field to increase the breakdown voltage of the drift region. Compared with using a conductive column as a field plate, the thin film conductive layer can be used as a field plate. Since it can be directly formed as a thin film layer on the surface of the SAB barrier layer during production, any pattern can be formed using a metal etching process. No matter how many shapes are required, the size can be completed in one etching step. The process steps are simple and easy to implement. At the same time, the thin film conductive layer is used as a field plate, so that the balance between the size of the field plate and the resistance value does not need to be limited by the height of the conductive column. It can be relatively free to choose and balance between a larger spreading coverage area and a lower thickness, and the design balance is easier, and there is no need to occupy a larger device volume. In addition, the thickness of the thin film conductive layer can also be designed and adjusted as needed to meet other design requirements. And the corresponding field plate conductive column can be set to a smaller size, and there is no need to occupy a larger device volume.
[0013] Optionally, the step of forming a SAB barrier layer includes: forming an initial SAB barrier layer, the initial SAB barrier layer completely covering the surface of the semiconductor substrate layer and the surface of the gate structure; patterning the initial SAB barrier layer, etching and removing part of the initial SAB barrier layer, the removed part including a part located on the surface of the gate structure, so that part of the gate conductive layer is exposed, and the remaining initial SAB barrier layer forms a SAB barrier layer; the step of forming a thin film conductive layer includes: forming an initial thin film conductive layer on the surface of the unpatterned initial SAB barrier layer; the step of patterning the initial SAB barrier layer is performed after the initial thin film conductive layer is formed; and the initial thin film conductive layer is patterned while the initial SAB barrier layer is patterned.
[0014] In the method for forming an LDMOS device provided by the present invention, since the thin film conductive layer is formed on the surface of the SAB barrier layer, its own patterning can be performed together with the patterning of the SAB barrier layer, saving process steps. Compared with forming the filling holes of field plate conductive columns of different sizes in one step, it is easier to implement and the process steps are simple.
[0015] Optionally, after the step of patterning the initial SAB barrier layer, the step further includes: secondary patterning of the remaining initial thin film conductive layer, removing the initial thin film conductive layer on the surface of the gate structure and a portion of the initial thin film conductive layer on the surface of the SAB barrier layer located on the surface of the semiconductor substrate layer, and forming a thin film conductive layer from the remaining initial thin film conductive layer after the secondary patterning.
[0016] The method for forming an LDMOS device provided by the present invention can control the field plate coverage area to a part of the SAB barrier layer located on the surface of the semiconductor substrate layer through a metal etching step as needed, which is simple to implement.
[0017] Optionally, after the step of patterning the initial SAB barrier layer, the remaining initial thin film conductive layer is used as the thin film conductive layer. In the method for forming an LDMOS device provided by the present invention, the thin film conductive layer covering the entire surface of the SAB barrier layer after the SAB barrier layer is patterned can be used as the field plate, which can save the secondary patterning of the initial thin film conductive layer, further save the process steps, and at the same time, the thickness of the thin film conductive layer used as the field plate can be further reduced.
[0018] Optionally, the method for forming an LDMOS device also includes: forming a source and a drain, the source and the drain are located in the semiconductor substrate layer, and one side surface of the source and the drain exposes the surface of the semiconductor substrate layer; a gate structure is formed between the source and the drain; the gate structure includes a gate conductive layer and side walls on both sides of the gate conductive layer; the SAB barrier layer covers at least a portion of the gate conductive layer, extends toward the drain side, extends along the side wall to the surface of the semiconductor substrate layer, and continues to extend to the side edge of the drain; a gate lead-out conductive column, a source lead-out conductive column and a drain lead-out conductive column are formed; the gate lead-out conductive column is formed on the portion of the gate conductive layer surface not covered by the SAB barrier layer, and penetrates the device dielectric layer and is connected to the gate lead-out conductive layer on the surface of the device dielectric layer; the source lead-out conductive column is formed on the source surface, penetrates the device dielectric layer, and is connected to the source lead-out conductive layer on the surface of the device dielectric layer; the drain lead-out conductive column is formed on the drain surface, penetrates the device dielectric layer, and is connected to the drain lead-out conductive layer on the surface of the device dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0020] Figure 1 A schematic diagram of the structure of an LDMOS device;
[0021] Figure 2 A schematic structural diagram of an LDMOS device according to an embodiment of the present invention;
[0022] Figure 3 It is a schematic diagram of the state when an initial thin film conductive layer is formed in a method for forming an LDMOS device according to an embodiment of the present invention;
[0023] Figure 4 It is a schematic diagram of the state after the initial SAB barrier layer is patterned in the method for forming an LDMOS device according to an embodiment of the present invention;
[0024] Figure 5 It is a schematic diagram of the state after the remaining initial thin film conductive layer is patterned twice in the method for forming an LDMOS device according to an embodiment of the present invention;
[0025] Figure 6 It is a schematic diagram of a state of forming a device dielectric layer in a method for forming an LDMOS device according to an embodiment of the present invention;
[0026] Figure 7 The figure is a schematic diagram of the state of forming each lead-out conductive pillar and the field plate lead-out conductive layer in the method for forming an LDMOS device according to an embodiment of the present invention.
[0027] Description of reference numerals:
[0028] 100-semiconductor substrate layer; 210-source; 220-drain; 230-gate structure; 231-gate conductive layer; 232-side wall; 300-SAB barrier layer; 400-device dielectric layer; 500-thin film conductive layer; 600-field plate metal column; 610-source lead conductive column; 620-drain lead conductive column; 630-gate lead conductive column; 640-field plate lead conductive column; 700-field plate lead conductive layer. DETAILED DESCRIPTION
[0029] refer to Figure 1 , a schematic structural diagram of an LDMOS device, comprising: a semiconductor substrate layer 100; a source electrode 210 and a drain electrode 220, wherein the source electrode 210 and the drain electrode 220 are located in the semiconductor substrate layer 100, and one side surface of the source electrode 210 and the drain electrode 220 exposes the surface of the semiconductor substrate layer 100; a gate structure 230, located on the surface of the semiconductor substrate layer 100 and located between the source electrode 210 and the drain electrode 220; a SAB barrier layer 300, wherein the SAB barrier layer 300 at least covers the gate structure The gate structure 230 is partially formed on the surface of the semiconductor substrate layer 100, and extends to one side along the side of the gate structure 230 to the surface of the semiconductor substrate layer 100, and further extends on the surface of the semiconductor substrate layer 100; a device dielectric layer 400, covering the gate structure 230 and the SAB barrier layer; a field plate lead-out conductive layer 700 located on the surface of the device dielectric layer 400 on the side facing away from the semiconductor substrate layer 100, and a field plate metal column 600 extending from the field plate lead-out conductive layer 700 to the SAB barrier layer 300 and penetrating the device dielectric layer 400.
[0030] In the device, a drift region D is formed in the semiconductor substrate layer 100 between the drain 220 and the gate structure 230. The breakdown voltage of this part is low, so a field plate needs to be arranged above the drift region D to provide an electric field that affects the drift region D, so as to increase the breakdown voltage of this part. Figure 1In the LDMOS device shown, a conductive metal column is arranged above the SAB barrier layer 300 as a field plate, namely, a field plate metal column 600. This structural design can provide the field plate function and improve the breakdown voltage. However, on the one hand, the conductive metal column needs to cover the drift region as much as possible, and on the other hand, it must penetrate the device dielectric layer to connect to the conductive layer above, and a suitable resistance value is required. Therefore, the diameter is relatively large in size, resulting in a large volume occupied by the field plate part. Balancing the resistance and volume of the field plate becomes a cumbersome problem during design. On the other hand, there is usually more than one size of LDMOS device in the entire semiconductor structure, and thus there are also multiple sizes of field plates, and there are also multiple holes filled with corresponding field plate metal columns. Since the same-layer structure is usually prepared synchronously, it is difficult to form holes of different sizes in one step, and multiple steps are required to complete, resulting in cumbersome process steps.
[0031] Based on the above problems, the present invention provides an LDMOS device to solve the problem that the field plate of the LDMOS device is difficult to balance the relationship between resistance and volume, and the processing process is complicated due to the requirements of different sizes of apertures. The LDMOS device provided by the present invention includes: a semiconductor substrate layer; a gate structure, located on the surface of the semiconductor substrate layer; a SAB barrier layer, the SAB barrier layer at least covers a portion of the surface of the gate structure, and extends to one side along the side of the gate structure to the surface of the semiconductor substrate layer, and further extends on the surface of the semiconductor substrate layer; a device dielectric layer, covering the gate structure and the SAB barrier layer; a field plate lead-out conductive layer located on the surface of the device dielectric layer facing away from the semiconductor substrate layer, and a field plate lead-out conductive column extending from the field plate lead-out conductive layer to the SAB barrier layer and penetrating the device dielectric layer; and also includes: a thin film conductive layer, serving as a field plate of the LDMOS device; the thin film conductive layer is located on the surface of the SAB barrier layer facing away from the semiconductor substrate layer, and is connected to the field plate lead-out conductive column, and is covered by the device dielectric layer; the area of the thin film conductive layer covering the SAB barrier layer is larger than the area of the projection of the field plate lead-out conductive column on the SAB barrier layer.
[0032] The present invention also provides a method for forming an LDMOS device to solve the problem that the field plate of the LDMOS device is difficult to balance the relationship between the resistance value and the volume, and the processing process has complicated steps due to the requirements of apertures of different sizes. The method for forming an LDMOS device provided by the present invention comprises the following steps: providing a semiconductor substrate layer; forming a gate structure on the surface of the semiconductor substrate layer; forming a SAB barrier layer, the SAB barrier layer at least covering a part of the surface of the gate structure, and extending to one side along the side of the gate structure to the surface of the semiconductor substrate layer, and further extending on the surface of the semiconductor substrate layer; forming a device dielectric layer, the device dielectric layer covering the gate structure and the SAB barrier layer; forming a field plate lead-out conductive layer on the surface of the device dielectric layer facing away from the semiconductor substrate layer; forming a field plate lead-out conductive column in the device dielectric layer, the field plate lead-out conductive column extending from the field plate lead-out conductive layer to the SAB barrier layer and penetrating the device dielectric layer; and further comprising: forming a thin film conductive layer as a field plate of the LDMOS device; the thin film conductive layer is formed on the surface of the SAB barrier layer facing away from the semiconductor substrate layer; the formed thin film conductive layer is covered by the device dielectric layer, and in the step of forming the field plate lead-out conductive column, the field plate lead-out conductive column is connected; the area of the thin film conductive layer covering the SAB barrier layer is larger than the area of the projection of the field plate lead-out conductive column on the SAB barrier layer.
[0033] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0034] Example 1
[0035] refer to Figure 2 , this embodiment provides an LDMOS device, including:
[0036] Semiconductor substrate layer 100;
[0037] The gate structure 230 is located on the surface of the semiconductor substrate layer 100;
[0038] A SAB barrier layer 300, the SAB barrier layer 300 covers at least a portion of the surface of the gate structure 230, and extends along a side of the gate structure 230 to the surface of the semiconductor substrate layer 100, and further extends on the surface of the semiconductor substrate layer 100;
[0039] A device dielectric layer 400 covering the gate structure 230 and the SAB barrier layer 300;
[0040] A field plate lead-out conductive layer 700 located on the surface of the device dielectric layer 400 facing away from the semiconductor substrate layer 100 and a field plate lead-out conductive column 640 extending from the field plate lead-out conductive layer 700 toward the SAB barrier layer 300 and penetrating the device dielectric layer 400;
[0041] It also includes: a thin film conductive layer 500, which serves as a field plate of the LDMOS device; the thin film conductive layer 500 is located on the surface of the SAB barrier layer 300 on the side facing away from the semiconductor substrate layer 100, and is connected to the field plate lead-out conductive column 640, and is covered by the device dielectric layer 400; the area of the SAB barrier layer 300 covered by the thin film conductive layer 500 is larger than the area of the projection of the field plate lead-out conductive column 640 on the SAB barrier layer 300.
[0042] The LDMOS device provided in this embodiment has a thin film conductive layer 500 disposed on the surface of the SAB barrier layer 300 facing away from the semiconductor substrate layer 100, which can serve as a field plate of the device to provide an electric field to increase the drift region ( Figure 2 Not shown, corresponding Figure 1 The breakdown voltage of the area marked D in the figure). Compared with using a conductive column as a field plate, the thin film conductive layer 500 is used as a field plate. Since it can be directly formed as a thin film layer on the surface of the SAB barrier layer 300 during production, any pattern can be formed using a metal etching process. No matter how many shapes are required, the size can be completed in one etching step, and the process steps are simple. At the same time, the thin film conductive layer 500 is used as a field plate, so that the balance between the size of the field plate and the resistance value is not limited by the height of the conductive column. It can be relatively free to choose and balance between a larger spreading coverage area and a lower thickness, making the design balance easier and without occupying a larger device volume. In addition, the thickness of the thin film conductive layer 500 can also be designed and adjusted as needed to meet other design requirements. And the corresponding field plate lead-out conductive column 640 can be set to a smaller size, and there is no need to occupy a larger device volume.
[0043] Further, in some embodiments of the present invention, the thickness of the SAB barrier layer 300 is 100A to 2000A; the thickness of the thin film conductive layer 500 is 100A to 2000A; and the material of the thin film conductive layer 500 includes metal. The LDMOS device provided in this embodiment can achieve a thickness of the thin film conductive layer 500 of 100A to 2000A, and a thickness of the SAB barrier layer 300 of 100A to 2000A, which occupies less height space and is conducive to reducing the size of the device.
[0044] Furthermore, in some embodiments of the present invention, the thin film conductive layer 500 at least covers a portion of the SAB barrier layer 300 located on the surface of the semiconductor substrate layer 100 (eg Figure 5By using the thin film conductive layer 500 as the field plate, the coverage of the field plate can be controlled to be a portion of the portion of the SAB barrier layer 300 located on the surface of the semiconductor substrate layer by means of graphics, which is simple to implement.
[0045] Furthermore, in some embodiments of the present invention, the thin film conductive layer 500 completely covers the surface of the SAB barrier layer 300 facing away from the semiconductor substrate layer 100 (eg Figure 4 Using the thin film conductive layer 500 as the field plate, the thin film conductive layer 500 and the SAB barrier layer 300 can be patterned together during the manufacturing process, and the remaining portion can be directly used as the field plate to cover the entire surface of the SAB barrier layer 300, and the processing technology is simple.
[0046] Furthermore, the LDMOS device further includes: a source 210 and a drain 220, the source 210 and the drain 220 are located in the semiconductor substrate layer 100, and one side surface of the source 210 and the drain 220 exposes the surface of the semiconductor substrate layer 100; a gate structure 230 is located between the source and the drain; the gate structure includes a gate conductive layer 231 and sidewalls 232 on both sides of the gate conductive layer 231; the SAB barrier layer 300 at least covers a portion of the gate conductive layer 231, extends toward one side of the drain 220, extends along the sidewall 232 to the surface of the semiconductor substrate layer 100, and continues to extend to the side of the drain 220 edge; a gate lead-out conductive column 630, located on the surface of the gate conductive layer 231 not covered by the SAB barrier layer 300, and penetrating the device dielectric layer 400, and connected to the gate lead-out conductive layer (not shown in the figure) on the surface of the device dielectric layer; a source lead-out conductive column 610, located on the surface of the source 210, and penetrating the device dielectric layer 400, and connected to the source lead-out conductive layer (not shown in the figure) on the surface of the device dielectric layer 400; a drain lead-out conductive column 620, located on the surface of the drain 220, and penetrating the device dielectric layer 400, and connected to the drain lead-out conductive layer (not shown in the figure) on the surface of the device dielectric layer 400.
[0047] Example 2
[0048] refer to Figure 3-Figure 7 This embodiment provides a method for forming an LDMOS device, comprising the following steps:
[0049] Providing a semiconductor substrate layer 100; forming a gate structure 230 on a surface of the semiconductor substrate layer 100;
[0050] Forming a SAB barrier layer 300, the SAB barrier layer 300 at least covers a portion of the surface of the gate structure 230, and extends along the side of the gate structure 230 to the surface of the semiconductor substrate layer 100, and further extends on the surface of the semiconductor substrate layer 100;
[0051] Forming a device dielectric layer 400 , wherein the device dielectric layer 400 covers the gate structure 230 and the SAB barrier layer 300 ;
[0052] A field plate lead-out conductive layer 700 is formed on the surface of the device dielectric layer 400 facing away from the semiconductor substrate layer 100;
[0053] A field plate lead-out conductive column 640 is formed in the device dielectric layer 400 , and the field plate lead-out conductive column 640 extends from the field plate lead-out conductive layer to the SAB barrier layer 300 and penetrates the device dielectric layer 400 . In the actual formation process, the field plate lead-out conductive column 640 is formed first, and then the field plate lead-out conductive layer 700 is formed.
[0054] The method also includes: forming a thin film conductive layer 500 as a field plate of the LDMOS device; the thin film conductive layer 500 is formed on the surface of the SAB barrier layer 300 facing away from the semiconductor substrate layer 100; the formed thin film conductive layer 500 is covered by the device dielectric layer 400, and is connected to the field plate lead-out conductive column 640 in the step of forming the field plate lead-out conductive column 640; the area of the SAB barrier layer 300 covered by the thin film conductive layer 500 is larger than the area of the projection of the field plate lead-out conductive column 640 on the SAB barrier layer 300.
[0055] The method for forming the LDMOS device provided in this embodiment forms a thin film conductive layer 500 on the surface of the SAB barrier layer 300 facing away from the semiconductor substrate layer 100, as a field plate of the device, to provide an electric field to increase the breakdown voltage of the drift region. Compared with using a conductive column as a field plate, the thin film conductive layer 500 can be used as a field plate. Since it can be directly formed as a thin film layer on the surface of the SAB barrier layer 300 during production, any pattern can be formed using a metal etching process. No matter how many shapes are required, the size can be completed in one etching step. The process steps are simple and easy to implement. At the same time, the thin film conductive layer 500 is used as a field plate, so that the balance between the size and resistance value of the field plate is not limited by the height of the conductive column, and it can be relatively free to choose and balance between a larger spreading coverage area and a lower thickness, making the design balance easier and without occupying a larger device volume. In addition, the thickness of the thin film conductive layer 500 can also be designed and adjusted as needed to meet other design requirements. And the corresponding field plate lead-out conductive column 640 can be set to a smaller size, and it does not need to occupy a larger device volume.
[0056] For further reference, Figure 3 In some embodiments, the step of forming the SAB barrier layer includes:
[0057] An initial SAB barrier layer 300' is formed, wherein the initial SAB barrier layer 300' completely covers the surface of the semiconductor substrate layer 100 and the surface of the gate structure 230; the initial SAB barrier layer 300' is patterned, and a portion of the initial SAB barrier layer 300' is removed by etching, wherein the removed portion includes a portion located on the surface of the gate structure 230, so that a portion of the gate conductive layer 231 is exposed, and the remaining initial SAB barrier layer 300' forms a SAB barrier layer 300; the step of forming a thin film conductive layer 500 includes: forming an initial thin film conductive layer 500' on the surface of the unpatterned initial SAB barrier layer 300'; the step of patterning the initial SAB barrier layer 300' is performed after the initial thin film conductive layer 500' is formed; and the initial thin film conductive layer 500' is patterned while the initial SAB barrier layer 300' is patterned. Since the thin film conductive layer 500 is formed on the surface of the SAB barrier layer 300, its own patterning can be performed together with the SAB barrier layer patterning, saving process steps. It is easier to implement than forming the filling holes of field plate conductive pillars of different sizes in one step, and the process steps are simple.
[0058] Further, such as Figure 5 As shown, in some embodiments, after the step of patterning the initial SAB barrier layer 300', the process further includes: secondary patterning the remaining initial thin film conductive layer 500', removing the initial thin film conductive layer 500' on the surface of the gate structure 230 and a portion of the initial thin film conductive layer 500' on the surface of the SAB barrier layer 300 located on the surface of the semiconductor substrate layer 100, and the remaining initial thin film conductive layer 500' after the secondary patterning forms a thin film conductive layer 500. The thin film conductive layer 500 used as the field plate can be controlled to cover a portion of the portion of the SAB barrier layer 300 located on the surface of the semiconductor substrate layer through a metal etching step as needed, which is simple to implement.
[0059] Further, such as Figure 4 As shown, in some embodiments, after the step of patterning the initial SAB barrier layer 300', the remaining initial thin film conductive layer 500' is used as a thin film conductive layer. As the thin film conductive layer 500 of the field plate, the remaining thin film conductive layer 500 covering the entire surface of the SAB barrier layer 300 after the SAB barrier layer 300 is patterned can be used as the field plate, which can save the secondary patterning of the initial thin film conductive layer 500', further save the process steps, and at the same time, the thickness of the thin film conductive layer 500 used as the field plate can be further reduced.
[0060] For further reference, Figure 2 , the method for forming the LDMOS device provided in this embodiment further includes:
[0061] A source electrode 210 and a drain electrode 220 are formed, wherein the source electrode 210 and the drain electrode 220 are located in the semiconductor substrate layer 100, and one side surface of the source electrode 210 and the drain electrode 220 exposes the surface of the semiconductor substrate layer 100; a gate structure 230 is formed between the source electrode 210 and the drain electrode 220;
[0062] The gate structure 230 includes a gate conductive layer 231 and sidewalls 232 on both sides of the gate conductive layer 231; the SAB barrier layer 300 covers at least a portion of the gate conductive layer 231, extends toward the drain 220, extends along the sidewalls 232 to the surface of the semiconductor substrate layer 100, and continues to extend to the side edge of the drain 220;
[0063] Afterwards, refer to Figure 6 , forming a device dielectric layer 400 , wherein the device dielectric layer 400 covers the gate structure 230 and the SAB barrier layer 300 ;
[0064] For further reference, Figure 7 , the method for forming the LDMOS device provided in this embodiment further includes:
[0065] Forming a gate lead-out conductive column 630 , a source lead-out conductive column 610 , and a drain lead-out conductive column 620 ;
[0066] The gate lead conductive pillar 630 is formed on the surface of the gate conductive layer 231 which is not covered by the SAB barrier layer 300, and penetrates the device dielectric layer 400, and is connected to the gate lead conductive layer on the surface of the device dielectric layer 400 (not shown in the figure);
[0067] The source lead-out conductive column 610 is formed on the surface of the source 210 and penetrates the device dielectric layer 400 and is connected to the source lead-out conductive layer on the surface of the device dielectric layer 400 (not shown in the figure);
[0068] The drain lead-out conductive pillar 620 is formed on the surface of the drain 220 , penetrates the device dielectric layer 400 , and is connected to the drain lead-out conductive layer on the surface of the device dielectric layer 400 (not shown in the figure).
[0069] Furthermore, a field plate lead-out conductive layer 700 is formed on the surface of the device dielectric layer 400 facing away from the semiconductor substrate layer 100 .
[0070] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.
Claims
1. An LDMOS device, characterized in that: include: Semiconductor substrate layer; A gate structure, located on the surface of the semiconductor substrate layer; A SAB barrier layer, the SAB barrier layer at least covers a portion of the surface of the gate structure, and extends along a side of the gate structure to a surface of the semiconductor substrate layer, and further extends on the surface of the semiconductor substrate layer; A device dielectric layer, wherein the device dielectric layer covers the gate structure and the SAB barrier layer; A field plate lead-out conductive layer located on a surface of the device dielectric layer facing away from the semiconductor substrate layer, and a field plate lead-out conductive column extending from the field plate lead-out conductive layer toward the SAB barrier layer and penetrating the device dielectric layer; Also includes: A thin film conductive layer, serving as a field plate of the LDMOS device; The thin film conductive layer is located on the surface of the SAB barrier layer facing away from the semiconductor substrate layer, is connected to the field plate lead-out conductive column, and is covered by the device dielectric layer; the area of the SAB barrier layer covered by the thin film conductive layer is larger than the projection area of the field plate lead-out conductive column on the SAB barrier layer.
2. The LDMOS device according to claim 1, characterized in that: The thin film conductive layer at least covers a portion of the SAB barrier layer located on the surface of the semiconductor substrate layer.
3. The LDMOS device according to claim 1, characterized in that: The thin film conductive layer completely covers the surface of the SAB barrier layer facing away from the semiconductor substrate layer.
4. The LDMOS device according to claim 1, characterized in that: Also includes: A source electrode and a drain electrode, wherein the source electrode and the drain electrode are located in the semiconductor substrate layer, and one side surface of the source electrode and the drain electrode exposes the surface of the semiconductor substrate layer; The gate structure is located between the source and the drain; the gate structure includes a gate conductive layer and sidewalls on both sides of the gate conductive layer; The SAB barrier layer at least covers a portion of the gate conductive layer, extends toward the drain, extends along the sidewall to the surface of the semiconductor substrate layer, and continues to extend to the side edge of the drain; A gate lead-out conductive column is located at a portion of the surface of the gate conductive layer that is not covered by the SAB barrier layer, penetrates the device dielectric layer, and is connected to the gate lead-out conductive layer on the surface of the device dielectric layer; A source lead-out conductive column is located on the surface of the source electrode, penetrates the device dielectric layer, and is connected to the source lead-out conductive layer on the surface of the device dielectric layer; The drain lead-out conductive column is located on the surface of the drain, penetrates the device dielectric layer, and is connected to the drain lead-out conductive layer on the surface of the device dielectric layer.
5. The LDMOS device according to claim 1, characterized in that: The thickness of the SAB barrier layer is 100A to 2000A; The thickness of the thin film conductive layer is 100A to 2000A; The material of the thin film conductive layer includes metal.
6. A method for forming an LDMOS device, characterized in that: The following steps are involved: providing a semiconductor substrate layer; forming a gate structure on the surface of the semiconductor substrate layer; Forming a SAB barrier layer, wherein the SAB barrier layer at least covers a portion of the surface of the gate structure and extends along a side of the gate structure to a surface of the semiconductor substrate layer and further extends on the surface of the semiconductor substrate layer; forming a device dielectric layer, wherein the device dielectric layer covers the gate structure and the SAB barrier layer; Forming a field plate lead-out conductive layer on a surface of the device dielectric layer facing away from the semiconductor substrate layer; Forming a field plate lead-out conductive column in the device dielectric layer, wherein the field plate lead-out conductive column extends from the field plate lead-out conductive layer to the SAB barrier layer and penetrates the device dielectric layer; Also includes: A thin film conductive layer is formed as a field plate of the LDMOS device; the thin film conductive layer is formed on a surface of the SAB barrier layer facing away from the semiconductor substrate layer; the formed thin film conductive layer is covered by the device dielectric layer, and is connected to the field plate lead-out conductive column in the step of forming the field plate lead-out conductive column; the area of the SAB barrier layer covered by the thin film conductive layer is larger than the area of the projection of the field plate lead-out conductive column on the SAB barrier layer.
7. The method for forming an LDMOS device according to claim 6, characterized in that: The step of forming the SAB barrier layer comprises: forming an initial SAB barrier layer, wherein the initial SAB barrier layer completely covers the surface of the semiconductor substrate layer and the surface of the gate structure; Patterning the initial SAB barrier layer, etching and removing a portion of the initial SAB barrier layer, wherein the removed portion includes a portion located on the surface of the gate structure, so that a portion of the gate conductive layer is exposed, and the remaining initial SAB barrier layer forms the SAB barrier layer; The step of forming a thin film conductive layer comprises: forming an initial thin film conductive layer on the surface of the unpatterned initial SAB barrier layer; The step of patterning the initial SAB barrier layer is performed after forming the initial thin film conductive layer; and the initial thin film conductive layer is patterned while the initial SAB barrier layer is patterned.
8. The method for forming an LDMOS device according to claim 7, characterized in that: After the step of patterning the SAB barrier layer, the method further comprises: The remaining initial thin film conductive layer is patterned for the second time, the initial thin film conductive layer on the surface of the gate structure and part of the initial thin film conductive layer on the surface of the SAB barrier layer on the surface of the semiconductor substrate layer are removed, and the remaining initial thin film conductive layer after the second patterning forms the thin film conductive layer.
9. The method for forming an LDMOS device according to claim 7, characterized in that: After the step of patterning the SAB barrier layer, the remaining initial thin film conductive layer serves as the thin film conductive layer.
10. The method for forming an LDMOS device according to claim 6, wherein: Also includes: forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located in the semiconductor substrate layer, and one side surface of the source electrode and the drain electrode exposes the surface of the semiconductor substrate layer; The gate structure is formed between the source and the drain; the gate structure includes a gate conductive layer and sidewalls on both sides of the gate conductive layer; The SAB barrier layer at least covers a portion of the gate conductive layer, extends toward the drain, extends along the sidewall to the surface of the semiconductor substrate layer, and continues to extend to the side edge of the drain; forming a gate lead-out conductive column, a source lead-out conductive column and a drain lead-out conductive column; The gate lead conductive column is formed on a portion of the surface of the gate conductive layer that is not covered by the SAB barrier layer, penetrates the device dielectric layer, and is connected to the gate lead conductive layer on the surface of the device dielectric layer; A source lead-out conductive column is formed on the surface of the source electrode, penetrates the device dielectric layer, and is connected to the source lead-out conductive layer on the surface of the device dielectric layer; The drain lead-out conductive column is formed on the surface of the drain, penetrates the device dielectric layer, and is connected to the drain lead-out conductive layer on the surface of the device dielectric layer.