Semiconductor device

Abstract

The semiconductor device includes a drain electrode, a base layer, first and second source contacts, first and second gate electrodes, a gate connection structure, and a gate insulating layer. The first and second gate electrodes are located between the first and second source contacts. The gate insulating layer surrounds the first and second gate electrodes and the gate connection structure. The gate insulation layer includes an extension portion between the first and second gate electrodes, and a vertical projection area of the gate connection structure on the substrate layer is smaller than a vertical projection area of the extension portion of the gate insulation layer on the substrate layer. The gate connection structure is located between the first gate electrode and the second gate electrode and is connected with the first gate electrode and the second gate electrode, so that the overlapping area of the gate connection structure and the drain electrode in the vertical direction can be reduced, the capacitance between the gate and the drain is reduced, the switching speed and the stability of the switching process are improved, the layout of the gate electrodes is compact, and the switching efficiency is improved. The channel density per unit area is increased, the current density is increased, and the resistance after conduction is reduced.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Art

[0002] With advancements in semiconductor technology, metal-oxide-semiconductor (MOSFET) field-effect transistors are finding increasingly widespread applications. Power semiconductors can be used as switches in electronic components. They are suitable for high-voltage and high-current device designs. The switching speed and on-resistance of power semiconductors are closely related to the design of their gate structure. Summary of the Invention

[0003] The technical specification disclosed herein is a semiconductor device.

[0004] In one embodiment of this disclosure, a semiconductor device includes a drain electrode, a substrate layer, a first source contact and a second source contact, a first gate electrode and a second gate electrode, a gate connection structure, and a gate insulating layer. The substrate layer is located on the drain electrode. The first source contact and the second source contact are located on the substrate layer. The first gate electrode and the second gate electrode are located on the substrate layer and between the first source contact and the second source contact. The gate connection structure is located between the first gate electrode and the second gate electrode and connects the first gate electrode and the second gate electrode, respectively. The gate insulating layer surrounds the first gate electrode, the second gate electrode, and the gate connection structure, wherein the gate insulating layer includes an extension located between the first gate electrode and the second gate electrode, and the area of ​​the gate connection structure projected vertically onto the substrate layer is smaller than the area of ​​the extension of the gate insulating layer projected vertically onto the substrate layer.

[0005] The technical specification disclosed herein is a semiconductor device.

[0006] In one embodiment of this disclosure, a semiconductor device includes a drain electrode, a substrate layer, a first source contact and a second source contact disposed on the substrate layer, a first gate electrode and a second gate electrode, a gate connection structure, and a dielectric layer. The first gate electrode and the second gate electrode are disposed on the substrate layer and between the first source contact and the second source contact. The gate connection structure is disposed between the first gate electrode and the second gate electrode and connects the first gate electrode and the second gate electrode, respectively. The dielectric layer is disposed between the gate connection structure and the substrate layer. The first gate electrode has a first bottom surface facing the substrate layer, and the gate connection structure has a second bottom surface contacting the dielectric layer. A first distance between the first bottom surface and the upper surface of the substrate layer is less than a second distance between the second bottom surface and the upper surface of the substrate layer.

[0007] In the above embodiments, by connecting adjacent first and second gate electrodes through a gate connection structure, the area of ​​overlap between the gate connection structure and the drain electrode in the vertical direction can be reduced, thereby decreasing the capacitance between the gate and the drain and achieving the technical effect of improving switching speed and the stability of the switching process. Furthermore, this structural design allows for a denser layout of the gate electrodes, increasing the channel density per unit area of ​​the semiconductor device, increasing current density, and reducing resistance after conduction. Attached Figure Description

[0008] Figure 1 This is a perspective view of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 for Figure 1 Top view of a semiconductor device.

[0010] Figure 3 This is a top view of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4A This is a perspective view of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 4B For along Figure 4A Cross-sectional view of the middle segment 4B-4B.

[0013] Figure 5A This is a perspective view of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 5B for Figure 5A Top view of a semiconductor device.

[0015] Figure 6 This is a top view of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 7 This is a perspective view of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0017] Several embodiments of the present invention will be disclosed below with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention.

[0018] Figure 1This is a perspective view of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes a drain electrode 110, a substrate layer 120, a first source contact 130, a second source contact 132, a first gate electrode 140, a second gate electrode 142, a gate connection structure 150, and a gate insulating layer 160, constituting the source S, drain D, and gate G of the semiconductor device 100. The first gate electrode 140 and the second gate electrode 142, which are not connected, are connected through the gate connection structure 150, providing the same voltage.

[0019] A substrate layer 120 is located on the drain electrode 110. A first source contact 130 and a second source contact 132 are located on the substrate layer 120. A first gate electrode 140 and a second gate electrode 142 are located on the substrate layer 120 and between the first source contact 130 and the second source contact 132. A gate connection structure 150 is located between the first gate electrode 140 and the second gate electrode 142. A gate insulating layer 160 surrounds the first gate electrode 140, the second gate electrode 142, and the gate connection structure 150.

[0020] The materials of the first gate electrode 140, the second gate electrode 142, and the gate connection structure 150 may include conductive materials such as polysilicon, tungsten (W), tungsten silicide (WSi), titanium (Ti), titanium nitride (TiN), nickel (Ni), and nickel-silicon alloy (NixSiy).

[0021] For example, the semiconductor device 100 in this embodiment is an N-type (first conductivity type) metal-oxide-semiconductor field-effect transistor. The substrate 120 has the first conductivity type (N-type). The substrate 120 is an N-type heavily doped substrate (N+). The substrate 120 also includes an epitaxial layer, and the doping concentration of the epitaxial layer is lower than the doping concentration of the substrate 120 (N-). The epitaxial layer can serve as a drift region between the source (S) and the drain (D).

[0022] The semiconductor device 100 further includes a doped well region 122, a source doped region 124, and a contact doped region 126. The doped well region 122 is a P-type doped region (second conductivity type), and the source doped region 124 is an N-type doped region. The source doped region 124 and the contact doped region 126 are located within the doped well region 122. The contact doped region 126 is a heavily P-type doped region (P+). The P-type doped well region 122 and the N-type source doped region 124 form a channel region CH.

[0023] Figure 2 for Figure 1The semiconductor device 100 is shown in the top view. The gate insulating layer 160 includes an extension 162 located between the first gate electrode 140 and the second gate electrode 142, that is, the extension 162 fills the space between the first gate electrode 140 and the second gate electrode 142.

[0024] like Figure 1 and Figure 2 As shown, in this embodiment, the first gate electrode 140, the gate connection structure 150, and the second gate electrode 142 are arranged in a first direction D1. The first gate electrode 140 and the second gate electrode 142 extend in a second direction D2, and in this embodiment, the first direction D1 is perpendicular to the second direction D2. The first gate electrode 140 and the second gate electrode 142 have a first length L1 in the second direction D2. The gate connection structure 150 has a second length L2 in the second direction D2. The first length L1 is greater than the second length L2. The area of ​​the vertical projection of the gate connection structure 150 onto the substrate layer 120 is smaller than the area of ​​the vertical projection of the extension 162 of the gate insulating layer 160 onto the substrate layer 120.

[0025] It should be noted that the gate connection structure 150 disclosed herein does not extend from the first gate electrode 140 along the first direction D1 to the region where the second gate electrode 142 is located, but is connected only through the smaller gate connection structure 150. In this way, the area of ​​overlap between the gate connection structure 150 and the drain electrode 110 in the vertical direction D3 can be reduced, the capacitance between the gate G and the drain D can be reduced, and the technical effect of improving the switching speed and the stability of the switching process can be achieved.

[0026] In this embodiment, the first gate electrode 140 and the second gate electrode 142 are elongated strips, and an H-shaped structure is formed by the gate connection structure 150, the first gate electrode 140, and the second gate electrode 142. The second length L2 of the gate connection structure 150 in the second direction D2 is less than the third length L3 of the extension 162 of the gate insulating layer 160 in the second direction D2.

[0027] like Figure 2 As shown, the vertical projection of the gate connection structure 150 onto the drain electrode 110 is approximately located between the vertical projections of the two doped well regions 122 onto the drain electrode 110. In other words, the volume of the gate connection structure 150 can be minimized as much as possible, as long as the area of ​​the first gate electrode 140 and the second gate electrode 142 does not affect the characteristics of the channel region CH.

[0028] The first gate electrode 140 has a first inner wall 1402 and a first outer wall 1404, with the first inner wall 1402 close to the first source contact 130 and the first outer wall 1404 close to the second gate electrode 142. The second gate electrode 142 has a second inner wall 1422 and a second outer wall 1424, with the second inner wall 1422 close to the second source contact 132 and the second outer wall 1424 close to the first gate electrode 140.

[0029] The gate connection structure 150 has a sidewall 152 connected to the first outer wall 1404 and the second outer wall 1424. The gate connection structure 150 is generally rectangular in shape, so the sidewall 152 is perpendicular to the first outer wall 1404 and the second outer wall 1424. In other embodiments, the gate connection structure 150 can be of any shape, such as circular, elliptical, polygonal, or irregular.

[0030] Figure 3 This is a top view of a semiconductor device 100a according to another embodiment of the present disclosure. In a top view, the first gate electrode 140a and the second gate electrode 142a of the semiconductor device 100a laterally surround the first source contact 130a and the second source contact 132a, respectively. Therefore, in a top view, both the first gate electrode 140a and the second gate electrode 142a are hollow annular structures.

[0031] The semiconductor device 100a further includes a third source contact 134a, a fourth source contact 136a, a third gate electrode 144a, and a fourth gate electrode 146a. The third gate electrode 144a surrounds the third source contact 134a, and the fourth gate electrode 146a surrounds the fourth source contact 136a.

[0032] The gate connection structure 150a is located at the corners of the first gate electrode 140a, the second gate electrode 142a, the third gate electrode 144a and the fourth gate electrode 146a, respectively, so as to connect the four gate electrodes simultaneously.

[0033] exist Figure 3 In some embodiments, the shapes of the first gate electrode 140a, the second gate electrode 142a, the third gate electrode 144a, and the fourth gate electrode 146a are the same as or correspond to the shapes of the first source contact 130a, the second source contact 132a, the third source contact 134a, and the fourth source contact 136a, and are square. In some embodiments, they may be other shapes, such as circles, rectangles, rhombuses, triangles, or any equilateral or scalene polygons. In some embodiments, more than four gate electrodes and source contacts may be provided, connected to opposite corners or edges between multiple gate electrodes through two or more gate connection structures.

[0034] In this embodiment, the extension 162a of the gate insulating layer 160a includes a first portion 1622a, a second portion 1624a, a third portion 1626a, and a fourth portion 1628a, which are respectively located between the first gate electrode 140a and the second gate electrode 142a, between the first gate electrode 140a and the third gate electrode 144a, between the second gate electrode 142a and the fourth gate electrode 146a, and between the third gate electrode 144a and the fourth gate electrode 146a.

[0035] In this embodiment, a plurality of gate electrodes are arranged in a first direction D1 and a second direction D2, and each gate electrode includes a segment extending in both directions D1 and D2. For example, the segment of the first gate electrode 140a extending in the first direction D1 has a fourth length L4, and the fourth length L4 is greater than the second length L2 of the gate connection structure 150a. The segment of the first gate electrode 140a extending in the second direction D2 has a fifth length L5, and the fifth length L5 is greater than the second length L2 of the gate connection structure 150a. The third length L3 of the extension 162a of the gate insulating layer 160a is greater than the second length L2 of the gate connection structure 150a.

[0036] With the above structural design, most of the two adjacent gate electrodes are separated by the extension 162a of the gate insulating layer 160a, so that the gate connection structure 150a occupies only a small portion of the volume and area. In this way, the gate electrodes are densely arranged, which can increase the channel density per unit area of ​​the semiconductor device 100a, thereby increasing the current density and reducing the resistance after conduction.

[0037] Figure 4A This is a perspective view of a semiconductor device 200 according to another embodiment of the present disclosure. Figure 4B for Figure 4A Cross-sectional view of midline segment 4B-4B. Semiconductor device 200 and... Figure 1 Similar to the semiconductor device 100, the difference being that the semiconductor device 200 has a dielectric layer 170 located between the substrate layer 120 and the gate connection structure 250, and the dielectric layer 170 is located between the first gate electrode 140 and the second gate electrode 142. The gate connection structure 250 connects the entire first outer wall 1404 of the first gate electrode 140 and the entire second outer wall 1424 of the second gate electrode 142.

[0038] The first gate electrode 140 has a first bottom surface 1406 facing the substrate layer 120, and the gate connection structure 250 has a second bottom surface 2506 contacting the dielectric layer 170. The second gate electrode 142 has a third bottom surface 1426 facing the substrate layer 120. A first distance I1 exists between the first bottom surface 1406 and the upper surface 120S of the substrate layer 120, and a second distance I2 exists between the second bottom surface 2506 and the upper surface 120S of the substrate layer 120. The first distance I1 is less than the second distance I2. In other words, the dielectric layer 170 can increase the distance between the gate connection structure 250 and the substrate layer 120 and the drain electrode 110, thereby reducing the capacitance between the gate G and the drain D, achieving the technical effect of improving switching speed and the stability of the switching process.

[0039] The area of ​​the dielectric layer 170 projected vertically onto the drain electrode 110 is larger than the area of ​​the gate connection structure 250 projected vertically onto the drain electrode 110, or the dielectric layer 170 only needs to raise the gate connection structure 250 along the vertical direction D3. The gate insulating layer 160 surrounds the first gate electrode 140, the second gate electrode 142, the gate connection structure 250, and the dielectric layer 170.

[0040] The dielectric layer 170 may have different length or width ratios with the first gate electrode 140, the second gate electrode 142, and the gate connection structure 250. The thickness and tilt angle of the dielectric layer 170 are also not limited to... Figure 4A The dielectric layer 170 is shown in the diagram. The dielectric layer 170 is made of materials including silicon dioxide (SiO2), undoped silicon glass (USG), boro-silicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), high dielectric constant materials, silicon nitride (SiN), or oxynitride, etc., as insulating materials. The dielectric layer 170 and the gate insulating layer 160 may be made of the same or different materials.

[0041] Figure 5A This is a perspective view of a semiconductor device 300 according to another embodiment of the present disclosure. Figure 5B for Figure 5A A top view of the semiconductor device 300. The semiconductor device 300 and... Figure 4A Similar to semiconductor device 200, the difference being that the gate connection structure 350 of semiconductor device 300 has the same characteristics as... Figure 1The gate connection structure 350 has the same structure as the gate connection structure 150. The second length L2 of the gate connection structure 350 is less than the first length L1 of the first gate electrode 240 and the second gate electrode 242. The second length L2 of the gate connection structure 350 is less than the third length L3 of the extension 362 of the gate insulating layer 360. In this way, the area of ​​overlap between the gate connection structure 350 and the drain electrode 110 in the vertical direction D3 can be reduced, the capacitance between the gate G and the drain D can be reduced, and the technical effect of improving the switching speed and the stability of the switching process can be achieved.

[0042] A portion of the upper surface 172 of the dielectric layer 170 is exposed from the gate connection structure 350. The extension 362 is collectively surrounded by the first outer wall 2404, the second outer wall 2424, the upper surface 172, and the sidewall 352. The structural relationship between the dielectric layer 170 and the gate connection structure 350 is... Figure 4B The same as shown in the diagram. Therefore, the dielectric layer 170 allows the gate connection structure 350 to be further away from the substrate layer 120 and the drain electrode 110, thereby reducing the capacitance between the gate G and the drain D, achieving the technical effect of improving the switching speed and the stability of the switching process.

[0043] Figure 6 This is a top view of a semiconductor device 300a according to an embodiment of the present disclosure. Semiconductor device 300a and... Figure 3 Similar to semiconductor device 100a, the difference being that semiconductor device 300a also includes, Figure 5A The dielectric layer 170 is shown. Figure 6 When the four gate electrodes are arranged in a repeating pattern, it is equivalent to the dielectric layer 170 surrounding the first gate electrode 140a, the second gate electrode 142a, the third gate electrode 144a, and the fourth gate electrode 146a. The semiconductor device 300a has... Figure 3 Semiconductor device 100a and Figure 5A The same technical effects as the semiconductor device 300 will not be elaborated here.

[0044] Figure 7 This is a perspective view of a semiconductor device 400 according to an embodiment of the present disclosure. Semiconductor device 400 and... Figure 1 The semiconductor device 400 is substantially the same as the semiconductor device 100, except that it further includes a dielectric layer 270 located between the gate connection structure 150 and the substrate layer 120. The area of ​​the dielectric layer 270 projected vertically onto the drain electrode 110 is approximately equal to the area of ​​the gate connection structure 150 projected vertically onto the drain electrode 110. The dielectric layer 270 described above can also be applied to, for example... Figure 6 In this embodiment, it means that the dielectric layer 170 can simply raise the gate connection structure 150 along the vertical direction D3.

[0045] In summary, this disclosure connects a first gate electrode and a second gate electrode that are spaced apart by a gate connection structure. Furthermore, the area of ​​the vertical projection of the gate connection structure onto the substrate is smaller than the area of ​​the vertical projection of the extension of the gate insulating layer onto the substrate. In other words, the first and second gate electrodes are connected only by a smaller gate connection structure, which reduces the area of ​​vertical overlap between the gate connection structure and the drain electrode, lowers the capacitance between the gate and drain, and achieves the technical effect of improving switching speed and the stability of the switching process. In addition, this structural design allows for a denser arrangement of the gate electrodes, increasing the channel density per unit area of ​​the semiconductor device, increasing the current density, and reducing the resistance after conduction. In some embodiments, the dielectric layer located between the gate connection structure and the substrate can increase the distance between the gate connection structure and the substrate and the drain electrode, thereby reducing the capacitance between the gate and drain and achieving the technical effect of improving switching speed and the stability of the switching process.

[0046] [Symbol Explanation]

[0047] 100, 100a, 200, 300, 300a, 400: Semiconductor devices

[0048] 110: Drain electrode

[0049] 120: Basal layer

[0050] 120S: Top surface

[0051] 122: Doped well region

[0052] 124: Source doped region

[0053] 126: Contact Doped Region

[0054] 130, 130a: First source contact

[0055] 132, 132a: Second source contact

[0056] 134a: Third source electrode contact

[0057] 136a: Fourth source contact

[0058] 140, 140a, 240: First gate electrode

[0059] 1402: First inner wall

[0060] 1404, 2404: First outer wall

[0061] 1406: First base

[0062] 142, 142a, 242: Second gate electrode

[0063] 1422: Second inner wall

[0064] 1424, 2424: Second outer wall

[0065] 1426: Third base

[0066] 144a: Third gate electrode

[0067] 146a: Fourth gate electrode

[0068] 150, 150a, 250, 350: Gate connection structure

[0069] 152,352: Sidewall

[0070] 2506: Second bottom surface

[0071] 160, 160a, 360: Gate insulating layer

[0072] 162, 162a, 362: Extension

[0073] 1622, 1622a: Part I

[0074] 1624, 1624a: Part Two

[0075] 1626a: Part Three

[0076] 1628a: Part Four

[0077] 170, 270: Dielectric layer

[0078] 172: Upper surface

[0079] D1: First Direction

[0080] D2: Second Direction

[0081] D3: vertical direction

[0082] L1: First length

[0083] L2: Second length

[0084] L3: Third Length

[0085] L4: Fourth Length

[0086] L5: Fifth Length

[0087] I1: First distance

[0088] I2: Second distance

[0089] S: Source

[0090] D: Drain electrode

[0091] G: Gate

[0092] CH: Passage Area

[0093] 4B-4B: Line segment.

Claims

1. A semiconductor device, characterized in that: Include: drain electrode; A base layer, located on the drain electrode; A first source contact and a second source contact are located on the base layer; A first gate electrode and a second gate electrode are located on the base layer and between the first source contact and the second source contact; A gate connection structure, located between the first gate electrode and the second gate electrode and respectively connecting the first gate electrode and the second gate electrode; as well as A gate insulating layer surrounds the first gate electrode, the second gate electrode and the gate connection structure, wherein the gate insulating layer includes an extension portion located between the first gate electrode and the second gate electrode, and the area of ​​the vertical projection of the gate connection structure on the base layer is smaller than the area of ​​the vertical projection of the extension portion of the gate insulating layer on the base layer.

2. The semiconductor device according to claim 1, wherein: The first gate electrode, the gate connection structure and the second gate electrode are arranged in a first direction, the first gate electrode and the second gate electrode extend in a second direction, and the first length of the first gate electrode and the second gate electrode in the second direction is greater than the second length of the gate connection structure in the second direction.

3. The semiconductor device according to claim 2, wherein: The first gate electrode and the second gate electrode are in the shape of long strips, and a second length of the gate connection structure in the second direction is smaller than a third length of the extension portion of the gate insulation layer in the second direction.

4. The semiconductor device according to claim 1, wherein: The first gate electrode and the second gate electrode respectively surround the first source electrode and contact the second source electrode laterally.

5. The semiconductor device according to claim 1, wherein: Also includes: The dielectric layer is located between the base layer and the gate connection structure, and between the first gate electrode and the second gate electrode.

6. A semiconductor device, characterized in that: Include: drain electrode; A base layer, located on the drain electrode, wherein the base layer has an upper surface; A first source contact and a second source contact are located on the base layer; A first gate electrode and a second gate electrode are located on the base layer and between the first source contact and the second source contact; A gate connection structure, located between the first gate electrode and the second gate electrode and respectively connecting the first gate electrode and the second gate electrode; as well as A dielectric layer is located between the gate connection structure and the base layer, wherein the first gate electrode has a first bottom surface facing the base layer, the gate connection structure has a second bottom surface contacting the dielectric layer, and a first distance between the first bottom surface and the upper surface of the base layer is smaller than a second distance between the second bottom surface and the upper surface of the base layer.

7. The semiconductor device according to claim 6, wherein: The area of ​​the vertical projection of the dielectric layer on the drain electrode is larger than the area of ​​the vertical projection of the gate connection structure on the drain electrode.

8. The semiconductor device according to claim 6, wherein: The area of ​​the vertical projection of the dielectric layer on the drain electrode is equal to the area of ​​the vertical projection of the gate connection structure on the drain electrode.

9. The semiconductor device according to claim 6, wherein: The invention also comprises a gate insulating layer surrounding the first gate electrode, the second gate electrode, the gate connecting structure and the dielectric layer.

10. The semiconductor device according to claim 6, wherein: The first gate electrode and the second gate electrode laterally surround the first source contact and the second source contact respectively, and the dielectric layer laterally surrounds the first gate electrode and the second gate electrode.

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