Novel separation gate SiC MOSFET device with semi-super junction structure and preparation method of novel separation gate SiC MOSFET device

Abstract

The invention discloses a novel separation gate SiC MOSFET device with a semi-super junction structure and a preparation method of the novel separation gate SiC MOSFET device, and relates to the semiconductor technology. The epitaxial layer and the substrate are arranged in a stacked mode, a plurality of P well regions are arranged in the epitaxial layer in the first direction, and the P well regions are located on the side, away from the substrate, of the epitaxial layer; n + column regions are further arranged in the epitaxial layer, the N + column regions are located on the side, away from the substrate, of the epitaxial layer, and the N + column regions are located among the P well regions in the first direction and are arranged at intervals; a P + column region is also arranged in the epitaxial layer, and the P + column region is positioned on one side, close to the substrate, of the P well region; wherein the P + column region and the N + column region are arranged at intervals with the substrate. According to the invention, the performance of the SiC MOSFET device can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a novel separated-gate SiC MOSFET device with a semi-superjunction structure and a preparation method thereof. Background Art

[0002] SiC MOSFET has been commercialized and has a considerable number of high-frequency switching application scenarios. Due to structural differences, planar SiC MOSFET has a poorer HF-FOM (high-frequency figure of merit) than trench SiC MOSFET, making planar SiC MOSFET not advantageous in high-frequency applications.

[0003] The gate oxide preparation process of SiC MOSFET is thermal oxidation to form silicon dioxide. This process will produce carbon-containing byproduct defects and traps formed by structural defects at the interface such as dangling bonds and lattice mismatch. Such traps will lead to problems such as unstable threshold voltage and large gate leakage current. Such defects will also cause gate oxide reliability problems. For example, under long-term HTGB (high temperature gate reverse bias) assessment, gate breakdown will eventually occur, causing device failure. In order to reduce the on-resistance, a current enhancement layer is usually introduced in the JFET (Junction Field Effect Transistor) region below the gate, which will further aggravate the gate oxide reliability failure problem.

[0004] At present, the trend of improving the static and dynamic capabilities of devices by continuously reducing the specific on-resistance often sacrifices the short-circuit capability of the device, and it is difficult to give a compromise between the two. For example, SDG MOSFET (Split Dummy Gate Metal Oxide Semiconductor Field Effect Transistor), although it reduces the dynamic loss in high-frequency application scenarios, sacrifices the on-resistance and gate oxide layer reliability; on the one hand, when SDG MOSFET is subjected to a higher voltage, the edge of the separated gate will be subjected to a higher electric field, and under long-term gate stress, the gate oxide layer may degrade, causing device failure; on the other hand, since the JFET region of SDG MOSFET is a virtual gate, the threshold voltage of the device increases, resulting in an increase in the on-resistance of the device, and a lower specific on-resistance. Therefore, it is urgent to provide a new type of split-gate SiC MOSFET device to improve the above defects. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a novel split-gate SiC MOSFET device with a semi-superjunction structure and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a novel split-gate SiC MOSFET device having a semi-superjunction structure, comprising:

[0007] substrate;

[0008] An epitaxial layer is stacked with a substrate, and a plurality of P-well regions are arranged in the epitaxial layer along a first direction, and the P-well region is located on a side of the epitaxial layer away from the substrate; an N+ column region is also arranged in the epitaxial layer, and the N+ column region is located on a side of the epitaxial layer away from the substrate, and along the first direction, the N+ column region is located between the plurality of P-well regions and is arranged at intervals; a P+ column region is also arranged in the epitaxial layer, and the P+ column region is located on a side of the P-well region close to the substrate; wherein both the P+ column region and the N+ column region are arranged at intervals from the substrate;

[0009] The first direction is perpendicular to the thickness direction of the substrate.

[0010] In a second aspect, the present invention further provides a method for preparing a novel split-gate SiC MOSFET device having a semi-superjunction structure, which is used to prepare the novel split-gate SiC MOSFET device having a semi-superjunction structure provided above, comprising:

[0011] providing a substrate;

[0012] Growing an epitaxial layer on a substrate; using a first hard mask plate and an ion implantation process to form a plurality of P-well regions in the epitaxial layer along a first direction; using a second hard mask plate and a high-energy ion implantation process to form a P+ column region on a side of the P-well region close to the substrate; using a third hard mask plate and an ion implantation process to form an N+ column region in the epitaxial layer; wherein the P+ column region and the N+ column region are both spaced apart from the substrate;

[0013] The first direction is perpendicular to the thickness direction of the substrate.

[0014] Beneficial effects of the present invention:

[0015] The present invention provides a novel separated-gate SiC MOSFET device with a semi-superjunction structure and a preparation method thereof, comprising a substrate and an epitaxial layer arranged on the substrate, the epitaxial layer being a drift region, P-well regions being arranged on both sides of the epitaxial layer along a first direction, a P+ column region being arranged below the P-well region, an N+ column region being arranged between the P-well regions, the N+ column region being located in the middle region of the epitaxial layer along the first direction, the P+ column region and the N+ column region being spaced apart from the substrate, the P+ column region extending deeply from the lower surface of the P-well region into the epitaxial layer; in this way, the P+ column region and the N+ column region form a semi-superjunction structure, so that a relatively ideal breakdown voltage can be obtained with a relatively thin epitaxial layer thickness, thereby reducing the on-resistance; in addition, due to the relatively deep injection of the P+ column region, under a short-circuit condition, the electric field distribution of the device is far away from the surface of the device, the probability of hot carrier injection into the oxide layer is greatly reduced, the gate oxide can be well protected from degradation, thereby improving the short-circuit capability of the device.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a schematic diagram of a novel split-gate SiC MOSFET device with a semi-superjunction structure provided by an embodiment of the present invention;

[0018] Figure 2 It is a flow chart of a method for preparing a novel split-gate SiC MOSFET device with a semi-superjunction structure provided by an embodiment of the present invention;

[0019] Figures 3a to 3k It is a schematic diagram of a method for preparing a novel split-gate SiC MOSFET device with a semi-superjunction structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0021] See also Figure 1 , Figure 1 1 is a schematic diagram of a novel split-gate SiC MOSFET device with a semi-superjunction structure provided by an embodiment of the present invention. The novel split-gate SiC MOSFET device with a semi-superjunction structure provided by the present invention comprises:

[0022] substrate;

[0023] An epitaxial layer is stacked with a substrate, and a plurality of P-well regions are arranged in the epitaxial layer along a first direction, and the P-well region is located on a side of the epitaxial layer away from the substrate; an N+ column region is also arranged in the epitaxial layer, and the N+ column region is located on a side of the epitaxial layer away from the substrate, and along the first direction, the N+ column region is located between the plurality of P-well regions and is arranged at intervals; a P+ column region is also arranged in the epitaxial layer, and the P+ column region is located on a side of the P-well region close to the substrate; wherein both the P+ column region and the N+ column region are arranged at intervals from the substrate;

[0024] The first direction is perpendicular to the thickness direction of the substrate.

[0025] For more details, please see Figure 1 The novel separated-gate SiCMOSFET device with a semi-superjunction structure provided in the present embodiment includes a substrate and an epitaxial layer arranged on the substrate, the epitaxial layer is a drift region, P-well regions are arranged on both sides of the epitaxial layer along a first direction, a P+ column region is arranged below the P-well region, and an N+ column region is arranged between the P-well regions. Along the first direction, the N+ column region is located in the middle area of ​​the epitaxial layer, the P+ column region and the N+ column region are both spaced apart from the substrate, and the P+ column region extends deeply from the lower surface of the P-well region into the epitaxial layer; in this way, the P+ column region and the N+ column region form a semi-superjunction structure, so that a relatively ideal breakdown voltage can be obtained with a relatively thin epitaxial layer thickness, thereby reducing the on-resistance; in addition, due to the deeper injection of the P+ column region, under the short-circuit condition, the electric field distribution of the device is far away from the surface of the device, and the probability of hot carrier injection into the oxide layer is greatly reduced, which can better protect the gate oxide from degradation, thereby improving the short-circuit capability of the device.

[0026] It should be noted that the distance between the P+ column region and the N+ column region and the lower surface of the epitaxial layer is 2 to 10 μm.

[0027] It should be noted that Figure 1 The illustrated embodiment only schematically shows the positional relationship between the P+ column region and the N+ column region, and does not represent their actual sizes.

[0028] In an optional embodiment of the present invention, please continue to refer to Figure 1 , further comprising: a plurality of polysilicon gates and auxiliary polysilicon gates;

[0029] Along the first direction, the auxiliary polysilicon gate is located between multiple polysilicon gates, a first gate dielectric layer is arranged between the lower surface of the polysilicon gate and the epitaxial layer, and a second gate dielectric layer is arranged between the lower surface of the auxiliary polysilicon gate and the epitaxial layer; wherein the thickness of the first gate dielectric layer is different from the thickness of the second gate dielectric layer.

[0030] For more details, please see Figure 1In this embodiment, a gate dielectric layer is arranged on the upper surface of the epitaxial layer, and two polysilicon gates and an auxiliary polysilicon gate are arranged on the upper surface of the gate dielectric layer. The two polysilicon gates are respectively located on both sides of the gate dielectric layer along the first direction, and the auxiliary polysilicon gate is located between the two polysilicon gates. The gate dielectric layer located on the lower surface of the polysilicon gate is a first gate dielectric layer, and the gate dielectric layer located on the lower surface of the auxiliary polysilicon gate is a second gate dielectric layer. The thickness of the first gate dielectric layer is different from the thickness of the second gate dielectric layer.

[0031] It should be noted that Figure 1 The illustrated embodiment only schematically shows the positional relationship between the polysilicon gate and the auxiliary polysilicon gate, and the thickness of the first gate dielectric layer and the second gate dielectric layer, and does not represent their actual sizes.

[0032] In an optional embodiment of the present invention, please continue to refer to Figure 1 , an N+ source region and a P+ region are provided in the P-well region, and the N+ source region and the P+ region are located on a side of the P-well region away from the substrate, and the N+ source region and the P+ region are arranged in parallel and in contact along a first direction;

[0033] Along the second direction, the orthographic projection of part of the P-well region is located within the range of the orthographic projection of the polysilicon gate, and the orthographic projection of the polysilicon gate overlaps with the orthographic projection of part of the N+ source region and the orthographic projection of part of the epitaxial layer;

[0034] Along the second direction, the orthographic projection of the auxiliary polysilicon gate is located within the range of the orthographic projection of the N+ column region;

[0035] The second direction intersects with the first direction. Optionally, the second direction is perpendicular to the first direction.

[0036] For more details, please see Figure 1 In this embodiment, an N+ source region and a P+ region are provided in the P-well region, the P+ region is located on a side of the P-well region away from the N+ column region, the N+ source region is connected to the P+ region and arranged in parallel, no other film layer is provided on the upper surface of the P-well region close to the N+ column region, a portion of the upper surface is exposed, and the orthographic projection of the P-well region that exposes a portion of the upper surface is located within the range of the orthographic projection of the polysilicon gate, and the orthographic projection of the polysilicon gate overlaps with the orthographic projection of a portion of the N+ source region and the orthographic projection of a portion of the epitaxial layer, and the orthographic projection of the auxiliary polysilicon gate is located within the range of the orthographic projection of the N+ column region.

[0037] It should be noted that Figure 1 The illustrated embodiment only schematically shows the positional relationship among the N+ source region, the P+ region, the polysilicon gate, and the auxiliary polysilicon gate, and does not represent their actual sizes.

[0038] In an optional embodiment of the present invention, the thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer.

[0039] Specifically, in this embodiment, the second gate dielectric layer is used as a gate thick dielectric layer and is disposed on the lower surface of the auxiliary polysilicon gate. The introduction of the gate thick dielectric layer can increase the barrier height between silicon carbide and the gate, thereby reducing the tunneling current. Figure 1 As shown in the figure, the increase in the thickness of this area can reduce the gate oxide capacitance Cox = Cox1 + Cox2 + Cox3, so it has a lower Crss (reverse transfer capacitance) and lower switching loss. At the same time, due to the reduction of gate oxide capacitance, the transconductance of the device is also reduced, the saturation current is reduced, and when the area of ​​the active area of ​​the device remains unchanged, the short circuit time that the device can withstand is also increased.

[0040] In an optional embodiment of the present invention, along the second direction, the thickness of the first gate dielectric layer is 20-80 nm, and the thickness of the second gate dielectric layer is 40-200 nm.

[0041] Optionally, the thickness of the first gate dielectric layer is 40 nm, and the thickness of the second gate dielectric layer is 100 nm.

[0042] In an optional embodiment of the present invention, please continue to refer to Figure 1 The upper surface and side surfaces of the polysilicon gate are covered with a first interlayer dielectric layer, the upper surface and side surfaces of the auxiliary polysilicon gate are covered with a second interlayer dielectric layer, the first interlayer dielectric layer and the second interlayer dielectric layer are spaced apart to form a groove, and a source field plate structure is arranged in the groove.

[0043] For more details, please see Figure 1 In this embodiment, the upper surface and side surfaces of the polysilicon gate are covered with a first interlayer dielectric layer, the upper surface and side surfaces of the auxiliary polysilicon gate are covered with a second interlayer dielectric layer, the first interlayer dielectric layer on the side surface of the polysilicon gate and the first interlayer dielectric layer on the side surface of the auxiliary polysilicon gate are spaced apart to form a groove, and a source field plate structure is arranged in the groove; in this way, introducing a source field plate structure between the separation gates can better alleviate the problem of a high electric field at the edge of the separation gate and enhance the reliability of the gate oxide layer.

[0044] It should be noted that the width and number of the source field plate structures can be determined according to actual conditions, and the first interlayer dielectric layer and the second interlayer dielectric layer play an insulating role.

[0045] It should be noted that Figure 1 The illustrated embodiment only schematically shows the location of the source field plate structure and does not represent its actual size.

[0046] In an optional embodiment of the present invention, please continue to refer to Figure 1, also including: a source electrode, the source electrode covers the upper surface of the source field plate structure, and covers the surface of the first interlayer dielectric layer and the second interlayer dielectric layer; wherein the source electrode and the source field plate structure are prepared at the same time.

[0047] For more details, please see Figure 1 The novel separated-gate SiCMOSFET device with a semi-superjunction structure provided in this embodiment also includes a source, which covers the upper surface of the source field plate structure, as well as the surfaces of the first interlayer dielectric layer, the second interlayer dielectric layer, the P+ region and part of the upper surface of the N+ source region, and the source and source field plate structures are prepared at the same time, thus saving manufacturing processes.

[0048] It should be noted that Figure 1 The illustrated embodiment only schematically shows the location of the source electrode and does not represent its actual size.

[0049] Based on the same inventive concept, see Figure 2 , Figure 2 The present invention further provides a method for preparing a novel split-gate SiC MOSFET device with a semi-super junction structure, which is used to prepare the novel split-gate SiC MOSFET device with a semi-super junction structure provided by the above embodiment of the present invention. The embodiment of the device is referred to above and will not be repeated here. The preparation method comprises:

[0050] S101, providing a substrate;

[0051] S102, growing an epitaxial layer on a substrate; using a first hard mask plate and an ion implantation process to form a plurality of P-well regions in the epitaxial layer along a first direction; using a second hard mask plate and a high-energy ion implantation process to form a P+ column region on a side of the P-well region close to the substrate; using a third hard mask plate and an ion implantation process to form an N+ column region in the epitaxial layer; wherein the P+ column region and the N+ column region are both spaced apart from the substrate;

[0052] The first direction is perpendicular to the thickness direction of the substrate.

[0053] In an optional embodiment of the present invention, it also includes:

[0054] On the upper surface of the epitaxial layer, an oxide is generated by a thermal oxidation process to form a gate dielectric layer, and on both sides of the gate dielectric layer along the first direction, a mask plate and an etching process are used to etch away part of the gate dielectric layer to form a first gate dielectric layer, and the gate dielectric layer that is not etched forms a second gate dielectric layer;

[0055] Polysilicon is deposited on the first gate dielectric layer to form a polysilicon gate, and polysilicon is deposited on the second gate dielectric layer to form an auxiliary polysilicon gate.

[0056] In an optional embodiment of the present invention, it also includes:

[0057] Depositing a dielectric layer on the upper surface and side of the polysilicon gate to form a first interlayer dielectric layer, and depositing a dielectric layer on the upper surface and side of the auxiliary polysilicon gate to form a second interlayer dielectric layer; the first interlayer dielectric layer and the second interlayer dielectric layer are spaced apart to form a groove;

[0058] Metal is deposited on the surface of the first interlayer dielectric layer, the surface of the second interlayer dielectric layer and in the groove to form a source electrode.

[0059] In an optional embodiment of the present invention, the preparation of a novel split-gate SiC MOSFET device having a semi-superjunction structure is achieved by the following process, specifically:

[0060] S1. Grow an epitaxial layer on an N+ substrate, i.e., an N-drift region, such as Figure 3a shown.

[0061] Specifically, the substrate is heavily doped with a doping concentration of 1×10 18 ~6×10 20 , the N-drift region is lightly doped with a doping concentration of 1×10 14 ~1×10 17 .

[0062] S2, using a hard mask SiO2, using an ion implantation process in the N-drift region, implanting Al ions to form a P-well region, such as Figure 3b shown.

[0063] Specifically, the P-well region is lightly doped with a doping concentration of 8×10 15 ~1×10 18 .

[0064] S3, using a hard mask SiO2, high energy ion implantation process in the N-drift region, implanting Al ions to form a P+ column region, such as Figure 3c shown.

[0065] Specifically, the doping concentration of the P+ column region is higher than that of the P+ region, and the doping concentration is 1×10 17 ~1×10 20 .

[0066] S4, using the same hard mask SiO2 implanted in the P+ column area, an ion implantation process is used in the P well area to implant N ions to form an N+ source area, such as Figure 3d shown.

[0067] Specifically, the doping concentration of the N+ source region is lower than the doping concentration of the N+ substrate, and the doping concentration is 1×10 17 ~1×10 20 .

[0068] S5, using a hard mask SiO2, using an ion implantation process in the N+ source region, implanting Al ions to form a P+ region, such as Figure 3e shown.

[0069] Specifically, the P+ region is heavily doped with a doping concentration of 1×10 16 ~1×10 19 .

[0070] S6, using a hard mask SiO2, an ion implantation process is used in the N-drift region to implant N ions to form an N+ column region, such as Figure 3f shown.

[0071] Specifically, the doping concentration of the N+ column region is slightly lower than that of the N+ source region, and the doping concentration is 5×10 16 ~5×10 19 .

[0072] S7, on the surface of silicon carbide, an oxide is grown by a thermal oxidation process to form a gate dielectric layer with a thickness of 50 to 100 nm, such as Figure 3g shown.

[0073] S8, performing an etching process on the basis of the thick gate dielectric layer through a mask to obtain a 30-50 nm thin gate dielectric layer, i.e., the first gate dielectric layer, and the unetched area is the second gate dielectric layer, such as Figure 3h shown.

[0074] S9, using a deposition process to deposit polysilicon on the gate oxide, and forming a 100-300nm polysilicon gate and an auxiliary polysilicon gate through an etching process, such as Figure 3i shown.

[0075] S10, depositing an interlayer dielectric ILD of 300nm to 1000nm on the polysilicon gate and the auxiliary polysilicon gate and on both sides thereof through a deposition process, and forming a source contact hole and a source field plate contact hole through an etching process, such as Figure 3j shown.

[0076] S11, after the ohmic contact process at 1200±100℃ for 3-5 minutes, metal is deposited on the N+ source region, P+ region, and ILD to form a metal source and source field plate, and metal is deposited at the bottom of the device to form a drain. The thickness of the metal source and metal drain is 3-10um. Figure 3k shown.

[0077] In an optional embodiment of the present invention, please refer to Table 1, which shows the size parameters of each film layer of the device.

[0078] Table 1 Device size parameters

[0079] Structural parameters Depth / um Width / um <![CDATA[Doping concentration / cm -3 > Cell pitch / 3～10 / Substrate 100-1000 / <![CDATA[1×10 18 ~6×10 20 ]]> Epitaxial layer 5-25 / <![CDATA[1×10 14 ~1×10 17 ]]> P-well 0.5～3 1～5 <![CDATA[8×10 15 ~1×10 18 ]]> N+ source region 0.3～2 0.5～4 <![CDATA[1×10 17 ~1×10 20 ]]> P+ column area 3～20 0.5～4 <![CDATA[1×10 17 ~1×10 20 ]]> P+ Zone 0.4～2.5 0.3～1.2 <![CDATA[1×10 16 ~1×10 19 ]]> N+ column area 3～20 0.6～3 <![CDATA[5×10 16 ~5×10 18 ]]>

[0080] The novel split-gate SiC MOSFET device with a semi-superjunction structure and the preparation method thereof proposed in the present invention have the following beneficial effects:

[0081] 1. By introducing the N+ column area, adding a current enhancement layer (N+ column area), and setting a thick gate dielectric layer, the barrier height between the oxide layer and SiC is increased to reduce the tunneling current and enhance the reliability of the gate oxide layer.

[0082] 2. By introducing a thick gate dielectric layer, the thickness of the oxide layer is increased, which reduces the gate oxide capacitance above the N+ column region to reduce the saturation current of the device, thereby improving the short-circuit withstand time.

[0083] 3. Adding a field plate structure between the separated gates can reduce the electric field of the gate and improve the reliability of the gate oxide.

[0084] 4. By introducing P+ column area and N+ column area, a semi-super junction structure is formed. The semi-super junction structure increases the breakdown voltage of the device, thereby reducing the thickness of the epitaxial layer and obtaining a lower on-resistance. This structure makes the electric field distribution away from the device surface, which can prevent gate oxide degradation, thereby further improving the short-circuit tolerance of the device.

[0085] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0086] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0087] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A novel split-gate SiC MOSFET device with a semi-superjunction structure, characterized in that: include: substrate; An epitaxial layer is stacked with the substrate, and along a first direction, a plurality of P-well regions are arranged in the epitaxial layer, and the P-well region is located on a side of the epitaxial layer away from the substrate; an N+ column region is also arranged in the epitaxial layer, and the N+ column region is located on a side of the epitaxial layer away from the substrate, and along the first direction, the N+ column region is located between the plurality of P-well regions and is arranged at intervals; a P+ column region is also arranged in the epitaxial layer, and the P+ column region is located on a side of the P-well region close to the substrate; wherein the P+ column region and the N+ column region are both arranged at intervals from the substrate; The first direction is perpendicular to the thickness direction of the substrate.

2. The novel split-gate SiC MOSFET device with a semi-superjunction structure according to claim 1, characterized in that: Also includes: A plurality of polysilicon gates and an auxiliary polysilicon gate; Along the first direction, the auxiliary polysilicon gate is located between the multiple polysilicon gates, a first gate dielectric layer is arranged between the lower surface of the polysilicon gate and the epitaxial layer, and a second gate dielectric layer is arranged between the lower surface of the auxiliary polysilicon gate and the epitaxial layer; wherein the thickness of the first gate dielectric layer is different from the thickness of the second gate dielectric layer.

3. The novel split-gate SiC MOSFET device with a semi-superjunction structure according to claim 2, characterized in that: An N+ source region and a P+ region are provided in the P-well region, and the N+ source region and the P+ region are located on a side of the P-well region away from the substrate, and the N+ source region and the P+ region are arranged in parallel and in contact along a first direction; Along the second direction, the orthographic projection of part of the P-well region is located within the range of the orthographic projection of the polysilicon gate, and the orthographic projection of the polysilicon gate overlaps with the orthographic projection of part of the N+ source region and the orthographic projection of part of the epitaxial layer; Along the second direction, the orthographic projection of the auxiliary polysilicon gate is located within the range of the orthographic projection of the N+ column region; The second direction intersects with the first direction.

4. The novel split-gate SiC MOSFET device with a semi-superjunction structure according to claim 2, characterized in that: The thickness of the first gate dielectric layer is smaller than the thickness of the second gate dielectric layer.

5. The novel split-gate SiC MOSFET device with a semi-superjunction structure according to claim 4, characterized in that: Along the second direction, the thickness of the first gate dielectric layer is 20-80 nm, and the thickness of the second gate dielectric layer is 40-200 nm.

6. The novel split-gate SiC MOSFET device with a semi-superjunction structure according to claim 2, characterized in that: The upper surface and side surfaces of the polysilicon gate are covered with a first interlayer dielectric layer, and the upper surface and side surfaces of the auxiliary polysilicon gate are covered with a second interlayer dielectric layer. The first interlayer dielectric layer and the second interlayer dielectric layer are spaced apart to form a groove, and a source field plate structure is arranged in the groove.

7. The novel split-gate SiC MOSFET device with a semi-superjunction structure according to claim 6, characterized in that: Also includes: A source electrode, the source electrode covers the upper surface of the source field plate structure and covers the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer; wherein the source electrode and the source field plate structure are prepared simultaneously.

8. A method for preparing a novel split-gate SiC MOSFET device with a semi-superjunction structure, used to prepare the novel split-gate SiC MOSFET device with a semi-superjunction structure as claimed in any one of claims 1 to 7, characterized in that: include: providing a substrate; growing an epitaxial layer on the substrate; A first hard mask plate and an ion implantation process are used to form a plurality of P-well regions in the epitaxial layer along a first direction; a second hard mask plate and a high-energy ion implantation process are used to form a P+ column region on a side of the P-well region close to the substrate; a third hard mask plate and an ion implantation process are used to form an N+ column region in the epitaxial layer; wherein the P+ column region and the N+ column region are both spaced apart from the substrate; The first direction is perpendicular to the thickness direction of the substrate.

9. The method for preparing a novel split-gate SiC MOSFET device having a semi-superjunction structure according to claim 8, characterized in that: Also includes: On the upper surface of the epitaxial layer, an oxide is generated by a thermal oxidation process to form a gate dielectric layer, and on both sides of the gate dielectric layer along the first direction, a mask plate and an etching process are used to etch away part of the gate dielectric layer to form a first gate dielectric layer, and the gate dielectric layer that is not etched forms a second gate dielectric layer; Polysilicon is deposited on the first gate dielectric layer to form a polysilicon gate, and polysilicon is deposited on the second gate dielectric layer to form an auxiliary polysilicon gate.

10. The method for preparing a novel split-gate SiC MOSFET device with a semi-superjunction structure according to claim 9, characterized in that: Also includes: Depositing a dielectric layer on the upper surface and side surfaces of the polysilicon gate to form a first interlayer dielectric layer, and depositing a dielectric layer on the upper surface and side surfaces of the auxiliary polysilicon gate to form a second interlayer dielectric layer; The first interlayer dielectric layer and the second interlayer dielectric layer are spaced apart to form a groove; Metal is deposited on the surface of the first interlayer dielectric layer, the surface of the second interlayer dielectric layer and in the groove to form a source electrode.

Images