Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for simplifying the manufacturing process of manufacturing at least five types of ring gate transistors with different threshold voltage absolute values and reducing the manufacturing difficulty of the semiconductor device. The semiconductor device comprises a semiconductor substrate and at least five types of ring gate transistors arranged on the semiconductor substrate. The different types of ring gate transistors are distributed at intervals in the direction parallel to the surface of the semiconductor substrate. Wherein in the different types of ring gate transistors, at least parts of the materials of the nanostructures included in the different channel regions are different, and the parts, with different materials, in the nanostructures included in the different channel regions are distributed in a staggered mode in the thickness direction of the semiconductor substrate. In the at least five types of ring gate transistors, parts of the nano structures included in different channel regions belonging to the at least two types of ring gate transistors are made of the same material, and the parts, made of the same material, in the nano structures included in the different channel regions are aligned in the thickness direction of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The gate stack included in the ring-gate transistor is not only formed on the top and sidewalls of the channel, but also formed at the bottom of the channel. Therefore, compared with planar transistors and fin field-effect transistors, the ring-gate transistor has advantages such as higher gate control capability.

[0003] However, when the semiconductor device includes at least two types of ring-gate transistors formed on a semiconductor substrate, and the absolute values ​​of the threshold voltages of the at least two types of ring-gate transistors are different, the process of manufacturing the two types of ring-gate transistors using the existing manufacturing method is complex and has high requirements, resulting in greater difficulty in manufacturing the semiconductor device. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are used to simplify the manufacturing process of at least five types of ring-gate transistors with different threshold voltage absolute values ​​and reduce the manufacturing difficulty of the semiconductor device.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a semiconductor device, which includes: a semiconductor substrate, and at least five types of ring-gate transistors arranged on the semiconductor substrate. Different types of ring-gate transistors are spaced apart in a direction parallel to the surface of the semiconductor substrate. Among the different types of ring-gate transistors, at least part of the materials of the nanostructures included in different channel regions are different, and the parts of the nanostructures with different materials included in different channel regions are staggered along the thickness direction of the semiconductor substrate. Among the at least five types of ring-gate transistors, the parts of the nanostructures included in different channel regions belonging to at least two types of ring-gate transistors are the same, and the parts of the nanostructures with the same materials included in different channel regions are aligned along the thickness direction of the semiconductor substrate.

[0006] When the above technical solution is adopted, in the semiconductor device provided by the present invention, in different types of ring-gate transistors, at least part of the materials of the nanostructures included in different channel regions are different, and the nanostructures with at least part of different materials may have different conductive characteristics. Therefore, the nanostructures included in different types of ring-gate transistors are manufactured respectively using at least part of different semiconductor materials, which is beneficial for making the channel regions of different types of ring-gate transistors have different conduction characteristics, thereby helping different types of ring-gate transistors have threshold voltages with different absolute values ​​to meet corresponding working requirements.

[0007] In addition, the parts of the nanostructures with different materials included in different channel regions are staggered along the thickness direction of the semiconductor substrate. Moreover, among at least five types of ring-gate transistors, the parts of the nanostructures included in different channel regions belonging to at least two types of ring-gate transistors have the same material, and the parts of the nanostructures with the same material included in different channel regions are aligned along the thickness direction of the semiconductor substrate. Based on this, when manufacturing the semiconductor device provided by the present invention, at least three semiconductor layers with different materials and alternately stacked can be formed on the semiconductor substrate, and at least three semiconductor layers alternately stacked are mutually channel layers / sacrificial layers. The above-mentioned at least five types of ring-gate transistors can be manufactured by only selecting different semiconductor layers and combining adjacent different semiconductor layers in the channel region of some types of ring-gate transistors, so as to achieve different absolute value threshold voltages of different types of ring-gate transistors. At the same time, it is not necessary to adopt a complex method of deposition-etching-deposition to obtain different types of ring-gate transistors with different absolute value threshold voltages by forming gate stack structures with different thicknesses and / or materials, thereby simplifying the manufacturing process of semiconductor devices.

[0008] In one example, when the nanostructures included in the channel regions of at least two types of all-around gate transistors have at least two materials, the thicknesses of portions of the nanostructures made of different materials are the same.

[0009] In one example, the material of the nanostructure included in the gate-all-around transistor includes Si 1-x Ge x , 0≤x≤1. In different types of all-around gate transistors, different channel regions include nanostructures having different germanium contents in at least a portion of the material.

[0010] In one example, in different types of all-around gate transistors, germanium contents in at least a portion of the material of the nanostructure included in different channel regions differ by at least 20%.

[0011] In one example, among the at least five types of gate-all-around transistors, different channel regions belonging to at least two types of gate-all-around transistors include nanostructures having different thicknesses.

[0012] In one example, portions of the channel regions of different types of all-around gate transistors that are made of the same material are integrally formed.

[0013] In one example, the gate stack structures included in different types of all-around gate transistors are made of the same material.

[0014] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, which comprises: first, providing a semiconductor substrate. Next, forming at least five types of ring-gate transistors on the semiconductor substrate. Different types of ring-gate transistors are spaced apart in a direction parallel to the surface of the semiconductor substrate. Among the different types of ring-gate transistors, at least part of the materials of the nanostructures included in different channel regions are different, and the parts of the nanostructures with different materials included in different channel regions are staggered along the thickness direction of the semiconductor substrate. Among the at least five types of ring-gate transistors, the parts of the nanostructures included in different channel regions belonging to at least two types of ring-gate transistors are the same, and the parts of the nanostructures with the same materials included in different channel regions are aligned along the thickness direction of the semiconductor substrate.

[0015] In one example, at least five types of ring-gate transistors are formed on a semiconductor substrate, including: forming at least five types of fin structures that are spaced and have the same structure on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, each type of fin structure includes at least three semiconductor layers that are alternately stacked and made of different materials. Next, a first mask structure is formed across each type of fin structure. Next, the portions of each type of fin structure exposed outside the first mask structure are processed separately to form a source region and a drain region included in each type of ring-gate transistor. Next, at least a portion of the first mask structure is removed. Next, a portion of the semiconductor layers in a type of fin structure is selectively removed so that the remaining semiconductor layers in this type of fin structure form a channel region included in the corresponding type of ring-gate transistor; and this step is repeated until the channel regions included in all types of ring-gate transistors are formed. Next, a gate stack structure is formed around the periphery of the channel region included in each type of ring-gate transistor.

[0016] In one example, the nanostructure includes a gate-all-around transistor of a portion of the semiconductor layer located at the bottom as a target type of gate-all-around transistor. Furthermore, after removing at least a portion of the first mask structure and before forming a gate stack structure surrounding the periphery of the channel region included in each type of gate-all-around transistor, the method for manufacturing a semiconductor device further includes: selectively removing a portion of the thickness of the semiconductor substrate located below the target type of gate-all-around transistor.

[0017] In one example, at least five types of fin-shaped structures that are spaced and have the same structure are formed on a semiconductor substrate, including: forming at least three semiconductor layers of different materials that are alternately stacked along a thickness direction of the semiconductor substrate on the semiconductor substrate. Next, selectively etching at least the at least three semiconductor layers that are alternately stacked to form at least five types of fin-shaped structures.

[0018] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0020] Figure 1 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 1 ;

[0021] Figure 2 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 ;

[0022] Figure 3 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 ;

[0023] Figure 4 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 4 ;

[0024] Figure 5 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 5 ;

[0025] Figure 6 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 6 ;

[0026] Figure 7 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 7 ;

[0027] Figure 8 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 8 ;

[0028] Fig. 9 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 9 ;

[0029] Fig.10 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 ;

[0030] Fig.11 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 one;

[0031] Fig.12 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 two;

[0032] Fig.13 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 three;

[0033] Fig.14 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 Four;

[0034] Fig.15 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 five;

[0035] Fig.16 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 six;

[0036] Fig.17 A schematic longitudinal cross-sectional view of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 seven.

[0037] Figure numerals: 11 is a semiconductor substrate, 12 is a ring-gate transistor, 13 is a channel region, 14 is a nanostructure, 15 is a source region, 16 is a drain region, 17 is a gate stack structure, 18 is a shallow trench isolation structure, 19 is a gate sidewall, 20 is an interlayer dielectric layer, 21 is a fin structure, 22 is a semiconductor layer, 23 is a first mask structure, 24 is a second mask structure, 25 is a third mask structure, and 26 is a target-type ring-gate transistor. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0039] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0040] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0042] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] The gate stack included in the ring-gate transistor is not only formed on the top and sidewalls of the channel, but also formed at the bottom of the channel. Therefore, compared with planar transistors and fin field effect transistors, the ring-gate transistor has advantages such as higher gate control capability. Based on this, when the different transistors included in the semiconductor device all adopt the ring-gate transistor, the working performance of the semiconductor device can be improved.

[0044] Secondly, in the actual manufacturing process of semiconductor devices, multiple "deposition-etching-deposition" methods are usually used to form gate stack structures of different thicknesses and / or different materials on the channels included in different types of transistors in the semiconductor device, so that different transistors correspond to different threshold control parameters, thereby realizing the regulation of the threshold voltage of different transistors in the semiconductor device. With the development of semiconductor technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space between each component, element or each element itself also need to be further reduced. For ring-gate transistors, the space between two adjacent nanostructures in the channel and between the nanostructure and the semiconductor substrate is small. It is difficult to form gate stack structures of different thicknesses and / or different materials in a small space, resulting in reduced yield and performance of semiconductor devices.

[0045] In response to the above technical problems, those skilled in the art have developed a dipole threshold control technology that does not occupy space to achieve the control of the threshold voltage of different transistors in semiconductor devices. Specifically, taking the transistor as a ring-gate transistor as an example, after the channel included in the corresponding ring-gate transistor is formed on different types of regions, a gate dielectric layer is formed on the periphery of the channel located on each type of region. Then, a dipole layer of corresponding thickness and corresponding material is formed on the gate dielectric layer, and the key elements in the dipole layer (for example: lanthanum element in lanthanum oxide dipole layer) are pushed to the interface through annealing treatment, so that different types of regions correspond to different threshold control parameters. Finally, the remaining dipole layer is removed, and the threshold voltage control of different ring-gate transistors is achieved without reducing the formation space of the gate, thereby not affecting the subsequent filling of the gate.

[0046] However, the process complexity of the above-mentioned dipole threshold control technology is relatively large, and the process requirements are relatively high, which makes the manufacturing of semiconductor devices more difficult. In addition, the annealing treatment in the dipole threshold control technology pushes the key elements in the dipole layer to the interface, and there are certain compatibility issues. For example: when the material of the channel included in the ring-gate transistor is germanium silicon or germanium material, the above-mentioned annealing treatment will cause the transmission performance of carriers in the channel to change, thereby making the conductivity of the ring-gate transistor worse.

[0047] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. Among them, in the semiconductor device provided by the embodiment of the present invention, in different types of ring-gate transistors, at least part of the materials of the nanostructures included in different channel regions are different, so that different types of ring-gate transistors have threshold voltages with different absolute values. In addition, the parts of the nanostructures with different materials included in different channel regions are staggered along the thickness direction of the semiconductor substrate. Moreover, among at least five types of ring-gate transistors, the parts of the nanostructures included in different channel regions belonging to at least two types of ring-gate transistors are made of the same material, and the parts of the nanostructures with the same materials included in different channel regions are aligned along the thickness direction of the semiconductor substrate to simplify the manufacturing process of the semiconductor device.

[0048] Specifically, in a first aspect, an embodiment of the present invention provides a semiconductor device. Fig.17 As shown, the semiconductor device includes: a semiconductor substrate 11, and at least five types of ring-gate transistors 12 arranged on the semiconductor substrate 11. Different types of ring-gate transistors 12 are spaced apart in a direction parallel to the surface of the semiconductor substrate 11. Among the different types of ring-gate transistors 12, at least part of the materials of the nanostructures 14 included in different channel regions 13 are different, and the parts of the nanostructures 14 included in different channel regions 13 with different materials are staggered along the thickness direction of the semiconductor substrate 11. Among the at least five types of ring-gate transistors 12, the parts of the nanostructures 14 included in different channel regions 13 belonging to at least two types of ring-gate transistors 12 are the same, and the parts of the nanostructures 14 included in different channel regions 13 with the same materials are aligned along the thickness direction of the semiconductor substrate 11.

[0049] When the above technical solution is adopted, Fig.17 As shown, in the semiconductor device provided by the embodiment of the present invention, in different types of ring-gate transistors 12, at least part of the materials of the nanostructures 14 included in different channel regions 13 are different, and at least part of the nanostructures 14 with different materials may have different conductive characteristics. Therefore, the nanostructures 14 included in different types of ring-gate transistors 12 are manufactured using at least part of different semiconductor materials, which is conducive to making the channel regions 13 of different types of ring-gate transistors 12 have different conduction characteristics, thereby facilitating different types of ring-gate transistors 12 to have threshold voltages with different absolute values ​​to meet corresponding working requirements. In addition, the parts of the nanostructures 14 included in different channel regions 13 with different materials are staggered along the thickness direction of the semiconductor substrate 11. Moreover, in at least five types of ring-gate transistors 12, the parts of the nanostructures 14 included in different channel regions 13 belonging to at least two types of ring-gate transistors 12 are made of the same material, and the parts of the nanostructures 14 included in different channel regions 13 with the same material are aligned along the thickness direction of the semiconductor substrate 11. Based on this, as Figures 1 to 17As shown, when manufacturing the semiconductor device provided by the embodiment of the present invention, the above-mentioned at least five types of ring-gate transistors 12 can be manufactured by forming at least three semiconductor layers 22 of different materials and alternately stacked on the semiconductor substrate 11, and the at least three semiconductor layers 22 alternately stacked are channel layers / sacrificial layers for each other, and only by selecting different semiconductor layers 22 and combining adjacent different semiconductor layers 22 in the channel region 13 of some types of ring-gate transistors 12, the above-mentioned channel region 13 with different conductive characteristics can be obtained, so that different types of ring-gate transistors 12 have different threshold voltages of absolute values. At the same time, it is not necessary to adopt a complex method of deposition-etching-deposition to obtain different types of ring-gate transistors 12 with different threshold voltages of absolute values ​​by forming a gate stack structure 17 with different thicknesses and / or materials, thereby simplifying the manufacturing process of semiconductor devices.

[0050] In the actual application process, the specific structure of the above-mentioned semiconductor substrate can be set according to the actual application scenario, and is not specifically limited here. For example, the semiconductor substrate provided in the embodiment of the present invention can be a semiconductor substrate such as silicon, silicon germanium, germanium, etc. without any structure formed. Alternatively, the semiconductor substrate can also be a semiconductor substrate formed with some structures. For example: when the semiconductor device provided in the embodiment of the present invention is a second-layer or higher-layer device in an integrated circuit, the semiconductor substrate includes a semiconductor structure located below at least five types of ring-gate transistors, etc.

[0051] For the above-mentioned at least five types of ring-gate transistors, the embodiment of the present invention does not specifically limit the number of types of ring-gate transistors arranged on the semiconductor substrate, the number of ring-gate transistors and the threshold voltage of each type of ring-gate transistor, and the distribution between different ring-gate transistors, and can be set according to actual needs. Specifically, the semiconductor device provided by the embodiment of the present invention may include only five types of ring-gate transistors, or six, eight, ten... types of ring-gate transistors. In the same type of ring-gate transistors, there may be only one ring-gate transistor, or there may be multiple ring-gate transistors.

[0052] From a structural perspective, Fig.17As shown, each type of ring-gate transistor 12 includes a source region 15, a drain region 16, a channel region 13 and a gate stack structure 17. In the same ring-gate transistor 12, the source region 15 and the drain region 16 are distributed at intervals. The channel region 13 is located between the source region 15 and the drain region 16, and is in contact with the source region 15 and the drain region 16 respectively. The channel region 13 may include only one layer of nanostructure 14, or may include multiple layers of nanostructure 14 distributed at intervals along the thickness direction of the semiconductor substrate 11. There is a gap between each layer of nanostructure 14 and the semiconductor substrate 11. The gate stack structure 17 surrounds the periphery of each layer of nanostructure 14. The gate stack structure 17 may include a gate dielectric layer and a gate. The gate dielectric layer surrounds the periphery of each layer of nanostructure 14 included in the channel region 13, and covers the portion of the semiconductor substrate 11 corresponding to the gate formation region. The gate is located on the gate dielectric layer.

[0053] In terms of materials, the source and drain regions may be made of any semiconductor material such as silicon, germanium silicon or germanium. In the gate stack structure, the gate dielectric layer may be made of insulating materials such as HfO2, ZrO2, TiO2 or Al2O3, and the gate may be made of conductive materials such as TiN, TaN or TiSiN.

[0054] As for the material of the channel region of each type of ring-gate transistor, it can be determined according to the threshold voltage requirement of each type of ring-gate transistor in the actual application scenario, as long as at least part of the materials of the nanostructures included in different channel regions of different types of ring-gate transistors are different.

[0055] Specifically, Fig.17 As shown, among the different types of all-around gate transistors 12, the nanostructure 14 in the channel region 13 of some of the all-around gate transistors 12 may be a single-layer structure, and the nanostructure 14 in the channel region 13 of some of the all-around gate transistors 12 may be a stacked structure including at least two semiconductor layers 22 arranged along the thickness direction of the semiconductor substrate 11. In the same nanostructure 14, different semiconductor layers 22 are made of different materials.

[0056] For example, the material of the nanostructure included in the gate-all-around transistor includes Si 1-x Ge x , and when 0≤x≤1, in different types of all-around gate transistors, the germanium content in at least part of the material of the nanostructure included in different channel regions is different. Among them, the difference in the germanium content in at least part of the material of the nanostructure included in different channel regions of different types of all-around gate transistors can be determined according to the requirements for the threshold voltage of different types of all-around gate transistors in actual application scenarios, and is not specifically limited here.

[0057] For example, in different types of all-around gate transistors, the germanium content in at least a portion of the material of the nanostructure included in different channel regions may differ by at least 20%.

[0058] For example: Fig.17 As shown, five types of all-round gate transistors 12 may be arranged on the semiconductor substrate 11. Among them, the nanostructure 14 included in the channel region 13 of three types of all-round gate transistors 12 is a single-layer structure. The nanostructure 14 included in the channel region 13 of two types of all-round gate transistors 12 is a double-layer structure. Specifically, the material of the nanostructure 14 included in the channel region 13 of the first type of all-round gate transistor may include Si, and the material of the nanostructure 14 included in the channel region 13 of the second type of all-round gate transistor may include Si. 0.75 Ge 0.25 The material of the nanostructure 14 included in the channel region 13 of the third type of all-around gate transistor may include Si 0.5 Ge 0.5 The material of the nanostructure 14 included in the channel region 13 of the fourth type of all-around gate transistor may include Si and Si 0.5 Ge 0.5 The material of the nanostructure 14 included in the channel region 13 of the fifth type of all-around gate transistor may include Si 0.75 Ge 0.25 and Si 0.5 Ge 0.5 In the above case, the nanostructures 14 included in the first to third types of all-around gate transistors are staggered, and the Si material in the nanostructures 14 included in the fourth type of all-around gate transistors is staggered with the nanostructures 14 included in the second, third and fifth types of all-around gate transistors, respectively, and aligned with the nanostructures 14 included in the first type of all-around gate transistors. 0.5 Ge 0.5 The material portion is respectively the same as the nanostructure 14 included in the first and second types of all-around gate transistors, and the nanostructure 14 included in the fifth type of all-around gate transistor, wherein the material is Si 0.5 Ge 0.5 The portions of the Si in the nanostructure 14 of the third type of all-around gate transistor are staggered and aligned with the nanostructure 14 included in the third type of all-around gate transistor. Similarly, the Si in the nanostructure 14 of the fifth type of all-around gate transistor 0.5 Ge 0.5 The material portion is respectively connected to the nanostructure 14 of the first and second types of all-around gate transistors, and the material Si in the nanostructure 14 of the fifth type of all-around gate transistor. 0.75 Ge 0.25 The portions are staggered and aligned with the nanostructure 14 included in the third type of all-around gate transistor. The Si in the nanostructure 14 included in the fourth type of all-around gate transistor 0.75 Ge 0.25 Portions of the material are interleaved with the nanostructures 14 included in the first, third and fifth types of gate-all-around transistors, respectively, and aligned with the nanostructures 14 included in the second type of gate-all-around transistors.

[0059] Among them, in the case where the nanostructure included in the channel region of at least two types of ring-gate transistors has at least two materials, the thickness of the parts of different materials in the nanostructure can be the same or different. In addition, in at least five types of ring-gate transistors, the thickness of the nanostructure included in different channel regions belonging to at least two types of ring-gate transistors can be the same or different. The thickness of the parts of the same material in the nanostructure included in each type of ring-gate transistor, as well as the number and distribution of the parts of different materials can be determined according to the requirements for the threshold voltage of the ring-gate transistor in the actual application scenario, and are not specifically limited here.

[0060] In addition, in actual application, the parts of the channel regions of different types of all-around gate transistors that are made of the same material can be integrally formed to further simplify the manufacturing process of the semiconductor device and help control the manufacturing cost of the semiconductor device.

[0061] It should be noted that if Figures 10 to 17 As shown, the gate-all-around transistor 12 whose nanostructure 14 includes a portion of the semiconductor layer 22 at the bottom is defined as a target gate-all-around transistor 26. The portion of the semiconductor layer 22 at the bottom is determined relative to the manufacturing process of the semiconductor device and the specific structure of the nanostructure 14 included in the other gate-all-around transistor 12. For example: Figures 10 to 17 As shown, the nanostructure 14 in the first type of gate-all-around transistor and the fourth type of gate-all-around transistor includes a portion of the semiconductor layer 22 located at the bottom layer, and the first type of gate-all-around transistor and the fourth type of gate-all-around transistor are target type gate-all-around transistors. At this time, the thickness of the portion of the semiconductor substrate 11 located below the target type gate-all-around transistor is less than the thickness of the portion of the semiconductor substrate 11 located below the other type of gate-all-around transistors 12, so that the gate stack structure 17 can surround the periphery of the nanostructure 14 located at the bottom layer in the first type of gate-all-around transistor and the fourth type of gate-all-around transistor.

[0062] Secondly, if Fig.17 As shown, the gate stack structures 17 included in different types of all-around gate transistors 12 are made of the same material to further simplify the manufacturing process of the semiconductor device and reduce the difficulty of manufacturing the semiconductor device.

[0063] In some cases, such as Fig.17 As shown, the gate-all-around transistor 12 may further include a gate spacer 19. The gate spacer 19 is disposed on both sides of the gate stack structure 17 along the length direction to isolate the gate stack structure 17 from other conductive structures to ensure that the semiconductor device has stable electrical characteristics.

[0064] In some cases, such as Figures 3 to 17As shown, the semiconductor device provided by the present invention may also include a shallow trench isolation structure 18 and / or an interlayer dielectric layer 20. The shallow trench isolation structure 18 is located on the semiconductor substrate 11, and is used to isolate different active areas of the semiconductor substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 18 can be set according to actual conditions. The interlayer dielectric layer 20 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 17, and is used to protect the source region 15 and the drain region 16 from being affected by operations such as etching and cleaning when removing at least part of the first mask structure 23 and the corresponding semiconductor layer 22.

[0065] The material of at least one of the gate sidewall, the shallow trench isolation structure and the interlayer dielectric layer may be an insulating material such as SiN, Si3N4, SiO2 or SiCO.

[0066] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 1 to 17 The manufacturing process is described by a stereoscopic or cross-sectional view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps: First, a semiconductor substrate 11 is provided. Next, at least five types of ring-gate transistors 12 are formed on the semiconductor substrate 11. Different types of ring-gate transistors 12 are spaced apart in a direction parallel to the surface of the semiconductor substrate 11. Among the different types of ring-gate transistors 12, at least part of the materials of the nanostructures 14 included in different channel regions 13 are different, and the parts of the nanostructures 14 with different materials included in different channel regions 13 are staggered along the thickness direction of the semiconductor substrate 11. Among the at least five types of ring-gate transistors 12, the parts of the nanostructures 14 included in different channel regions 13 belonging to at least two types of ring-gate transistors 12 are the same, and the parts of the nanostructures 14 with the same materials included in different channel regions 13 are aligned along the thickness direction of the semiconductor substrate 11.

[0067] It should be noted that the structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the embodiment of the present invention is the same as the structure of the semiconductor device provided in the first aspect, so the structure and materials of various types of ring-gate transistors in the second aspect can refer to the structure and materials of various types of ring-gate transistors in the first aspect. In addition, the beneficial effects of the second aspect and its various implementations in the embodiment of the present invention can also refer to the analysis of the beneficial effects in the first aspect and its various implementations, which will not be repeated here.

[0068] Exemplarily, the forming of at least five types of all-around gate transistors on the semiconductor substrate may include the following steps:

[0069] like Figure 1 and Figure 2As shown, at least five types of fin structures 21 with the same structure and spaced apart are formed on the semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, each type of fin structure 21 includes at least three semiconductor layers 22 alternately stacked and made of different materials.

[0070] Specifically, each of the above-mentioned semiconductor layers can be used to manufacture at least a portion of the region of the corresponding layer of nanostructure in the corresponding ring-gate transistor. At this time, the material, number of layers, and positional relationship between semiconductor layers of different materials in the fin structure can be determined based on the materials of different parts of the nanostructure and the relative positional relationship between parts of different materials along the thickness direction of the semiconductor substrate. Alternatively, only part of the semiconductor layers in the fin structure are used to manufacture at least a portion of the region of the corresponding layer of nanostructure in the corresponding ring-gate transistor, and part of the semiconductor layers are used to form at least a portion of the gap between two adjacent layers of nanostructure included in the same channel region. At this time, the material of the semiconductor layer corresponding to the gap can be any semiconductor material different from the nanostructure material, and the thickness of the semiconductor layer corresponding to the gap can be determined based on the thickness of the gate stack structure, which is not specifically limited here.

[0071] For example: Figures 1 to 17 As shown, when the manufactured semiconductor device includes five types of ring-gate transistors 12, if each semiconductor layer 22 is used to manufacture at least a portion of the corresponding layer of nanostructure 14 in the corresponding type of ring-gate transistor 12, the fin structure 21 may only include three semiconductor layers 22 of different materials.

[0072] For another example, when the manufactured semiconductor device includes five types of all-around gate transistors, if only some semiconductor layers are used to manufacture at least some areas of corresponding layers of nanostructures in corresponding types of all-around gate transistors, the fin structure may include at least four semiconductor layers.

[0073] In the actual manufacturing process, Figure 1 As shown, epitaxy or other processes can be used to form at least three semiconductor layers 22 of different materials alternately stacked along the thickness direction of the semiconductor substrate 11 on the semiconductor substrate 11. Next, as Figure 2 As shown, photolithography and etching processes can be used to selectively etch at least three semiconductor layers 22 alternately stacked to form at least five types of fin structures 21. Specifically, when the manufactured semiconductor device does not include a shallow trench isolation structure, only the at least three semiconductor layers alternately stacked need to be selectively etched, and the remaining at least three semiconductor layers after the selective etching form a fin structure. Or, as Figure 2As shown, when the manufactured semiconductor device also includes a shallow trench isolation structure 18, it is necessary to selectively etch at least three semiconductor layers 22 and a portion of the semiconductor substrate 11 to form a fin portion; then, as shown in FIG. Figure 2 As shown, a shallow trench isolation structure 18 is formed on a semiconductor substrate 11 by using deposition and etching processes. The top height of the shallow trench isolation structure 18 is lower than the bottom height of the semiconductor layer 22 at the bottom, and the part of the fin exposed outside the shallow trench isolation structure 18 is a fin-shaped structure 21.

[0074] Next, if Figure 3 As shown, a first mask structure 23 is formed across each type of fin-shaped structure 21 .

[0075] In the actual manufacturing process, a deposition process can be used to form a mask material covering the semiconductor substrate. Then, the mask material is selectively etched using processes such as photolithography and etching to form the above-mentioned first mask structure. As for the material of the first mask structure, it can be set according to actual needs, as long as it can play a mask protection role in the subsequent process.

[0076] Exemplarily, the first mask structure may include a sacrificial gate. The material of the sacrificial gate may include a material that is easy to remove, such as polysilicon. Secondly, the first mask structure may also include a gate oxide layer, and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include materials such as silicon oxide. In addition, the first mask structure may also include a sacrificial gate, and gate sidewalls located at least on both sides of the sacrificial gate along the length direction. The material of the gate sidewall can be referred to in the above text and will not be repeated here. Furthermore, the first mask structure may also include the gate oxide layer, the sacrificial gate and the gate sidewalls at the same time.

[0077] Next, if Figures 4 to 7 As shown, the portion of each type of fin structure 21 exposed outside the first mask structure 23 is processed to form the source region 15 and the drain region 16 included in each type of all-around gate transistor 12 .

[0078] In the actual manufacturing process, ion implantation and other processes can be used to directly dope the portion of each type of fin structure exposed outside the first mask structure to form the source region and drain region of the corresponding type of ring-gate transistor. Alternatively, wet etching or dry etching and other processes can be used to selectively remove the portion of the fin structure exposed outside the first mask structure; then, epitaxy and other processes are used to form the source region and drain region of the ring-gate transistor on both sides of the remaining fin structure.

[0079] It should be noted that, when the source and drain regions of different types of all-around gate transistors are the same in terms of material, conductivity type, and doping, the above operations can be performed on different types of fin structures at the same time, and the source and drain regions of different types of all-around gate transistors can be formed at the same time, so as to improve the manufacturing efficiency of semiconductor devices and reduce the manufacturing cost of semiconductor devices. Or, Figure 6 and Figure 7 As shown, the above treatment may also be performed on a type of fin-like structure under the protection of a corresponding second mask structure 24 (photoresist mask or silicon nitride mask, etc.) to form the source region 15 and drain region 16 included in the type of all-around gate transistor. Then, the previously formed second mask structure 24 is removed, and a new second mask structure 24 is formed to cover the corresponding type of fin-like structure and the previously formed source region 15 and drain region 16, and the previous operation is repeated until the source region 15 and drain region 16 included in all type-all-around gate transistors are formed.

[0080] Next, if Figure 8 As shown, deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 20 covering the semiconductor substrate 11. The top of the interlayer dielectric layer 20 is flush with the top of the first mask structure 23. The material of the interlayer dielectric layer 20 can be referred to above and will not be repeated here.

[0081] Next, if Fig. 9 As shown, at least a portion of the first mask structure is removed by using a dry etching process or a wet etching process.

[0082] Specifically, whether to completely remove the first mask structure can be determined according to the specific structure of the first mask structure. For example, when the first mask structure only includes a gate oxide layer and a sacrificial gate, the first mask structure needs to be completely removed. For another example, when the first mask structure includes a sacrificial gate and a gate sidewall, only the sacrificial gate needs to be removed, that is, only part of the first mask structure needs to be removed.

[0083] Next, if Figures 10 to 16 As shown, part of the semiconductor layer in a type of fin-like structure is selectively removed so that the remaining semiconductor layer in this type of fin-like structure forms a channel region 13 included in the corresponding ring-gate transistor 12; and this step operation is repeated until the channel region 13 included in all the ring-gate transistors 12 is formed.

[0084] In the actual manufacturing process, the fin structure to be processed is defined as the target fin structure. Figures 10 to 16As shown, deposition and etching processes can be used to form a third mask structure 25 (photolithography mask or silicon nitride mask, etc.) covering the remaining fin-like structures except the target fin-like structure. Then, according to the material of the nanostructure 14 included in the corresponding ring-gate transistor formed by the target fin-like structure, and using dry etching or wet etching processes, a part of the semiconductor layer in a type of fin-like structure (i.e., the target fin-like structure) is selectively removed (the part of the semiconductor layer to be removed is a semiconductor layer different from the nanostructure material included in the corresponding ring-gate transistor), so that the remaining semiconductor layer in this type of fin-like structure forms the channel region 13 included in the corresponding ring-gate transistor. Then, the third mask structure formed previously is removed. And the above operation is repeated until the channel region 13 included in all the ring-gate transistors is formed.

[0085] It should be noted that if Fig.11 and Fig.14 As shown, if there is a nanostructure 14 in a part of the ring-gate transistor 12 including a part of the semiconductor layer 22 located at the bottom layer, the ring-gate transistor 12 in which the nanostructure 14 includes a part of the semiconductor layer 22 located at the bottom layer is defined as a target type ring-gate transistor 26. Then, after removing at least a part of the first mask structure, before forming a gate stack structure 17 surrounding the periphery of the channel region 13 included in each type of ring-gate transistor 12, it is also necessary to selectively remove a part of the thickness of the semiconductor substrate 11 located below the target type ring-gate transistor 26 by a dry etching or wet etching process under the protection of the corresponding third mask structure 25 to release the nanostructure 14 located at the bottom layer.

[0086] Next, if Fig.17 As shown, atomic layer deposition and other processes can be used to form a gate stack structure 17 surrounding the channel region 13 of each type of all-around gate transistor 12. The material of the gate stack structure 17 can be referred to above and will not be described again here.

[0087] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0088] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, and at least five types of all-round gate transistors disposed on the semiconductor substrate; the all-round gate transistors of different types are spaced apart in a direction parallel to a surface of the semiconductor substrate; Among them, in different types of the ring-gate transistors, at least part of the materials of the nanostructures included in different channel regions are different, and the parts of the nanostructures with different materials included in different channel regions are staggered along the thickness direction of the semiconductor substrate; in the at least five types of ring-gate transistors, different channel regions belonging to at least two types of the ring-gate transistors include part of the materials of the nanostructures included in different channel regions are the same, and the parts of the nanostructures with the same materials included in different channel regions are aligned along the thickness direction of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein: In the case where the nanostructures included in the channel regions of at least two types of the all-around gate transistors have at least two materials, the thicknesses of portions of the nanostructures made of different materials are the same.

3. The semiconductor device according to claim 1, wherein: The material of the nanostructure of the ring-gate transistor includes Si 1-x Ge x , 0≤x≤1; In different types of the all-around gate transistors, different channel regions include nanostructures having different germanium contents in at least a portion of the material.

4. The semiconductor device according to claim 3, characterized in that In the different types of the ring-gate transistors, the germanium content in at least a portion of the material of the nanostructure included in different channel regions differs by at least 20%.

5. The semiconductor device according to claim 1, wherein: Among the at least five types of all-around gate transistors, different channel regions belonging to at least two types of all-around gate transistors have nanostructures with different thicknesses.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The parts of the channel regions of the different types of the ring-gate transistors that are made of the same material are integrally formed; And / or, the gate stack structures included in different types of the ring-gate transistors are made of the same material.

7. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate; At least five types of ring-gate transistors are formed on the semiconductor substrate; different types of the ring-gate transistors are spaced apart in a direction parallel to the surface of the semiconductor substrate; wherein, among the different types of the ring-gate transistors, at least a portion of the nanostructures included in different channel regions are made of different materials, and portions of the nanostructures with different materials included in different channel regions are staggered along the thickness direction of the semiconductor substrate; among the at least five types of ring-gate transistors, different channel regions of at least two types of the ring-gate transistors include portions of the nanostructures with the same material, and portions of the nanostructures with the same material included in different channel regions are aligned along the thickness direction of the semiconductor substrate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The step of forming at least five types of gate-all-around transistors on the semiconductor substrate comprises: At least five types of fin-shaped structures which are spaced apart and have the same structure are formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, each type of the fin-shaped structures comprises at least three semiconductor layers which are alternately stacked and made of different materials; forming a first mask structure across each type of the fin-shaped structure; Respectively processing the portions of each type of the fin-shaped structure exposed outside the first mask structure to form source regions and drain regions included in each type of the all-around gate transistor; removing at least a portion of the first mask structure; Selectively removing a portion of the semiconductor layer in one type of the fin-shaped structure, so that the remaining semiconductor layer in this type of the fin-shaped structure forms a channel region included in a corresponding type of the all-around gate transistor; and repeating this step until the channel regions included in all types of the all-around gate transistor are formed; A gate stack structure is formed around the periphery of the channel region included in each type of the all-around gate transistor.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The nanostructure includes a portion of the semiconductor layer located at the bottom, and the gate-all-around transistor is a target-type gate-all-around transistor; After removing at least a portion of the first mask structure, before forming a gate stack structure surrounding the periphery of the channel region included in each type of the ring-gate transistor, the method for manufacturing the semiconductor device further includes: selectively removing a portion of the thickness of the semiconductor substrate located below the target type of ring-gate transistor.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: The at least five types of fin-shaped structures which are spaced and have the same structure are formed on the semiconductor substrate, including: Forming at least three semiconductor layers of different materials on the semiconductor substrate, which are alternately stacked along the thickness direction of the semiconductor substrate; At least the at least three semiconductor layers alternately stacked are selectively etched to form the at least five types of fin structures.

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