Cascode enhanced diamond and gallium nitride heterogeneous integrated power device

Abstract

The invention discloses a cascode enhanced diamond and gallium nitride heterogeneous integrated power device which comprises a GaN-based field effect transistor unit, a diamond-based field effect transistor unit and electrode interconnection metal. The GaN-based field effect transistor unit is an enhancement mode transistor, and the diamond-based field effect transistor unit is a depletion mode transistor and is arranged on the same diamond substrate. A diamond transistor gate electrode and a GaN transistor source electrode are connected and serve as a source electrode of the device; the source electrode of the diamond transistor is connected with the drain electrode of the GaN transistor; the gate electrode of the GaN transistor is used as the gate of the device; and the drain electrode of the diamond transistor is used as the drain electrode of the device to form a cascode enhanced device. Monolithic heterogeneous integration of a GaN-based transistor and a diamond-based transistor is realized through a diamond substrate GaN wafer material, and a cascode enhanced diamond and gallium nitride heterogeneous integrated power device is formed through electrode interconnection, so that technical support is provided for a next-generation high-performance power electronic system.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device. Background Art

[0002] Power devices are widely used in many converters such as rectifiers, switching power supplies and frequency converters, involving almost all power electronic products. Although power electronic devices only account for about 20%-30% of the total value of the entire power electronic device, the performance of the device has a very important impact on the performance of various technical indicators of the entire power electronic device. High frequency, high power density, high withstand voltage and high reliability are the inevitable trends in the development of future converters.

[0003] In terms of current market applications, silicon-based power metal oxide semiconductor field effect transistors (SiMOSFET) dominate low-voltage applications, and are generally several hundred kHz in power supply applications. In high-voltage and high-power applications, silicon-based insulated gate bipolar transistors (Si IGBTs) are widely used, but the switching speed is slower, and the switching frequency of 50kHz-90kHz is the limit of IGBTs. The switching speed and switching loss restrict the realization of high-frequency silicon devices, making it impossible to improve the power density of the converter, and it is even more difficult to achieve a lightweight design.

[0004] Gallium nitride (GaN) is a wide bandgap semiconductor and a typical representative of the third generation of semiconductors. High electron mobility transistors made of gallium nitride materials, namely GaN HEMTs, can operate at high frequency and high power. Compared with the first generation of semiconductor silicon-based devices, GaN devices have higher voltage resistance, faster switching frequency, smaller on-resistance and other characteristics, and are widely used in the field of power electronic devices. Relevant research shows that GaN devices are suitable for 68% of the power device market; the application of GaN devices in power conversion circuits can eliminate 90% of the energy loss of the rectifier during AC-DC conversion, greatly improving energy efficiency;

[0005] All GaN devices work based on the principle of two-dimensional electron gas (2DEG) as a conductive channel. According to the conduction mode of the channel, GaN HEMT is divided into two basic structures: depletion mode (D-mode) and enhancement mode (E-mode); depletion mode GaN HEMT is a normally-on device. Only when a negative voltage is applied to the gate source, the electrons in the 2DEG are depleted, and the depletion mode GaN tube can be turned off; the enhancement mode GaN HEMT is a device that transforms the gate or barrier layer of the device to form a normally-off type, so that the device has the switching characteristics of an enhancement mode device. In practical applications, depletion mode devices have great limitations, because when the converter is turned on, a negative bias needs to be applied to the depletion mode device first to avoid a short circuit. Therefore, high-reliability enhancement mode devices are more commonly used in power electronic systems.

[0006] The design level and manufacturing process of GaN HEMT are becoming more mature, the device frequency is getting higher and higher, the size is getting smaller and smaller, and various output characteristics have been greatly improved. However, there are still some reliability and stability issues that restrict the device output from approaching the theoretical value. Among these problems, the heat dissipation problem of the device is the most difficult technical problem.

[0007] Traditional GaN HEMT devices grow materials on a silicon substrate and then manufacture HEMT devices. However, silicon has poor thermal conductivity, which is not conducive to effective heat dissipation of the device. Therefore, a common source and common gate enhanced diamond and gallium nitride heterogeneous integrated power device is designed to solve the above problem. Summary of the invention

[0008] The main purpose of the present invention is to provide a common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device.

[0009] The purpose of the present invention can be achieved by adopting the following technical solutions:

[0010] A common source and common gate enhanced diamond and gallium nitride heterogeneous integrated power device includes a GaN-based field effect transistor unit, a diamond-based field effect transistor unit, and an electrode interconnection metal. The GaN-based field effect transistor unit and the diamond-based field effect transistor unit are arranged on the same diamond substrate. The GaN-based field effect transistor unit is an enhancement-type transistor, the diamond-based field effect transistor unit is a depletion-type transistor, and the GaN-based field effect transistor unit and the diamond-based field effect transistor unit form a common source and common gate structure through the electrode interconnection metal.

[0011] In one embodiment of the present invention, the GaN-based field effect transistor unit includes a diamond substrate, a GaN transistor transition layer, a GaN transistor buffer layer, a GaN transistor channel layer, a GaN transistor barrier layer, a dielectric passivation layer, a GaN transistor source electrode, a GaN transistor gate electrode, and a GaN transistor drain electrode;

[0012] The GaN transistor transition layer, GaN transistor buffer layer, GaN transistor channel layer, and GaN transistor barrier layer are group III nitrides, and the group III nitride semiconductor is a combination of any two or more of GaN, AlN, and InN. A two-dimensional electron gas is formed between the GaN transistor channel layer and the GaN transistor barrier layer, which is a conductive channel of the GaN-based transistor;

[0013] The GaN transistor transition layer is located on the diamond substrate; due to the lattice mismatch between the dielectric substrate and the GaN transistor buffer layer, a transition layer (AlGaN or AlN) of a certain thickness needs to be introduced to reduce the interface tension caused by the mismatch. The transition layer plays an important role in reducing the current collapse caused by interface mismatch, defects or trap effects, reducing static current leakage and radio frequency conduction, and improving radio frequency performance.

[0014] The GaN transistor buffer layer is located on the GaN transistor transition layer; the GaN transistor buffer layer is intentionally doped to achieve high resistance and low leakage, and its thickness is usually at the micron level, which is used to reduce the background carrier concentration to reduce the drain current collapse caused by the buffer layer trap effect.

[0015] The GaN transistor channel layer is located on the GaN transistor buffer layer; the GaN transistor channel layer is unintentionally doped, forming a two-dimensional electron gas channel on the upper surface, and is isolated from the GaN transistor buffer layer into which certain doping impurities are intentionally introduced;

[0016] The GaN transistor barrier layer is located on the GaN transistor channel layer; since group III nitrides have strong polarization charges, near the interface between the GaN transistor barrier layer and the GaN transistor channel layer, the positive polarization charge density on the lower surface of the GaN transistor barrier layer is much greater than the negative polarization charge density of the GaN transistor channel layer, resulting in a certain positive polarization charge at the interface between the GaN transistor barrier layer and the GaN transistor channel layer, thereby inducing the generation of a two-dimensional electron gas within a nanometer-scale thickness range on the upper surface of the GaN transistor channel layer. The two-dimensional electron gas has a large concentration and a high mobility, and can be used as a conductive channel of the GaN transistor;

[0017] The GaN transistor source electrode and the GaN transistor drain electrode are located on both sides above the GaN transistor barrier layer;

[0018] The GaN transistor gate electrode is located on the GaN transistor barrier layer; the GaN transistor barrier layer below the GaN transistor gate electrode is processed in a certain manner so that the GaN transistor is in an enhanced working mode; the GaN transistor gate electrode is the gate of the common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device;

[0019] The dielectric passivation layer is located on the barrier layer of the GaN transistor, between the source electrode of the GaN transistor and the gate electrode of the GaN transistor, and between the gate electrode of the GaN transistor and the drain electrode of the GaN transistor. The dielectric passivation layer plays an important role in reducing the collapse of the drain current and maintaining the two-dimensional electron gas generated by the polarization characteristics. At the same time, it can also reduce the gate leakage current and enhance the source and drain ohmic contact and breakdown voltage.

[0020] In one embodiment of the present invention, the diamond-based field effect transistor unit comprises a diamond substrate, a p-channel diamond layer, a diamond transistor gate dielectric layer, a dielectric passivation layer, a diamond transistor source electrode, a diamond transistor gate electrode, and a diamond transistor drain electrode;

[0021] The p-channel diamond layer is located on a diamond substrate;

[0022] The upper surface of the p-channel diamond layer is hydrogen-terminated, forming a two-dimensional hole gas, which is a conductive channel of the diamond transistor;

[0023] The diamond transistor source electrode and the diamond transistor drain electrode are located on both sides above the p-channel diamond layer;

[0024] The diamond transistor drain electrode is the drain electrode of the common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device;

[0025] The diamond transistor gate dielectric layer is located on the p-channel diamond layer and between the diamond transistor source electrode and the diamond transistor drain electrode;

[0026] The diamond transistor gate electrode is located on the diamond transistor gate dielectric layer;

[0027] The dielectric passivation layer is located on the diamond transistor gate dielectric layer, between the diamond transistor source electrode and the diamond transistor gate electrode, and between the diamond transistor gate electrode and the diamond transistor drain electrode.

[0028] In one embodiment of the present invention, the electrode interconnection metal includes gate-gate electrode connection metal and source-drain electrode connection metal;

[0029] The gate-source electrode connection metal connects the diamond transistor gate electrode and the GaN transistor source electrode and serves as the source of the device;

[0030] The source-drain electrode connection metal connects the diamond transistor source electrode and the GaN transistor drain electrode;

[0031] In one embodiment of the present invention, the material of the GaN transistor transition layer is AlN, with a thickness of 50nm-300nm, and the GaN transistor transition layer is used to release the lattice mismatch stress and thermal stress between the buffer layer and the substrate. The material of the GaN transistor buffer layer is undoped GaN or AlGaN, with a thickness of 200nm to 5μm.

[0032] The material of the GaN transistor channel layer is GaN, InGaN or AlGaN, and the thickness is 50nm to 500nm.

[0033] The material of the GaN transistor barrier layer is AlGaN, InGaN or AlN, and the thickness is 5nm to 50nm.

[0034] The GaN transistor source electrode and the GaN transistor drain electrode in the GaN transistor unit are stacked structures of Ti, Al, Ni and Au stacked from bottom to top; the GaN transistor gate electrode is a stacked structure of Ni and Au stacked from bottom to top; the electrode interconnection metal material is one or more of Ti, Al, Ni, Au, Cu, TiN and Ta.

[0035] In one embodiment of the present invention, the gate dielectric layer material of the diamond transistor in the diamond-based field effect transistor unit is Al2O3, MoO3, WO3, V2O5, HfO2, ZrO2, BN, and has a thickness of 1-30nm;

[0036] The material of the diamond transistor source electrode and the diamond transistor drain electrode is one or more of Ni, Al, Au, and Ti; the material of the diamond transistor gate electrode is one or more of Ti, Al, TiN, Ta, and TaN;

[0037] In one embodiment of the present invention, the GaN-based field effect transistor unit and the diamond-based field effect transistor unit are not connected, and a certain interval is reserved, wherein the certain interval refers to a minimum process size limit greater than the electrode connection metal; the isolation between the GaN-based field effect transistor unit and the diamond-based field effect transistor unit can be dielectric isolation, groove isolation, or ion implantation isolation; the gate-gate electrode connection metal and the source-drain electrode connection metal of the electrode connection metal are staggered in space front to back or up and down;

[0038] In one embodiment of the present invention, in order to improve the breakdown characteristics, the distance between the drain electrode of the GaN transistor and the gate electrode of the GaN transistor in the GaN-based field effect transistor unit is 1.5-2 times the distance between the gate electrode of the GaN transistor and the source electrode of the GaN transistor;

[0039] In one embodiment of the present invention, to improve the breakdown characteristics, the distance between the diamond transistor drain electrode and the diamond transistor gate electrode in the diamond-based field effect transistor unit is 1.5-2 times the distance between the diamond transistor gate electrode and the diamond transistor source electrode.

[0040] Beneficial technical effects of the present invention:

[0041] The present invention provides a common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device;

[0042] (1) In the common-source and common-gate enhancement-type power device, gallium nitride-based transistors and diamond-based transistors are selected; the gallium nitride-based transistor has a high two-dimensional electron gas concentration, high mobility, and low square resistance, and the gallium nitride-based channel material has a wide bandgap width, low on-resistance and on-state loss; the diamond-based transistor uses a diamond-based semiconductor structure with a high breakdown field strength, and a high two-dimensional hole gas concentration, high mobility, low on-resistance, and high device on-state current. The combined power device has the characteristics of high withstand voltage, low on-resistance, fast switching speed, and low power consumption.

[0043] (2) Diamond substrates with high thermal conductivity can effectively solve the problems of low performance and poor reliability caused by poor heat dissipation in traditional silicon-based gallium nitride transistors.

[0044] (3) By setting the enhanced gate drive control mode, GaN-based transistors effectively solve the problem of overshoot or loss of power control during the startup process of depletion-mode GaN transistor devices in actual circuits, further improving the reliability of the device.

[0045] (4) Taking advantage of the high breakdown voltage of diamond-based field-effect transistors, the enhanced gallium nitride-based transistors and diamond-based transistors are connected in series through a common source and common gate structure, further improving the voltage resistance level of the power device.

[0046] (5) The monolithic heterogeneous integrated chip is manufactured using the existing mature processes of gallium nitride and diamond, with a short process development cycle and high solution feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of a common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device provided by the present invention.

[0048] Figure 2 It is a structural diagram of a common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device provided in Example 1 of the present invention.

[0049] Figure 3 It is a structural diagram of a common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device provided by Example 2 of the present invention;

[0050] Figure 5a - Fluoride ion implantation, the remaining icon numbers represent the same meanings as Figure 2 same.

[0051] Figure 4 It is a structural diagram of a common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device provided in Example 3 of the present invention.

[0052] In the figure: d-drain; g-gate; s-source; 001-GaN-based field effect transistor unit; 002-diamond-based field effect transistor unit; 003-electrode interconnection metal; 1-diamond substrate; 2-GaN transistor transition layer; 3-GaN transistor buffer layer; 4-GaN transistor channel layer; 5-GaN transistor barrier layer; 6-dielectric passivation layer; 7-GaN transistor source electrode; 8-GaN transistor gate electrode; 9-GaN transistor drain electrode; 10-p-channel diamond layer; 11-diamond transistor gate dielectric layer; 12-diamond transistor source electrode; 13-diamond transistor gate electrode; 14-diamond transistor drain electrode; 15a-gate-source electrode connection metal; 15b-source-drain electrode connection metal; 2DEG-two-dimensional electron gas; 2DHG-two-dimensional hole gas. DETAILED DESCRIPTION

[0053] In order to make the technical solution of the present invention more clear and specific to those skilled in the art, the present invention is further described in detail below in conjunction with embodiments and drawings, but the implementation manner of the present invention is not limited thereto.

[0054] Example 1

[0055] like Figure 2 As shown, the present invention is a common source and common gate enhanced diamond and gallium nitride heterogeneous integrated power device, characterized in that it includes: a GaN-based field effect transistor unit 001, a diamond-based field effect transistor unit 002, and an electrode interconnect metal 003. The GaN-based field effect transistor unit 001 and the diamond-based field effect transistor unit 002 are arranged on the same diamond substrate 1.

[0056] The GaN-based field effect transistor unit 001 includes a diamond substrate 1, a GaN transistor transition layer 2, a GaN transistor buffer layer 3, a GaN transistor channel layer 4, a GaN transistor barrier layer 5, a dielectric passivation layer 6, a GaN transistor source electrode 7, a GaN transistor gate electrode 8, and a GaN transistor drain electrode 9; the GaN transistor transition layer 2, the GaN transistor buffer layer 3, the GaN transistor channel layer 4, and the GaN transistor barrier layer 5 are group III nitrides, and the group III nitride semiconductor is a combination of any two or more of GaN, AlN, and InN; a two-dimensional electron gas is formed between the GaN transistor channel layer 4 and the GaN transistor barrier layer 5, which is a conductive channel of the GaN transistor;

[0057] The GaN transistor transition layer 2 is located on the diamond substrate 1;

[0058] The GaN transistor buffer layer 3 is located on the GaN transistor transition layer 2;

[0059] The GaN transistor channel layer 4 is located on the GaN transistor buffer layer 3;

[0060] The GaN transistor barrier layer 5 is located on the GaN transistor channel layer 4;

[0061] The GaN transistor source electrode 7 and the GaN transistor drain electrode 9 are located on both sides above the GaN transistor barrier layer 5;

[0062] The GaN transistor gate electrode 8 is located on the GaN transistor barrier layer 5; the GaN transistor barrier layer 5 below the GaN transistor gate electrode 8 is etched to make the GaN transistor gate electrode 8 into a groove gate structure, thereby reducing the polarization charge density under the gate, suppressing the formation of a two-dimensional electron gas conductive channel under the gate when the gate voltage is zero, and realizing the enhancement mode of the GaN transistor;

[0063] The GaN transistor gate electrode 8 is the gate of the common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device;

[0064] The dielectric passivation layer 6 is located on the GaN transistor barrier layer 5 , between the GaN transistor source electrode 7 and the GaN transistor gate electrode 8 , and between the GaN transistor gate electrode 8 and the GaN transistor drain electrode 9 .

[0065] The diamond-based field effect transistor unit 002 includes a diamond substrate 1, a p-channel diamond layer 10, a diamond transistor gate dielectric layer 11, a dielectric passivation layer 6, a diamond transistor source electrode 12, a diamond transistor gate electrode 13, and a diamond transistor drain electrode 14;

[0066] The p-channel diamond layer 10 is located on the diamond substrate 1;

[0067] The upper surface of the p-channel diamond layer 10 is hydrogen-terminated, forming a two-dimensional hole gas, which is a conductive channel of the diamond transistor;

[0068] The diamond transistor source electrode 12 and the diamond transistor drain electrode 14 are located on both sides above the p-channel diamond layer 10;

[0069] The diamond transistor drain electrode 14 is the drain electrode of the common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device;

[0070] The diamond transistor gate dielectric layer 11 is located on the p-channel diamond layer 10 and between the diamond transistor source electrode 12 and the diamond transistor drain electrode 14;

[0071] The diamond transistor gate electrode 13 is located on the diamond transistor gate dielectric layer 11;

[0072] The dielectric passivation layer 6 is located on the diamond transistor gate dielectric layer 11 , between the diamond transistor source electrode 12 and the diamond transistor gate electrode 13 , and between the diamond transistor gate electrode 13 and the diamond transistor drain electrode 14 .

[0073] The electrode interconnection metal 003 includes a gate-source electrode connection metal 15a and a source-drain electrode connection metal 15b;

[0074] The gate-source electrode connection metal 15a connects the diamond transistor gate electrode 13 and the GaN transistor source electrode 7 and serves as the source of the device;

[0075] The source-drain electrode connection metal 15 b connects the diamond transistor source electrode 12 and the GaN transistor drain electrode 9 ;

[0076] For example, the material of the GaN transistor transition layer 2 is AlN, with a thickness of 50 nm to 300 nm. The GaN transistor transition layer 2 is used to release the lattice mismatch stress and thermal stress between the GaN transistor buffer layer 3 and the substrate.

[0077] In this embodiment, the material thickness of the GaN transistor transition layer 2 is 200 nm.

[0078] For example, the GaN transistor buffer layer 3 is made of undoped GaN or AlGaN, and has a thickness of 200 nm to 5 μm.

[0079] In this embodiment, the material of the GaN transistor buffer layer 3 is undoped AlGaN, and the thickness is 1500 nm.

[0080] For example, the material of the GaN transistor channel layer 4 is GaN, InGaN or AlGaN, and the thickness is 50 nm to 500 nm.

[0081] In this embodiment, the material of the GaN transistor channel layer 4 is GaN, and the thickness is 300 nm.

[0082] For example, the GaN transistor barrier layer 5 is made of AlGaN, InGaN or AlN, and has a thickness of 5 nm to 50 nm.

[0083] In this embodiment, the material of the GaN transistor barrier layer 5 is AlGaN, and the thickness is 20 nm.

[0084] For example, the GaN transistor barrier layer 5 below the GaN transistor gate electrode 8 is etched to a depth of 1 nm to 20 nm.

[0085] In this embodiment, the GaN transistor barrier layer 5 below the GaN transistor gate electrode 8 is etched to a depth of 10 nm.

[0086] For example, the GaN transistor source electrode 7 and the GaN transistor drain electrode 9 in the GaN-based field effect transistor unit 001 are stacked structures of Ti, Al, Ni and Au stacked from bottom to top;

[0087] In this embodiment, the GaN transistor source electrode 9 and the GaN transistor drain electrode 11 in the GaN-based field effect transistor unit 001 are Ti / Al / Ni / Au;

[0088] For example, the GaN transistor gate electrode 8 is a recessed gate structure formed by stacking Ni and Au from bottom to top;

[0089] In this embodiment, the material of the GaN transistor gate electrode 8 is Ni / Au;

[0090] For example, the electrode interconnection metal 003 material is one or more of Ti, Al, Ni, Au, Cu, TiN, and Ta.

[0091] In this embodiment, the material of the electrode interconnection metal 003 is Ti / Au.

[0092] For example, the material of the diamond transistor gate dielectric layer 11 in the diamond-based field effect transistor unit 002 is Al2O3, or MoO3, or WO3, or V2O5, or HfO2, or ZrO2, or BN; the thickness is 1-30nm;

[0093] In this embodiment, the material of the diamond transistor gate dielectric layer 11 in the diamond-based field effect transistor unit 002 is Al2O3, and the thickness is 3nm;

[0094] For example, the material of the diamond transistor source electrode 12 and the diamond transistor drain electrode 14 is one or more of Ni, Al, Au, and Ti;

[0095] In this embodiment, the material of the diamond transistor source electrode 12 and the diamond transistor drain electrode 14 is Ti / Au;

[0096] For example, the material of the diamond transistor gate electrode 13 is one or more of Ti, Al, TiN, Ta, and TaN;

[0097] In this embodiment, the material of the diamond transistor gate electrode 13 is Ti / Au;

[0098] For example, the GaN-based field effect transistor unit 001 and the diamond-based field effect transistor unit 002 are not connected, and a certain interval is retained, and the certain interval refers to a distance greater than the minimum process size limit of the electrode interconnection metal 003; the isolation between the GaN-based field effect transistor unit 001 and the diamond-based field effect transistor unit 002 can be dielectric isolation, groove isolation, or ion implantation isolation; the gate-source electrode connection metal 15a and the source-drain electrode connection metal 15b of the electrode interconnection metal 003 are staggered in space.

[0099] For example, to improve the breakdown characteristics, the distance between the GaN transistor drain electrode 9 and the GaN transistor gate electrode 8 in the GaN-based field effect transistor unit 001 is 1.5-2 times the distance between the GaN transistor gate electrode 8 and the GaN transistor source electrode 7 .

[0100] For example, to improve the breakdown characteristics, the distance between the diamond transistor drain electrode 14 and the diamond transistor gate electrode 13 in the diamond-based field effect transistor unit 002 is 1.5-2 times the distance between the diamond transistor gate electrode 13 and the diamond transistor source electrode 12 .

[0101] Example 2

[0102] like Figure 3 As shown, in this embodiment, the GaN transistor barrier layer 5 directly below the GaN transistor gate electrode 8 in the GaN-based field effect transistor unit 001 is subjected to fluorine ion implantation 5a to obtain an enhanced GaN-based field effect transistor;

[0103] Exemplarily, the fluorine ion implantation 5a is incorporated into the GaN transistor barrier layer 5 by carbon tetrafluoride CF4 plasma treatment;

[0104] The remaining features are the same as those in Example 1 and will not be described again here.

[0105] Example 3

[0106] like Figure 4 As shown, in this embodiment, a p-GaN cap layer 8a is inserted between the GaN transistor gate electrode 8 and the GaN transistor barrier layer 5 directly below in the GaN-based field effect transistor unit 001 to obtain an enhanced GaN-based field effect transistor;

[0107] For example, the material of the p-GaN layer 8a is one or more of Mg-doped GaN, InN, AlGaN, and InGaN; the thickness is 50-150nm;

[0108] In this embodiment, the material of the p-GaN layer 8a is Mg-doped GaN, and the thickness is 100 nm.

[0109] The above description is only a further embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and concepts of the present invention within the scope disclosed by the present invention, which belong to the protection scope of the present invention.

Claims

1. A common source and common gate enhanced diamond and gallium nitride heterogeneous integrated power device, characterized in that: include: GaN-based field effect transistor unit (001), diamond-based field effect transistor unit (002), electrode interconnection metal (003); A GaN-based field effect transistor unit (001) and a diamond-based field effect transistor unit (002) are arranged on the same diamond substrate (1); The GaN-based field effect transistor unit (001) is an enhancement-type transistor, the diamond-based field effect transistor unit (002) is a depletion-type transistor, and the GaN-based field effect transistor unit (001) and the diamond-based field effect transistor unit (002) form a common source and common gate structure through an electrode interconnection metal (003), thereby realizing an enhancement-type power device.

2. The cascode enhancement mode diamond and gallium nitride heterogeneous integrated power device according to claim 1, characterized in that: The GaN-based field effect transistor unit (001) comprises a diamond substrate (1), a GaN transistor transition layer (2), a GaN transistor buffer layer (3), a GaN transistor channel layer (4), a GaN transistor barrier layer (5), a dielectric passivation layer (6), a GaN transistor source electrode (7), a GaN transistor gate electrode (8), and a GaN transistor drain electrode (9); the GaN transistor transition layer (2), the GaN transistor buffer layer (3), the GaN transistor channel layer (4), and the GaN transistor barrier layer (5) are group III nitrides, and the group III nitride semiconductor is a combination of any two or more of GaN, AlN, and InN; a two-dimensional electron gas is formed between the GaN transistor channel layer (4) and the GaN transistor barrier layer (5), which is a conductive channel of the GaN transistor; The GaN transistor transition layer (2) is located on the diamond substrate (1); The GaN transistor buffer layer (3) is located on the GaN transistor transition layer (2); The GaN transistor channel layer (4) is located on the GaN transistor buffer layer (3); The GaN transistor barrier layer (5) is located on the GaN transistor channel layer (4); The GaN transistor source electrode (7) and the GaN transistor drain electrode (9) are located on both sides above the GaN transistor barrier layer (5); The GaN transistor gate electrode (8) is located on the GaN transistor barrier layer (5); The GaN transistor barrier layer (5) is subjected to certain processing at a portion below the GaN transistor gate electrode (8), such as a groove gate structure, fluorine ion implantation, and insertion of a p-GaN cap layer, so that the GaN transistor is in an enhanced working mode; The GaN transistor gate electrode (8) is the gate of the common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device; The GaN transistor source electrode (7) is the source electrode of the common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device; The dielectric passivation layer (6) is located on the GaN transistor barrier layer (5), between the GaN transistor source electrode (7) and the GaN transistor gate electrode (8), and between the GaN transistor gate electrode (8) and the GaN transistor drain electrode (9).

3. The cascode enhancement mode diamond and gallium nitride heterogeneous integrated power device according to claim 1, characterized in that: The diamond-based field effect transistor unit (002) comprises a diamond substrate (1), a p-channel diamond layer (10), a diamond transistor gate dielectric layer (11), a dielectric passivation layer (6), a diamond transistor source electrode (12), a diamond transistor gate electrode (13), and a diamond transistor drain electrode (14); The p-channel diamond layer (10) is located on the diamond substrate (1); The upper surface of the p-channel diamond layer (10) is a hydrogen terminal, forming a two-dimensional hole gas 2DHG, which is a conductive channel of the diamond transistor; The diamond transistor source electrode (12) and the diamond transistor drain electrode (14) are located on both sides above the p-channel diamond layer (10); The diamond transistor drain electrode (14) is the drain electrode of the common-source and common-gate enhanced diamond and gallium nitride heterogeneous integrated power device; The diamond transistor gate dielectric layer (11) is located on the p-channel diamond layer (10) and between the diamond transistor source electrode (12) and the diamond transistor drain electrode (14); The diamond transistor gate electrode (13) is located on the diamond transistor gate dielectric layer (11); The dielectric passivation layer (6) is located on the diamond transistor gate dielectric layer (11), between the diamond transistor source electrode (12) and the diamond transistor gate electrode (13), and between the diamond transistor gate electrode (13) and the diamond transistor drain electrode (14).

4. The commingled-source and commingled-gate enhanced diamond and gallium nitride heterogeneous integrated power device according to claim 1, characterized in that: The electrode interconnection metal (003) includes a gate-source electrode connection metal (15a) and a source-drain electrode connection metal (15b); The gate-source electrode connecting metal (15a) connects the diamond transistor gate electrode (13) and the GaN transistor source electrode (7) and serves as the source of the device; The source-drain electrode connection metal (15b) connects the diamond transistor source electrode (12) and the GaN transistor drain electrode (9).

5. The cascode enhanced diamond and gallium nitride heterogeneous integrated power device according to claim 2, characterized in that: The material of the GaN transistor transition layer (2) is AlN, and the thickness is 50nm-300nm. The GaN transistor transition layer (2) is used to release the lattice mismatch stress and thermal stress between the GaN transistor buffer layer (3) and the diamond substrate (1); The material of the GaN transistor buffer layer (3) is undoped GaN or AlGaN, and the thickness is 200nm to 5μm; The material of the GaN transistor channel layer (4) is GaN, InGaN or AlGaN, and the thickness is 50nm to 500nm; The GaN transistor barrier layer (5) is made of AlGaN, InGaN or AlN, and has a thickness of 5 nm to 50 nm; The GaN transistor source electrode (7) and the GaN transistor drain electrode (9) in the GaN-based field effect transistor unit (001) are stacked structures of Ti, Al, Ni and Au stacked from bottom to top; the GaN transistor gate electrode (8) is a stacked structure of Ni and Au stacked from bottom to top; and the electrode interconnection metal (003) material is one or more of Ti, Al, Ni, Au, Cu, TiN and Ta.

6. The cascode enhancement mode diamond and gallium nitride heterogeneous integrated power device according to claim 3, characterized in that: The diamond transistor gate dielectric layer (11) in the diamond-based field effect transistor unit (002) is made of Al2O3, or MoO3, or WO3, V2O5, HfO2, ZrO2, or BN; and has a thickness of 1-30 nm; The material of the diamond transistor source electrode (12) and the diamond transistor drain electrode (14) is one or more of Ni, Al, Au and Ti; The material of the diamond transistor gate electrode (13) is one or more of Ti, Al, TiN, Ta and TaN.

7. The cascode enhancement mode diamond and gallium nitride heterogeneous integrated power device according to claim 1, characterized in that: The GaN-based field effect transistor unit (001) and the diamond-based field effect transistor unit (002) are not connected and a gap is retained; The isolation between the GaN-based field effect transistor unit (001) and the diamond-based field effect transistor unit (002) may be dielectric isolation, groove isolation, or ion implantation isolation; The gate-source electrode connection metal (15a) and the source-drain electrode connection metal (15b) of the electrode interconnection metal (003) are staggered in space front to back or up to down.

8. The cascode enhancement mode diamond and gallium nitride heterogeneous integrated power device according to claim 2, characterized in that: The distance between the GaN transistor drain electrode (9) and the GaN transistor gate electrode (8) in the GaN-based field effect transistor unit (001) is 1.5-2 times the distance between the GaN transistor gate electrode (8) and the GaN transistor source electrode (7).

9. The cascode enhancement mode diamond and gallium nitride heterogeneous integrated power device according to claim 3, characterized in that: To improve the breakdown characteristics, the distance between the diamond transistor drain electrode (14) and the diamond transistor gate electrode (13) in the diamond-based field effect transistor unit (002) is 1.5-2 times the distance between the diamond transistor gate electrode (13) and the diamond transistor source electrode (12).

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