Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for reducing the integration difficulty of the semiconductor device and improving the yield and the working performance of the semiconductor device. The semiconductor device includes a semiconductor substrate, a first gate-all-around transistor and a second gate-all-around transistor. A material of a first channel region included in the first gate-all-around transistor is different from a material of a second channel region included in the second gate-all-around transistor. And each layer of nano structure of the first channel region and the corresponding layer of nano structure of the second channel region are distributed in a staggered manner along the thickness direction of the semiconductor substrate. The thickness of each layer of nano structure of the second channel region is roughly the same in different regions in the length direction of the second channel region. And the thickness of the nanostructure included in the second channel region is H1. A first gap is formed between the bottom nanostructure in the first channel region and the semiconductor substrate, the thickness of a first gate stack structure included in the first gate-all-around transistor at least located at the first gap is H2, and H1 is smaller than H2.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, the ring-gate transistor has emerged. Because the gate stack structure of the ring-gate transistor is not only formed on the top and sidewalls of the channel region, but also on the bottom of the channel region, compared with the planar transistor and the fin field effect transistor, the ring-gate transistor has a stronger gate control capability, which is conducive to suppressing the short channel effect.

[0003] However, when the semiconductor device includes two types of all-around gate transistors with different channel region materials, the integration of the semiconductor device is difficult, which is not conducive to improving the working performance of the semiconductor device. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to reduce the integration difficulty of the semiconductor device and improve the yield and working performance of the semiconductor device.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a semiconductor device, which includes: a semiconductor substrate, a first all-round gate transistor and a second all-round gate transistor. The material of the first channel region included in the first all-round gate transistor is different from the material of the second channel region included in the second all-round gate transistor. The first all-round gate transistor and the second all-round gate transistor are arranged on the semiconductor substrate at intervals along a direction parallel to the surface of the semiconductor substrate. Each layer of nanostructures in the first channel region is staggered with the corresponding layer of nanostructures in the second channel region along the thickness direction of the semiconductor substrate. The thickness of each layer of nanostructures in the first channel region along different regions of its own length direction is roughly the same. The thickness of each layer of nanostructures in the second channel region along different regions of its own length direction is roughly the same. Among them, the thickness of the nanostructure included in the second channel region is H1. There is a first gap between the bottom nanostructure in the first channel region and the semiconductor substrate, and the thickness of the first gate stack structure included in the first all-round gate transistor at least at the first gap is H2, and H1 is less than H2.

[0006] In the case of adopting the above technical solution, in the semiconductor device provided by the present invention, a first ring-gate transistor and a second ring-gate transistor are spaced apart on the semiconductor substrate. In addition, the material of the first channel region included in the first ring-gate transistor is different from the material of the second channel region included in the second ring-gate transistor, so as to meet the different requirements for the first ring-gate transistor and the second ring-gate transistor in the actual application scenario. For example: the requirement for different threshold voltages for the first ring-gate transistor and the second ring-gate transistor. Another example: the requirement for different conduction performance of the channel regions of the first ring-gate transistor and the second ring-gate transistor of opposite conductivity types, etc. In addition, in the actual manufacturing process, because the materials of the first channel region and the second channel region are different, and each layer of nanostructures in the first channel region is staggered with the corresponding layer of nanostructures in the second channel region along the thickness direction of the semiconductor substrate, the first ring-gate transistor and the second ring-gate transistor can also be manufactured together by using the first semiconductor layer used to manufacture the first channel region and the second semiconductor layer used to manufacture the second channel region as sacrificial layers / channel layers to simplify the manufacturing process of the semiconductor device, improve the manufacturing efficiency of the semiconductor device, and help control the manufacturing cost of the semiconductor device.

[0007] Furthermore, the thickness of each layer of nanostructures in the first channel region is substantially the same in different regions along its length direction, and the thickness of each layer of nanostructures in the second channel region is substantially the same in different regions along its length direction. In addition, the thickness of the nanostructure included in the second channel region is defined as H1. There is a first gap between the bottom nanostructure and the semiconductor substrate in the first channel region, and the thickness of the first gate stack structure included in the first ring-gate transistor is at least H2 at the first gap. Based on this, H1 is less than H2. At this time, although the first ring-gate transistor and the second ring-gate transistor are manufactured together by the above-mentioned first semiconductor layer and the second semiconductor layer serving as sacrificial layers / channel layers, there will be no problem that the second gate stack structure included in the second ring-gate transistor cannot be filled due to the thickness difference between the first semiconductor layer and the second semiconductor layer, thereby improving the yield and working performance of the semiconductor device. Furthermore, while the nanostructure included in the second channel region is thinned so that H1 is smaller than H2, since the thickness of each layer of the nanostructure in the second channel region is roughly the same in different regions along its length direction, even if the second ring-gate transistor includes an inner side wall, the height of the inner side wall can be equal to the thickness of the second gate stack structure, so that there is a smaller parasitic capacitance between the second source / drain region and the second gate stack structure, thereby improving the yield and operating performance of the semiconductor device.

[0008] In one example, the first ring-gate transistor and the second ring-gate transistor also include inner sidewalls. In the first ring-gate transistor, the inner sidewall is located between the first gate stack structure and the first source / drain region. The height of the inner sidewall included in the first ring-gate transistor is H3, and H3 is equal to H2. In the second ring-gate transistor, the inner sidewall is located between the second gate stack structure and the second source / drain region. There is a second gap between the underlying nanostructure and the semiconductor substrate in the second channel region, and the second gate stack structure included in the second ring-gate transistor has a thickness of H4 at least at the second gap, and the height of the inner sidewall included in the second ring-gate transistor is H5, and H5 is equal to H4.

[0009] In one example, H3 is different from H5.

[0010] In one example, a thickness of a portion of the semiconductor substrate located below the second all-around gate transistor is smaller than a thickness of a portion of the semiconductor substrate located below the first all-around gate transistor.

[0011] In one example, the second all-around gate transistor includes multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate. In the second all-around gate transistor, the spacing between the nanostructures at the bottom layer and the semiconductor substrate is less than or equal to the spacing between two adjacent nanostructures.

[0012] In one example, the first gate-all-around transistor and the second gate-all-around transistor have opposite conductivity types.

[0013] In one example, the conductivity type of the first all-around gate transistor is N-type, and the conductivity type of the second all-around gate transistor is P-type.

[0014] In one example, the material of the first channel region includes silicon or silicon germanium, the material of the second channel region includes silicon germanium or germanium, and the germanium content in the material of the second channel region is greater than the germanium content in the material of the first channel region.

[0015] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising: first, providing a semiconductor substrate. Next, forming a first gate-all-around transistor and a second gate-all-around transistor on the semiconductor substrate. The first gate-all-around transistor and the second gate-all-around transistor are arranged on the semiconductor substrate in a direction parallel to the surface of the semiconductor substrate. The material of the first channel region included in the first gate-all-around transistor is different from the material of the second channel region included in the second gate-all-around transistor. Each layer of nanostructures in the first channel region is staggered with the corresponding layer of nanostructures in the second channel region along the thickness direction of the semiconductor substrate. The thickness of each layer of nanostructures in the first channel region along different regions of its own length direction is substantially the same. The thickness of each layer of nanostructures in the second channel region along different regions of its own length direction is substantially the same. Wherein, the thickness of the nanostructures included in the second channel region is H1. There is a first gap between the bottom nanostructure in the first channel region and the semiconductor substrate, and the thickness of the first gate stack structure included in the first gate-all-around transistor at least at the first gap is H2, and H1 is less than H2.

[0016] In one example, a first ring-gate transistor and a second ring-gate transistor are formed on a semiconductor substrate, including: forming a first fin structure and a second fin structure that are spaced and have the same structure on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the first fin structure and the second fin structure both include a first semiconductor layer and a second semiconductor layer that are alternately arranged. In the alternately arranged first semiconductor layer and the second semiconductor layer, the film layer located at the bottom is the second semiconductor layer, and the thickness of the second semiconductor layer is greater than the thickness of the first semiconductor layer. The material of the second semiconductor layer is different from the material of the semiconductor substrate close to the second semiconductor layer and the material of the first semiconductor layer. Next, a mask structure is formed across the first fin structure and the second fin structure. Next, the portion of the first fin structure exposed outside the mask structure is processed to form a first source / drain region included in the first ring-gate transistor. Next, at least a portion of the mask structure corresponding to the first fin structure is removed, and each layer of the second semiconductor layer in the remaining first fin structure is removed, so that each layer of the first semiconductor layer in the remaining first fin structure forms a corresponding layer of nanostructure included in the first channel region. Next, the portion of the second fin structure exposed outside the mask structure is removed, and a portion of the semiconductor substrate is continuously etched downward. After the semiconductor substrate is etched, the protruding portion remaining under the second fin structure is a sacrificial layer. Next, the first semiconductor layer included in the remaining second fin structure is removed, and the sacrificial layer is removed; and the second semiconductor layer included in the remaining second fin structure is thinned to form a first dielectric filling area. Next, a first dielectric layer is formed in the first dielectric filling area. Next, a second source / drain region included in a second ring-gate transistor is formed on both sides of the remaining second fin structure along the length direction. Next, at least part of the mask structure corresponding to the second fin structure is removed, and the first dielectric layer is removed, so that each second semiconductor layer in the remaining second fin structure forms a corresponding layer of nanostructure included in the second channel region.

[0017] In one example, a portion of the first fin structure exposed outside the mask structure is processed to form a first source / drain region included in a first all-around gate transistor, including: removing the portion of the first fin structure exposed outside the mask structure. Next, removing the edge portions of both sides of each second semiconductor layer in the remaining first fin structure along the length direction to form a second dielectric filling region. Next, an inner sidewall included in the first all-around gate transistor is formed in the second dielectric filling region.

[0018] In one example, after forming the first dielectric layer in the first dielectric filling region, before forming the second source / drain region included in the second all-around gate transistor on both sides of the remaining second fin structure along the length direction, the method for manufacturing the semiconductor device further includes: removing the edge portions on both sides of the first dielectric layer along the length direction to form a third dielectric filling region. Next, forming the inner sidewall included in the second all-around gate transistor in the third dielectric filling region.

[0019] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0021] Figure 1 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 1 ;

[0022] Figure 2 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 2 ;

[0023] Figure 3 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 3 ;

[0024] Figure 4 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 4 ;

[0025] Figure 5 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 5 ;

[0026] Figure 6 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 6 ;

[0027] Figure 7 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 7 ;

[0028] Figure 8 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 8 ;

[0029] Fig. 9 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 9 ;

[0030] Fig.10 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 ;

[0031] Fig.11 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 one;

[0032] Fig.12 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 two;

[0033] Fig.13 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 three;

[0034] Fig.14 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 Four;

[0035] Fig.15 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 five;

[0036] Fig.16 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 six;

[0037] Fig.17 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 seven;

[0038] Fig.18 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 eight;

[0039] Fig.19 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 10 Nine;

[0040] Fig. 20 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 2 ten;

[0041] Fig.21 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 2 eleven;

[0042] Fig. 22 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 2 twelve;

[0043] Fig.23 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 2 Thirteen;

[0044] Fig.24 Schematic diagram of the results of the semiconductor device provided in the embodiment of the present invention during the manufacturing process Figure 2 fourteen.

[0045] Figure numerals: 11 is a semiconductor substrate, 12 is a first ring-gate transistor, 13 is a second ring-gate transistor, 14 is a first channel region, 15 is a second channel region, 16 is a first gap, 17 is a first gate stack structure, 18 is a first source / drain region, 19 is a second gap, 20 is a second gate stack structure, 21 is a second source / drain region, 22 is an inner sidewall, 23 is a shallow trench isolation structure, 24 is a gate sidewall, 25 is an interlayer dielectric layer, 26 is a first fin structure, 27 is a second fin structure, 28 is a first semiconductor layer, 29 is a second semiconductor layer, 30 is a mask structure, 31 is a sacrificial layer, 32 is a first dielectric filling region, 33 is a first dielectric layer, 34 is a second dielectric filling region, and 35 is a third dielectric filling region. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0047] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0048] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0050] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0051] With the development of semiconductor technology, the ring-gate transistor has emerged. Because the gate stack structure of the ring-gate transistor is not only formed on the top and sidewalls of the channel region, but also on the bottom of the channel region, compared with the planar transistor and the fin field effect transistor, the ring-gate transistor has a stronger gate control capability, which is conducive to suppressing the short channel effect.

[0052] However, when the semiconductor device includes two types of ring-gate transistors (first ring-gate transistor and second ring-gate transistor) with different channel region materials, the integration difficulty of the semiconductor device is relatively high, which is not conducive to improving the working performance of the semiconductor device.

[0053] Specifically, in order to improve the manufacturing efficiency of semiconductor devices and control the manufacturing cost of semiconductor devices, two types of ring-gate transistors with different channel region materials are usually formed on the same semiconductor substrate by using a first semiconductor layer (the first semiconductor layer is used to manufacture the first channel region included in the first ring-gate transistor) and a second semiconductor layer (the second semiconductor layer is used to manufacture the second channel region included in the second ring-gate transistor) as sacrificial layers / channel layers. However, for the first ring-gate transistor, the second semiconductor layer is a sacrificial layer for releasing the nanostructure, and a space for filling the first gate stack structure included in the first ring-gate transistor will be formed by removing part of the second semiconductor layer. Compared with the thickness of the nanostructure included in the first channel region, the first gate stack structure filled between the underlying nanostructure and the semiconductor substrate, and / or, the thickness filled in the gap between two adjacent nanostructures is greater, so the thickness of the first semiconductor layer is smaller, while the thickness of the second semiconductor layer is larger. This will result in that in the second ring-gate transistor manufactured using the same first semiconductor layer and second semiconductor layer as the first ring-gate transistor, the thickness of the second semiconductor layer used to manufacture the nanostructure included in the second channel region is larger, while the thickness of the first semiconductor layer used to release the nanostructure included in the second channel region is smaller, which in turn causes the thicker second gate stack structure included in the second ring-gate transistor to be unable to normally fill the smaller space released by removing part of the first semiconductor layer, resulting in high difficulty in integrating the semiconductor device, which is not conducive to improving the working performance of the semiconductor device.

[0054] In view of the above technical problems, those skilled in the art, after removing the sacrificial gate and the first semiconductor layer corresponding to the second all-around gate transistor and located in the gate formation region, thin the second semiconductor layer with a larger thickness located in the gate formation region, so that the second gate stack structure can be filled normally. However, before the thinning process, specifically, before forming the second source / drain region included in the second all-around gate transistor, the inner sidewall included in the second all-around gate transistor is formed. Figure 1 As shown, the height of the inner sidewall 22 is equal to the thickness of the first semiconductor layer with a smaller thickness, and is less than the thickness of the second gate stack structure 20 filling the gap, resulting in a large parasitic capacitance between the second source / drain region 21 and the second gate stack structure 20, which is not conducive to improving the working performance of the semiconductor device.

[0055] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. In the semiconductor device provided in the embodiment of the present invention, the material of the first channel region included in the first ring-gate transistor is different from the material of the second channel region included in the second ring-gate transistor, and each layer of nanostructure in the first channel region is staggered with the corresponding layer of nanostructure in the second channel region along the thickness direction of the semiconductor substrate. The first ring-gate transistor and the second ring-gate transistor can be manufactured together by using the first semiconductor layer used to manufacture the first channel region and the second semiconductor layer used to manufacture the second channel region as sacrificial layers / channel layers. In addition, the thickness H1 of the nanostructure included in the second channel region is less than the thickness H2 of the first gate stack structure included in the first ring-gate transistor at least at the first gap, so as to improve the yield and working performance of the semiconductor device.

[0056] Specifically, in a first aspect, an embodiment of the present invention provides a semiconductor device. Fig.24 As shown, the semiconductor device includes: a semiconductor substrate 11, a first all-round gate transistor 12 and a second all-round gate transistor 13. The material of the first channel region 14 included in the first all-round gate transistor 12 is different from the material of the second channel region 15 included in the second all-round gate transistor 13. The first all-round gate transistor 12 and the second all-round gate transistor 13 are arranged on the semiconductor substrate 11 in a direction parallel to the surface of the semiconductor substrate 11. Each layer of nanostructures in the first channel region 14 is staggered with the corresponding layer of nanostructures in the second channel region 15 along the thickness direction of the semiconductor substrate 11. The thickness of each layer of nanostructures in the first channel region 14 in different regions along its own length direction is roughly the same. The thickness of each layer of nanostructures in the second channel region 15 in different regions along its own length direction is roughly the same. Among them, the thickness of the nanostructures included in the second channel region 15 is H1. There is a first gap 16 between the bottom nanostructure in the first channel region 14 and the semiconductor substrate 11, and the thickness of the first gate stack structure 17 included in the first all-round gate transistor 12 at least at the first gap 16 is H2, and H1 is less than H2.

[0057] In the actual application process, the specific structure of the above-mentioned semiconductor substrate can be set according to the actual application scenario, and is not specifically limited here. For example, the semiconductor substrate provided in the embodiment of the present invention can be a semiconductor substrate such as silicon, silicon germanium, germanium, etc. without any structure formed. Alternatively, the semiconductor substrate can also be a semiconductor substrate formed with some structures. For example: when the semiconductor device provided in the embodiment of the present invention is a second-layer or higher-layer device in an integrated circuit, the semiconductor substrate includes a semiconductor structure located below the first ring-gate transistor and the second ring-gate transistor, etc.

[0058] In addition, from the perspective of surface morphology, the thickness of the portion of the semiconductor substrate located below the second all-round gate transistor may be equal to the thickness of the portion of the semiconductor substrate located below the first all-round gate transistor. Alternatively, the thickness of the portion of the semiconductor substrate located below the second all-round gate transistor may be less than the thickness of the portion of the semiconductor substrate located below the first all-round gate transistor. It is understandable that if, in the actual manufacturing process, the first all-round gate transistor and the second all-round gate transistor are manufactured together in a manner where the second semiconductor layer used to manufacture the second channel region is a sacrificial layer / channel layer, the second semiconductor layer located at the bottom layer is in direct contact with the semiconductor substrate. For the second all-round gate transistor, the bottom second semiconductor layer is used to manufacture the bottom nanostructure. Therefore, when the thickness of the portion of the semiconductor substrate located below the second all-round gate transistor is less than the thickness of the portion of the semiconductor substrate located below the first all-round gate transistor, the second semiconductor layer located at the bottom layer may be released by etching the thickness of the portion of the semiconductor substrate located below the second channel region, thereby ensuring that the second gate stack structure can surround the periphery of the nanostructure located at the bottom layer in the second channel region, thereby improving the gate control capability of the second all-round gate transistor, and further improving the working performance of the semiconductor device.

[0059] As for the difference between the thickness of the portion of the semiconductor substrate located below the second ring-gate transistor and the thickness of the portion of the semiconductor substrate located below the first ring-gate transistor, it can be determined based on the thickness of the first semiconductor layer and the second semiconductor layer, and the thickness of the second gate stack structure, and is not specifically limited here.

[0060] For the first ring-gate transistor and the second ring-gate transistor, from the aspect of the conductivity type, the embodiment of the present invention does not specifically limit the conductivity type of the first ring-gate transistor and the second ring-gate transistor. The conductivity type of the first ring-gate transistor and the second ring-gate transistor can be the same; in other words, the conductivity type of the first ring-gate transistor and the second ring-gate transistor can both be N-type or P-type. Alternatively, the conductivity types of the first ring-gate transistor and the second ring-gate transistor can also be opposite. In this case, the conductivity types of the first ring-gate transistor and the second ring-gate transistor can be determined according to the actual application scenario, and are not specifically limited here. For example: the conductivity type of the first ring-gate transistor can be N-type, and the conductivity type of the second ring-gate transistor is P-type. For another example: the conductivity type of the first ring-gate transistor can be P-type, and the conductivity type of the second ring-gate transistor can be N-type.

[0061] From a structural perspective, Fig.24As shown in part (1) of the figure, the first ring-gate transistor 12 includes a first source / drain region 18, a first channel region 14 and a first gate stack structure 17. The first channel region 14 is located between the first source / drain regions 18, and the first channel region 14 is in contact with the first source / drain region 18 at both ends along the length direction of the first gate stack structure 17. The first channel region 14 may include only one layer of nanostructure, or may include multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate 11. When the first channel region 14 includes multiple layers of nanostructures, the gap between the bottom nanostructure and the semiconductor substrate 11, and the gap between two adjacent layers of nanostructures are both first gaps 16. The size of the first gap 16 can be set according to actual needs, as long as H1 is less than H2.

[0062] Specifically, the material of the first source / drain region may include any semiconductor material such as silicon, silicon germanium or germanium. The material of the first channel region may include any semiconductor material different from that of the second channel region. The specific material type of the first channel region can be determined according to the requirements for the conductivity type and threshold voltage of the first ring-gate transistor in the actual application scenario, and is not specifically limited here.

[0063] The first gate stack structure may include a first gate dielectric layer and a first gate. The first gate dielectric layer surrounds the periphery of each layer of nanostructures included in the first channel region, and covers the portion of the semiconductor substrate corresponding to the first gate formation region. The first gate is located on the first gate dielectric layer. The material of the first gate dielectric layer may be an insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the first gate may be a conductive material such as TiN, TaN or TiSiN.

[0064] In addition, if Fig.24 As shown in part (1) of the figure, the first all-round gate transistor 12 may further include an inner sidewall 22. In the first all-round gate transistor 12, the inner sidewall 22 is located between the first gate stack structure 17 and the first source / drain region 18. Moreover, the height of the inner sidewall 22 included in the first all-round gate transistor 12 is H3, and H3 is equal to H2, so that there is a relatively small parasitic capacitance between the first source / drain region 18 and the first gate stack structure 17, thereby improving the working performance of the first all-round gate transistor 12. Among them, the material of the inner sidewall 22 included in the first all-round gate transistor 12 may include any insulating material such as silicon oxide, silicon nitride or silicon oxynitride, as long as it can be applied to the semiconductor device provided in the embodiment of the present invention.

[0065] As for the second gate-all-around transistor, Fig.24As shown in part (2) of the figure, the second ring-gate transistor 13 includes a second source / drain region 21, a second channel region 15 and a second gate stack structure 20. The second channel region 15 is located between the second source / drain regions 21, and the second channel region 15 is in contact with the second source / drain region 21 at both ends along the length direction of the second gate stack structure 20. The second channel region 15 may include only two layers of nanostructures, or may include multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate 11. When the second channel region 15 includes multiple layers of nanostructures, the gap between the bottom nanostructure and the semiconductor substrate 11, and the gap between two adjacent layers of nanostructures are both second gaps 19. The size of the second gap 19 can be set according to actual needs, as long as it is applied to the semiconductor device provided in the embodiment of the present invention.

[0066] When the second ring-gate transistor includes multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate, in the second ring-gate transistor, the spacing between the bottom nanostructure and the semiconductor substrate can be less than, equal to, or greater than the spacing between two adjacent nanostructures, as long as the second gate stack structure can be normally filled between the bottom nanostructure included in the second channel region and the semiconductor substrate.

[0067] Among them, the materials of the second source / drain region and the second gate stack structure can refer to the materials of the first source / drain region and the first gate stack structure described above, respectively, and will not be repeated here. Specifically, the materials of the second source / drain region and the first source / drain region can be the same or different. The materials of the second gate stack structure and the first gate stack structure can be the same or different.

[0068] The material of the second channel region may include any semiconductor material different from that of the first channel region. The specific material type of the second channel region may be determined according to the requirements for the conductivity type and threshold voltage of the second all-around gate transistor in the actual application scenario, and is not specifically limited here.

[0069] Exemplarily, the material of the first channel region may include silicon or silicon germanium, the material of the second channel region may include silicon germanium or germanium, and the germanium content in the material of the second channel region is greater than the germanium content in the material of the first channel region. In this case, if the conductivity type of the first all-around gate transistor is N-type, and the conductivity type of the second all-around gate transistor is P-type, the first channel region and the second channel region can both have higher carrier mobility, further improving the working performance of the semiconductor device.

[0070] As for the specific difference in the germanium content in the first channel region and the second channel region, it can be set according to actual needs and is not specifically limited here. For example, the germanium content in the material of the second channel region is at least 20% higher than the germanium content in the material of the first channel region, so as to improve the etching selectivity between the first semiconductor layer and the second semiconductor layer, and further improve the yield of the semiconductor device.

[0071] For example, Fig.24 As shown in part (2) of the figure, the second all-round gate transistor 13 may further include an inner sidewall 22. In the second all-round gate transistor 13, the inner sidewall 22 is located between the second gate stack structure 20 and the second source / drain region 21. Secondly, there is a second gap between the underlying nanostructure in the second channel region 15 and the semiconductor substrate 11. Based on this, the thickness of the second gate stack structure 20 included in the second all-round gate transistor 13 at least at the second gap is defined as H4, and the height of the inner sidewall 22 included in the second all-round gate transistor 13 is defined as H5, and H5 is equal to H4, so that there is a relatively small parasitic capacitance between the second source / drain region 21 and the second gate stack structure 20, thereby improving the working performance of the second all-round gate transistor 13.

[0072] In addition, when both the first gate-all-around transistor and the second gate-all-around transistor include inner sidewalls, the height H3 of the inner sidewalls included in the first gate-all-around transistor may be equal to the height H5 of the inner sidewalls included in the second gate-all-around transistor. Alternatively, H3 may also be different from H5. The specific heights of the inner sidewalls included in the first gate-all-around transistor and the second gate-all-around transistor may be determined according to the thickness of the first gate stack structure at the first gap and the thickness of the second gate stack structure at the second gap, respectively, and are not specifically limited here.

[0073] The material of the inner sidewall of the second all-around gate transistor may refer to the material of the inner sidewall of the first all-around gate transistor mentioned above, and will not be described in detail here.

[0074] In some cases, such as Fig.24 As shown, the semiconductor device may further include gate sidewalls 24 located on both sides of the first gate stack structure 17 and / or the second gate stack structure 20 along its length direction to isolate the first gate stack structure 17 and / or the second gate stack structure 20 from other conductive structures to ensure that the semiconductor device has stable electrical characteristics.

[0075] In some cases, such as Figure 6 and Fig.24As shown, the semiconductor device provided by the embodiment of the present invention may also include a shallow trench isolation structure 23 and / or an interlayer dielectric layer 25. The shallow trench isolation structure 23 is located on the semiconductor substrate 11, and is used to isolate different active areas of the semiconductor substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 23 can be set according to actual conditions. The interlayer dielectric layer 25 covers the semiconductor substrate 11, and its top is flush with the top of the first gate stack structure 17 and the second gate stack structure 20, and is used to protect the first source / drain region 18 and the second source / drain region 21 from being affected by operations such as etching and cleaning when removing the sacrificial gate.

[0076] The material of at least one of the gate sidewall, the shallow trench isolation structure and the interlayer dielectric layer may be an insulating material such as SiN, Si3N4, SiO2 or SiCO.

[0077] From the above content, we can see that Fig.24 As shown, in the semiconductor device provided by the embodiment of the present invention, a first all-round gate transistor 12 and a second all-round gate transistor 13 are spaced apart on a semiconductor substrate 11. Moreover, the material of the first channel region 14 included in the first all-round gate transistor 12 is different from the material of the second channel region 15 included in the second all-round gate transistor 13, so as to meet different requirements for the first all-round gate transistor 12 and the second all-round gate transistor 13 in actual application scenarios. For example: the requirement for different threshold voltages for the first all-round gate transistor 12 and the second all-round gate transistor 13. Another example: the requirement for different conduction performance of the channel regions of the first all-round gate transistor 12 and the second all-round gate transistor 13 of opposite conductivity types, etc. In addition, in the actual manufacturing process, since the materials of the first channel region 14 and the second channel region 15 are different, and each layer of nanostructures of the first channel region 14 is staggered with the corresponding layer of nanostructures of the second channel region 15 along the thickness direction of the semiconductor substrate 11, the first ring-gate transistor 12 and the second ring-gate transistor 13 can be manufactured together by using the first semiconductor layer 28 used to manufacture the first channel region 14 and the second semiconductor layer 29 used to manufacture the second channel region 15 as sacrificial layers / channel layers to simplify the manufacturing process of the semiconductor device, improve the manufacturing efficiency of the semiconductor device, and help control the manufacturing cost of the semiconductor device.

[0078] Furthermore, if Fig.24As shown, the thickness of each layer of nanostructures in the first channel region 14 is substantially the same in different regions along its length direction, and the thickness of each layer of nanostructures in the second channel region 15 is substantially the same in different regions along its length direction. In addition, the thickness of the nanostructures included in the second channel region 15 is defined as H1. There is a first gap 16 between the bottom nanostructure in the first channel region 14 and the semiconductor substrate 11, and the thickness of the first gate stack structure 17 included in the first ring-gate transistor 12 is at least located at the first gap 16 is H2. Based on this, H1 is less than H2. At this time, although the first ring-gate transistor 12 and the second ring-gate transistor 13 are manufactured together by the above-mentioned first semiconductor layer 28 and the second semiconductor layer 29 serving as sacrificial layers / channel layers, the problem of the second gate stack structure 20 included in the second ring-gate transistor 13 being unable to be filled due to the thickness difference between the first semiconductor layer 28 and the second semiconductor layer 29 will not occur, thereby improving the yield and working performance of the semiconductor device. Furthermore, while the nanostructure included in the second channel region 15 is thinned so that H1 is smaller than H2, since the thickness of each layer of the nanostructure in the second channel region 15 is roughly the same in different regions along its length direction, even if the second ring-gate transistor 13 includes an inner side wall 22, the height of the inner side wall 22 can be equal to the thickness of the second gate stack structure 20, so that there is a smaller parasitic capacitance between the second source / drain region 21 and the second gate stack structure 20, thereby improving the yield and operating performance of the semiconductor device.

[0079] Among them, the thickness of each layer of nanostructure in the first channel region 14 in different regions along its own length direction is roughly the same, and the thickness of each layer of nanostructure in the second channel region 15 in different regions along its own length direction is roughly the same, where "roughly the same" can be equal or the thickness difference between different regions can be less than 3nm, both of which can be considered to be roughly the same.

[0080] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 2 to 24 The manufacturing process is described in the perspective view or cross-sectional view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0081] First, a semiconductor substrate is provided. Next, Fig.24As shown, a first all-round gate transistor 12 and a second all-round gate transistor 13 are formed on a semiconductor substrate 11. The first all-round gate transistor 12 and the second all-round gate transistor 13 have opposite conductivity types. The first all-round gate transistor 12 and the second all-round gate transistor 13 are arranged on the semiconductor substrate 11 in a direction parallel to the surface of the semiconductor substrate 11. The material of the first channel region 14 included in the first all-round gate transistor 12 is different from the material of the second channel region 15 included in the second all-round gate transistor 13. Each layer of nanostructures in the first channel region 14 is staggered with the corresponding layer of nanostructures in the second channel region 15 along the thickness direction of the semiconductor substrate 11. The thickness of each layer of nanostructures in the first channel region 14 is substantially the same in different regions along its own length direction. The thickness of each layer of nanostructures in the second channel region 15 is substantially the same in different regions along its own length direction. Among them, the thickness of the nanostructures included in the second channel region 15 is H1. A first gap 16 is provided between the bottom nanostructure in the first channel region 14 and the semiconductor substrate 11 . The first gate-all-around transistor 12 includes a first gate stack structure 17 having a thickness H2 at least located at the first gap 16 , and H1 is smaller than H2 .

[0082] Among them, the structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the embodiment of the present invention is the same as the result of the semiconductor device provided in the first aspect. Therefore, the structure and material of the above-mentioned semiconductor substrate, as well as the structure and material of the first ring-gate transistor and the second ring-gate transistor and other information can be referred to the previous text and will not be repeated here.

[0083] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0084] In an actual manufacturing process, illustratively, the steps of forming the first gate-all-around transistor and the second gate-all-around transistor on the semiconductor substrate may include:

[0085] like Figures 2 to 5 As shown, a first fin structure 26 and a second fin structure 27 with the same structure and spaced apart are formed on the semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the first fin structure 26 and the second fin structure 27 both include a first semiconductor layer 28 and a second semiconductor layer 29 that are alternately arranged. Among the alternately arranged first semiconductor layers 28 and second semiconductor layers 29, the film layer located at the bottom is the second semiconductor layer 29, and the thickness of the second semiconductor layer 29 is greater than the thickness of the first semiconductor layer 28. The material of the second semiconductor layer 29 is different from the material of the semiconductor substrate 11 close to the second semiconductor layer 29 and the material of the first semiconductor layer 28.

[0086] Specifically, the first semiconductor layer included in the first fin structure is used to manufacture the nanostructure in the first channel region included in the first all-around gate transistor, so the material, thickness and number of layers of the first semiconductor layer in the first fin structure and the second fin structure can be determined based on the material, thickness and number of layers of the nanostructure included in the first channel region. Similarly, the second semiconductor layer included in the second fin structure is used to manufacture the nanostructure in the second channel region included in the second all-around gate transistor, so the material and number of layers of the second semiconductor layer in the first fin structure and the second fin structure can be determined based on the material and number of layers of the nanostructure included in the second channel region.

[0087] In addition, in the alternately arranged first semiconductor layer and second semiconductor layer, the film layer at the bottom is the second semiconductor layer. The film layer at the top can be the first semiconductor layer or the second semiconductor layer. Secondly, the thickness of the second semiconductor layer can be determined according to the thickness of the first gate stack structure at the first gap, which is not specifically limited here.

[0088] In the actual manufacturing process, Figure 1 As shown, epitaxy or other processes may be used to form a first semiconductor material layer and a second semiconductor material layer on the semiconductor substrate 11 according to the relative position relationship between the first semiconductor layer and the second semiconductor layer in the first fin structure and the second fin structure. Figure 2 As shown, photolithography and etching processes can be used to etch at least the first semiconductor material layer and the second semiconductor material layer. If the manufactured semiconductor device also includes a shallow trench isolation structure, it is necessary to further etch a portion of the semiconductor substrate 11 downward to form the first fin and the second fin. Next, as Figure 3 As shown, a shallow trench isolation structure 23 is formed on the semiconductor substrate 11 by using processes such as deposition and etching. The material of the shallow trench isolation structure 23 can refer to the above. Secondly, the top height of the shallow trench isolation structure 23 is less than or equal to the bottom height of the second semiconductor layer 29, and the portions of the first fin and the second fin exposed outside the shallow trench isolation structure 23 are the first fin structure 26 and the second fin structure 27, respectively. Alternatively, if the manufactured semiconductor device does not include the above-mentioned shallow trench isolation structure, it is only necessary to etch the first semiconductor material layer and the second semiconductor material layer to obtain the first fin structure and the second fin structure.

[0089] Next, if Figure 6 and Figure 7 As shown, a mask structure 30 is formed spanning over the first fin structure 26 and the second fin structure 27 .

[0090] In the actual manufacturing process, a deposition process can be used to form a mask material covering the semiconductor substrate. Then, processes such as photolithography and etching are used to selectively etch the mask material to form the above-mentioned mask structure. As for the material of the mask structure, it can be set according to actual needs, as long as it can play a protective role in the subsequent mask.

[0091] Exemplarily, the mask structure may include a sacrificial gate. The material of the sacrificial gate may include a material that is easy to remove, such as polysilicon. Secondly, the mask structure may also include a gate oxide layer, and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include materials such as silicon oxide. In addition, the mask structure may also include a sacrificial gate, and gate sidewalls located at least on both sides of the sacrificial gate along the length direction. The material of the gate sidewall can be referred to in the above text and will not be repeated here.

[0092] Next, the manufacturing process of the first all-round gate transistor and the second all-round gate transistor is described in the order of first forming the first source / drain region and the first channel region included in the first all-round gate transistor, and then forming the second source / drain region and the second channel region included in the second all-round gate transistor:

[0093] like Figures 8 to 11 As shown, the portion of the first fin structure 26 exposed outside the mask structure 30 is processed to form a first source / drain region 18 included in the first all-around gate transistor.

[0094] In the actual manufacturing process, ion implantation and other processes can be used to directly dope the portion of the first fin structure exposed outside the mask structure to form the first source / drain region included in the first all-around gate transistor. Alternatively, wet etching or dry etching and other processes can be used to selectively remove the portion of the first fin structure exposed outside the mask structure; then, epitaxy and other processes are used to form the first source / drain region included in the first all-around gate transistor on both sides of the remaining first fin structure.

[0095] Exemplarily, if the manufactured first all-around gate transistor also includes an inner sidewall, after removing the portion of the first fin structure exposed outside the mask structure and before forming the first source / drain region included in the first all-around gate transistor on both sides of the remaining first fin structure, the manufacturing method of the semiconductor device further includes: Fig. 9 As shown in FIG. 1 , the edge portions of both sides of each second semiconductor layer 29 in the remaining first fin structure along the length direction are removed to form a second dielectric filling region 34. Next, as shown in FIG. Fig.10 As shown, an inner sidewall 22 of the first all-around gate transistor is formed in the second dielectric filling region.

[0096] Next, if Fig.12As shown, deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 25 covering the portion of the semiconductor substrate 11 corresponding to the first all-around gate transistor. The top of the interlayer dielectric layer 25 is flush with the top of the mask structure 30. The material of the interlayer dielectric layer 25 can be referred to above and will not be repeated here.

[0097] Next, if Fig.13 As shown, a dry etching or wet etching process is used to remove at least a portion of the mask structure corresponding to the first fin structure, and each second semiconductor layer in the remaining first fin structure is removed, so that each first semiconductor layer in the remaining first fin structure forms a corresponding layer of nanostructure included in the first channel region 14.

[0098] It should be noted that when manufacturing the first source / drain region, if the portion of the first fin-shaped structure exposed outside the mask structure is selectively removed, the portion of the second fin-shaped structure exposed outside the mask structure can also be removed at the same time. Then, before removing each second semiconductor layer in the remaining first fin-shaped structure, a mask material covering the periphery of the remaining second fin-shaped structure is formed to protect the remaining second fin-shaped structure; and after forming the first channel region, the mask material is removed to facilitate the subsequent formation of the second source / drain region and the second channel region.

[0099] Alternatively, when manufacturing the first source / drain region, if the portion of the first fin structure exposed outside the mask structure is selectively removed, a mask material covering the periphery of the second fin structure can be formed before removing the portion of the first fin structure exposed outside the mask structure. After the first channel region is formed, the mask material can be removed to facilitate the subsequent formation of the second source / drain region and the second channel region.

[0100] Next, if Fig.15 As shown, the portion of the second fin-shaped structure exposed outside the mask structure 30 is removed, and a portion of the semiconductor substrate 11 is further etched downward. The protruding portion of the semiconductor substrate 11 remaining below the second fin-shaped structure after etching is a sacrificial layer 31 .

[0101] In the actual manufacturing process, dry etching or wet etching and other processes can be used to remove the portion of the second fin structure exposed outside the mask structure, and continue to etch down part of the semiconductor substrate. Before etching the second fin structure and the semiconductor substrate, it is necessary to form a mask material covering the periphery of the first channel region to prevent the etching operation from affecting the first channel region. In addition, the depth of the semiconductor substrate etched can be determined according to the thickness of the second gate stack structure filled in the second gap, which is not specifically limited here.

[0102] Next, if Fig.16 and Fig.17As shown, the remaining first semiconductor layer included in the second fin-shaped structure is removed, and the sacrificial layer is removed; and the second semiconductor layer 29 included in the remaining second fin-shaped structure is thinned to form a first dielectric filling region 32 .

[0103] In actual application, dry etching or wet etching can be used to remove the first semiconductor layer included in the remaining second fin structure and the sacrificial layer. Then, the second semiconductor layer included in the remaining second fin structure can be thinned by wet etching, atomic layer etching or oxidation. The thickness of the thinned second semiconductor layer can be determined according to the thickness of the second gate stack structure filling the second gap, which is not specifically limited here.

[0104] Next, if Fig.18 As shown, deposition and etching processes may be used in sequence to form a first dielectric layer 33 in the first dielectric filling region. The material of the first dielectric layer 33 may include insulating dielectric materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0105] Exemplarily, in the case where the manufactured second all-around gate transistor further includes an inner sidewall, after forming a first dielectric layer in the first dielectric filling region, as shown in FIG. Fig.19 As shown, wet etching or dry etching can be used to remove the edge portions of both sides of the first dielectric layer 33 along the length direction to form the third dielectric filling area 35. Next, as shown in Fig. 20 As shown, deposition and etching processes can be used in sequence to form the inner sidewall 22 of the second all-around gate transistor in the third dielectric filling region. The material of the inner sidewall 22 of the second all-around gate transistor can be referred to above and will not be repeated here.

[0106] It should be noted that when the manufactured second all-around gate transistor also includes an inner sidewall, the material of the first dielectric layer needs to be different from the material of the inner sidewall included in the second all-around gate transistor, so as to release the nanostructure included in the second channel region by subsequently removing the first dielectric layer.

[0107] Next, if Fig.21 As shown, epitaxial growth or other processes may be used to form second source / drain regions 21 included in the second all-around gate transistor on both sides of the remaining second fin structure along the length direction.

[0108] Next, if Fig. 22 As shown, deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 25 covering the portion of the semiconductor substrate 11 corresponding to the second all-around gate transistor. The top of the interlayer dielectric layer 25 is flush with the top of the mask structure 30. The material of the interlayer dielectric layer 25 can be referred to above and will not be repeated here.

[0109] Next, if Fig.23 As shown, dry etching or wet etching processes can be used to remove at least part of the mask structure corresponding to the second fin structure and remove the first dielectric layer, so that each second semiconductor layer in the remaining second fin structure forms a corresponding layer of nanostructure included in the second channel region 15.

[0110] It should be noted that the above text describes the manufacturing process of the first gate-all-around transistor and the second gate-all-around transistor in the order of first forming the first source / drain region and the first channel region included in the first gate-all-around transistor, and then forming the second source / drain region and the second channel region included in the second gate-all-around transistor. This does not mean that the manufacturing can only be carried out in the above order. Alternatively, the second source / drain region and the second channel region included in the second gate-all-around transistor can be formed first, and then the first source / drain region and the first channel region included in the first gate-all-around transistor are formed; the manufacturing method of the first gate-all-around transistor and the second gate-all-around transistor in this order can refer to the above text and will not be repeated here.

[0111] Next, if Fig.14 and Fig.24 As shown, a process such as atomic layer deposition can be used to form a first gate stack structure 17 surrounding the periphery of each layer of nanostructures included in the first channel region 14; and a second gate stack structure 20 surrounding the periphery of each layer of nanostructures included in the second channel region 15. The materials of the first gate stack structure 17 and the second gate stack structure 20 can be referred to above and will not be repeated here.

[0112] In addition, the first gate stack structure and the second gate stack structure can be formed simultaneously or separately in different operations. For example, when the first source / drain region and the first channel region are formed first, the first gate stack structure can be formed after the first channel region is formed and before the second source / drain region is formed. For another example, when the second source / drain region and the second channel region are formed first, the second gate stack structure can be formed after the second channel region is formed and before the first source / drain region is formed.

[0113] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0114] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, a first all-around gate transistor and a second all-around gate transistor; a material of a first channel region included in the first all-around gate transistor is different from a material of a second channel region included in the second all-around gate transistor; The first ring-gate transistor and the second ring-gate transistor are arranged on the semiconductor substrate at intervals along a direction parallel to the surface of the semiconductor substrate; each layer of the nanostructure in the first channel region is staggered with the corresponding layer of the nanostructure in the second channel region along the thickness direction of the semiconductor substrate; the thickness of each layer of the nanostructure in the first channel region in different regions along its own length direction is substantially the same; the thickness of each layer of the nanostructure in the second channel region in different regions along its own length direction is substantially the same; Among them, the thickness of the nanostructure included in the second channel region is H1; there is a first gap between the bottom nanostructure in the first channel region and the semiconductor substrate, and the thickness of the first gate stack structure included in the first ring-gate transistor is H2 at least at the first gap, and H1 is smaller than H2.

2. The semiconductor device according to claim 1, wherein: The first all-around gate transistor and the second all-around gate transistor also each include an inner sidewall; In the first all-around gate transistor, the inner sidewall is located between the first gate stack structure and the first source / drain region; the height of the inner sidewall included in the first all-around gate transistor is H3, and H3 is equal to H2; In the second ring-gate transistor, the inner side wall is located between the second gate stack structure and the second source / drain region; there is a second gap between the bottom nanostructure in the second channel region and the semiconductor substrate, the second gate stack structure included in the second ring-gate transistor has a thickness of H4 at least located at the second gap, and the height of the inner side wall included in the second ring-gate transistor is H5, and H5 is equal to H4.

3. The semiconductor device according to claim 2, characterized in that H3 is different from H5.

4. The semiconductor device according to claim 1, wherein: The thickness of a portion of the semiconductor substrate located below the second all-around gate transistor is smaller than the thickness of a portion of the semiconductor substrate located below the first all-around gate transistor.

5. The semiconductor device according to claim 1, wherein: The second ring-gate transistor includes multiple layers of the nanostructures spaced apart along the thickness direction of the semiconductor substrate; in the second ring-gate transistor, the distance between the nanostructure at the bottom layer and the semiconductor substrate is less than or equal to the distance between two adjacent layers of the nanostructures.

6. The semiconductor device according to claim 1, wherein: The first gate-all-around transistor and the second gate-all-around transistor have opposite conductivity types; And / or, the conductivity type of the first all-around gate transistor is N-type, and the conductivity type of the second all-around gate transistor is P-type; And / or, the material of the first channel region includes silicon or silicon germanium, the material of the second channel region includes silicon germanium or germanium, and the germanium content in the material of the second channel region is greater than the germanium content in the material of the first channel region.

7. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate; forming a first all-around gate transistor and a second all-around gate transistor on the semiconductor substrate; The first all-around gate transistor and the second all-around gate transistor are arranged on the semiconductor substrate in a direction parallel to the surface of the semiconductor substrate with an interval; the material of the first channel region included in the first all-around gate transistor is different from the material of the second channel region included in the second all-around gate transistor; Each layer of nanostructures in the first channel region is staggered with the corresponding layer of nanostructures in the second channel region along the thickness direction of the semiconductor substrate; the thickness of each layer of the nanostructures in the first channel region in different regions along its own length direction is roughly the same; the thickness of each layer of the nanostructures in the second channel region in different regions along its own length direction is roughly the same; wherein, the thickness of the nanostructures included in the second channel region is H1; there is a first gap between the bottom layer of the nanostructures in the first channel region and the semiconductor substrate, and the thickness of the first gate stack structure included in the first ring-gate transistor at least at the first gap is H2, and H1 is less than H2.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The step of forming a first all-around gate transistor and a second all-around gate transistor on the semiconductor substrate comprises: A first fin structure and a second fin structure which are spaced apart and have the same structure are formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, the first fin structure and the second fin structure both include first semiconductor layers and second semiconductor layers which are alternately arranged; among the first semiconductor layers and the second semiconductor layers which are alternately arranged, the film layer located at the bottom is the second semiconductor layer, and the thickness of the second semiconductor layer is greater than that of the first semiconductor layer; the material of the second semiconductor layer is different from the material of the semiconductor substrate on a side close to the second semiconductor layer and the material of the first semiconductor layer; forming a mask structure spanning the first fin structure and the second fin structure; Processing a portion of the first fin structure exposed outside the mask structure to form a first source / drain region included in a first all-around gate transistor; Removing at least a portion of the mask structure corresponding to the first fin structure, and removing each second semiconductor layer in the remaining first fin structure, so that each first semiconductor layer in the remaining first fin structure forms a corresponding layer of nanostructure included in the first channel region; Removing the portion of the second fin-shaped structure exposed outside the mask structure, and continuing to etch downward a portion of the semiconductor substrate; the protruding portion of the semiconductor substrate remaining below the second fin-shaped structure after etching is a sacrificial layer; Removing the first semiconductor layer included in the remaining second fin-shaped structure and the sacrificial layer; and thinning the second semiconductor layer included in the remaining second fin-shaped structure to form a first dielectric filling region; forming a first dielectric layer in the first dielectric filling region; forming a second source / drain region included in the second all-around gate transistor on both sides of the remaining second fin-shaped structure along the length direction; At least a portion of the mask structure corresponding to the second fin structure is removed, and the first dielectric layer is removed, so that each second semiconductor layer in the remaining second fin structure forms a corresponding layer of nanostructure included in the second channel region.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The processing of the portion of the first fin structure exposed outside the mask structure to form a first source / drain region included in the first all-around gate transistor includes: removing a portion of the first fin-shaped structure exposed outside the mask structure; Removing edge portions of both sides of each second semiconductor layer in the remaining first fin structure along the length direction to form a second dielectric filling region; An inner sidewall of the first all-around gate transistor is formed in the second dielectric filling region.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: After forming the first dielectric layer in the first dielectric filling region, and before forming the second source / drain regions included in the second all-around gate transistor on both sides of the remaining second fin structure along the length direction, the method for manufacturing the semiconductor device further includes: removing edge portions of both sides of the first dielectric layer along the length direction to form a third dielectric filling area; An inner sidewall of the second all-around gate transistor is formed in the third dielectric filling region.

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