Semiconductor device and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor device and a forming method thereof, and the semiconductor device comprises a plurality of first nanostructures which are formed in a first stack. The device also includes a plurality of second nanostructures formed in the second stack. The device further includes a first source / drain structure adjacent the plurality of first nanostructures, the first source / drain structure including a first semiconductor having silicon and germanium. The device further includes a second source / drain structure vertically stacked over the first source / drain structure and adjacent to the plurality of second nanostructures, the second source / drain structure having a second semiconductor in which a germanium concentration exceeds a germanium concentration of the first semiconductor.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] There is a continuing demand for increased computing power in electronic devices including smartphones, tablet computers, desktop computers, laptop computers, and many other types of electronic devices. Integrated circuits provide the computing power for these electronic devices. One method of increasing the computing power of an integrated circuit is to increase the number of transistors and other integrated circuit components that can be included in a given area of ​​a semiconductor substrate.

[0003] Complementary field effect transistors (CFETs) can be used to increase the density of transistors in integrated circuits. A CFET can include an N-type transistor and a P-type transistor stacked vertically. The gate electrodes of the N-type and P-type transistors can be electrically shorted together. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a plurality of first nanostructures formed in a first stack; a plurality of second nanostructures formed in a second stack; a first source / drain structure adjacent to the plurality of first nanostructures, the first source / drain structure comprising a first semiconductor having silicon and germanium; and a second source / drain structure vertically stacked above the first source / drain structure and adjacent to the plurality of second nanostructures, the second source / drain structure having a second semiconductor in which a germanium concentration exceeds a germanium concentration of the first semiconductor.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a first semiconductor nanostructure corresponding to a channel region of a first transistor; forming a second semiconductor nanostructure located above the first semiconductor nanostructure and corresponding to a channel region of a second transistor; forming a first source / drain structure adjacent to the first semiconductor nanostructure; forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure, the sacrificial source / drain structure comprising a first semiconductor having a first germanium concentration; and forming a second source / drain structure adjacent to the second semiconductor nanostructure by replacing the sacrificial source / drain structure with a second semiconductor having a second germanium concentration exceeding the first germanium concentration.

[0006] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a first semiconductor nanostructure corresponding to a channel region of a first transistor; forming a second semiconductor nanostructure located above the first semiconductor nanostructure and corresponding to a channel region of a second transistor; forming a first source / drain structure adjacent to the first semiconductor nanostructure; and before forming the first source / drain structure: forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure; and replacing the sacrificial source / drain structure with a second source / drain structure having a germanium concentration exceeding the germanium concentration of the sacrificial source / drain structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1A-1F is a cross-sectional view of an integrated circuit including a CFET at different processing stages according to some embodiments;

[0009] Figure 2A and Figure 2B is a cross-sectional view of an integrated circuit at different processing stages according to some embodiments;

[0010] Figure 3A - FIG. 3J is a cross-sectional view of an integrated circuit at different processing stages according to some embodiments;

[0011] Figure 4 is a flow chart of a process for forming an integrated circuit according to some embodiments. DETAILED DESCRIPTION

[0012] In the following description, many thicknesses and materials for various layers and structures within the integrated circuit die are described. For various embodiments, specific dimensions and materials are given by way of example. Those skilled in the art will recognize that other dimensions and materials may be used in many cases without departing from the scope of the present invention, according to the present invention.

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] In the following description, certain specific details are set forth to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the art will appreciate that the present disclosure can be practiced without these specific details. In other cases, well-known structures associated with electronic components and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the description of the embodiments of the present invention.

[0016] Unless the context requires otherwise, throughout the specification and the following claims, the word "comprise" and variations such as "comprises" and "comprising" should be interpreted in an open and inclusive sense, i.e., "including but not limited to".

[0017] The use of ordinal numbers such as first, second, and third does not necessarily imply a sequential ordering but may simply distinguish multiple instances of an action or structure.

[0018] References throughout this specification to "one embodiment" or "an embodiment" mean that the described particular features, structures, or characteristics associated with that embodiment are included in at least some embodiments. Therefore, the phrases "in one embodiment," "in an embodiment," or "in some embodiments" that appear in various places throughout this specification do not necessarily all refer to the same embodiment. In addition, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0019] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense, including "and / or," unless the content clearly dictates otherwise.

[0020] As used in this specification and the appended claims, the terms "fill", "fills", "filling", and "filled" include the meaning of partially filling and completely filling (or fillings, filling, filled, etc.). For example, a conductive layer can be said to "fill" an opening, which can include the conductive layer contacting the adjacent walls of the opening, or the conductive layer being present in the opening with one or more different material layers between the conductive layer and the adjacent walls.

[0021] As used in this specification and the appended claims, the terms "surround", "surrounds", "surrounding", and "surrounded" include the meanings of completely surrounding and partially surrounding (or surrounds, surrounding, and surrounded, etc.). For example, a "surrounded" hexahedron (such as a rectangular prism) includes the meaning of being completely surrounded by material on all six faces, or it may be partially surrounded, such that one or more of the six faces are not completely covered by the material, and at least a portion thereof is exposed.

[0022] In many CFETs, SiGe is used as source / drain (S / D). To avoid damaging the epitaxial layer during sheet formation, a SiB layer (formed in the channel adjacent to the epitaxial layer) and a lower Ge composition SiGe layer (L1) are grown before growing a high Ge layer (L2).

[0023] In the embodiments of the present disclosure, the silicon germanium layer can be replaced with a pure germanium layer or a high concentration germanium layer for the source / drain. The replacement can occur after the source / drain epitaxy process of growing the upper source / drain, the lower source / drain, or both.

[0024] Using pure Ge or high Ge%SiGe (e.g., 75%-100% Ge) as source / drain can increase the lattice constant and greatly increase the strain applied to the channel, thereby increasing the drive current. Using pure Ge or high Ge%SiGe (e.g., 75%-100% Ge) as source / drain can reduce the source / drain contact resistance, thereby increasing the current.

[0025] Figure 1A-1F is a cross-sectional view of an integrated circuit 100 including a CFET at different processing stages according to some embodiments. For clarity of illustration, some features may be omitted from the figure.

[0026] Figure 4 A flow chart of a method 1000 for forming an IC device or a portion thereof from a workpiece in accordance with one or more aspects of the present invention is depicted. Method 1000 is merely an example and is not intended to limit the present invention to that explicitly shown in method 1000. Additional actions may be provided before, during, and after method 1000, and some of the described actions may be replaced, eliminated, or moved for additional embodiments of the method. For example, action 1020 may be eliminated or may be performed after action 1060. For simplicity, not all actions are described in detail herein. Figure 1A-Figure 3H 1 and 10. The method 1000 is described with partial perspective views and / or cross-sectional views of a workpiece shown in FIG. 1 at different stages of manufacture according to an embodiment of the method 1000. For the avoidance of doubt, throughout the figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X direction and the Y direction. It should be noted that since the workpiece can be manufactured into a semiconductor device, the workpiece may be referred to as a semiconductor device as the context requires.

[0027] The integrated circuit 100 includes a complementary field effect transistor (CFET) 102. The CFET 102 includes a first transistor 20A of a first conductivity type and a second transistor 20B of a second conductivity type. The first transistor 20A is vertically stacked on the second transistor 20B. The CFET 102 uses an isolation structure 126 to separate the stacked channel region of the first transistor 20A from the stacked channel region of the second transistor 20B to improve the electrical characteristics of the CFET 102. In other words, a hybrid nanostructure (e.g., a hybrid sheet) including the stacked channel region of the first transistor 20A, the isolation structure 126, and the stacked channel region of the second transistor 20B is formed.

[0028] The CFET transistor 20A may correspond to a full-ring gate transistor. The full-ring gate transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more lithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes may combine lithography and self-alignment processes, allowing the creation of patterns with smaller spacing, for example, than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the full-ring gate structure. In addition, the full-ring gate CFET 102 may include a plurality of semiconductor nanostructures corresponding to the channel region of the CFET 102. The semiconductor nanostructure may include a nanosheet, a nanowire, or other types of nanostructures. The full-ring gate transistor may also be referred to as a nanostructure transistor.

[0029] Figure 1A The view is an X-view of the integrated circuit 100, where the X-axis is the horizontal axis, the Z-axis is the vertical axis, and the Y-axis extends in a direction into and out of the drawing sheet. The term "X-view" as used herein corresponds to a cross-sectional view where the X-axis is the horizontal dimension and the Z-axis is the vertical dimension. The term "Y-view" as used herein corresponds to a cross-sectional view where the Y-axis is the horizontal dimension and the Z-axis is the vertical dimension.

[0030] Integrated circuit 100 includes substrate 101. Substrate 101 may include a semiconductor layer, a dielectric layer, or a combination of a semiconductor layer and a dielectric layer. In addition, conductive structures may be formed in substrate 101 as backside conductive vias and interconnects, as will be described in more detail below. In some embodiments, substrate 101 includes a single crystal semiconductor layer on at least one surface portion. Substrate 101 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP.

[0031] In some embodiments, the substrate 101 may include a dielectric layer, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbon nitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric materials. In some embodiments, the substrate 101 may include a shallow trench isolation region formed in the semiconductor layer. Various configurations of the substrate 101 may be utilized without departing from the scope of the present invention. In some embodiments, for example, when the substrate 101 is removed before forming the backside interconnect structure, the substrate 101 does not exist.

[0032] The transistor 20B is formed on the substrate 101. Figure 1A 1 , integrated circuit 100 is flipped, corresponding to processing performed through the back side of integrated circuit 100. Transistor 20A is located above transistor 20B. In some embodiments, transistor 20A is an N-type transistor and transistor 20B is a P-type transistor. In some embodiments, transistor 20A can be a P-type transistor and transistor 20B can be an N-type transistor.

[0033] The transistor 20A includes a plurality of semiconductor nanostructures 106. The semiconductor nanostructures 106 are stacked along a vertical direction or a Z direction. Figure 1A In the example of FIG. 20A, two stacked semiconductor nanostructures 106 are depicted. However, in practice, there may be three or more stacked semiconductor nanostructures 106 without departing from the scope of the present invention. In addition, in some embodiments, there may be only a single semiconductor nanostructure 106 and a single semiconductor nanostructure 107. The semiconductor nanostructure 106 corresponds to the channel region of the transistor 20A. The semiconductor nanostructure 106 may be a nanosheet, a nanowire, or other types of nanostructures.

[0034] The transistor 20B includes a plurality of semiconductor nanostructures 107. The semiconductor nanostructures 107 are stacked along a vertical direction or a Z direction. Figure 1A In the example of FIG. 1 , there are three stacked semiconductor nanostructures 107. However, in practice, there may be only two stacked nanostructures 107, or there may be more than three stacked nanostructures 107 without departing from the scope of the present invention. The semiconductor nanostructure 107 corresponds to the channel region of the transistor 20B. The semiconductor nanostructure 107 may be a nanosheet, a nanowire, or another type of nanostructure. The number of semiconductor nanostructures 107 may be the same as the number of semiconductor nanostructures 106, or may be different from the number of semiconductor nanostructures 106.

[0035] Semiconductor nanostructures 106 and 107 may include Si, SiGe, Ge, SiGeSn, GeSn, or other semiconductor materials. In the non-limiting examples described herein, semiconductor nanostructure 106 is silicon. The vertical thickness of semiconductor nanostructure 106 may be between 2nm and 5nm. Semiconductor nanostructures 106 may be separated from each other by 4nm to 10nm along the vertical direction. Other thicknesses and materials may be used for semiconductor nanostructure 106 without departing from the scope of the present invention. Semiconductor nanostructure 107 may have the same material and size as semiconductor nanostructure 106, or may have a semiconductor material different from semiconductor nanostructure 106.

[0036] Transistors 20A and 20B include gate dielectrics. The gate dielectric includes an interfacial gate dielectric layer 108 and a high-K gate dielectric layer 110. The interfacial gate dielectric layer 108 is a low-K gate dielectric layer. For example, the interfacial gate dielectric layer 108 can be a thin oxide layer of the underlying material of the semiconductor nanostructures 106 and 107. The interfacial gate dielectric layer 108 is in contact with the semiconductor nanostructures 106 and 107. The high-K gate dielectric layer 110 is in contact with the low-K gate dielectric layer 108. The interfacial gate dielectric layer 108 is located between the semiconductor nanostructure 106 and the high-K gate dielectric layer 110, and between the semiconductor nanostructure 107 and the high-K gate dielectric layer 110.

[0037] The interface gate dielectric layer 108 may include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interface dielectric layer 108 may include a relatively low-K dielectric relative to a high-K dielectric such as hafnium oxide or other high-K dielectric materials that may be used for transistor gate dielectrics. The interface dielectric layer 108 may include a native oxide layer grown on the surface of the semiconductor nanostructures 106 and 107. The interface dielectric layer 108 may have a thickness between 0.4 nm and 2 nm. Other materials, configurations, and thicknesses may be used for the interface dielectric layer 108 without departing from the scope of the present invention.

[0038] The high-k gate dielectric layer includes one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The thickness of the high-k dielectric is in the range of about 1nm to about 3nm. Other thicknesses, deposition processes, and materials may be used for the high-k gate dielectric layer without departing from the scope of the present invention. The high-k gate dielectric layer may include a first layer and a second layer, the first layer including HfO2 with a dipole doping including La and Mg, and the second layer including a high-k ZrO layer with crystallization.

[0039] The transistor 20A includes a gate metal 112. The gate metal 112 surrounds the semiconductor nanostructure 106. The gate metal 112 contacts the high-K gate dielectric layer 110. The gate metal 112 corresponds to the gate electrode of the transistor 20A. In an example where the transistor 20A is an N-type transistor, the gate metal 112 may include a material that produces a beneficial work function with the semiconductor nanostructure 106. In one example, the gate metal 112 includes titanium aluminum, titanium, aluminum, tungsten, ruthenium, molybdenum, copper, gold, or other conductive materials. In some embodiments, the gate metal 112 surrounds the semiconductor nanostructure 106 on four sides, such as the top, bottom, left, and right sides. In some embodiments, such as in a fork-sheet transistor, the gate metal 112 may surround the semiconductor nanostructure 106 on three sides, while the gate metal 112 is substantially absent on the fourth side. For example, the gate metal 112 may be present on the outer edge of the fourth side and may occupy less than about 5% of the area of ​​the fourth side.

[0040] Figure 1A A single gate metal 112 is shown. However, in practice, the gate electrode of transistor 20A may include multiple metal layers. For example, gate metal 112 may include one or more liner layers or adhesion layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. Gate metal 112 may include a gate fill material that fills the remaining volume between semiconductor nanostructures 106 after depositing one or more liner layers. Various materials, combinations of materials, and configurations may be used for gate metal 112 without departing from the scope of the present invention.

[0041] Transistor 20B includes gate metal 113. Gate metal 113 surrounds semiconductor nanostructure 107. Gate metal 113 contacts high-K gate dielectric layer 110. Gate metal 113 corresponds to the gate electrode of transistor 20B. In an example where transistor 20B is a P-type transistor, gate metal 113 may include a material that produces a desired work function with semiconductor nanostructure 107. In one example, gate metal 113 includes titanium nitride, titanium, aluminum, tungsten, ruthenium, molybdenum, copper, gold, or other conductive materials. In some embodiments, gate metal 113 is or includes one or more materials different from gate metal 112.

[0042] Figure 1AA single gate metal 113 is shown. However, in practice, the gate electrode of transistor 20B may include multiple metal layers surrounding semiconductor nanostructure 107. For example, gate metal 113 may include one or more liner layers or adhesion layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. Gate metal 113 may include a gate fill material that fills the remaining volume between semiconductor nanostructures 107 after depositing one or more liner layers. Various materials, combinations of materials, and configurations may be used for gate metal 113 without departing from the scope of the present invention.

[0043] Transistor 20A includes source / drain regions 116. Source / drain regions 116 are in contact with each semiconductor nanostructure 106. Each semiconductor nanostructure 106 extends along the X direction between source / drain regions 116. Source / drain regions 116 include semiconductor material. Transistor 20B includes sacrificial source / drain regions 117. Sacrificial source / drain regions 117 are in contact with each semiconductor nanostructure 107. Each semiconductor nanostructure 107 extends along the X direction between sacrificial source / drain regions 117. Sacrificial source / drain regions 117 include semiconductor material.

[0044] In an example where transistor 20A is an N-type transistor and transistor 20B is a P-type transistor, source / drain region 116 may be doped with an N-type dopant substance. The N-type dopant substance may include P, As, or other N-type dopant substances. In the case of a P-type transistor, sacrificial source / drain region 117 may be doped with a P-type dopant substance. The P-type dopant substance may include B or other P-type dopant substances. Doping may be performed in situ during the epitaxial growth process of source / drain region 117. Without departing from the scope of the present invention, source / drain regions 116 and 117 may include other materials and structures. Typically, since sacrificial source / drain region 117 is sacrificial, in many embodiments, sacrificial source / drain region 117 is not doped with a dopant substance, which is beneficial to reducing processing steps. In some embodiments, when it is beneficial to improve the etching selectivity of sacrificial source / drain region 117 relative to adjacent structures and / or elements, sacrificial source / drain region 117 may be doped with one or more appropriate dopants.

[0045] As used herein, the term "source / drain region" may refer to a source region or a drain region, either individually or collectively, depending on the context. Thus, one of the source / drain regions 116 may be a source region while the other source / drain region 116 is a drain region, or vice versa. Additionally, in some cases, one or both of the source / drain regions 116 may be shared with one or more laterally adjacent transistors.

[0046] Transistors 20A and 20B each include an internal spacer 114. Without departing from the scope of the present invention, internal spacer 114 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric materials. In one example, internal spacer 114 includes silicon oxycarbon nitride.

[0047] Internal spacers 114 of transistor 20A physically separate gate metal 112 from source / drain regions 116. This prevents shorts between gate metal 112 and source / drain regions 116. Internal spacers 114 of transistor 20B physically separate gate metal 113 from sacrificial source / drain regions 117. This prevents shorts between gate metal 113 and replacement source / drain regions or “active” source / drain regions formed in subsequent operations.

[0048] Transistor 20A may include source / drain contacts 124. Each source / drain contact 124 is located above a corresponding source / drain region 116 and is electrically connected to or in contact with the corresponding source / drain region 116, and optionally in contact with a sacrificial source / drain region 117. An electrical signal may be applied to the source / drain region 116 through the source / drain contact. Source / drain contact 124 may include silicide (not depicted separately to simplify the illustration). The silicide is formed on top of the source / drain region 116. The silicide may include titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicides. Figure 1A , the source / drain contact 124 can extend completely through one of the source / drain regions 116 and land on the sacrificial source / drain region 117 thereover. In some embodiments, one or more of the source / drain regions 116 or the sacrificial source / drain region 117 do not have a source / drain contact 124 connected thereto or in contact therewith. In some embodiments, both source / drain contacts 124 extend completely through the respective source / drain regions 116 to land on the respective sacrificial source / drain region 117.

[0049] Source / drain contacts 124 may be or include a conductive layer, a barrier layer, or both on a silicide. The barrier layer may include titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive materials. The conductive layer may include conductive materials such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive materials. Other materials and configurations may be used for source / drain contacts 124 without departing from the scope of the present invention.

[0050] Transistor 20A includes sidewall spacers 131. Sidewall spacers 131 are located near the uppermost portion of gate metal 112 and electrically isolate gate metal 112 from source / drain contacts 124. Sidewall spacers 131 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), low-K dielectric materials, or other dielectric materials. Other thicknesses and materials may be used for sidewall spacers 131 without departing from the scope of the present invention.

[0051] Transistor 20A may include a gate capping metal (not separately depicted for simplicity of illustration) located on the uppermost portion of gate metal 112. In some embodiments, the gate capping metal includes tungsten, fluorine-free tungsten, or other suitable conductive materials. The gate capping metal may have a height between 1 nm and 10 nm. Other configurations, materials, and thicknesses may be used for the gate capping metal without departing from the scope of the present invention.

[0052] The operation of CFET 102 can generally be referred to as Figure 1A However, it should be noted that in later operations, the source / drain region 117' is used, which is a pure Ge or high Ge concentration source / drain region 117' (for example, see Figure 1D ), to replace the source / drain region 117. The CFET 102 can be operated by applying a voltage to the source / drain region 116 / 117' and the gate metal 112 / 113. A voltage can be applied to the source / drain region 116 / 117' through the source / drain contact 124 / 125. Figure 1A A gate contact, not shown, applies voltage to the gate metal 112 / 113. Figure 1A 102. It is not obvious in the view of FIG. 104, but gate metal 112 and gate metal 113 can be shorted together. Therefore, gate metal 112 and gate metal 113 can correspond together to the gate electrode of CFET 102. A voltage applied to gate metal 112 / 113 can turn on transistor 20A and turn off transistor 20B, or can turn on transistor 20B and turn off transistor 20A. When gate metal 112 / 113 are shorted together, source / drain region 116 is not shorted together with source / drain region 117'. Depending on the specific circuit configuration, current flow through source / drain regions 116 and 117' can be selectively enabled or disabled individually.

[0053] As previously described, it may be beneficial to obtain the desired work function for transistors 20A and 20B by using different materials for gate metals 112 and 113. One possible way to form gate metals 112 / 113 is to first deposit gate metal 113 around all semiconductor nanostructures 106 and 107, and then perform a timed etch to remove gate metal 113 from around semiconductor nanostructure 106. Subsequently, gate metal 112 is deposited around semiconductor nanostructure 106 after the timed etch of gate metal 113. However, one disadvantage of this process is that, in some cases, gate metal 113 may not be completely removed directly below the lowest semiconductor nanostructure 106. This can interfere with the work function of transistor 20A, thereby affecting the threshold voltage of transistor 20A in an undesirable manner.

[0054] CFET 102 avoids or reduces the possibility of work function interference by utilizing isolation structure 126 between semiconductor nanostructure 106 and semiconductor nanostructure 107. More specifically, isolation structure 126 is directly between the lowest semiconductor nanostructure 106 and the highest semiconductor nanostructure 107. Isolation structure 126 may include upper and lower semiconductor layers 127, and dielectric layer 129 between the upper and lower semiconductor layers 127. Various structures and compositions may be used for isolation structure 126 without departing from the scope of the present invention.

[0055] The dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), low-K dielectric material, or other dielectric materials. The dielectric layer 129 may have a length between 15nm and 30nm along the X direction. The length within this range may be sufficient to match or exceed the length of the semiconductor nanostructures 106 and 107 along the X direction. However, depending on the length of the semiconductor nanostructures 106 and 107, a larger or smaller length of the dielectric layer 129 may be selected. The dielectric layer 129 may have a height between 5nm and 25nm along the Z direction. These dimensions may be sufficient to ensure that there is no possibility that the gate metal 113 will interfere with the work function of the semiconductor nanostructure 106. In addition, these dimensions can provide a reduced gate-to-drain capacitance. Without departing from the scope of the present invention, other materials, dimensions, and configurations may be used for the dielectric layer 129. The dielectric layer 129 may be referred to as a dielectric nanostructure. The dielectric nanostructures may include dielectric nanosheets, dielectric nanowires, or another type of dielectric nanostructure.

[0056] Each semiconductor layer 127 may have a vertical thickness between 1 nm and 5 nm. The semiconductor layers 127 may include silicon or another suitable semiconductor material. Other materials and dimensions may be used for the semiconductor layers 127 without departing from the scope of the present invention.

[0057] although Figure 1A A single dielectric layer 129 is shown, but in practice, the dielectric layer 129 may include multiple layers of different dielectric materials located between the semiconductor layers 127. For example, a first dielectric layer of silicon oxide may be located in contact with each semiconductor layer 127. A second dielectric layer of silicon nitride may be located between the upper and lower portions of the first dielectric layer. Various configurations for the dielectric barrier between the top semiconductor nanostructure 107 and the bottom semiconductor nanostructure 106 may be utilized without departing from the scope of the present invention.

[0058] Figure 1A The formation of the device 100 depicted in FIG. 1 may include forming nanostructure channels 106, 107, which correspond to Figure 4 In some embodiments, the formation of device 100 further includes forming source / drain 116 adjacent to nanostructure channel 106, which corresponds to Figure 4 The formation of the device 100 includes forming a sacrificial source / drain 117 adjacent to the nanostructure channel 107 .

[0059] exist Figure 1A-1F In some embodiments, the sacrificial source / drain 117 is replaced with a replacement source / drain 117' that can increase the strain in the semiconductor nanostructure or channel 107. Increasing the strain can improve the drive current that can be conducted through the channel 107. In some embodiments where the replacement source / drain 117' includes pure germanium or high concentration germanium instead of SiGe, the source / drain contact resistance can be reduced, which can also improve current conduction. Throughout the description, the replacement source / drain 117' can be referred to as a second source / drain 117' or an active source / drain 117'.

[0060] exist Figure 1A In the embodiment, a first opening 57 is formed to expose the upper surface of the sacrificial source / drain 117. For example, the first opening 57 can be formed by Figure 1A As shown in FIG. 5 , the interlayer dielectric is formed by partially or completely removing the interlayer dielectric in the cross-sectional view of FIG. As depicted, when forming the first opening 57, the interlayer dielectric is completely removed. The formation of the first opening 57 can be achieved by a suitable etching operation such as wet etching, dry etching, or atomic layer etching (ALE), which is selective to the material of the interlayer dielectric without substantially corroding the material of the dielectric layer 130.

[0061] In some embodiments, after forming the first opening 57, the upper surface of the sacrificial source / drain 117 is recessed in profile. In some embodiments, the upper surface is flat in profile. In some embodiments, the depth D1 between the highest level of the upper surface of the sacrificial source / drain 117 and the lowest level of the upper surface can be in the range of about 0 nm to about 15 nm. That is, the depth D1 can measure the recessed depth of the sacrificial source / drain 117 after forming the first opening 57. The recess may be caused by over-etching into the material of the sacrificial source / drain 117 when removing the interlayer dielectric above the sacrificial source / drain 117.

[0062] exist Figure 1B In the embodiment, an oxidation process is performed to form a porous oxide layer 1172 on the exposed upper surface of the sacrificial source / drain region 117, corresponding to Figure 4 Action 1040. The thickness of the porous oxide layer 1172 can be in the range of about 0.8 nm to about 2 nm, for example, about 1 nm. The formation of the porous oxide layer 1172 may include thermal oxidation, in which the SiGe sacrificial source / drain region 117 is exposed to oxygen or water vapor at a high temperature. The thermal oxidation process causes the silicon in the SiGe alloy to react with oxygen to form silicon dioxide (SiO2). Since the oxidation of germanium is different from that of silicon, less stable germanium oxide (GeOx) may be formed, which may volatilize at the oxidation temperature, thereby affecting the uniformity and quality of the porous oxide layer 1172. That is, there may be holes in the porous oxide layer 1172 that extend completely through the porous oxide layer 1172, so that the sacrificial source / drain region 117 is at least partially exposed through the porous oxide layer 117.

[0063] exist Figure 1C In the embodiment, the sacrificial source / drain region 117 is removed to form an opening 117H corresponding to Figure 4 Action 1050. The sacrificial source / drain region 117 may be removed by a suitable etching operation, which may include a chlorine-based etchant, a fluorine-based etchant, etc. The etchant may be a gas that can penetrate the porous oxide layer 1172 and etch the SiGe of the sacrificial source / drain region 117, thereby removing the sacrificial source / drain region 117 and forming an opening 117H. The opening 117H may inherit the shape of the sacrificial source / drain region 117, such as Figure 1C In some embodiments, as described in reference Figure 2A and Figure 2B As described, some over-etching may occur, which may remove the ends of the nanostructures 107 .

[0064] exist Figure 1DIn FIG. 1 , after forming the opening 117H, a replacement or “active” source / drain region 117′ is formed in the opening 117H by the porous oxide layer 1172, corresponding to Figure 4 Action 1060. The replacement source / drain region 117' can be formed by growing the material of the replacement source / drain region 117' in the opening 117H by an appropriate epitaxial growth operation. The replacement source / drain region 117' can be or include one or more semiconductor materials, which can include SiGe, Ge, GeSn, SiGeSn. In the replacement source / drain region 117', the concentration of germanium ("germanium concentration") can be in the range of about 75% to 100% (i.e., pure germanium). The epitaxial growth of Ge or SiGe in the source / drain opening can be implemented by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), etc. In CVD, a gas containing selected elements (e.g., germanium for Ge, silane for Si, and optionally diborane, phosphine, TMGa, TEGa, AsH3, or TBA for doping) is introduced into a reaction chamber. The device 100 can be heated to a high temperature so that the gas reacts or decomposes to form an epitaxial layer. CVD is advantageous for good uniformity and control over layer composition. MBE can provide the benefit of increased precision, where elements are evaporated in a high vacuum environment and then condensed on a heating device 100. MBE can provide excellent control over the thickness and composition of the epitaxial layer replacing the source / drain region 117' at the atomic level, which is advantageous for nanoscale devices.

[0065] In CVD and MBE, the porous oxide layer 1172 is permeable to gas (e.g., germane, silane, diborane, phosphine, etc.) so that the gas can react or decompose at the nanostructure 107 in the opening 117H. That is, the exposed side of the end of the nanostructure 107 can have the semiconductor material grown thereon. Figure 1D As depicted by the dashed lines in , during the growth process, growth may initially occur to form a first region 117A on the end of the nanostructure 107. Then, as the process continues over time, growth may continue such that the first region 117A expands and eventually merges to form a second region 117B. Finally, growth continues until the second regions 117B on both sides of the opening 117H merge with each other and contact at least the nanostructure 107, the internal spacer 114, the source / drain contact 124 (if present), the dielectric layer 130, and the porous oxide layer 1172. In some embodiments, one or more air gaps may be formed in the corner region of the replacement source / drain region 117' by the growth profile of the semiconductor material in the opening 117H. The formation of the air gaps will refer to Figure 1F A more detailed description is given.

[0066] In some embodiments, as described above, dopants are introduced in situ into the replacement source / drain region 117'. In some embodiments, the dopants include B, Ga, P, As, etc. During the growth process, diborane, phosphine, trimethylgallium, triethylgallium, arsenic, tert-butylarsenic, etc. can flow in a gaseous state to in situ dope the replacement source / drain region 117'. In some embodiments, the replacement source / drain region 117' can be doped in subsequent operations, such as by implanting one or more of B, Ga, P, As, etc.

[0067] exist Figure 1E In the embodiment, after forming the replacement source / drain region 117', a source / drain contact 125 may be formed on the replacement source / drain region 117', corresponding to Figure 4 Action 1070. Each source / drain contact 125 is located on a corresponding replacement source / drain region 117' and is electrically connected to the corresponding replacement source / drain region 117'. An electrical signal may be applied to the replacement source / drain region 117' through the source / drain contact 125.

[0068] The source / drain contact 125 may be or include one or more conductive layers on the silicide 121. For example, the barrier layer or liner layer may include titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive materials. The conductive fill layer may be located on the barrier layer or liner layer and may include a conductive material such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive materials. Other materials and configurations may be used for the source / drain contact 125 without departing from the scope of the present invention.

[0069] The source / drain contact 125 may include a silicide 121. The silicide 121 is formed at the interface between the replacement source / drain region 117' and the source / drain contact 125. The silicide 121 may reduce the source / drain contact resistance. In some embodiments, the silicide 121 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. In some embodiments, the silicide 121 is or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The silicide 121 may be an alloy between the source / drain contact 125 and the replacement source / drain region 117', which may be a mixture of one or more of Ti, Ru, Mo, Ni, Co, W, etc. and one or more of Ge, SiGe, SiGeSn, GeSn, etc. The silicide 121 may have a thickness in the range of about 1 nm to about 10 nm. A thickness below about 1 nm may result in insufficient reduction in contact resistance. A thickness greater than about 10 nm may result in an electrical short circuit with the nanostructure 107. In some embodiments, the silicide 121 is present below the dielectric layer 130 and in contact with it. Figure 1E As depicted in FIG. 1 , in some embodiments, backside silicide 121B is present at the interface between second source / drain 117′ and source / drain contact 124. Backside silicide 121B may be similar to silicide 121 in most respects, but may be formed during the growth of semiconductor material of second source / drain 117′ rather than during the formation of source / drain contact 125.

[0070] Figure 1F Optional air gaps 117G1, 117G2 are depicted that may exist at the corner regions of the second source / drain region 117'. The first air gap 117G1 may exist near the silicide 121 and the inner spacer 114 proximate to the substrate 101. The second air gap 117G2 may exist near the source / drain contact 124 and the inner spacer 114 proximate to the isolation structure 126. As previously described with reference to Figure 1DAs described, during the growth process of the second source / drain region 117', growth may initially occur on the end of the nanostructure 107 to form a first region 117A depicted by a first dashed line. Then, as the process continues over time, growth may continue, causing the first region 117A to expand and eventually merge to form a second region 117B. Finally, growth continues until the second regions 117B on both sides of the opening 117H merge with each other and contact at least the nanostructure 107, the internal spacer 114, the source / drain contact 124 (if present), the dielectric layer 130, and the porous oxide layer 1172.

[0071] In some embodiments, the growth of the second source / drain region 117' may terminate before its semiconductor material reaches the uppermost portion of the inner spacer 114 adjacent to the substrate 101, thereby forming an air gap 117G1. The height of the air gap 117G1 along the Z-axis direction may be in the range of 0 nm to about 5 nm.

[0072] The air gap 117G2 may be formed due to the merging or overhanging of semiconductor materials before filling the lateral small space between the source / drain contacts 124 and the inner spacers 114 adjacent to the isolation structure 126. The height of the air gap 117G2 along the Z-axis direction may be in the range of 0 nm to about 5 nm.

[0073] In some embodiments, air gap 117G1 exists, while air gap 117G2 does not exist. In some embodiments, air gap 117G2 exists, while air gap 117G1 does not exist. In some embodiments, air gaps 117G1 and 117G2 do not exist or both exist.

[0074] In some embodiments, due to the merging of semiconductor materials of the second source / drain region 117', a seam 117S may exist. The seam 117S may be an air gap as shown, or may be a visible interface extending generally along a vertical direction such as the Z-axis direction.

[0075] like Figure 1F , when the underside of the replacement source / drain 117′ is immediately adjacent to the interlayer or inter-layer dielectric 128 and the dielectric layer 130, e.g., when no source / drain contact 124 extends through the inter-layer dielectric 128 to electrically connect with the replacement source / drain 117′, the growth of the replacement source / drain 117′ may be different than in regions of the device 100 where the source / drain contact 124 does extend through the inter-layer dielectric 128. For example, as depicted, the second air gap 117G2, the seam 117S, or both may not be present in these regions.

[0076] Figure 2A and Figure 2B is a cross-sectional view of an integrated circuit 100 at various processing stages in accordance with some embodiments.

[0077] Figure 2A An embodiment is depicted in which, after forming the porous oxide layer 1172, the opening 117H is formed by removing the sacrificial source / drain 117 through the porous oxide layer 1172. Figure 1C As described, the etchant gas can penetrate the pores of the porous oxide layer 1172, react with the semiconductor material (eg, SiGe) of the sacrificial source / drain 117', and remove it. Figure 2A As depicted in , during the removal of the sacrificial source / drain 117', some over-etching may occur, wherein the ends of the nanostructure 107 are removed or recessed. The removal of the ends of the nanostructure 107 may result in a recess 107R, such that the sides of the nanostructure 107 are recessed from the sides of the inner spacer 114. In some embodiments, the length of the recess 107R, such as the distance between the inner spacer 114 and the sides of the nanostructure 107 therebetween along the X-axis direction, may be in the range of about 0.5 nm to about 3 nm. Due to the recessing of the nanostructure 107 during the replacement of the sacrificial source / drain 117 with the active source / drain 117', the width of the nanostructure 107 may be shorter than the width of the nanostructure 106 along the X-axis direction. The width difference between the nanostructure 107 and the nanostructure 106 may be in the range of about 1 nm to about 4 nm. That is, the width of the nanostructure 106 irrespective of the replacement of the source / drain 116 may exceed the width of the nanostructure 107 related to the replacement of the source / drain 117 by about 1 nm to about 4 nm.

[0078] exist Figure 2B In the embodiment, after forming the opening 117H having the recess 117R, the second source / drain 117 ′ is formed in the opening 117H through the porous oxide layer 1172 . Figure 2B The formation of the second source / drain 117' in most aspects is similar to that of reference Figure 1D Those described, except Figure 2B The second source / drain 117' is formed in the recess 117R and has a portion extending into the space of the recess 117R vertically located between the inner spacers 114. Figure 2AAs discussed, due to the partial etching of the ends of nanostructure 107, nanostructure 106 may have a width that exceeds the width of nanostructure 107. Similarly, due to the reduced width of nanostructure 107 relative to nanostructure 106, second source / drain 117' may have a width that exceeds the width of source / drain 116. For example, the width of second source / drain 117' may exceed the width of source / drain 116 by about 1 nm to about 4 nm.

[0079] In reference Figure 1D and Figure 2B In the description of , the second source / drain 117' is formed by flowing a precursor gas of its semiconductor material and optionally its dopant through the holes in the porous oxide layer 1172. In some embodiments, the porous oxide layer 1172 may be removed before forming the second source / drain 117'. For example, a suitable etching operation, such as dry etching or vapor etching, may be performed to remove the material of the porous oxide layer 1172, and then a cleaning operation may be performed before forming the second source / drain 117' to remove any residue of the porous oxide layer 1172.

[0080] In some embodiments, before growing the high Ge concentration semiconductor material, the recess 117R may be filled with another semiconductor material, such as SiB, instead of filling the recess 117R with the high Ge concentration semiconductor material.

[0081] In reference Figures 1A to 2B In the depicted embodiment, source / drain 116 and sacrificial source / drain 117 are formed before replacing sacrificial source / drain 117 with active source / drain 117′. In some embodiments, sacrificial source / drain 117 is formed before source / drain 116. Thus, replacing sacrificial source / drain 117 with active source / drain 117′ can occur before forming source / drain 116.

[0082] Figure 3A - Figure 3J is a schematic cross-sectional side view depicting a process for forming device 100, wherein sacrificial source / drain 117 is replaced prior to forming source / drain 116. To simplify the illustration, FIG. 3A to FIG. 3E A partial view of device 100 is depicted in FIG.

[0083] exist Figure 3A, before forming the source / drain 116, the sacrificial source / drain 117 is formed in the source / drain opening 77, which extends through the nanostructure 106, the isolation structure 126, and the nanostructure 107, and lands on the substrate 101. In some embodiments, the source / drain opening 77 extends into the substrate 101 when initially formed, so that the upper surface of the substrate 101 below the source / drain opening 77 is recessed. The recessed portion can be regrown with undoped silicon to form a semiconductor region 101A, which can have a horizontal upper surface that is substantially coplanar with the upper surface of the substrate 101 and the lower surface of the bottommost internal spacer 114. The semiconductor region 101A can advantageously provide a substantially flat surface from which the sacrificial source / drain 117 can grow in addition to growing from the sides of the nanostructure 107 exposed by the source / drain opening 77.

[0084] To prevent sacrificial source / drain 117 from growing on nanostructure 106, dielectric layer 130 may be present on the sides of nanostructure 106 and completely cover it. Dielectric layer 130 may also cover the sides of semiconductor layer 127 of isolation structure 126. For example, dielectric layer 130 may be a thin conformal layer extending from sidewall spacer 131 to a level between the upper and lower surfaces of uppermost inner spacer 114 located between uppermost nanostructure 107 and isolation structure 126.

[0085] The sacrificial source / drain 117 may be formed by an appropriate epitaxial growth operation of the material of the sacrificial source / drain 117 grown in the source / drain opening 77. The sacrificial source / drain 117 may be or include one or more semiconductor materials, which may include SiGe, Ge, GeSn, SiGeSn. In the sacrificial source / drain 117, the concentration of germanium may be less than about 40%, less than about 30%, less than about 20%, or other values. A germanium concentration of the sacrificial source / drain 117 greater than about 40% may result in the diffusion of germanium into the nanostructure 107. The epitaxial growth of the semiconductor material in the source / drain opening may be performed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), etc.

[0086] In some embodiments, dopants are introduced into the sacrificial source / drain 117 in situ, as shown in FIG. Figure 1D As described. In some embodiments, the dopant includes B, Ga, P, As, etc. In the growth process, diborane, phosphine, trimethylgallium, triethylgallium, arsenic, tert-butylarsenic, etc. can flow in a gaseous state to in-situ dope the sacrificial source / drain 117. In some embodiments, the sacrificial source / drain 117 can be doped in subsequent operations, for example, by implanting one or more of B, Ga, P, As, etc.

[0087] like Figure 3B As depicted in , after forming the sacrificial source / drain 117, an interlayer dielectric (ILD) 300, an etch stop layer (ESL) 310, or both, is formed on and laterally adjacent to the sacrificial source / drain 117. Then, the ILD 300 may be recessed, and the ESL 310 may be penetrated to expose the upper surface of the sacrificial source / drain 117. This is Figure 3B For example, Figure 3B Material of the ILD 300 above the dashed line may be removed by a recessing operation.

[0088] exist Figure 3C In the embodiment of the present invention, after forming the sacrificial source / drain 117, the ILD 300, and the ESL 310, and recessing the ILD 300, a porous oxide layer 1174 is formed on the exposed upper surface of the sacrificial source / drain 117. The porous oxide layer 1174 can be similar to the reference 1 in most aspects. Figure 1B The porous oxide layer 1172 is depicted. In some embodiments, the porous oxide layer 1174 is substantially planar by sacrificing the planar surface of the source / drain 117.

[0089] exist Figure 3C In the embodiment of the present invention, an oxidation process is performed to form a porous oxide layer 1174 above the exposed upper surface of the sacrificial source / drain 117. The thickness of the porous oxide layer 1174 can be in the range of about 0.8 nm to about 2 nm, for example, about 1 nm. The formation of the porous oxide layer 1174 can include thermal oxidation, in which the SiGe sacrificial source / drain region 117 is exposed to oxygen or water vapor at a high temperature. The thermal oxidation process causes the silicon in the SiGe alloy to react with oxygen to form silicon dioxide (SiO2). Because the oxidation of germanium is different from that of silicon, less stable germanium oxide (GeOx) may be formed, which may volatilize at the oxidation temperature, thereby affecting the uniformity and quality of the porous oxide layer 1174. That is, there may be holes in the porous oxide layer 1174 that extend completely through the porous oxide layer 1174, so that the sacrificial source / drain region 117 is at least partially exposed through the porous oxide layer 1174. In the case where the dielectric layer 130 covers the nanostructures 106 , during the growth of the porous oxide layer 1174 on the sacrificial source / drain 117 , typically no oxide layer grows on the nanostructures 106 .

[0090] exist Figure 3D 1, opening 117H is formed by removing sacrificial source / drain 117 through porous oxide layer 1174. Removal of sacrificial source / drain 117 can be similar in most respects to that of reference 1. Figure 1CAs described. The sacrificial source / drain region 117 may be removed by an appropriate etching operation, which may include a chlorine-based etchant, a fluorine-based etchant, etc. The etchant may be a gas that can penetrate the porous oxide layer 1174 and etch the SiGe of the sacrificial source / drain region 117, thereby removing the sacrificial source region 117 and forming an opening 117H. The opening 117H may inherit the shape of the sacrificial source / drain region 117, such as Figure 3D In some embodiments, as described in reference Figure 2A and Figure 2B As described, some over-etching may occur, which may remove the ends of the nanostructures 107 .

[0091] exist Figure 3E In the embodiment of the present invention, a second source / drain 117' is formed through the porous oxide layer 1174. The formation of the second source / drain 117' can be similar in most aspects to the reference Figure 1D Those described. For example, after the opening 117H is formed, a second source / drain region 117' is formed in the opening 117H through the porous oxide layer 1174. The replacement source / drain 117' can be formed by growing the material of the replacement source / drain region 117' in the opening 117H through an appropriate epitaxial growth operation. The replacement source / drain 117' can be or include one or more semiconductor materials, which may include SiGe, Ge, GeSn, SiGeSn. In the replacement source / drain 117', the concentration of germanium can be in the range of about 75% to 100% (i.e., pure germanium). The epitaxial growth of Ge or SiGe in the source / drain opening can be implemented by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), etc. In CVD, a gas containing selected elements (e.g., germane for Ge, silane for Si, and optionally diborane, phosphine, TMGa, TEGa, AsH3, or TBA for doping) is introduced into a reaction chamber. The device 100 can be heated to a high temperature so that the gas reacts or decomposes to form an epitaxial layer. CVD is advantageous for good uniformity and control over the layer composition. MBE can provide the benefit of increased precision, where the elements evaporate in a high vacuum environment and then condense on the heating device 100. MBE can provide excellent control of the thickness and composition of the epitaxial layer replacing the source / drain 117' at the atomic level, which is advantageous for nanoscale devices.

[0092] In CVD and MBE, the porous oxide layer 1174 is permeable to precursor gases (e.g., germane, silane, diborane, phosphine, etc.) so that the precursor gases can react or decompose at the nanostructure 107 in the opening 117H. That is, the exposed side of the end of the nanostructure 107 can have a semiconductor material grown thereon. In some embodiments, dopants are introduced in situ into the replacement source / drain 117'. In some embodiments, the dopants include B, Ga, P, As, etc. In the growth process, diborane, phosphine, trimethylgallium, triethylgallium, arsenic, tert-butylarsenic, etc. can flow in a gaseous state to dope the replacement source / drain 117' in situ. In some embodiments, the replacement source / drain 117' can be doped in subsequent operations, for example, by implanting one or more of B, Ga, P, As, etc.

[0093] In some embodiments, as shown in reference Figure 1A-Figure 2B As described, the porous oxide layer 1174 may be removed before forming the second source / drain 117 ′.

[0094] exist Figure 3F In the embodiment of the present invention, the porous oxide layer 1174 is removed, and a dielectric isolation layer 150 is formed in the source / drain opening 77 on the second source / drain 117'. In some embodiments, the dielectric isolation layer 150 is formed by a dielectric material, such as SiN, SiCN, SiCON, etc. The dielectric isolation layer 150 can be formed by a suitable deposition process, such as PVD, CVD, ALD, etc. After the material of the dielectric isolation layer 150 is deposited, the excess material of the dielectric isolation layer 150 above the source / drain opening 77 can be removed by one or more removal operations, such as CMP. The upper surface of the dielectric isolation layer 150 can be initially coplanar with the upper surfaces of the sidewall spacers 131 and the dielectric layer 128.

[0095] Then, in Figure 3G In the embodiment of the present invention, the dielectric isolation layer 150 is recessed to a level below the nanostructure 106 to expose the nanostructure 106 for subsequent epitaxial growth of the source / drain 116. The recessing can be achieved by a suitable etching operation, such as wet etching or dry etching, which removes the material of the dielectric isolation layer 150 without substantially attacking the nanostructure 106, the inner spacer 114, and the sidewall spacer 131. In some embodiments, the dielectric isolation layer 150 includes the same material as the dielectric layer 130, so that the dielectric layer 130 is recessed to substantially the same level as the dielectric isolation layer 150 at the same time as the dielectric isolation layer 150. In some embodiments, when the dielectric isolation layer 150 and the dielectric layer 130 include different materials, the dielectric layer 130 can be recessed after the dielectric isolation layer 150.

[0096] Then, in Figure 3H and Fig. 3I In FIG. 1 , source / drain 116 is formed adjacent to nanostructure 106. The formation of source / drain 116 is similar in most aspects to reference Figure 1A , Figure 1D , Figure 2B , Figure 3A ,and Figure 3E The formation of the sacrificial source / drain 117 and source / drain 117' described differs in that the source / drain 116 can be an N-type source / drain 116, rather than the source / drain 117' being a P-type source / drain 117' which provides beneficial compressive strain to the nanostructure 107 by virtue of its high Ge concentration semiconductor material.

[0097] exist Figure 3H and Fig. 3I In the embodiment, after forming the source / drain 116, a source / drain contact 124 is formed on the source / drain 116 and optionally on the source / drain 117' by extending through the dielectric isolation layer 150. The formation of the source / drain contact 124 can be similar to the formation of the source / drain contact 125 in most aspects. The source / drain contact 124 ( Fig. 3I The interconnect (labeled as 124') may be referred to as MDLI ("source / drain contact interconnect" or "source / drain contact local interconnect").

[0098] After or before forming the source / drain contacts 125, as Fig. 3I As depicted in FIG. 1 , a vertical isolation structure 260 may be formed that physically isolates the first pair of source / drain electrodes 116 , 117 ′ and the second pair of source-drain electrodes 116 , 117 ′ that are offset from each other along the Y-axis direction. Fig. 3I It is also depicted that the dielectric isolation layer 150 can extend along the Y-axis direction and can vertically isolate the source / drain 116 from the source / drain 117 ′.

[0099] FIG3J depicts a schematic diagram of a Figure 1F As described above, air gaps 117G1, 117G2 are formed near the second source / drain 117'. That is, in the embodiment in which the dielectric isolation structure 150 is formed after forming the replacement source / drain 117' and before forming the source / drain 116, the reference Figure 1F Air gaps 117G1, 117G2 are described.

[0100] Embodiments of the present invention provide advantages. By forming a second source / drain structure with a high Ge concentration after forming an active gate, germanium is prevented from diffusing into the nanostructure channel, and adjacent structures (e.g., active gates) are in place, which provides additional support for increasing strain during the formation of the second source / drain region structure. Replacement with pure germanium or a semiconductor material with a high germanium concentration (e.g., SiGe) can increase the lattice constant, thereby increasing strain and drive current. Pure germanium or a semiconductor material with a high germanium concentration can also have a reduced source / drain contact resistance, which can increase current output.

[0101] In some embodiments, a semiconductor device includes: a plurality of first nanostructures formed in a first stack. The device also includes: a plurality of second nanostructures formed in a second stack. The device also includes: a first source / drain structure adjacent to the plurality of first nanostructures, the first source / drain structure including a first semiconductor having silicon and germanium. The device also includes: a second source / drain structure vertically stacked above the first source / drain structure and adjacent to the plurality of second nanostructures, the second source / drain structure having a second semiconductor in which a germanium concentration exceeds a germanium concentration of the first semiconductor.

[0102] In some embodiments, the germanium concentration in the second semiconductor exceeds about 75%.

[0103] In some embodiments, excluding dopants, the germanium concentration in the second semiconductor is 100%.

[0104] In some embodiments, the second semiconductor includes silicon germanium, pure germanium, germanium tin, or silicon germanium tin.

[0105] In some embodiments, the second semiconductor is doped with B, Ga, P, or As at a dopant concentration in a range from about 1e19 / cm3 to about 5e21 / cm3.

[0106] In some embodiments, the air gap is positioned adjacent to the second source / drain structure.

[0107] In some embodiments, the semiconductor device further includes: an internal spacer adjacent to one of the second nanostructures, one of the second nanostructures having a side recessed a first distance from a side of the internal spacer; wherein the second source / drain structure extends the first distance beyond the side of the internal spacer to contact one of the second nanostructures.

[0108] In some embodiments, the first distance is in a range from about 0.5 nm to about 2 nm.

[0109] In some embodiments, the semiconductor device further includes: a first silicide in contact with the first source / drain structure; and a second silicide in contact with the second source / drain structure, the second silicide having a germanium concentration exceeding the germanium concentration of the first silicide.

[0110] In some embodiments, a width of the plurality of first nanostructures exceeds a width of the plurality of second nanostructures by about 1 nanometer to about 4 nanometers.

[0111] In some embodiments, a method of forming a semiconductor device includes: forming a first semiconductor nanostructure corresponding to a channel region of a first transistor. The method also includes: forming a second semiconductor nanostructure located above the first semiconductor nanostructure and corresponding to a channel region of a second transistor. The method also includes: forming a first source / drain structure adjacent to the first semiconductor nanostructure. The method also includes: forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure, the sacrificial source / drain structure including a first semiconductor having a first germanium concentration. The method also includes: forming a second source / drain structure adjacent to the second semiconductor nanostructure by replacing the sacrificial source / drain structure with a second semiconductor having a second germanium concentration exceeding the first germanium concentration.

[0112] In some embodiments, replacing the sacrificial source / drain structure includes: forming a porous oxide layer on an upper surface of the sacrificial source / drain structure; and removing the sacrificial source / drain structure by etching through the porous oxide layer.

[0113] In some embodiments, replacing the sacrificial source / drain structure includes: forming an opening by removing the sacrificial source / drain structure, the opening having a first height; and forming a second source / drain structure by growing a second semiconductor in the opening, the second semiconductor having a second height not exceeding the first height.

[0114] In some embodiments, the method further includes forming a source / drain contact on the second source / drain structure, the air gap being between the second source / drain structure and the source / drain contact.

[0115] In some embodiments, replacing the sacrificial source / drain structure includes: forming an opening by removing the sacrificial source / drain structure; forming a recess by removing an end of a second semiconductor nanostructure during the removal of the sacrificial source / drain structure; and forming a second source / drain structure by growing a second semiconductor in the opening, including growing the second semiconductor in the recess.

[0116] In some embodiments, the method further includes: forming a sacrificial gate surrounding the second semiconductor nanostructure before forming the second source / drain structure; and forming an active gate by replacing the sacrificial gate.

[0117] In some embodiments, a method of forming a semiconductor device includes: forming a first semiconductor nanostructure corresponding to a channel region of a first transistor. The method also includes: forming a second semiconductor nanostructure located above the first semiconductor nanostructure and corresponding to a channel region of a second transistor. The method also includes: forming a first source / drain structure adjacent to the first semiconductor nanostructure. The method also includes: before forming the first source / drain structure. The method also includes: forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure. The method also includes: replacing the sacrificial source / drain structure with a second source / drain structure having a germanium concentration exceeding the germanium concentration of the sacrificial source / drain structure.

[0118] In some embodiments, replacing the sacrificial source / drain structure includes: forming a porous layer on the sacrificial source / drain structure; forming an opening by removing the sacrificial source / drain structure through the porous layer; and forming a second source / drain structure in the opening.

[0119] In some embodiments, forming the opening includes forming a recess by recessing the second semiconductor nanostructure; and forming the second source / drain structure includes forming the second source / drain structure in the recess.

[0120] In some embodiments, forming the second source / drain structure includes partially filling the opening with the second source / drain structure, and the method further includes: forming a source / source contact on the second source / drain structure, with an air gap between the source / drain contact and the second source / drain structure.

[0121] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a plurality of first nanostructures formed in a first stack; a plurality of second nanostructures formed in a second stack; a first source / drain structure adjacent to the plurality of first nanostructures, the first source / drain structure comprising a first semiconductor including silicon and germanium; as well as A second source / drain structure is vertically stacked above the first source / drain structure and adjacent to the plurality of second nanostructures, the second source / drain structure having a second semiconductor in which the germanium concentration exceeds the germanium concentration of the first semiconductor.

2. The semiconductor device according to claim 1, wherein The germanium concentration in the second semiconductor exceeds 75%.

3. The semiconductor device according to claim 2, wherein: Excluding dopants, the germanium concentration in the second semiconductor is 100%.

4. The semiconductor device according to claim 1, wherein: The second semiconductor has a peak value of 1e19 / cm 3 To 5e21 / cm 3 The dopant concentration is within the range of B, Ga, P, or As.

5. The semiconductor device according to claim 1, further comprising: an inner spacer adjacent to one of the second nanostructures, the one of the second nanostructures having a side recessed a first distance from a side of the inner spacer; The second source / drain structure extends beyond the side of the inner spacer by the first distance to contact the one of the second nanostructures.

6. The semiconductor device according to claim 1, further comprising: a first silicide, in contact with the first source / drain structure; and A second silicide is in contact with the second source / drain structure, and a germanium concentration of the second silicide exceeds a germanium concentration of the first silicide.

7. A method of forming a semiconductor device, comprising: forming a first semiconductor nanostructure corresponding to a channel region of a first transistor; forming a second semiconductor nanostructure located above the first semiconductor nanostructure and corresponding to a channel region of a second transistor; forming a first source / drain structure adjacent to the first semiconductor nanostructure; forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure, the sacrificial source / drain structure comprising a first semiconductor having a first germanium concentration; as well as A second source / drain structure is formed adjacent to the second semiconductor nanostructure by replacing the sacrificial source / drain structure with a second semiconductor having a second germanium concentration exceeding the first germanium concentration.

8. The method according to claim 7, wherein: The replacing of the sacrificial source / drain structure comprises: forming a porous oxide layer on an upper surface of the sacrificial source / drain structure; and The sacrificial source / drain structure is removed by etching through the porous oxide layer.

9. The method according to claim 7, wherein: The replacing of the sacrificial source / drain structure comprises: forming an opening by removing the sacrificial source / drain structure, the opening having a first height; and The second source / drain structure is formed by growing the second semiconductor in the opening, the second semiconductor having a second height not exceeding the first height.

10. A method of forming a semiconductor device, comprising: forming a first semiconductor nanostructure corresponding to a channel region of a first transistor; forming a second semiconductor nanostructure located above the first semiconductor nanostructure and corresponding to a channel region of a second transistor; forming a first source / drain structure adjacent to the first semiconductor nanostructure; as well as Before forming the first source / drain structure: forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure; and The sacrificial source / drain structure is replaced with a second source / drain structure having a germanium concentration exceeding the germanium concentration of the sacrificial source / drain structure.

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