Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The invention provides a semiconductor device that suppresses a reduction in the aperture ratio of pixels. The semiconductor device includes: a first gate electrode; an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode overlapping the first gate electrode and the oxide semiconductor layer over the source electrode and the drain electrode, the second gate electrode including a second oxide semiconductor having a polycrystalline structure, the second gate electrode being electrically connected to the first gate electrode.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor having a polycrystalline structure. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device using an oxide semiconductor having a polycrystalline structure. Background Art

[0002] In recent years, the development of semiconductor devices that use oxide semiconductor films as channels instead of silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon has been continuously developed (for example, see Patent Documents 1 to 6). Semiconductor devices including oxide semiconductor films have a simple structure like semiconductor devices including amorphous silicon films and can be formed by low-temperature processes. In addition, it is known that semiconductor devices including oxide semiconductor films have higher field effect mobility than semiconductor devices including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] The semiconductor device is formed in a pixel of a display device, for example. With the high-precision display device, the semiconductor device is required to have not only high field effect mobility but also to suppress the decrease in the aperture ratio of the pixel. One of the purposes of one embodiment of the present invention is to provide a semiconductor device that suppresses the decrease in the aperture ratio of the pixel. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device that suppresses the decrease in the aperture ratio of the pixel.

[0013] Means for solving problems

[0014] A semiconductor device involved in one embodiment of the present invention includes: a first gate electrode; an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure above the first gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode above the source electrode and the drain electrode overlapping the first gate electrode and the oxide semiconductor layer, the second gate electrode including a second oxide semiconductor having a polycrystalline structure, and the second gate electrode electrically connected to the first gate electrode.

[0015] In a method for manufacturing a semiconductor device involved in one embodiment of the present invention, a first gate electrode is formed, an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure is formed over the first gate electrode, a source electrode and a drain electrode connected to the oxide semiconductor layer are formed, the first oxide semiconductor film is formed over the source electrode and the drain electrode, the first oxide semiconductor film is heat-treated to form a second gate electrode including a second oxide semiconductor having a polycrystalline structure, and a nitride layer is formed to cover the second gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic exploded perspective view showing the structure of the display device.

[0017] Figure 2 It is a schematic plan view showing the circuit configuration of a display device.

[0018] Figure 3 It is a schematic plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0019] Figure 4 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0020] Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0021] Figure 6 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0022] Figure 7 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0023] Figure 8 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0024] Fig. 9 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0025] Fig.10 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0026] Fig.11 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0027] Fig.12 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] Fig.13 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0029] Fig.14 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] Fig.15 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Fig.16 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0032] Fig.17 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0033] Fig.18 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0034] Fig.19 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0035] Fig. 20 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0036] Fig.21 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0037] Fig. 22 It is a schematic plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0038] Fig.23 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0039] Fig.24 It is a schematic plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0040] Fig.25 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0041] Fig.26 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0042] Fig. 27 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0043] Fig.28 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0044] Fig.29 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0045] Fig.30 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0046] Fig.31 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0047] Fig.32 It is a schematic plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0048] Fig.33 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0049] Fig.34 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0050] Fig.35 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0051] Fig.36 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0052] Fig.37It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0053] Fig.38 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0054] Fig.39 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0055] Description of Reference Numerals

[0056] 1: display device, 2: display unit, 3: light source unit, DP: display unit, DRV: driving element, FPC: flexible wiring substrate, GD: scanning line driving circuit, GL: scanning line, PX: pixel, SD: signal line driving circuit, SL: signal line, TP: terminal portion, 10, 10A, 10B, 11, 11C: semiconductor device, 20: liquid crystal element, 100: first substrate, 110: first gate electrode, 120: scanning line, 130: first insulating layer, 140: oxide semiconductor layer, 140-1: first oxide semiconductor layer, 140-2: second oxide semiconductor layer, 1 40-3: third oxide semiconductor layer, 150: source electrode, 160: drain electrode, 170: connection electrode (first connection electrode), 180: second insulating layer, 190, 190A, 190C: second gate electrode, 200: nitride layer, 210, 210C: metal oxide layer, 220: third insulating layer, 230: second connection electrode, 300: second substrate, CF1: first conductive film, CF2: second conductive film, MO: metal oxide film, OP1: first opening, OP2: second opening, OP3: third opening, OS1, OS2, OS3: oxide semiconductor film DETAILED DESCRIPTION

[0057] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily thought of by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, film thickness and shape of the constituent elements are sometimes schematically indicated compared to the actual method. However, the illustrated shape is only an example and does not limit the interpretation of the present invention. In this specification and the accompanying drawings, the same figure mark is marked for the constituent elements that are the same as the constituent elements described in the figures that have appeared, and the detailed description is sometimes appropriately omitted.

[0058] In this specification, etc., the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for the sake of convenience, the above or below phrases are used for explanation, but the up-and-down relationship between the substrate and the oxide semiconductor layer may also be configured in the opposite direction to that shown in the figure. In addition, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer, and other components may be configured between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure in which a plurality of layers are stacked. In the case of the expression "pixel electrode above the semiconductor device", it may also be a positional relationship in which the semiconductor device and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of the expression "pixel electrode vertically above the semiconductor device", it means a positional relationship in which the semiconductor device and the pixel electrode overlap when viewed from above. It should be noted that viewing from above refers to viewing from a direction perpendicular to the surface of the substrate.

[0059] In this specification, etc., unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C. In addition, the above expressions do not exclude the case where α includes other constituent elements.

[0060] In this specification, "semiconductor device" refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are included in one embodiment of a semiconductor device. The semiconductor device of the embodiment shown below may also be a transistor used in an integrated circuit (IC) such as a display device, a microprocessor (MPU), or a memory circuit.

[0061] In this specification, etc., "display device" refers to a structure that uses an electro-optical layer to display an image. For example, the term display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure equipped with other optical components (for example, polarization components, backlight sources, touch panels, etc.) relative to a display unit. As long as there is no technical contradiction, the "electro-optical layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer.

[0062] In this specification and the like, the term "film" and the term "layer" can be interchanged with each other as appropriate.

[0063] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0064] <First embodiment>

[0065] [1. Configuration of Display Device 1]

[0066] Reference Figure 1 and Figure 2 A display device 1 including a semiconductor device 10 according to an embodiment of the present invention will be described.

[0067] Figure 1 It is a schematic exploded perspective view showing the structure of the display device 1 . Figure 2 It is a schematic plan view showing the circuit configuration of the display device 1 .

[0068] like Figure 1 As shown, the display device 1 includes a display unit 2 and a light source unit 3. In the display device 1, the light source unit 3 emits light to the display unit 2. The light source unit 3 includes, for example, a light emitting diode (LED). The light source unit 3 may also use a plurality of LEDs. When a plurality of LEDs are used in the light source unit 3, LEDs of the same color may be used, or LEDs of different colors may be used. It should be noted that the light source unit 3 is not limited to a configuration including LEDs. The light source unit 3 only needs to include an element or device that can emit light. In addition, the light source unit 3 may also include a light guide plate or an optical sheet, etc. Figure 1 In the display device 1 shown, the light source unit 3 is arranged below the display unit 2 , but the light source unit 3 may be arranged on the side of the display unit 2 .

[0069] The display unit 2 includes a first substrate 100 and a second substrate 300. A liquid crystal layer (not shown) is sandwiched between the first substrate 100 and the second substrate 300. Figure 2 As shown in FIG. 1 , a display portion DP, a scan line driving circuit GD (a scan line driving circuit is sometimes referred to as a gate driver), a signal line driving circuit SD (a signal line driving circuit is sometimes referred to as a source driver), and a terminal portion TP are provided on the first substrate 100. The display portion DP is provided in the central portion of the first substrate 100. The scan line driving circuit GD is provided outside the display portion DP along the y direction. The signal line driving circuit SD is provided outside the display portion DP along the x direction. The terminal portion TP is provided at the end of the first substrate 100.

[0070] The scanning line driving circuit GD and the signal line driving circuit SD are electrically connected to the terminal portion TP. A flexible wiring substrate FPC is connected to the terminal portion TP, and a signal from the driving element DRV is input to the terminal portion TP (see Figure 1) That is, the signal from the driving element DRV is input to the scanning line driving circuit GD and the signal line driving circuit SD via the terminal portion TP.

[0071] The display unit DP includes a plurality of pixels PX, a plurality of scan lines GL (the scan lines are sometimes referred to as gate lines), and a plurality of signal lines SL (the signal lines are sometimes referred to as source lines). The plurality of pixels PX are respectively arranged in an area surrounded by the scan lines GL and the signal lines SL. The scan lines GL are electrically connected to the scan line drive circuit GD and extend along the x direction. A first signal generated by the scan line drive circuit GD is input to the scan lines GL. The signal lines SL are electrically connected to the signal line drive circuit SD and extend along the y direction. A second signal generated by the signal line drive circuit SD is input to the signal lines SL. The plurality of pixels PX are respectively controlled based on the first signal and the second signal.

[0072] Each of the pixels PX includes a semiconductor device 10 and a liquid crystal element 20 . Figure 2 The semiconductor device 10 shown is a so-called transistor, but the structure of the semiconductor device 10 is not limited to the transistor itself. The semiconductor device 10 can be any structure as long as it includes a transistor. In each of the plurality of pixels PX, the semiconductor device 10 is controlled based on the first signal and the second signal to drive the liquid crystal element 20. It should be noted that in this embodiment, the semiconductor device 10 included in the pixel PX of the display device 1 is described, but the semiconductor device 10 can also be used in the scanning line driving circuit GD and the signal line driving circuit SD. In addition, the display device 1 is a so-called liquid crystal display device, but it can also be other display devices.

[0073] [2. Configuration of Semiconductor Device 10]

[0074] Reference Figure 3 and Figure 4 A semiconductor device 10 according to an embodiment of the present invention will be described.

[0075] Figure 3 It is a schematic plan view showing the structure of a semiconductor device 10 according to an embodiment of the present invention. Figure 4 It is a schematic cross-sectional view showing the structure of a semiconductor device 10 according to an embodiment of the present invention. Figure 4 It is used Figure 3 1 is a cross-sectional view of the semiconductor device 10 taken along line A1 - A2 in FIG.

[0076] like Figure 4As shown, the semiconductor device 10 includes a first substrate 100, a first gate electrode 110, a scan line 120, a first insulating layer 130, an oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a connecting electrode 170, a second insulating layer 180, a second gate electrode 190, and a nitride layer 200. The first gate electrode 110 and the scan line 120 are disposed on the first substrate 100. The first insulating layer 130 covers the upper surface and end surface of the first gate electrode 110 and the scan line 120, respectively, and is disposed on the first gate electrode 110 and the scan line 120. The first insulating layer 130 has a first opening OP1 for exposing a portion of the upper surface of the scan line 120. The oxide semiconductor layer 140 is disposed on the first insulating layer 130 so as to overlap with the first gate electrode 110. The source electrode 150 and the drain electrode 160 respectively cover a portion of the upper surface and a portion of the end surface of the oxide semiconductor layer 140, and are disposed on the first insulating layer 130. The connection electrode 170 is provided on the first insulating layer 130 and is connected to the scan line 120 via the first opening OP1. The second insulating layer 180 covers the upper surface of the oxide semiconductor layer 140, the upper surface and the end surface of the source electrode 150, the upper surface and the end surface of the drain electrode 160, and the upper surface and the end surface of the connection electrode 170, and is provided on the first insulating layer 130. The second insulating layer 180 has a second opening OP2 for exposing a portion of the connection electrode 170. The second gate electrode 190 is provided on the second insulating layer 180 to overlap with the oxide semiconductor layer 140 and the connection electrode 170. The second gate electrode 190 is connected to the connection electrode 170 via the second opening OP2. The nitride layer 200 covers the upper surface and the end surface of the second gate electrode 190 and is provided on the second insulating layer 180.

[0077] like Figure 3 As shown in FIG. 1 , the first gate electrode 110 is provided so as to protrude from the scan line 120 extending along the x direction toward the y direction, and is formed continuously with the scan line 120. In other words, the first gate electrode is formed of the same layer as the scan line 120. In addition, although the source electrode 150, the drain electrode 160, and the connection electrode 170 are provided separately from each other, the source electrode 150, the drain electrode 160, and the connection electrode 170 are formed of the same layer.

[0078] The first gate electrode 110 is formed continuously with the scanning line 120. In this case, it can also be said that the first gate electrode 110 is electrically connected to the scanning line. The second gate electrode 190 is electrically connected to the first gate electrode 110 via the connecting electrode 170. Therefore, the voltage included in the signal input to the scanning line 120 is applied to both the first gate electrode 110 and the second gate electrode 190.

[0079] The source electrode 150 is electrically connected to the signal line (the signal line here is equivalent to Figure 2 The signal line SL in Figure 3 and Figure 4 The drain electrode 160 is electrically connected to a pixel electrode (not shown) provided in the pixel PX. The liquid crystal layer provided between the first substrate 100 and the second substrate 300 is driven by an electric field generated between the pixel electrode provided on the first substrate 100 and the counter electrode (not shown) provided on the second substrate 300. By driving the liquid crystal layer in each of the plurality of pixels PX, the transmission of light emitted from the light source unit 3 is controlled in each of the plurality of pixels PX. In the pixel PX, a part of the components of the semiconductor device 10 blocks the light emitted from the light source unit 3.

[0080] There is a case where the aperture ratio of the pixel PX is reduced due to the configuration of the semiconductor device. In particular, if the size of the pixel PX is reduced, the ratio of the semiconductor device to the size of the pixel PX increases, so the reduction in the aperture ratio of the pixel PX becomes significant. However, in the semiconductor device 10, since the second gate electrode 190 has light transmittance, the reduction in the aperture ratio of the pixel PX can be suppressed.

[0081] When viewed from above, the second gate electrode 190 includes an area that overlaps with any one of the first gate electrode 110, the scan line 120, the source electrode 150, and the drain electrode 160 (hereinafter referred to as the "overlapping area"), and on the other hand, includes an area that does not overlap with the first gate electrode 110, the scan line 120, the source electrode 150, and the drain electrode 160 (hereinafter referred to as the "non-overlapping area"). The non-overlapping area is an area for light emitted from the light source unit 3 to pass through, so if the non-overlapping area has a light-shielding property, the aperture ratio of the pixel PX will be reduced. However, in the semiconductor device 10, since the non-overlapping area of ​​the second gate electrode 190 is light-transmissive, it is possible to suppress the reduction in the aperture ratio of the pixel PX while ensuring the freedom of configuration of the second gate electrode 190.

[0082] Here, the above-mentioned components of the semiconductor device 10 will be described in more detail. It should be noted that the detailed structures of the oxide semiconductor layer 140 and the second gate electrode 190 will be described later.

[0083] The first substrate 100 can support each layer constituting the semiconductor device 10. For example, as the first substrate 100, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. In addition, as the first substrate 100, a silicon substrate or other non-light-transmitting rigid substrate can also be used. In addition, as the first substrate 100, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate or a fluororesin substrate or other light-transmitting flexible substrate can also be used. In order to improve the heat resistance of the first substrate 100, impurities can also be introduced into the above-mentioned flexible substrate. It should be noted that the second substrate 300 can use the same substrate as the first substrate 100.

[0084] The first insulating layer 130 and the second insulating layer 180 can each function as a gate insulating layer. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ) or aluminum oxide nitride (AlO x N y ) or silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum nitride (AlN x ) or aluminum nitride (AlN x O y The first insulating layer 130 and the second insulating layer 180 may each have a single layer structure or a stacked structure.

[0085] Here, silicon oxide nitride (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are oxides containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y ) and aluminum nitride (AlN x O y ) is a nitride containing oxygen at a ratio (x>y) less than nitrogen. It should be noted that for the sake of convenience, silicon oxide (SiO x ) and silicon oxide nitride (SiO x N y ) is referred to as "silicon oxide", and silicon nitride (SiN x ) and silicon oxide nitride (SiN x O y) is referred to as "silicon nitride". Similarly, aluminum oxide (AlO x ) and aluminum oxide nitride (AlO x N y ) is referred to as "aluminum oxide", aluminum nitride (AlN x ) and aluminum nitride (AlN x O y ) is referred to as "aluminum nitride".

[0086] The oxide semiconductor layer 140 is preferably in contact with an oxide. If the oxide semiconductor layer 140 is in contact with an oxide, oxygen can be supplied from the oxide to the oxide semiconductor layer 140 by heat treatment. Therefore, in the case where the first insulating layer 130 and the second insulating layer 180 each have a single-layer structure, it is preferred that silicon oxide be used in the first insulating layer 130 and the second insulating layer 180, respectively. In addition, in the case where the first insulating layer 130 has a stacked structure, it is preferred that the first insulating layer 130 has a structure in which silicon oxide is stacked on silicon nitride in such a manner that silicon oxide is in contact with the oxide semiconductor layer 140. Similarly, in the case where the second insulating layer 180 has a stacked structure, it is preferred that the second insulating layer 180 has a structure in which silicon nitride is stacked on silicon oxide in such a manner that silicon oxide is in contact with the oxide semiconductor layer 140.

[0087] The first gate electrode 110 preferably has not only conductivity but also a function of reflecting or absorbing light emitted from the light source unit 3. That is, the first gate electrode 110 preferably has a light shielding function. In a plan view, the first gate electrode 110 overlaps the entire oxide semiconductor layer 140 (see Figure 3 ). Therefore, if the first gate electrode 110 has a light shielding function, it is possible to shield light incident on the oxide semiconductor layer 140. As described above, the first gate electrode 110 is formed of the same layer as the scan line 120. That is, the first gate electrode 110 is formed of the same material as the scan line 120. For example, as the first gate electrode 110 and the scan line 120, a metal such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy thereof, or a compound thereof, etc. can be used. The first gate electrode 110 and the scan line 120 may have a single-layer structure or a stacked structure.

[0088] The source electrode 150, the drain electrode 160, and the connecting electrode 170 are conductive. As described above, the source electrode 150, the drain electrode 160, and the connecting electrode 170 are formed of the same layer. That is, the source electrode 150, the drain electrode 160, and the connecting electrode 170 are formed of the same material. As the source electrode 150, the drain electrode 160, and the connecting electrode 170, the same material as the first gate electrode 110 and the scanning line 120 can be used.

[0089] The nitride layer 200 can function as an interlayer insulating layer. In addition, the nitride layer 200 can also function as a hydrogen supply layer facing the second gate electrode 190, and the details will be described later. For example, silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum nitride (AlN x ) or aluminum nitride (AlN x O y ) and other nitrides.

[0090] [3. Configuration of Oxide Semiconductor Layer 140]

[0091] [3-1. Composition of Oxide Semiconductor Layer 140]

[0092] An oxide semiconductor containing two or more metal elements including indium (In) is used as the oxide semiconductor layer 140. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanoids are used.

[0093] The oxide semiconductor layer 140 is light-transmissive and has a polycrystalline structure including a plurality of crystal grains. In order to make the oxide semiconductor layer 140 have a polycrystalline structure, it is preferred to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in terms of atomic ratio. If the ratio of indium increases, the oxide semiconductor layer 140 is easily crystallized. In addition, as a metal element other than indium, gallium is preferably included. Gallium and indium also belong to the 13th group element. Therefore, there is almost no situation where the crystallinity of the oxide semiconductor layer 140 is hindered by gallium.

[0094] The oxide semiconductor layer 140 has properties different from those of an existing oxide semiconductor having a polycrystalline structure, and the details will be described later. Therefore, in order to distinguish the oxide semiconductor included in the oxide semiconductor layer 140 from the existing oxide semiconductor having a polycrystalline structure, the oxide semiconductor included in the oxide semiconductor layer 140 is referred to as Poly-OS (Poly-crystalline Oxide Semiconductor) for description below.

[0095] The Poly-OS included in the oxide semiconductor layer 140 can be formed by using a sputtering method and a heat treatment. Here, a method of forming the oxide semiconductor layer 140 is described.

[0096] First, a sputtering method is used to form an oxide semiconductor film. The oxide semiconductor film after film formation has an amorphous structure. Here, an amorphous structure refers to a structure in which there is no long-range ordered structure and no periodic lattice arrangement is observed. For example, when an X-ray diffraction (X-ray Diffraction: XRD) method is used to observe an oxide semiconductor film having an amorphous structure, a specific peak based on a crystal structure cannot be obtained in the diffraction pattern. It should be noted that an oxide semiconductor film having an amorphous structure sometimes has a short-range ordered structure in a tiny area. However, such an oxide semiconductor film does not exhibit the characteristics of Poly-OS and can therefore be classified as an oxide semiconductor film having an amorphous structure.

[0097] The oxide semiconductor film having an amorphous structure is formed at a low temperature. For example, the temperature of the substrate for forming the oxide semiconductor film is below 150°C, preferably below 100°C, and more preferably below 50°C. If the temperature of the substrate is high, microcrystals are easily generated in the oxide semiconductor being formed. In addition, the oxygen partial pressure in the chamber during film formation is above 1% and below 10%, preferably above 1% and below 5%, and more preferably above 2% and below 4%. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor film due to the excess oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor film becomes uneven, and an oxide semiconductor film containing a large number of microcrystals or an oxide semiconductor film that does not crystallize even after heat treatment is formed will be formed.

[0098] Next, the oxide semiconductor film formed by sputtering is subjected to heat treatment. The heat treatment is performed in the air, but the atmosphere for the heat treatment is not limited thereto. The temperature for the heat treatment is between 300°C and 500°C, preferably between 350°C and 450°C. In addition, the heat treatment time is between 15 minutes and 120 minutes, preferably between 30 minutes and 60 minutes. By performing the heat treatment, the oxide semiconductor film having an amorphous structure is crystallized to form an oxide semiconductor layer 140 containing Poly-OS.

[0099] The composition of the oxide semiconductor layer 140 is roughly consistent with the composition of the sputtering target. Therefore, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the composition of the metal elements of the sputtering target. In addition, the composition of the oxide semiconductor layer 140 can also be determined using the XRD method. Specifically, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer 140 obtained according to the XRD method. In addition, the composition of the metal elements of the oxide semiconductor layer 140 can also be determined using fluorescent X-ray analysis or electron probe microanalyzer (Electron Probe Micro Analyzer: EPMA) analysis, etc. It should be noted that the oxygen contained in the oxide semiconductor layer 140 will change according to the process conditions of the sputtering method, etc., and is therefore not limited to this.

[0100] [3-2. Characteristics of Oxide Semiconductor Layer 140]

[0101] Next, the characteristics of the oxide semiconductor layer 140 including Poly-OS are described.

[0102] The oxide semiconductor layer 140 has excellent etching resistance. Specifically, with respect to the oxide semiconductor layer 140, the etching rate when etching is performed using an etching solution for wet etching is very small. This means that the oxide semiconductor layer 140 is hardly etched by the etching solution. When the oxide semiconductor layer 140 is etched using an etching solution containing phosphoric acid as a main component (hereinafter referred to as a "mixed acid etching solution") at 40°C, the etching rate is less than 3nm / min, less than 2nm / min, or less than 1nm / min. The proportion of phosphoric acid in the mixed acid etching solution is greater than 50%, greater than 60%, or greater than 70%. Acetic acid and nitric acid may also be contained in the mixed acid etching solution in addition to phosphoric acid. In an oxide semiconductor film that does not contain Poly-OS, such as an oxide semiconductor film having an amorphous structure before heat treatment, the etching rate when the oxide semiconductor film is etched using a mixed acid etching solution at 40°C is greater than 100nm / min. In addition, the etching rate when the oxide semiconductor layer 140 is etched using a 0.5% hydrofluoric acid solution at room temperature is less than 5nm / min, less than 4nm / min, or less than 3nm / min. It should be noted that in an oxide semiconductor film that does not contain Poly-OS, the etching rate when etching the oxide semiconductor film using a 0.5% hydrofluoric acid solution at room temperature is 15 nm / min or more. Here, "40°C" refers to 40±5°C, which can be the temperature of the etching solution or the set temperature of the etching solution. In addition, "room temperature" refers to 25±5°C.

[0103] An embodiment of the oxide semiconductor layer 140 is shown in Table 1. Table 1 shows the etching rates of each sample produced in a mixed acid etching solution ("Mixed Acid AT-2F" manufactured by RASA Industries, Ltd., in which the ratio of phosphoric acid in the mixed acid etching solution is 65%) and a 0.5% hydrofluoric acid solution. In addition, when etching each sample, the temperature of the mixed acid etching solution is 40°C, and the temperature of the 0.5% hydrofluoric acid solution is room temperature (22°C). In Table 1, sample 1 is an oxide semiconductor layer 140 including Poly-OS, sample 2 is an oxide semiconductor film having an amorphous structure before heat treatment, and sample 3 is an oxide semiconductor film of indium gallium zinc oxide (IGZO) containing less than 50% indium.

[0104] [Table 1]

[0105] Mixed acid etching solution 0.5% hydrofluoric acid solution Sample 1 <0.1nm / min <2nm / min Sample 2 111nm / min >18nm / min Sample 3 162nm / min -

[0106] As shown in Table 1, for sample 1 (oxide semiconductor layer 140 containing Poly-OS), etching was almost impossible using a mixed acid etching solution, and etching was performed at a maximum of 2 nm / min using a 0.5% hydrofluoric acid solution. In the etching using a mixed acid etching solution, the etching rate of sample 1 was less than 1 / 100 of the etching rate of sample 2 (oxide semiconductor film having an amorphous structure before heat treatment). In the etching using a 0.5% hydrofluoric acid solution, the etching rate of sample 1 was less than about 1 / 10 of the etching rate of sample 2. In addition, in the etching using a mixed acid etching solution, the etching rate of sample 1 was less than 1 / 100 of the etching rate of sample 3 (oxide semiconductor film containing IGZO with an indium ratio of less than 50%). That is, sample 1 is significantly superior in etching resistance compared to samples 2 and 3.

[0107] Such excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS is a property that cannot be obtained in the conventional oxide semiconductor having a polycrystalline structure produced by a process below 500° C. Although the detailed mechanism of the excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS is unknown, it is believed that it is because Poly-OS has a polycrystalline structure different from the conventional one.

[0108] As described above, the etching rate of the oxide semiconductor layer 140 including Poly-OS in the etching solution is very low. Therefore, it is very difficult to pattern the oxide semiconductor layer 140. Therefore, in the case of forming an island-shaped oxide semiconductor layer 140, the oxide semiconductor film having an amorphous structure before heat treatment is patterned into an island shape, and then heat treatment is performed to crystallize it. In this way, an island-shaped oxide semiconductor layer 140 including Poly-OS can be formed.

[0109] [4. Configuration of the Second Gate Electrode 190]

[0110] If a large number of oxygen defects are contained in Poly-OS, carriers will be generated. In addition, even if hydrogen is captured in the oxygen defects, carriers will be generated. In this way, Poly-OS containing oxygen defects and hydrogen has conductivity. In addition, Poly-OS with conductivity has light transmittance. Therefore, Poly-OS with conductivity can be used as a transparent conductive material. In this embodiment, Poly-OS with conductivity is used as the second gate electrode 190. As the second gate electrode 190, the same material as the oxide semiconductor layer 140 can be used. That is, as the second gate electrode 190, an oxide semiconductor containing two or more metal elements including indium (In) is used. In addition, the second gate electrode 190 has a polycrystalline structure.

[0111] The second gate electrode 190 including the conductive Poly-OS can be formed by generating oxygen defects and supplying hydrogen, and the details will be described later. The sheet resistance of the second gate electrode 190 is less than 1000Ω / sq., preferably less than 500Ω / sq., and more preferably less than 250Ω / sq. The film thickness of the second gate electrode 190 is, for example, more than 30nm and less than 200nm, preferably more than 50nm and less than 180nm, and more preferably more than 100nm and less than 150nm. If the film thickness of the second gate electrode 190 is less than 30nm, the second gate electrode 190 is not sufficiently low in resistance. In addition, if the film thickness of the second gate electrode 190 is greater than 200nm, there is a situation in which the second gate electrode 190 is not sufficiently low in resistance due to the inclusion of an area in the second gate electrode 190 where no oxygen defects are generated. Therefore, the film thickness of the second gate electrode 190 is preferably within the above range.

[0112] [4. Method for Manufacturing Semiconductor Device 10]

[0113] Reference Figure 5 to Figure 16 A method for manufacturing the semiconductor device 10 will be described.

[0114] Figure 5 1 is a flowchart illustrating a method for manufacturing the semiconductor device 10 according to an embodiment of the present invention. Figure 6 to Figure 16 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Figure 5 The steps of the flowchart shown.

[0115] In step S100, a first conductive film CF1 is formed on the first substrate 100 by sputtering (see Figure 6 ).

[0116] In step S110, the first conductive film CF1 is patterned by photolithography to form the first gate electrode 110 and the scanning line 120 (see FIG. Figure 7 ).

[0117] In step S120, a first insulating layer 130 (see FIG. 1 ) is formed by using a CVD method to cover the first gate electrode 110 and the scanning line 120. Figure 8 ).

[0118] In step S130, the oxide semiconductor film OS1 is formed on the first insulating layer 130 by sputtering. The film forming conditions of the oxide semiconductor film OS1 are as described above. Since the oxide semiconductor film OS1 has an amorphous structure, it is easy to etch the oxide semiconductor film OS1. Therefore, the oxide semiconductor film OS1 is patterned by photolithography (see FIG. 1 ). Fig. 9 ).

[0119] In step S140, the oxide semiconductor film OS1 is subjected to a first heat treatment. The conditions of the first heat treatment are as described above. The oxide semiconductor film OS1 is crystallized by the first heat treatment to form an oxide semiconductor layer 140 including Poly-OS (see Fig.10 ).

[0120] In step S150, a first opening OP1 is formed in the first insulating layer 130 by using a photolithography method (see Fig.11 ). In the first opening OP1, a portion of the scanning line 120 is exposed.

[0121] In step S160, a second conductive film CF2 (see FIG. 1 ) is formed by sputtering to cover the oxide semiconductor layer 140 and the first opening OP1. Fig.12 ). For example, the second conductive film CF2 is a stacked film (Ti / Al / Ti film) including titanium and aluminum.

[0122] In step S170, the second conductive film CF2 is patterned by photolithography to form the source electrode 150, the drain electrode 160, and the connection electrode 170 (see Fig.13). The source electrode 150 and the drain electrode 160 are connected to the oxide semiconductor layer 140, and the connecting electrode 170 is connected to the scanning line 120 via the first opening OP1. The etching of the second conductive film CF2 is preferably wet etching using an etching solution. As described above, the oxide semiconductor layer 140 including Poly-OS has excellent etching resistance. Therefore, when the second conductive film CF2 is etched using an etching solution, the oxide semiconductor layer 140 is hardly etched. Therefore, in the oxide semiconductor layer 140, the difference between the film thickness of the first region connected to one of the source electrode 150 and the drain electrode and the film thickness of the second region not connected to the source electrode 150 and the drain electrode is 3 nm or less. It should be noted that the difference between the film thickness of the first region and the film thickness of the second region can also be set to less than 2 nm by adjusting the etching conditions, preferably less than 1 nm, and more preferably less than 0.5 nm.

[0123] In step S180, the second insulating layer 180 is formed by CVD. In addition, the second opening OP2 is formed by photolithography in the second insulating layer 180. In the second opening OP2, a part of the connection electrode 170 is exposed.

[0124] In step S190, the oxide semiconductor film OS2 is formed on the second insulating layer 180 by sputtering. The film forming conditions of the oxide semiconductor film OS2 are as described above. Since the oxide semiconductor film OS2 has an amorphous structure, it is easy to etch the oxide semiconductor film OS2. Therefore, the oxide semiconductor film OS2 is patterned by photolithography (see Fig.15 ).

[0125] In step S200, a second heat treatment is performed on the oxide semiconductor layer 140 and the oxide semiconductor film OS2. Oxygen defects may be generated in the oxide semiconductor layer 140 due to a process after the formation of the oxide semiconductor layer 140. By performing the second heat treatment, oxygen is supplied from the first insulating layer 130 and the second insulating layer 180 to the oxide semiconductor layer 140 to repair the oxygen defects. In particular, in the second heat treatment, since the oxide semiconductor film OS2 is formed on the second insulating layer 180 overlapping with the oxide semiconductor layer 140, the oxide semiconductor film OS2 suppresses the release of oxygen in the second insulating layer 180 to the outside, thereby enabling efficient supply of oxygen to the oxide semiconductor layer 140. In addition, by the second heat treatment, the oxide semiconductor film OS2 is crystallized to form a second gate electrode 190 including Poly-OS (see Fig.16 ). However, the second gate electrode 190 formed in step S200 may not have a sufficiently low resistance. Therefore, in order to reduce the resistance of the second gate electrode 190, step S210 is performed.

[0126] In step S210, the nitride layer 200 is formed by a CVD method, a sputtering method or an ALD method. As the nitride layer 200, silicon nitride is preferably used. Although the silicon nitride is formed by the CVD method, oxygen defects are generated in the second gate electrode 190 due to the reactive gas present in the chamber. In addition, the gas used in the CVD method mostly contains hydrogen, and a large amount of hydrogen exists in the chamber during film formation. In addition, the first substrate 100 is heated in the CVD method. Therefore, when the silicon nitride is formed on the second gate electrode 190 in step S210, oxygen defects are generated in the second gate electrode 190, and hydrogen diffuses into the second gate electrode 190 and is captured by the oxygen defects. As a result, the second gate electrode 190 is sufficiently low in resistance. When the second gate electrode 190 is not sufficiently low in resistance only by the formation of the nitride layer 200, heat treatment may also be performed after step S210. Since the second gate electrode 190 is in contact with the nitride layer 200, oxygen in the second gate electrode 190 is extracted into the nitride layer 200 by the heat treatment, thereby generating oxygen defects in the second gate electrode 190. In addition, hydrogen contained in the nitride layer 200 is diffused into the second gate electrode 190 by the heat treatment. Thus, the resistance of the second gate electrode 190 is further reduced.

[0127] Through the above steps, we can produce Figure 3 and Figure 4 The semiconductor device 10 manufactured in this way has a 30 cm 2 / Vs or higher field effect mobility.

[0128] According to the semiconductor device 10, since the second gate electrode 190 has light transmittance, it is possible to suppress a decrease in the aperture ratio of the pixel PX. In addition, according to the manufacturing method of the semiconductor device 10, it is possible to repair oxygen defects in the oxide semiconductor layer 140 including Poly-OS and reduce the resistance of the second gate electrode 190 including Poly-OS by a single heat treatment. Therefore, it is possible to suppress the manufacturing cost of the semiconductor device 10. In addition, since the oxide semiconductor layer 140 includes Poly-OS and has excellent etching resistance, it has stable properties not only during the manufacture of the semiconductor device 10 but also after the manufacture. Therefore, the semiconductor device 10 has high reliability.

[0129] <Modification 1 of the first embodiment>

[0130] Reference Figure 17 to Figure 19 A modified example of the method for manufacturing the semiconductor device 10 will be described. Note that, in the following, description of the same configuration as that of the semiconductor device 10 may be omitted.

[0131] Fig.17 1 is a flowchart illustrating a method for manufacturing the semiconductor device 10 according to an embodiment of the present invention. Fig.18 and Fig.19 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Fig.17 The steps of the flowchart shown.

[0132] Steps S100 to S190 are as follows: Figure 5 The steps described above are the same, so description thereof is omitted here. In this modification, step S210 is performed after step S190 and before step S200.

[0133] In step S210, a nitride layer 200 is formed by using a CVD method, a sputtering method, or an ALD method (see Fig.18 ). In step S210 of this modification, a nitride layer 200 is formed on the oxide semiconductor film OS2 having an amorphous structure. Oxygen vacancies are generated in the oxide semiconductor film OS2 by the formation of the nitride layer 200, and hydrogen is trapped in the generated oxygen vacancies. Step S200 is performed after step S210.

[0134] In step S200, the oxide semiconductor layer 140 and the oxide semiconductor film OS2 are subjected to a second heat treatment. In the second heat treatment, since the oxide semiconductor film OS2 is formed on the second insulating layer 180 overlapping with the oxide semiconductor layer 140, the oxide semiconductor film OS2 suppresses the release of oxygen in the second insulating layer 180 to the outside, thereby enabling efficient supply of oxygen to the oxide semiconductor layer 140. The oxide semiconductor film OS2 is crystallized by the second heat treatment to form a second gate electrode 190 including Poly-OS (see Fig.19 ). In step S200 of this modification, since hydrogen is trapped in the oxygen vacancies of the oxide semiconductor film OS2, it is difficult to repair the oxygen vacancies. Therefore, the resistance of the second gate electrode 190 is reduced.

[0135] Through the above steps, we can produce Figure 3 and Figure 4 The semiconductor device 10 manufactured in this way also has a 30cm 2 / Vs or higher field effect mobility.

[0136] In the semiconductor device 10 manufactured in this modification, since the second gate electrode 190 has light transmittance, the decrease in the aperture ratio of the pixel PX can also be suppressed. In addition, according to the manufacturing method of the semiconductor device 10 in this modification, the oxygen defects of the oxide semiconductor layer 140 containing Poly-OS and the second gate electrode 190 containing Poly-OS can be repaired by a single heat treatment. Therefore, the manufacturing cost of the semiconductor device 10 can be suppressed. In addition, since the oxide semiconductor layer 140 contains Poly-OS, it has excellent etching resistance and thus has stable properties not only during the manufacture of the semiconductor device 10 but also after the manufacture. Therefore, the semiconductor device 10 has high reliability.

[0137] <Modification 2 of the first embodiment>

[0138] Reference Fig. 20 and Fig.21 Hereinafter, another modification of the method for manufacturing the semiconductor device 10 will be described. Note that, in the following, description of the same configuration as that of the semiconductor device 10 may be omitted.

[0139] Fig. 20 1 is a flowchart illustrating a method for manufacturing the semiconductor device 10 according to an embodiment of the present invention. Fig.21 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Fig. 20 The steps of the flowchart shown.

[0140] Steps S100 to S190 and step S210 are similar to those in the reference Fig.17 The steps described are the same, and thus description thereof is omitted. In this modification, step S220 is performed after step S210 and before step S200.

[0141] In step S220, an impurity element is added to the oxide semiconductor film OS2 by an ion implantation method, thereby forming an oxide semiconductor film OS3 including the impurity element and having an amorphous structure (see Fig.21 ). The impurity element is added to the oxide semiconductor film OS2 via the nitride layer 200. For example, the impurity element is boron (B) or phosphorus (P), but is not limited thereto. In the oxide semiconductor film OS3 to which the impurity element is added, oxygen defects are generated. Step S200 is performed after step S220.

[0142] In step S200, a second heat treatment is performed on the oxide semiconductor layer 140 and the oxide semiconductor film OS3. The oxide semiconductor film OS2 is crystallized by the second heat treatment to form a second gate electrode 190 including a Poly-OS. It should be noted that the second gate electrode 190 includes an impurity element. In a Poly-OS in which oxygen defects are generated and which includes an impurity element, it is difficult to repair the oxygen defects by the impurity element. In addition, since hydrogen is captured in the oxygen defects, the oxygen defects in the Poly-OS are stabilized. Therefore, the conductivity of the second gate electrode 190 including the Poly-OS containing the impurity element is stable.

[0143] Through the above steps, we can produce Figure 3 and Figure 4 The semiconductor device 10 manufactured in this way also has a 30cm 2 / Vs or higher field effect mobility.

[0144] In the semiconductor device 10 manufactured in this variant, since the second gate electrode 190 is light-transmissive, the decrease in the aperture ratio of the pixel PX can be suppressed. In addition, according to the manufacturing method of the semiconductor device 10 in this variant, the oxygen defects of the oxide semiconductor layer 140 containing Poly-OS and the low resistance of the second gate electrode 190 containing Poly-OS can be repaired by a single heat treatment. Therefore, the manufacturing cost of the semiconductor device 10 can be suppressed. In addition, since the oxide semiconductor layer 140 contains Poly-OS, it has excellent etching resistance and thus has stable properties not only during the manufacture of the semiconductor device 10 but also after the manufacture. In addition, the conductivity of the second gate electrode 190 is also stable. Therefore, the semiconductor device 10 has high reliability.

[0145] <Modification 3 of the first embodiment>

[0146] Reference Fig. 22 and Fig.23 A semiconductor device 10A will be described as a modified example of the semiconductor device 10. In the following, description of the same configuration as that of the semiconductor device 10 may be omitted.

[0147] Fig. 22 It is a schematic plan view showing the structure of a semiconductor device 10A according to one embodiment of the present invention. Fig.23 It is a schematic cross-sectional view showing the structure of a semiconductor device 10A according to one embodiment of the present invention.

[0148] In a plan view, the second gate electrode 190A is located between the source electrode 150 and the drain electrode 160. The second gate electrode 190A has a gap g with respect to the source electrode 150. sThe configuration has a gap g with respect to the drain electrode 160. d Here, the gap g s is the distance from one end surface of the second gate electrode 190 to the end surface of the source electrode 150, and the gap g d The gap g is the distance from the other end surface of the second gate electrode 190A to the end surface of the drain electrode 160. s Can be with gap g d Same as the gap g d Different. Gap g s and gap g d The gap g is 0.1 μm to 2.0 μm, preferably 0.3 μm to 1.5 μm, and more preferably 0.5 μm to 1.0 μm. s and gap g d , thereby preventing the occurrence of an inter-electrode short circuit between the second gate electrode 190A and the source electrode 150 or the drain electrode 160. In the semiconductor device 10A, the first gate electrode 110 and the oxide semiconductor layer 140 corresponding to the gap g s and gap g d Therefore, a channel is also formed in this region. s and gap g d If the gap g is smaller than 0.1 μm, short circuits between electrodes are likely to occur between the second gate electrode 190A and the source electrode 150 or the drain electrode 160. s and gap g d If the gap g is larger than 2.0 μm, the current flowing in the channel decreases, and the field effect mobility decreases. s and gap g d The range of is preferably within the above range.

[0149] As described above, in order to suppress the occurrence of inter-electrode short circuits between the second gate electrode 190A and the source electrode 150 or the drain electrode 160, the second gate electrode 190A does not overlap with the source electrode 150 and the drain electrode 160 in a plan view. Fig. 22 As shown, the second gate electrode 190A extends to surround the end of the drain electrode 160. It should be noted that the second gate electrode 190A only needs to extend to surround the end of one of the source electrode 150 and the drain electrode 160 and be electrically connected to the scanning line 120.

[0150] According to the semiconductor device 10A, even when the second gate electrode 190A surrounds the end of the source electrode 150 or the drain electrode 160 in a plan view and the area of ​​the non-overlapping region is large, the second gate electrode 190A has light transmittance, so it is possible to suppress a decrease in the aperture ratio of the pixel PX. In addition, by arranging the second gate electrode 190A with a gap between the source electrode 150 and the drain electrode 160 without overlapping the source electrode 150 and the drain electrode 160 in a plan view, it is possible to suppress the occurrence of a short circuit between electrodes. Therefore, the semiconductor device 10A has high reliability.

[0151] <Variation 4 of the first embodiment>

[0152] Reference Fig.24 A semiconductor device 10B will be described as another modified example of the semiconductor device 10. In the following, description of the same configuration as that of the semiconductor device 10 may be omitted.

[0153] Fig.24 It is a schematic plan view showing the structure of a semiconductor device 10B according to an embodiment of the present invention.

[0154] The semiconductor device 10B includes a plurality of oxide semiconductor layers 140 (a first oxide semiconductor layer 140-1, a second oxide semiconductor layer 140-2, and a third oxide semiconductor layer 140-3). The first oxide semiconductor layer 140-1 to the third oxide semiconductor layer 140-3 are respectively formed in an island shape. That is, the first oxide semiconductor layer 140-1 to the third oxide semiconductor layer 140-3 are arranged separately from each other. In the semiconductor device 10B having a high field effect mobility, since a large current flows through a channel formed in the oxide semiconductor layer 140, the oxide semiconductor layer 140 sometimes generates heat. In particular, the larger the area of ​​the oxide semiconductor layer 140, the more significantly the heat generated by the oxide semiconductor layer 140 is manifested. Therefore, in the semiconductor device 10B, the area of ​​one oxide semiconductor layer 140 is reduced, and a plurality of oxide semiconductor layers 140 are arranged. As a result, the amount of current flowing in the channel can be maintained while suppressing the heat generated by the oxide semiconductor layer 140.

[0155] According to the semiconductor device 10B, since the second gate electrode 190 has light-transmitting properties, a decrease in the aperture ratio of the pixel PX can be suppressed. In addition, in the semiconductor device 10B, heat generation of the oxide semiconductor layer 140 can be suppressed. Therefore, the semiconductor device 10B has high reliability.

[0156] <Second embodiment>

[0157] Poly-OS can control crystallinity by using a buffer layer. Therefore, in this embodiment, a semiconductor device 11 including a buffer layer is described. It should be noted that the description of the same configuration as that of the semiconductor device 10 may be omitted below.

[0158] [1. Configuration of Semiconductor Device 11]

[0159] Reference Fig.25 A semiconductor device 11 according to an embodiment of the present invention will be described.

[0160] Fig.25 It is a schematic cross-sectional view showing the structure of a semiconductor device 11 according to an embodiment of the present invention.

[0161] like Fig.25 As shown, the semiconductor device 11 includes a first substrate 100, a first gate electrode 110, a scanning line 120, a first insulating layer 130, an oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a connecting electrode 170, a second insulating layer 180, a metal oxide layer 210, a second gate electrode 190 and a nitride layer 200. The metal oxide layer 210 is provided on the second insulating layer 180 in a manner overlapping with the oxide semiconductor layer 140. The second insulating layer 180 and the metal oxide layer 210 have a second opening OP2 for exposing a portion of the upper surface of the connecting electrode 170. The second gate electrode 190 is provided on the metal oxide layer 210 in contact with the metal oxide layer 210. The second gate electrode 190 has a planar shape substantially the same as that of the metal oxide layer 210. That is, the end face of the second gate electrode 190 is substantially consistent with the end face of the metal oxide layer 210. The second gate electrode 190 is in contact with the connecting electrode 170 via the second opening OP2. The nitride layer 200 is provided on the second insulating layer 180 so as to cover the end surface of the metal oxide layer 210 and the upper surface and the end surface of the second gate electrode 190 .

[0162] The metal oxide layer 210 can function as a buffer layer that improves the crystallinity of the Poly-OS included in the second gate electrode 190. The second gate electrode 190 including the Poly-OS having improved crystallinity can further reduce the resistance.

[0163] For example, a metal oxide containing aluminum as a main component may be used as the metal oxide layer 210. The ratio of aluminum contained in the metal oxide layer 210 may be 5% to 70%, 10% to 60% or 30% to 50% of the entire metal oxide layer 210. The above ratio may be a mass ratio or a weight ratio.

[0164] The thickness of the metal oxide layer 210 is 1 nm to 10 nm, preferably 1 nm to 5 nm. Aluminum oxide is preferably used as the metal oxide layer 210. Aluminum oxide has a high barrier property against gases such as oxygen and hydrogen. Here, barrier property refers to the function of inhibiting the permeation of gases such as oxygen and hydrogen.

[0165] It should be noted that a metal oxide mainly composed of a metal other than aluminum may be used as the metal oxide layer 210. For example, the metal oxide layer 210 may be indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO).

[0166] [2. Method for Manufacturing Semiconductor Device 11]

[0167] Reference Figure 26 to Figure 31 A method for manufacturing the semiconductor device 11 will be described.

[0168] Fig.26 1 is a flowchart illustrating a method for manufacturing the semiconductor device 11 according to an embodiment of the present invention. Figure 27 to Figure 31 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 11 according to an embodiment of the present invention. Fig.26 The steps of the flowchart shown.

[0169] Steps S100 to S170 are similar to those in the first embodiment. Figure 5 The steps described are the same, and thus description thereof is omitted here. In the manufacture of the semiconductor device 11 , step S181 is performed after step S170 .

[0170] In step S181, the second insulating layer 180 and the metal oxide film MO are sequentially formed (see Fig. 27 ). The second insulating layer 180 is formed by a CVD method. The metal oxide film MO is formed by a sputtering method or an atomic layer deposition method (ALD method). For example, the second insulating layer 180 includes silicon oxide in contact with the oxide semiconductor layer 140. In addition, for example, aluminum oxide is used as the metal oxide film MO. Step S182 is performed after step S181.

[0171] In step S182, a second opening OP2 is formed in the second insulating layer 180 and the metal oxide film MO by using a photolithography method (see Fig.28 ). In the second opening OP2, a portion of the connection electrode 170 is exposed. After step S182, step S190 is performed.

[0172] In step S190, the oxide semiconductor film OS2 is formed on the metal oxide film MO by sputtering. The film forming conditions of the oxide semiconductor film OS2 are as described above. Since the oxide semiconductor film OS2 has an amorphous structure, it is easy to etch the oxide semiconductor film OS2. Therefore, the oxide semiconductor film OS2 is patterned by photolithography (see Fig.29 ). The oxide semiconductor film OS2 is in contact with the connection electrode 170 via the second opening OP2. Step S200 is performed after step S190.

[0173] In step S200, the oxide semiconductor layer 140 and the oxide semiconductor film OS2 are subjected to a second heat treatment. In the second heat treatment, since the metal oxide film MO covering the second insulating layer 180 is formed, the metal oxide film MO suppresses the release of oxygen in the second insulating layer 180 to the outside, thereby enabling efficient supply of oxygen to the oxide semiconductor layer 140. In addition, the oxide semiconductor film OS2 is crystallized by the second heat treatment to form the second gate electrode 190 including Poly-OS (see Fig.30 The metal oxide film MO functions as a buffer layer, and the crystallinity of the second gate electrode 190 is controlled. Specifically, the size of the crystal grains included in the second gate electrode 190 is increased to increase the crystallinity of the second gate electrode 190. After step S200, step S230 is performed.

[0174] In step S230, the metal oxide film MO is patterned using the second gate electrode 190 as a mask to form a metal oxide layer 210 (see Fig.31 ). The second gate electrode 190 including Poly-OS has excellent etching resistance. Therefore, even when the metal oxide film MO is etched during patterning of the metal oxide film MO, the second gate electrode 190 used as a mask will not be etched. In the semiconductor device 11, the second gate electrode 190 can be used as a mask in the formation of the metal oxide layer 210, so the photolithography process can be omitted. Step S210 is performed after step S230.

[0175] In step S210, the nitride layer 200 is formed by CVD, sputtering, or ALD. When the nitride layer 200 is formed on the second gate electrode 190, oxygen defects are generated in the second gate electrode 190, and hydrogen diffuses into the second gate electrode 190 and is trapped by the oxygen defects. As a result, the resistance of the second gate electrode 190 is sufficiently reduced.

[0176] Through the above steps, we can produce Fig.25 The semiconductor device 11 manufactured in this way has a 30 cm 2 / Vs or higher field effect mobility.

[0177] According to the semiconductor device 11, since the second gate electrode 190 has light transmittance, it is possible to suppress a decrease in the aperture ratio of the pixel PX. In addition, according to the manufacturing method of the semiconductor device 11, it is possible to repair oxygen defects in the oxide semiconductor layer 140 including Poly-OS and reduce the resistance of the second gate electrode 190 including Poly-OS by a single heat treatment. Therefore, it is possible to suppress the manufacturing cost of the semiconductor device 11. In addition, the crystallinity of the second gate electrode 190 is increased and stabilized by the metal oxide layer 210. Therefore, the semiconductor device 11 has high reliability.

[0178] <Modification of Second Embodiment>

[0179] Reference Figure 32 to Figure 39 A semiconductor device 11C is described as a modified example of the semiconductor device 11. It should be noted that the description of the same configuration as the semiconductor device 10 is sometimes omitted below. In addition, for convenience of description, the connection electrode 170 described in the first embodiment is described below as the first connection electrode 170.

[0180] [1. Configuration of Semiconductor Device 11C]

[0181] Fig.32 It is a schematic plan view showing the structure of a semiconductor device 11C according to one embodiment of the present invention. Fig.33 It is a schematic cross-sectional view showing the structure of a semiconductor device 11C according to one embodiment of the present invention. Fig.33 It is used Fig.32 11C is a cross-sectional view of the semiconductor device 11C taken along the line B1 - B2 in FIG.

[0182] like Fig.33As shown, the semiconductor device 11C includes a first substrate 100, a first gate electrode 110, a scanning line 120, a first insulating layer 130, an oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a first connection electrode 170, a second insulating layer 180, a metal oxide layer 210C, a second gate electrode 190C, a nitride layer 200, a third insulating layer 220 and a second connection electrode 230. The metal oxide layer 210C is disposed on the second insulating layer 180 in a manner overlapping with the oxide semiconductor layer 140. The second gate electrode 190C is disposed on the metal oxide layer 210C in contact with the metal oxide layer 210C. The second gate electrode 190C has a planar shape substantially the same as that of the metal oxide layer 210C. That is, the end face of the second gate electrode 190C is substantially consistent with the end face of the metal oxide layer 210C. In a plan view, the metal oxide layer 210C and the second gate electrode 190C do not overlap with the first connection electrode 170. The nitride layer 200 covers the end surface of the metal oxide layer 210C and the upper surface and end surface of the second gate electrode 190C, and is disposed on the second insulating layer 180. The third insulating layer 220 is disposed on the nitride layer 200. The second insulating layer 180, the nitride layer 200, and the third insulating layer 220 have a second opening OP2 for exposing a portion of the upper surface of the first connecting electrode 170. In addition, the nitride layer 200 and the third insulating layer 220 have a third opening OP3 for exposing a portion of the upper surface of the second gate electrode 190. The second connecting electrode 230 is disposed on the third insulating layer 220. The second connecting electrode 230 is connected to the first connecting electrode 170 via the second opening OP2, and is connected to the second gate electrode 190C via the third opening OP3.

[0183] like Fig.32 As shown, the second gate electrode 190C is provided separately from the first connection electrode 170. However, as described above, the second connection electrode 230 is in contact with the first connection electrode 170 and the second gate electrode 190C. Therefore, the second gate electrode 190C is electrically connected to the first gate electrode 110 via the first connection electrode 170 and the second connection electrode 230. Therefore, the voltage included in the signal input to the scan line 120 is applied to both the first gate electrode 110 and the second gate electrode 190C.

[0184] The third insulating layer 220 can function as an interlayer insulating layer. For example, as the third insulating layer 220, the same material as the first insulating layer 130 and the second insulating layer 180 can be used. In addition, the third insulating layer 220 can also function as a planarization layer. In this case, for example, as the third insulating layer 220, a resin such as polyimide or acrylic can be used. The resin can also be a photosensitive resin. In the case where a photosensitive resin is used as the third insulating layer 220, since the photosensitive resin can be directly exposed to light for etching without applying a resist, the process using the photolithography method is simplified. In addition, the third insulating layer 220 can have a single-layer structure or a stacked structure. In the case where the third insulating layer 220 has a stacked structure, the third insulating layer 220 can also have a structure in which a resin is stacked on an oxide or a nitride.

[0185] The second connection electrode 230 is conductive. As the second connection electrode 230, the same material as the first connection electrode 170 can be used. In addition, as the second connection electrode 230, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) can also be used. Since the second connection electrode 230 not only overlaps with the source electrode 150 or the drain electrode 160 but also overlaps with the scanning line 120, the aperture ratio of the pixel PX is almost not reduced. Therefore, as the second connection electrode 230, not only a light-transmitting material can be used, but also a non-light-transmitting material can be used.

[0186] [2. Method for Manufacturing Semiconductor Device 11C]

[0187] Reference Figure 34 to Figure 39 A method for manufacturing the semiconductor device 11C will be described.

[0188] Fig.34 1 is a flowchart for explaining a method for manufacturing a semiconductor device 11C according to an embodiment of the present invention. Figure 35 to Figure 39 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 11C according to an embodiment of the present invention. Fig.34 The steps of the flowchart shown.

[0189] Steps S100 to S170 and step S181 are similar to those in the reference Fig.26 The steps described are the same, and thus description thereof is omitted here. In the manufacture of the semiconductor device 11C, step S190 is performed after step S170.

[0190] In step S190, the oxide semiconductor film OS2 is formed on the metal oxide film MO by sputtering. The film forming conditions of the oxide semiconductor film OS2 are as described above. Since the oxide semiconductor film OS2 has an amorphous structure, it is easy to etch the oxide semiconductor film OS2. Therefore, the oxide semiconductor film OS2 is patterned by photolithography (see Fig.35 ). Step S200 is implemented after step S190.

[0191] In step S200, the oxide semiconductor layer 140 and the oxide semiconductor film OS2 are subjected to a second heat treatment. In the second heat treatment, since the metal oxide film MO covering the second insulating layer 180 is formed, the metal oxide film MO suppresses the release of oxygen in the second insulating layer 180 to the outside, thereby enabling efficient supply of oxygen to the oxide semiconductor layer 140. In addition, the oxide semiconductor film OS2 is crystallized by the second heat treatment to form a second gate electrode 190C including Poly-OS (see Fig.36 The metal oxide film MO functions as a buffer layer, and the crystallinity of the second gate electrode 190C is controlled. Specifically, the size of the crystal grains included in the second gate electrode 190C is increased to increase the crystallinity of the second gate electrode 190C. Step S230 is performed after step S200.

[0192] In step S230, the metal oxide film MO is patterned using the second gate electrode 190C as a mask to form a metal oxide layer 210C (see Fig.37 ). The second gate electrode 190C including Poly-OS has excellent etching resistance. Therefore, even when the metal oxide film MO is etched during patterning of the metal oxide film MO, the second gate electrode 190C used as a mask will not be etched. In the semiconductor device 11C, the second gate electrode 190C can be used as a mask in the formation of the metal oxide layer 210C, so the photolithography process can be omitted. Step S210 is performed after step S230.

[0193] In step S210, a nitride layer 200 is formed by using a CVD method, a sputtering method, or an ALD method (see Fig.38 ). Oxygen defects are generated in the second gate electrode 190C, and hydrogen diffuses into the second gate electrode 190C and is trapped by the oxygen defects. As a result, the resistance of the second gate electrode 190C is sufficiently reduced. Step S240 is performed after step S210.

[0194] In step S240, the third insulating layer 220 is formed on the second insulating layer 180 by coating. In addition, the second opening OP2 penetrating the second insulating layer 180, the nitride layer 200 and the third insulating layer 220 and the third opening OP3 penetrating the nitride layer 200 and the third insulating layer 220 are formed by photolithography (see FIG. Fig.39 ). When the third insulating layer 220 is photosensitive, the second opening OP2 and the third opening OP3 can be formed without using a photoresist. In the second opening OP2, a portion of the first connection electrode 170 is exposed. In the third opening OP3, a portion of the second gate electrode 190C is exposed. Step S250 is performed after step S240.

[0195] In step S250, a fourth conductive film is formed on the third insulating layer 220 by sputtering, and the fourth conductive film is patterned by photolithography to form the second connection electrode 230. The second connection electrode 230 is connected to the first connection electrode 170 via the second opening OP2, and is connected to the second gate electrode 190C via the third opening OP3.

[0196] Through the above steps, we can produce Fig.32 and Fig.33 The semiconductor device 11C manufactured in this way has a 30 cm 2 / Vs or higher field effect mobility.

[0197] According to the semiconductor device 11C, since the second gate electrode 190 has light transmittance, it is possible to suppress a decrease in the aperture ratio of the pixel PX. In addition, according to the manufacturing method of the semiconductor device 11C, it is possible to repair oxygen defects in the oxide semiconductor layer 140 including Poly-OS and reduce the resistance of the second gate electrode 190 including Poly-OS by a single heat treatment. Therefore, it is possible to suppress the manufacturing cost of the semiconductor device 11C. In addition, the crystallinity of the second gate electrode 190 is increased and stabilized by the metal oxide layer 210. Therefore, the semiconductor device 11C has high reliability.

[0198] The various embodiments and variations described above as embodiments of the present invention can be appropriately combined and implemented as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or designing components or adding, omitting or changing conditions of processes based on the various embodiments and variations by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0199] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

Claims

1. A semiconductor device comprising: a first gate electrode; an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode on the source electrode and the drain electrode and overlapping the first gate electrode and the oxide semiconductor layer; the second gate electrode includes a second oxide semiconductor having a polycrystalline structure, The second gate electrode is electrically connected to the first gate electrode.

2. The semiconductor device according to claim 1, wherein The second gate electrode has a sheet resistance of 1000 Ω / sq. or less.

3. The semiconductor device according to claim 1, wherein The second gate electrode overlaps with at least one of the source electrode and the drain electrode in a plan view.

4. The semiconductor device according to claim 1, wherein The second gate electrode is arranged with gaps between the source electrode and the drain electrode in a plan view.

5. The semiconductor device according to claim 4, wherein: The second gate electrode extends so as to surround an end portion of one of the source electrode and the drain electrode in the plan view.

6. The semiconductor device according to claim 1, wherein Furthermore, a metal oxide layer is included below the second gate electrode and is in contact with the second gate electrode.

7. The semiconductor device according to claim 6, wherein: Furthermore, a connecting electrode connected to the second gate electrode is included on the second gate electrode. The second gate electrode is electrically connected to the first gate electrode via the connection electrode.

8. The semiconductor device according to claim 1, wherein The oxide semiconductor layer includes: a first region connected to one of the source electrode and the drain electrode; and a second region between the source electrode and the drain electrode and overlapping the second gate electrode, A difference between the film thickness of the first region and the film thickness of the second region is 3 nm or less.

9. The semiconductor device according to claim 1, wherein: When the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C., the etching rate is less than 3 nm / min.

10. The semiconductor device according to claim 9, wherein The etching solution includes nitric acid and acetic acid.

11. The semiconductor device according to claim 9, wherein The oxide semiconductor layer is formed by heat treating an oxide semiconductor film having an amorphous structure. When the oxide semiconductor film is etched using the etching solution at 40° C., an etching rate is 100 nm / min or more.

12. The semiconductor device according to claim 1, wherein When the oxide semiconductor layer is etched using a 0.5% hydrofluoric acid solution at room temperature, an etching rate is less than 5 nm / min.

13. The semiconductor device according to claim 1, wherein The oxide semiconductor layer and the second gate electrode respectively contain a plurality of metal elements, One of the plurality of metal elements is indium, The atomic ratio of the indium to the plurality of metal elements is 50% or more.

14. A method for manufacturing a semiconductor device, wherein: forming a first gate electrode, forming an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode, forming a source electrode and a drain electrode in contact with the oxide semiconductor layer, forming a first oxide semiconductor film on the source electrode and the drain electrode, performing heat treatment on the first oxide semiconductor film to form a second gate electrode including a second oxide semiconductor having a polycrystalline structure, A nitride layer is formed to cover the second gate electrode.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The oxide semiconductor layer includes: a first region connected to one of the source electrode and the drain electrode; and a second region between the source electrode and the drain electrode and overlapping the second gate electrode, A difference between the film thickness of the first region and the film thickness of the second region is 3 nm or less.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: When the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C., the etching rate is less than 3 nm / min.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The etching solution includes nitric acid and acetic acid.

18. The method for manufacturing a semiconductor device according to claim 16, wherein: The oxide semiconductor layer is formed by heat treating an oxide semiconductor film having an amorphous structure. When the oxide semiconductor film is etched using the etching solution at 40° C., an etching rate is 100 nm / min or more.

19. The method for manufacturing a semiconductor device according to claim 14, wherein: When the oxide semiconductor layer is etched using a 0.5% hydrofluoric acid solution at room temperature, an etching rate is less than 5 nm / min.

20. The method for manufacturing a semiconductor device according to claim 14, wherein: The oxide semiconductor layer and the second gate electrode respectively contain a plurality of metal elements, One of the plurality of metal elements is indium, The atomic ratio of the indium to the plurality of metal elements is 50% or more.

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