Semiconductor device

Abstract

The invention provides a semiconductor device with high reliability. The semiconductor device includes: a first gate electrode; an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode that overlaps the first gate electrode and the oxide semiconductor layer on the source electrode and the drain electrode, the second gate electrode being disposed so as to have a gap with each of the source electrode and the drain electrode in plan view, and the second gate electrode being electrically connected to the first gate electrode.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor having a polycrystalline structure. Background Art

[0002] In recent years, the development of semiconductor devices that use oxide semiconductor films as channels instead of silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon has been continuously developed (for example, see Patent Documents 1 to 6). Semiconductor devices including oxide semiconductor films have a simple structure like semiconductor devices including amorphous silicon films and can be formed by low-temperature processes. In addition, it is known that semiconductor devices including oxide semiconductor films have higher field effect mobility than semiconductor devices including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] Semiconductor devices are required to have not only high field effect mobility but also high reliability. One object of one embodiment of the present invention is to provide a semiconductor device with high reliability.

[0013] Means for solving problems

[0014] A semiconductor device involved in one embodiment of the present invention includes: a first gate electrode; an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure above the first gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode above the source electrode and the drain electrode and overlapping with the first gate electrode and the oxide semiconductor layer, wherein the second gate electrode is configured with a gap relative to the source electrode and the drain electrode, respectively, when observed from above, and the second gate electrode is electrically connected to the first gate electrode.

[0015] A semiconductor device according to one embodiment of the present invention includes: a first gate electrode; a scan line formed by the same layer as the first gate electrode and configured in a manner electrically connected to the first gate electrode; an oxide semiconductor layer including an oxide semiconductor having a polycrystalline structure above the first gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; a second gate electrode overlapping the first gate electrode and the oxide semiconductor layer above the source electrode and the drain electrode; an insulating layer above the second gate electrode, the insulating layer including a first opening portion through which a portion of the second gate electrode is exposed; and a first connecting electrode electrically connected to the second gate electrode via the first opening portion, wherein the second gate electrode and the source electrode and the drain electrode are respectively configured with gaps therebetween when viewed from above, and the first connecting electrode is electrically connected to the scan line via the second opening portion through which a portion of the scan line is exposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic exploded perspective view showing the structure of the display device.

[0017] Figure 2 It is a schematic plan view showing the circuit configuration of a display device.

[0018] Figure 3 It is a schematic plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0019] Figure 4 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0020] Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0021] Figure 6 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0022] Figure 7 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0023] Figure 8 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0024] Fig. 9 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0025] Fig.10It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0026] Fig.11 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0027] Fig.12 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] Fig.13 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0029] Fig.14 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] Fig.15 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Fig.16 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0032] Fig.17 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0033] Fig.18 It is a schematic plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0034] Fig.19 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0035] Fig. 20 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0036] Fig.21 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0037] Fig. 22 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0038] Fig.23 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0039] Fig.24 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0040] Fig.25 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0041] Fig.26 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0042] Fig. 27 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0043] Fig.28 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0044] Fig.29 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0045] Fig.30 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0046] Fig.31 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0047] Fig.32 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0048] Fig.33 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0049] Fig.34 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0050] Fig.35 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0051] Fig.36 It is a schematic plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0052] Fig.37 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0053] Fig.38 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0054] Fig.39 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0055] Fig.40 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0056] Fig.41 It is a schematic plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0057] Description of Reference Numerals

[0058] 1: display device, 2: display unit, 3: light source unit, DP: display portion, DRV: driving element, FPC: flexible wiring substrate, GD: scanning line driving circuit, GL: scanning line, PX: pixel, SD: signal line driving circuit, SL: signal line, TP: terminal portion, 10, 10A, 10B, 10C, 11, 12, 12A: semiconductor device, 20: liquid crystal element, 100: first substrate, 110: first gate electrode, 120: scanning line, 130: first insulating layer, 140: oxide semiconductor layer, 140-1: first oxide semiconductor layer, 140-2: second oxide semiconductor layer, 140-3: third oxide semiconductor layer, 150: source electrode, 160: Drain electrode, 170: connecting electrode (first connecting electrode), 180: second insulating layer, 190, 190B: second gate electrode, 200: metal oxide layer, 210: second gate electrode, 220: nitride layer, 230: second gate electrode, 240: second connecting electrode, 250: third insulating layer, 260, 260A: third connecting electrode, 300: second substrate, CF1: first conductive film, CF2: second conductive film, CF3: third conductive film, MO: metal oxide film, OP1: first opening, OP2: second opening, OP3: third opening, OP4: fourth opening, OS: oxide semiconductor film, OS1: oxide semiconductor film, OS2: oxide semiconductor film DETAILED DESCRIPTION

[0059] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily thought of by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, film thickness and shape of the constituent elements are sometimes schematically indicated compared to the actual method. However, the illustrated shape is only an example and does not limit the interpretation of the present invention. In this specification and the accompanying drawings, the same figure mark is marked for the constituent elements that are the same as the constituent elements described in the figures that have appeared, and the detailed description is sometimes appropriately omitted.

[0060] In this specification, etc., the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for the sake of convenience, the above or below phrases are used for explanation, but the up-and-down relationship between the substrate and the oxide semiconductor layer may also be configured in the opposite direction to that shown in the figure. In addition, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer, and other components may be configured between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure in which a plurality of layers are stacked. In the case of the expression "pixel electrode above the semiconductor device", it may also be a positional relationship in which the semiconductor device and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of the expression "pixel electrode vertically above the semiconductor device", it means a positional relationship in which the semiconductor device and the pixel electrode overlap when viewed from above. It should be noted that viewing from above refers to viewing from a direction perpendicular to the surface of the substrate.

[0061] In this specification, etc., unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C. In addition, the above expressions do not exclude the case where α includes other constituent elements.

[0062] In this specification, "semiconductor device" refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are included in one embodiment of a semiconductor device. The semiconductor device of the embodiment shown below may also be a transistor used in an integrated circuit (IC) such as a display device, a microprocessor (MPU), or a memory circuit.

[0063] In this specification, etc., "display device" refers to a structure that uses an electro-optical layer to display an image. For example, the term display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure equipped with other optical components (for example, polarization components, backlight sources, touch panels, etc.) relative to a display unit. As long as there is no technical contradiction, the "electro-optical layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer.

[0064] In this specification and the like, the term "film" and the term "layer" can be interchanged with each other as appropriate.

[0065] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0066] <First embodiment>

[0067] [1. Configuration of Display Device 1]

[0068] Reference Figure 1 and Figure 2 A display device 1 including a semiconductor device 10 according to an embodiment of the present invention will be described.

[0069] Figure 1 It is a schematic exploded perspective view showing the structure of the display device 1 . Figure 2 It is a schematic plan view showing the circuit configuration of the display device 1 .

[0070] like Figure 1 As shown, the display device 1 includes a display unit 2 and a light source unit 3. In the display device 1, the light source unit 3 emits light to the display unit 2. The light source unit 3 includes, for example, a light emitting diode (LED). The light source unit 3 may also use a plurality of LEDs. When a plurality of LEDs are used in the light source unit 3, LEDs of the same color may be used, or LEDs of different colors may be used. It should be noted that the light source unit 3 is not limited to a configuration including LEDs. The light source unit 3 only needs to include an element or device that can emit light. In addition, the light source unit 3 may also include a light guide plate or an optical sheet, etc. Figure 1 In the display device 1 shown, the light source unit 3 is arranged below the display unit 2 , but the light source unit 3 may be arranged on the side of the display unit 2 .

[0071] The display unit 2 includes a first substrate 100 and a second substrate 300. A liquid crystal layer (not shown) is sandwiched between the first substrate 100 and the second substrate 300. Figure 2As shown in FIG. 1 , a display portion DP, a scan line driving circuit GD (a scan line driving circuit is sometimes referred to as a gate driver), a signal line driving circuit SD (a signal line driving circuit is sometimes referred to as a source driver), and a terminal portion TP are provided on the first substrate 100. The display portion DP is provided in the central portion of the first substrate 100. The scan line driving circuit GD is provided outside the display portion DP along the y direction. The signal line driving circuit SD is provided outside the display portion DP along the x direction. The terminal portion TP is provided at the end of the first substrate 100.

[0072] The scanning line driving circuit GD and the signal line driving circuit SD are electrically connected to the terminal portion TP. A flexible wiring substrate FPC is connected to the terminal portion TP, and a signal from the driving element DRV is input to the terminal portion TP (see Figure 1 ) That is, the signal from the driving element DRV is input to the scanning line driving circuit GD and the signal line driving circuit SD via the terminal portion TP.

[0073] The display unit DP includes a plurality of pixels PX, a plurality of scan lines GL (the scan lines are sometimes referred to as gate lines), and a plurality of signal lines SL (the signal lines are sometimes referred to as source lines). The plurality of pixels PX are respectively arranged in an area surrounded by the scan lines GL and the signal lines SL. The scan lines GL are electrically connected to the scan line drive circuit GD and extend along the x direction. A first signal generated by the scan line drive circuit GD is input to the scan lines GL. The signal lines SL are electrically connected to the signal line drive circuit SD and extend along the y direction. A second signal generated by the signal line drive circuit SD is input to the signal lines SL. The plurality of pixels PX are respectively controlled based on the first signal and the second signal.

[0074] Each of the pixels PX includes a semiconductor device 10 and a liquid crystal element 20 . Figure 2 The semiconductor device 10 shown is a so-called transistor, but the structure of the semiconductor device 10 is not limited to the transistor itself. The semiconductor device 10 can be any structure as long as it includes a transistor. In each of the plurality of pixels PX, the semiconductor device 10 is controlled based on the first signal and the second signal to drive the liquid crystal element 20. It should be noted that in this embodiment, the semiconductor device 10 included in the pixel PX of the display device 1 is described, but the semiconductor device 10 can also be used in the scanning line driving circuit GD and the signal line driving circuit SD. In addition, the display device 1 is a so-called liquid crystal display device, but it can also be other display devices.

[0075] [2. Configuration of Semiconductor Device 10]

[0076] Reference Figure 3 and Figure 4 A semiconductor device 10 according to an embodiment of the present invention will be described.

[0077] Figure 3 It is a schematic plan view showing the structure of a semiconductor device 10 according to an embodiment of the present invention. Figure 4 It is a schematic cross-sectional view showing the structure of a semiconductor device 10 according to an embodiment of the present invention. Figure 4 It is used Figure 3 sectional view of the semiconductor device 10 taken along line A1 - A2 in FIG.

[0078] like Figure 4 As shown, the semiconductor device 10 includes a first substrate 100, a first gate electrode 110, a scan line 120, a first insulating layer 130, an oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a connecting electrode 170, a second insulating layer 180, and a second gate electrode 190. The first gate electrode 110 and the scan line 120 are disposed on the first substrate 100. The first insulating layer 130 covers the upper surface and end surface of the first gate electrode 110 and the scan line 120, respectively, and is disposed on the first gate electrode 110 and the scan line 120. The first insulating layer 130 has a first opening OP1 for exposing a portion of the upper surface of the scan line 120. The oxide semiconductor layer 140 is disposed on the first insulating layer 130 so as to overlap with the first gate electrode 110. The source electrode 150 and the drain electrode 160 respectively cover a portion of the upper surface and a portion of the end surface of the oxide semiconductor layer 140, and are disposed on the first insulating layer 130. The connection electrode 170 is provided on the first insulating layer 130 and is connected to the scan line 120 via the first opening OP1. The second insulating layer 180 covers the upper surface of the oxide semiconductor layer 140, the upper surface and end surface of the source electrode 150, the upper surface and end surface of the drain electrode 160, and the upper surface and end surface of the connection electrode 170, and is provided on the first insulating layer 130. The second insulating layer 180 has a second opening OP2 for exposing a portion of the connection electrode 170. The second gate electrode 190 is provided on the second insulating layer 180 so as to overlap with the oxide semiconductor layer 140 and the connection electrode 170. The end of the second gate electrode 190 is connected to the connection electrode 170 via the second opening OP2.

[0079] like Figure 3 As shown in FIG. 1 , the first gate electrode 110 is provided so as to protrude from the scan line 120 extending along the x direction toward the y direction, and is formed continuously with the scan line 120. In other words, the first gate electrode is formed of the same layer as the scan line 120. In addition, the source electrode 150, the drain electrode 160, and the connection electrode 170 are provided separately from each other. In this case, the source electrode 150, the drain electrode 160, and the connection electrode 170 are formed of the same layer.

[0080] The first gate electrode 110 is formed continuously with the scanning line 120, and it can be said that the first gate electrode 110 is electrically connected to the scanning line. The second gate electrode 190 is electrically connected to the first gate electrode 110 via the connecting electrode 170. Therefore, the voltage included in the signal input to the scanning line 120 is applied to both the first gate electrode 110 and the second gate electrode 190.

[0081] The source electrode 150 is electrically connected to the signal line (the signal line here is equivalent to Figure 2 The signal line SL in Figure 3 and Figure 4 ). The drain electrode 160 is electrically connected to a pixel electrode (not shown) provided in the pixel PX. The liquid crystal layer provided between the first substrate 100 and the second substrate 300 is driven by an electric field generated between the pixel electrode provided on the first substrate 100 and the counter electrode (not shown) provided on the second substrate 300. By driving the liquid crystal layer in each of the plurality of pixels PX, the transmission of light emitted from the light source unit 3 is controlled in each of the plurality of pixels PX. In the pixel PX, a part of the components of the semiconductor device 10 blocks the light emitted from the light source unit 3. Therefore, the aperture ratio of the pixel PX is sometimes reduced due to the semiconductor device 10. In particular, if the size of the pixel PX is reduced, the proportion of the semiconductor device 10 relative to the size of the pixel PX increases, and thus the reduction in the aperture ratio of the pixel PX becomes significant.

[0082] In a plan view, the second gate electrode 190 is located between the source electrode 150 and the drain electrode 160. The second gate electrode 190 has a gap g relative to the source electrode 150. s The configuration has a gap g with respect to the drain electrode 160. d Here, the gap g s is the distance from one end surface of the second gate electrode 190 to the end surface of the source electrode 150, and the gap g d The gap g is the distance from the other end surface of the second gate electrode 190 to the end surface of the drain electrode 160. s Can be with gap g d Same as the gap g d Different. Gap g s and gap g d The gap g is 0.1 μm to 2.0 μm, preferably 0.3 μm to 1.5 μm, and more preferably 0.5 μm to 1.0 μm. s and gap g d The occurrence of an inter-electrode short circuit between the second gate electrode 190 and the source electrode 150 or the drain electrode 160 is suppressed. In the semiconductor device 10, the first gate electrode 110 and the oxide semiconductor layer 140 have a gap corresponding to the gap g.s and gap g d The region overlaps, so a channel is also formed in this region. s and gap g d If the gap g is smaller than 0.1 μm, short circuit between electrodes may easily occur between the second gate electrode 190 and the source electrode 150 or the drain electrode 160. s and gap g d If the gap g is larger than 2.0 μm, the current flowing in the channel decreases, so the field effect mobility decreases. s and gap g d The range of is preferably within the above range.

[0083] As described above, in order to suppress the occurrence of inter-electrode short circuits between the second gate electrode 190 and the source electrode 150 or the drain electrode 160, the second gate electrode 190 does not overlap with the source electrode 150 and the drain electrode 160 in a plan view. Figure 3 As shown, the second gate electrode 190 extends to surround the end of the drain electrode 160. It should be noted that the second gate electrode 190 only needs to extend to surround the end of one of the source electrode 150 and the drain electrode 160 and be electrically connected to the scan line 120.

[0084] Here, the above-mentioned components of the semiconductor device 10 will be described in more detail. It should be noted that the detailed structure of the oxide semiconductor layer 140 will be described later.

[0085] The first substrate 100 can support each layer constituting the semiconductor device 10. For example, as the first substrate 100, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. In addition, as the first substrate 100, a silicon substrate or other non-light-transmitting rigid substrate can also be used. In addition, as the first substrate 100, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate or a fluororesin substrate or other light-transmitting flexible substrate can also be used. In order to improve the heat resistance of the first substrate 100, impurities can also be introduced into the above-mentioned flexible substrate. It should be noted that the second substrate 300 can use the same substrate as the first substrate 100.

[0086] The first insulating layer 130 and the second insulating layer 180 can each function as a gate insulating layer. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ) or aluminum oxide nitride (AlO x N y) or silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum nitride (AlN x ) or aluminum nitride (AlN x O y The first insulating layer 130 and the second insulating layer 180 may each have a single layer structure or a stacked structure.

[0087] Here, silicon oxide nitride (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are oxides containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y ) and aluminum nitride (AlN x O y ) is a nitride containing oxygen at a ratio (x>y) less than nitrogen. It should be noted that for the sake of convenience, silicon oxide (SiO x ) and silicon oxide nitride (SiO x N y ) is referred to as "silicon oxide", and silicon nitride (SiN x ) and silicon oxide nitride (SiN x O y ) is referred to as "silicon nitride". Similarly, aluminum oxide (AlO x ) and aluminum oxide nitride (AlO x N y ) is referred to as "aluminum oxide", aluminum nitride (AlN x ) and aluminum nitride (AlN x O y ) is referred to as "aluminum nitride".

[0088] The oxide semiconductor layer 140 is preferably in contact with an oxide. If the oxide semiconductor layer 140 is in contact with an oxide, oxygen can be supplied from the oxide to the oxide semiconductor layer 140 by heat treatment. Therefore, in the case where the first insulating layer 130 and the second insulating layer 180 each have a single-layer structure, it is preferred that silicon oxide be used in the first insulating layer 130 and the second insulating layer 180, respectively. In addition, in the case where the first insulating layer 130 has a stacked structure, it is preferred that the first insulating layer 130 has a structure in which silicon oxide is stacked on silicon nitride in such a manner that silicon oxide is in contact with the oxide semiconductor layer 140. Similarly, in the case where the second insulating layer 180 has a stacked structure, it is preferred that the second insulating layer 180 has a structure in which silicon nitride is stacked on silicon oxide in such a manner that silicon oxide is in contact with the oxide semiconductor layer 140.

[0089] The first gate electrode 110 preferably has not only conductivity but also a function of reflecting or absorbing light emitted from the light source unit 3. That is, the first gate electrode 110 preferably has a light shielding function. In a plan view, the first gate electrode 110 overlaps the entire oxide semiconductor layer 140 (see Figure 3 ). Therefore, if the first gate electrode 110 has a light shielding function, it is possible to shield light incident on the oxide semiconductor layer 140. As described above, the first gate electrode 110 is formed of the same layer as the scan line 120. That is, the first gate electrode 110 is formed of the same material as the scan line 120. For example, as the first gate electrode 110 and the scan line 120, a metal such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy thereof, or a compound thereof, etc. can be used. The first gate electrode 110 and the scan line 120 may have a single-layer structure or a stacked structure.

[0090] The source electrode 150, the drain electrode 160, and the connecting electrode 170 are conductive. As described above, the source electrode 150, the drain electrode 160, and the connecting electrode 170 are formed of the same layer. That is, the source electrode 150, the drain electrode 160, and the connecting electrode 170 are formed of the same material. As the source electrode 150, the drain electrode 160, and the connecting electrode 170, the same material as the first gate electrode 110 and the scanning line 120 can be used.

[0091] The second gate electrode 190 is conductive. As the second gate electrode 190, the same material as the first gate electrode 110 and the scanning line 120 can be used. In addition, as the second gate electrode 190, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) can also be used. In a top view, the second gate electrode 190 does not overlap with the first gate electrode 110 and the scanning line 120, and includes a region surrounding the end of the drain electrode 160. In the case where a transparent conductive material is used as the second gate electrode 190, since the region is light-transmissive, the aperture ratio of the pixel PX can be increased.

[0092] [3. Configuration of Oxide Semiconductor Layer 140]

[0093] [3-1. Composition of Oxide Semiconductor Layer 140]

[0094] An oxide semiconductor containing two or more metal elements including indium (In) is used as the oxide semiconductor layer 140. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanoids are used.

[0095] The oxide semiconductor layer 140 is light-transmissive and has a polycrystalline structure including a plurality of crystal grains. In order to make the oxide semiconductor layer 140 have a polycrystalline structure, it is preferred to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in terms of atomic ratio. If the ratio of indium increases, the oxide semiconductor layer 140 is easily crystallized. In addition, as a metal element other than indium, gallium is preferably included. Gallium and indium also belong to the 13th group element. Therefore, there is almost no situation where the crystallinity of the oxide semiconductor layer 140 is hindered by gallium.

[0096] The oxide semiconductor layer 140 has properties different from those of an existing oxide semiconductor having a polycrystalline structure, and the details will be described later. Therefore, in order to distinguish the oxide semiconductor included in the oxide semiconductor layer 140 from the existing oxide semiconductor having a polycrystalline structure, the oxide semiconductor included in the oxide semiconductor layer 140 is referred to as Poly-OS (Poly-crystalline Oxide Semiconductor) for description below.

[0097] The Poly-OS included in the oxide semiconductor layer 140 can be formed by using a sputtering method and a heat treatment. Here, a method of forming the oxide semiconductor layer 140 is described.

[0098] First, a sputtering method is used to form an oxide semiconductor film. The oxide semiconductor film after film formation has an amorphous structure. Here, an amorphous structure refers to a structure in which there is no long-range ordered structure and no periodic lattice arrangement is observed. For example, when an X-ray diffraction (X-ray Diffraction: XRD) method is used to observe an oxide semiconductor film having an amorphous structure, a specific peak based on a crystal structure cannot be obtained in the diffraction pattern. It should be noted that an oxide semiconductor film having an amorphous structure sometimes has a short-range ordered structure in a tiny area. However, such an oxide semiconductor film does not exhibit the characteristics of Poly-OS and can therefore be classified as an oxide semiconductor film having an amorphous structure.

[0099] The oxide semiconductor film having an amorphous structure is formed at a low temperature. For example, the temperature of the substrate for forming the oxide semiconductor film is below 150°C, preferably below 100°C, and more preferably below 50°C. If the temperature of the substrate is high, microcrystals are easily generated in the oxide semiconductor being formed. In addition, the oxygen partial pressure in the chamber during film formation is above 1% and below 10%, preferably above 1% and below 5%, and more preferably above 2% and below 4%. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor film due to the excess oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor film becomes uneven, and an oxide semiconductor film containing a large number of microcrystals or an oxide semiconductor film that does not crystallize even after heat treatment is formed will be formed.

[0100] Next, the oxide semiconductor film formed by sputtering is subjected to heat treatment. The heat treatment is performed in the air, but the atmosphere for the heat treatment is not limited thereto. The temperature for the heat treatment is between 300°C and 500°C, preferably between 350°C and 450°C. In addition, the heat treatment time is between 15 minutes and 120 minutes, preferably between 30 minutes and 60 minutes. By performing the heat treatment, the oxide semiconductor film having an amorphous structure is crystallized to form an oxide semiconductor layer 140 containing Poly-OS.

[0101] The composition of the oxide semiconductor layer 140 is roughly consistent with the composition of the sputtering target. Therefore, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the composition of the metal elements of the sputtering target. In addition, the composition of the oxide semiconductor layer 140 can also be determined using the XRD method. Specifically, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer 140 obtained according to the XRD method. In addition, the composition of the metal elements of the oxide semiconductor layer 140 can also be determined using fluorescent X-ray analysis or electron probe microanalyzer (Electron Probe Micro Analyzer: EPMA) analysis, etc. It should be noted that the oxygen contained in the oxide semiconductor layer 140 will change according to the process conditions of the sputtering method, etc., and is therefore not limited to this.

[0102] [3-2. Characteristics of Oxide Semiconductor Layer 140]

[0103] Next, the characteristics of the oxide semiconductor layer 140 including Poly-OS are described.

[0104] The oxide semiconductor layer 140 has excellent etching resistance. Specifically, with respect to the oxide semiconductor layer 140, the etching rate when etching is performed using an etching solution for wet etching is very small. This means that the oxide semiconductor layer 140 is hardly etched by the etching solution. When the oxide semiconductor layer 140 is etched using an etching solution containing phosphoric acid as a main component (hereinafter referred to as a "mixed acid etching solution") at 40°C, the etching rate is less than 3nm / min, less than 2nm / min, or less than 1nm / min. The proportion of phosphoric acid in the mixed acid etching solution is greater than 50%, greater than 60%, or greater than 70%. Acetic acid and nitric acid may also be contained in the mixed acid etching solution in addition to phosphoric acid. In an oxide semiconductor film that does not contain Poly-OS, such as an oxide semiconductor film having an amorphous structure before heat treatment, the etching rate when the oxide semiconductor film is etched using a mixed acid etching solution at 40°C is greater than 100nm / min. In addition, the etching rate when the oxide semiconductor layer 140 is etched using a 0.5% hydrofluoric acid solution at room temperature is less than 5nm / min, less than 4nm / min, or less than 3nm / min. It should be noted that in an oxide semiconductor film that does not contain Poly-OS, the etching rate when etching the oxide semiconductor film using a 0.5% hydrofluoric acid solution at room temperature is 15 nm / min or more. Here, "40°C" refers to 40±5°C, which can be the temperature of the etching solution or the set temperature of the etching solution. In addition, "room temperature" refers to 25±5°C.

[0105] An embodiment of the oxide semiconductor layer 140 is shown in Table 1. Table 1 shows the etching rates of each sample produced in a mixed acid etching solution ("Mixed Acid AT-2F" manufactured by RASA Industries, Ltd., in which the ratio of phosphoric acid in the mixed acid etching solution is 65%) and a 0.5% hydrofluoric acid solution. In addition, when etching each sample, the temperature of the mixed acid etching solution is 40°C, and the temperature of the 0.5% hydrofluoric acid solution is room temperature. In Table 1, sample 1 is an oxide semiconductor layer 140 including Poly-OS, sample 2 is an oxide semiconductor film having an amorphous structure before heat treatment, and sample 3 is an oxide semiconductor film of indium gallium zinc oxide (IGZO) including an indium ratio of less than 50%.

[0106] [Table 1]

[0107] Mixed acid etching solution 0.5% hydrofluoric acid solution Sample 1 <0.1nm / min <2nm / min Sample 2 111nm / min >18nm / min Sample 3 162nm / min -

[0108] As shown in Table 1, for sample 1 (oxide semiconductor layer 140 containing Poly-OS), etching was almost impossible using a mixed acid etching solution, and etching was performed at a maximum of 2 nm / min using a 0.5% hydrofluoric acid solution. In the etching using a mixed acid etching solution, the etching rate of sample 1 was less than 1 / 100 of the etching rate of sample 2 (oxide semiconductor film having an amorphous structure before heat treatment). In the etching using a 0.5% hydrofluoric acid solution, the etching rate of sample 1 was less than about 1 / 10 of the etching rate of sample 2. In addition, in the etching using a mixed acid etching solution, the etching rate of sample 1 was less than 1 / 100 of the etching rate of sample 3 (oxide semiconductor film containing IGZO with an indium ratio of less than 50%). That is, sample 1 is significantly superior in etching resistance compared to samples 2 and 3.

[0109] Such excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS is a property that cannot be obtained in the conventional oxide semiconductor having a polycrystalline structure produced by a process below 500° C. Although the detailed mechanism of the excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS is unknown, it is believed that it is because Poly-OS has a polycrystalline structure different from the conventional one.

[0110] As described above, the etching rate of the oxide semiconductor layer 140 including Poly-OS in the etching solution is very low. Therefore, it is very difficult to pattern the oxide semiconductor layer 140. Therefore, in the case of forming an island-shaped oxide semiconductor layer 140, the oxide semiconductor film having an amorphous structure before heat treatment is patterned into an island shape, and then heat treatment is performed to crystallize it. In this way, an island-shaped oxide semiconductor layer 140 including Poly-OS can be formed.

[0111] [4. Method for Manufacturing Semiconductor Device 10]

[0112] Reference Figure 5 to Figure 17 A method for manufacturing the semiconductor device 10 will be described.

[0113] Figure 5 1 is a flowchart illustrating a method for manufacturing the semiconductor device 10 according to an embodiment of the present invention. Figure 6 to Figure 17 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Figure 5 The steps of the flowchart shown.

[0114] In step S100, a first conductive film CF1 is formed on the first substrate 100 by sputtering (see Figure 6 ).

[0115] In step S110, the first conductive film CF1 is patterned by photolithography to form the first gate electrode 110 and the scanning line 120 (see FIG. Figure 7 ).

[0116] In step S120, a first insulating layer 130 (see FIG. 1 ) is formed by using a CVD method to cover the first gate electrode 110 and the scanning line 120. Figure 8 ).

[0117] In step S130, the oxide semiconductor film OS is formed on the first insulating layer 130 by sputtering. The film forming conditions of the oxide semiconductor film OS are as described above. Since the oxide semiconductor film OS has an amorphous structure, it is easy to etch the oxide semiconductor film OS. Therefore, the oxide semiconductor film OS is patterned by photolithography (see FIG. 1 ). Fig. 9 ).

[0118] In step S140, the oxide semiconductor film OS is subjected to a first heat treatment. The conditions of the first heat treatment are as described above. The oxide semiconductor film OS is crystallized by the first heat treatment to form an oxide semiconductor layer 140 including Poly-OS (see Fig.10 ).

[0119] In step S150, a first opening OP1 is formed in the first insulating layer 130 by using a photolithography method (see Fig.11 ) In the first opening OP1, a portion of the scanning line 120 is exposed.

[0120] In step S160, a second conductive film CF2 (see FIG. 1 ) is formed by sputtering to cover the oxide semiconductor layer 140 and the first opening OP1. Fig.12 ). For example, the second conductive film CF2 is a stacked film (Ti / Al / Ti film) including titanium and aluminum.

[0121] In step S170, the second conductive film CF2 is patterned by photolithography to form the source electrode 150, the drain electrode 160, and the connection electrode 170 (see Fig.13). The source electrode 150 and the drain electrode 160 are connected to the oxide semiconductor layer 140, and the connecting electrode 170 is connected to the scanning line 120 via the first opening OP1. The etching of the second conductive film CF2 is preferably wet etching using an etching solution. As described above, the oxide semiconductor layer 140 including Poly-OS has excellent etching resistance. Therefore, when the second conductive film CF2 is etched using an etching solution, the oxide semiconductor layer 140 is hardly etched. Therefore, in the oxide semiconductor layer 140, the difference between the film thickness of the first region connected to one of the source electrode 150 and the drain electrode and the film thickness of the second region not connected to the source electrode 150 and the drain electrode is 3 nm or less. It should be noted that the difference between the film thickness of the first region and the film thickness of the second region can also be set to less than 2 nm by adjusting the etching conditions, preferably less than 1 nm, and more preferably less than 0.5 nm.

[0122] In step S180, a second insulating layer 180 and a metal oxide film MO are sequentially formed (see Fig.14 ). The second insulating layer 180 is formed by a CVD method. The metal oxide film MO is formed by a sputtering method or an atomic layer deposition method (ALD method). For example, the second insulating layer 180 includes silicon oxide in contact with the oxide semiconductor layer 140. In addition, for example, as the metal oxide film MO, a metal oxide containing aluminum as a main component can be used. The ratio of aluminum contained in the metal oxide film MO can also be 5% to 70%, 10% to 60% or 30% to 50% of the entire metal oxide film MO. The above ratios can be mass ratios or weight ratios.

[0123] The thickness of the metal oxide film MO is 1 nm to 50 nm, preferably 1 nm to 30 nm. As the metal oxide film MO, aluminum oxide is preferably used. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. Here, barrier properties refer to the function of inhibiting the permeation of gases such as oxygen and hydrogen.

[0124] It should be noted that a metal oxide containing a metal other than aluminum as a main component may be used as the metal oxide film MO. For example, indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO) may be used as the metal oxide film MO.

[0125] In step S190, the oxide semiconductor layer 140 is subjected to a second heat treatment (see Fig.15). Oxygen defects may be generated in the oxide semiconductor layer 140 due to a process after the formation of the oxide semiconductor layer 140. By performing the second heat treatment, oxygen is supplied from the first insulating layer 130 and the second insulating layer 180 to the oxide semiconductor layer 140, and the oxygen defects are repaired. In particular, in the second heat treatment, since the second insulating layer 180 is covered with the metal oxide film MO, the metal oxide film MO suppresses the release of oxygen in the second insulating layer 180 to the outside, thereby enabling efficient supply of oxygen to the oxide semiconductor layer 140.

[0126] It should be noted that the metal oxide film MO is removed after the second heat treatment. When aluminum oxide is used as the metal oxide film MO, the metal oxide film MO can be removed using diluted hydrofluoric acid (DHF).

[0127] In step S200, a second opening OP2 is formed in the second insulating layer 180 by using a photolithography method (see Fig.16 ) In the second opening OP2, a portion of the connection electrode 170 is exposed.

[0128] In step S210, a third conductive film CF3 is formed on the second insulating layer 180 by sputtering (see Fig.17 ).

[0129] In step S220, the third conductive film CF3 is patterned using a photolithography method to form the second gate electrode 190. The second gate electrode 190 is in contact with the connection electrode 170 via the second opening OP2.

[0130] Through the above steps, we can produce Figure 3 and Figure 4 The semiconductor device 10 manufactured in this way has a 30 cm 2 / Vs or higher field effect mobility.

[0131] According to the semiconductor device 10, the second gate electrode 190 does not overlap with the source electrode 150 and the drain electrode 160 in a plan view, but is arranged with a gap between the source electrode 150 and the drain electrode 160, thereby suppressing the occurrence of short circuit between electrodes. In addition, since the oxide semiconductor layer 140 includes Poly-OS, it has excellent etching resistance, and thus has stable properties not only during the manufacture of the semiconductor device 10 but also after the manufacture. Therefore, the semiconductor device 10 has high reliability.

[0132] <Modification 1 of the first embodiment>

[0133] Reference Fig.18A semiconductor device 10A will be described as a modified example of the semiconductor device 10. In the following, description of the same configuration as that of the semiconductor device 10 may be omitted.

[0134] Fig.18 It is a schematic plan view showing the structure of a semiconductor device 10A according to one embodiment of the present invention.

[0135] The semiconductor device 10A includes a plurality of oxide semiconductor layers 140 (a first oxide semiconductor layer 140-1, a second oxide semiconductor layer 140-2, and a third oxide semiconductor layer 140-3). The first oxide semiconductor layer 140-1 to the third oxide semiconductor layer 140-3 are respectively formed in an island shape. That is, the first oxide semiconductor layer 140-1 to the third oxide semiconductor layer 140-3 are arranged separately from each other. In the semiconductor device 10A having a high field effect mobility, since a large current flows through a channel formed in the oxide semiconductor layer 140, the oxide semiconductor layer 140 sometimes generates heat. In particular, the larger the area of ​​the oxide semiconductor layer 140, the more significantly the heat generated by the oxide semiconductor layer 140 is manifested. Therefore, in the semiconductor device 10A, the area of ​​one oxide semiconductor layer 140 is reduced, and a plurality of oxide semiconductor layers 140 are arranged. As a result, the amount of current flowing in the channel can be maintained while suppressing the heat generated by the oxide semiconductor layer 140.

[0136] According to the semiconductor device 10A, the second gate electrode 190 does not overlap with the source electrode 150 and the drain electrode 160 in a plan view, but is arranged with a gap relative to the source electrode 150 and the drain electrode 160, thereby suppressing the occurrence of short circuit between electrodes. In addition, the oxide semiconductor layer 140 includes Poly-OS, which has stable properties not only during the manufacture of the semiconductor device 10A but also after the manufacture. In addition, in the semiconductor device 10A, the heat generation of the oxide semiconductor layer 140 can be suppressed. Therefore, the semiconductor device 10A has high reliability.

[0137] <Modification 2 of the first embodiment>

[0138] Reference Fig.19 A semiconductor device 10B will be described as another modified example of the semiconductor device 10. In the following, description of the same configuration as that of the semiconductor device 10 may be omitted.

[0139] Fig.19 It is a schematic cross-sectional view showing the structure of a semiconductor device 10B according to an embodiment of the present invention.

[0140] In the semiconductor device 10B, the connection electrode 170 is not formed, but a first opening OP1 is formed to penetrate the first insulating layer 130 and the second insulating layer 180. A portion of the scanning line 120 is exposed in the first opening OP1. The end of the second gate electrode 190B is directly connected to the scanning line 120 through the first opening OP1.

[0141] By not implementing Figure 5 In step S150 and in step S200 , a first opening OP1 penetrating the first insulating layer 130 and the second insulating layer 180 is formed, thereby manufacturing the semiconductor device 10B, and a detailed description of the method for manufacturing the semiconductor device 10B is omitted.

[0142] According to the semiconductor device 10B, the second gate electrode 190B does not overlap with the source electrode 150 and the drain electrode 160 in a plan view, but is configured with a gap between the source electrode 150 and the drain electrode 160, thereby suppressing the occurrence of short circuit between electrodes. In addition, the oxide semiconductor layer 140 includes Poly-OS, which has a stable property not only during the manufacture of the semiconductor device 10B but also after the manufacture. Therefore, the semiconductor device 10B has high reliability. In addition, since the number of steps in the manufacture of the semiconductor device 10B is reduced, the manufacturing tact of the semiconductor device 10B can be shortened and the manufacturing cost of the semiconductor device 10B can be reduced.

[0143] <Modification 3 of the first embodiment>

[0144] Reference Fig. 20 A semiconductor device 10C will be described as another modified example of the semiconductor device 10. In the following, description of the same configuration as that of the semiconductor device 10 may be omitted.

[0145] Fig. 20 It is a schematic cross-sectional view showing the structure of a semiconductor device 10C according to an embodiment of the present invention.

[0146] In the semiconductor device 10C, a metal oxide layer 200 is provided below the oxide semiconductor layer 140 and in contact with the oxide semiconductor layer 140. The metal oxide layer 200 has substantially the same planar shape as the oxide semiconductor layer 140. That is, the end surface of the metal oxide layer 200 substantially coincides with the end surface of the oxide semiconductor layer 140. The source electrode 150 and the drain electrode 160 respectively cover a portion of the end surface of the metal oxide layer 200.

[0147] The metal oxide layer 200 can function as a buffer layer that improves the crystallinity of the oxide semiconductor layer 140. In the semiconductor device 10C including the oxide semiconductor layer 140 having improved crystallinity, field effect mobility is further improved.

[0148] A metal oxide having aluminum as a main component is used as the metal oxide layer 200. That is, the same metal oxide as the metal oxide film MO formed in the above-mentioned step S180 can be used as the metal oxide layer 200. The film thickness of the metal oxide layer 200 is 1 nm to 10 nm, preferably 1 nm to 5 nm. As the metal oxide layer 200, aluminum oxide is preferably used.

[0149] Figure 21 to Figure 23 It is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 10C according to an embodiment of the present invention.

[0150] In the manufacture of the semiconductor device 10C, Figure 5 In step S130, not only the oxide semiconductor film OS is formed, but also the metal oxide film MO is formed. That is, the metal oxide film MO and the oxide semiconductor film OS are sequentially formed on the first insulating layer 130. Thereafter, the oxide semiconductor film OS is patterned using photolithography (see Fig.21 ). At this time, patterning of the metal oxide film MO is not performed.

[0151] Next, implement Figure 5 That is, the oxide semiconductor film OS is subjected to a first heat treatment to form an oxide semiconductor layer 140 including Poly-OS (see Fig. 22 ). During the crystallization of the oxide semiconductor film OS, the metal oxide layer 200 functions as a buffer layer, and the crystallinity of the oxide semiconductor layer 140 is controlled. Specifically, the size of the crystal grains included in the oxide semiconductor layer 140 is increased to increase the crystallinity of the oxide semiconductor layer 140. Thereafter, the metal oxide film MO is patterned using the oxide semiconductor layer 140 as a mask to form the metal oxide layer 200 (see Fig.23 ). As described above, the oxide semiconductor layer 140 including Poly-OS has excellent etching resistance. Therefore, even when the metal oxide film MO is etched during patterning of the metal oxide film MO, the oxide semiconductor layer 140 used as a mask will not be etched. In the semiconductor device 10C, the oxide semiconductor layer 140 can be used as a mask in the formation of the metal oxide layer 200, so that the photolithography process can be omitted.

[0152] According to the semiconductor device 10C, the second gate electrode 190 does not overlap with the source electrode 150 and the drain electrode 160 in a plan view, but is configured with a gap between the source electrode 150 and the drain electrode 160, thereby suppressing the occurrence of short circuits between electrodes. In addition, the oxide semiconductor layer 140 includes Poly-OS, which has stable properties not only during the manufacture of the semiconductor device 10C but also after the manufacture. Therefore, the semiconductor device 10C has high reliability. In addition, in the semiconductor device 10C, since the oxide semiconductor layer 140 is formed in contact with the metal oxide layer 200, the crystallinity of the oxide semiconductor layer 140 is improved, and the semiconductor device 10C has a higher field effect mobility.

[0153] <Second embodiment>

[0154] As described in the first embodiment, in the semiconductor device 10, when the aperture ratio of the pixel PX is to be increased, it is preferable to use a transparent conductive material as the second gate electrode 190. Poly-OS can be used as a semiconductor material, and Poly-OS containing impurity elements has a low resistance and can be used as a transparent conductive material. Therefore, in this embodiment, a semiconductor device 11 using the low-resistance Poly-OS as the second gate electrode is described. It should be noted that the following description of the same structure as the semiconductor device 10 is sometimes omitted.

[0155] [1. Configuration of Semiconductor Device 11]

[0156] Reference Fig.24 A semiconductor device 11 according to an embodiment of the present invention will be described.

[0157] Fig.24 It is a schematic cross-sectional view showing the structure of a semiconductor device 11 according to an embodiment of the present invention.

[0158] like Fig.24 As shown, the semiconductor device 11 includes a first substrate 100, a first gate electrode 110, a scan line 120, a first insulating layer 130, an oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a connecting electrode 170, a second insulating layer 180, and a second gate electrode 210. The second gate electrode 210 of the semiconductor device 11 corresponds to the second gate electrode 190 of the semiconductor device 10. Therefore, the second gate electrode 210 is provided on the second insulating layer 180 in a manner overlapping with the oxide semiconductor layer 140 and the connecting electrode 170. In addition, the second gate electrode 210 is electrically connected to the first gate electrode 110 via the connecting electrode 170. In addition, the second gate electrode 210 has a gap g with respect to the source electrode 150. s The configuration has a gap g with respect to the drain electrode 160. dTherefore, even if a voltage is applied to the second gate electrode 210 , it is possible to suppress the occurrence of an inter-electrode short circuit between the second gate electrode 210 and the source electrode 150 or the drain electrode 160 .

[0159] [2. Characteristics of the Second Gate Electrode 210]

[0160] The second gate electrode 210 includes conductive Poly-OS. As the second gate electrode 210, the same material as the oxide semiconductor layer 140 can be used. That is, as the second gate electrode 210, an oxide semiconductor including two or more metal elements including indium (In) is used. In addition, the second gate electrode 210 has a polycrystalline structure. Among them, the second gate electrode 210 further includes an impurity element. For example, the impurity element is boron (B) or phosphorus (P), but is not limited thereto.

[0161] The Poly-OS included in the second gate electrode 210 includes a large number of oxygen defects. In the Poly-OS including a large number of oxygen defects, carriers are generated. In addition, even if hydrogen is captured in the oxygen defects, carriers are generated. Therefore, the second gate electrode 210 has a greater carrier concentration than the oxide semiconductor layer 140 and has conductivity. In other words, a large number of oxygen defects are generated in the conductive Poly-OS.

[0162] The conductive Poly-OS can be formed by adding impurity elements to the Poly-OS. For example, an impurity element is added to an oxide semiconductor film including the Poly-OS using an ion implantation method. As a result, oxygen defects are generated in the Poly-OS, and the second gate electrode 210 including the conductive Poly-OS is formed. Alternatively, the second gate electrode 210 including the conductive Poly-OS is formed by adding impurity elements to an oxide semiconductor film having an amorphous structure using an ion implantation method and then performing a heat treatment.

[0163] In the Poly-OS in which oxygen defects are generated by adding impurity elements, it is difficult to repair the oxygen defects by the impurity elements. In addition, since hydrogen is captured in the oxygen defects, the oxygen defects in the Poly-OS are stabilized. Therefore, the conductivity of the second gate electrode 210 including the conductive Poly-OS is stable. For example, the sheet resistance of the second gate electrode 210 is 1000Ω / sq. or less, preferably 500Ω / sq. or less, and more preferably 250Ω / sq. or less.

[0164] The film thickness of the second gate electrode 210 is, for example, 30 nm to 200 nm, preferably 50 nm to 180 nm, and more preferably 100 nm to 150 nm. If the film thickness of the second gate electrode 210 is less than 30 nm, there is a case where the impurity element is added to the second insulating layer 180 through the second gate electrode 210, resulting in a decrease in the insulation of the second insulating layer 180. In addition, if the film thickness of the second gate electrode 210 is greater than 200 nm, there is a case where the second gate electrode 210 includes a region where no oxygen vacancies are generated, resulting in the second gate electrode 210 not being sufficiently low in resistance. Therefore, the film thickness of the second gate electrode 210 is preferably within the above range.

[0165] [3. Method for Manufacturing Semiconductor Device 11]

[0166] Reference Figure 25 to Figure 28 A method for manufacturing the semiconductor device 11 will be described.

[0167] Fig.25 1 is a flowchart illustrating a method for manufacturing the semiconductor device 11 according to an embodiment of the present invention. Figure 26 to Figure 28 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 11 according to an embodiment of the present invention. Fig.25 The steps of the flowchart shown.

[0168] Steps S100 to S200 are similar to those in the first embodiment. Figure 5 The steps described above are the same, and thus description thereof is omitted here. In the manufacturing of the semiconductor device 11 , step S230 is performed after step S200 .

[0169] In step S230, the oxide semiconductor film OS1 is formed on the second insulating layer 180 by sputtering. The film forming conditions of the oxide semiconductor film OS1 are described in the first embodiment, so the description is omitted here. Since the oxide semiconductor film OS1 has an amorphous structure, it is easy to etch the oxide semiconductor film OS1. Therefore, the oxide semiconductor film OS1 is patterned by photolithography (see Fig.26 ).

[0170] In step S240, the oxide semiconductor film OS1 is subjected to a third heat treatment. The conditions of the third heat treatment are the same as those of the first heat treatment. The oxide semiconductor film OS1 is crystallized by the third heat treatment to form an oxide semiconductor film OS2 including Poly-OS (see Fig. 27 ).

[0171] In step S250, an impurity element (for example, boron) is added to the oxide semiconductor film OS2 by an ion implantation method, thereby generating oxygen vacancies in the Poly-OS in the oxide semiconductor film OS2, and forming the second gate electrode 210 including the conductive Poly-OS.

[0172] Through the above steps, we can produce Fig.24 The semiconductor device 11 manufactured in this way has a 30 cm 2 It should be noted that since hydrogen diffused into the second gate electrode 210 is captured by oxygen defects in the process after step S250 (for example, the process of forming a planarization layer or a pixel electrode), the conductivity of the second gate electrode 210 is stable.

[0173] According to the semiconductor device 11, the second gate electrode 210 is configured with a gap between the source electrode 150 and the drain electrode 160, rather than overlapping with the source electrode 150 and the drain electrode 160 in a plan view, thereby suppressing the occurrence of short circuits between electrodes. In addition, since the second gate electrode 210 has light transmittance, the aperture ratio of the pixel PX can be increased. In addition, since the oxide semiconductor layer 140 includes Poly-OS, it has excellent etching resistance, and therefore has a stable property not only during the manufacture of the semiconductor device 11 but also after the manufacture. Therefore, the semiconductor device 11 has high reliability.

[0174] <Modification 1 of the Second Embodiment>

[0175] Reference Figure 29 to Figure 33 A modified example of the method for manufacturing the semiconductor device 11 will be described. Note that, in the following, descriptions of the same configurations as those of the semiconductor device 11 may be omitted.

[0176] Fig.29 1 is a flowchart illustrating a method for manufacturing the semiconductor device 11 according to an embodiment of the present invention. Figure 30 to Figure 33 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 11 according to an embodiment of the present invention. Fig.29 The steps of the flowchart shown.

[0177] Steps S100 to S200 are similar to those in the first embodiment. Figure 5 The steps described above are the same, so the description is omitted here. In this variation, step S231 is performed after step S200.

[0178] In step S231, an oxide semiconductor film OS1 is formed on the second insulating layer 180 by sputtering (see Fig.30). The oxide semiconductor film OS1 has an amorphous structure. In step S231, patterning of the oxide semiconductor film OS1 is not performed. Step S251 is performed after step S231.

[0179] In step S251, an impurity element (for example, boron) is added to the oxide semiconductor film OS1 by an ion implantation method, thereby forming an oxide semiconductor film OS2 containing the impurity element and having an amorphous structure. Step S232 is performed after step S251.

[0180] In step S232, the oxide semiconductor film OS2 is patterned using photolithography (see Fig.32 Since the oxide semiconductor film OS2 has an amorphous structure, it is easy to etch the oxide semiconductor film OS2. Step S240 is performed after step S232.

[0181] In step S240, the oxide semiconductor film OS2 is subjected to a third heat treatment. The third heat treatment conditions are the same as those of the first heat treatment in step S120. Although the oxide semiconductor film OS2 contains impurity elements, the amount thereof is much less than that of indium. Therefore, the impurity elements do not hinder the crystallization of the oxide semiconductor film OS2. However, oxygen defects are generated in the oxide semiconductor film OS2 by the impurity elements. Therefore, although the oxide semiconductor film OS2 is crystallized, a second gate electrode 210 (see FIG. 2 ) containing conductive Poly-OS is formed. Fig.33 ).

[0182] Through the above steps, we can produce Fig.24 The semiconductor device 11 shown in the figure. The semiconductor device 11 manufactured in this way also has a 30cm 2 / Vs or higher field effect mobility.

[0183] In the semiconductor device 11 manufactured in this modification, the second gate electrode 210 does not overlap with the source electrode 150 and the drain electrode 160 in a plan view, but is arranged with a gap relative to the source electrode 150 and the drain electrode 160, thereby suppressing the occurrence of short circuit between electrodes. In addition, since the second gate electrode 210 has light transmittance, the aperture ratio of the pixel PX can be increased. In addition, since the oxide semiconductor layer 140 contains Poly-OS and has excellent etching resistance, it has a stable property not only during the manufacture of the semiconductor device 11 but also after the manufacture. Therefore, the semiconductor device 11 has high reliability.

[0184] <Modification 2 of the Second Embodiment>

[0185] Reference Fig.34 and Fig.35Hereinafter, a further modification of the method for manufacturing the semiconductor device 11 will be described. It should be noted that, below, description of the same configuration as that of the semiconductor device 11 may be omitted.

[0186] Fig.34 1 is a flowchart illustrating a method for manufacturing the semiconductor device 11 according to an embodiment of the present invention. Fig.35 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 11 according to an embodiment of the present invention. Fig.34 The steps of the flowchart shown.

[0187] Steps S100 to S240 are similar to those in the first embodiment. Figure 5 The steps described above are the same, so the description is omitted here. In this variation, step S270 is performed after step S240.

[0188] In step S270, the nitride layer 220 is formed by using a CVD method, a sputtering method, or an ALD method. For example, silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum nitride (AlN x ) or aluminum nitride (AlN x O y ) and other nitrides. In particular, silicon nitride is preferably used as the nitride layer 220. Silicon nitride is formed into a film using the CVD method, but due to the reactive gas present in the chamber, oxygen defects are generated in the oxide semiconductor film OS2. In addition, the gases used in the CVD method mostly contain hydrogen, and a large amount of hydrogen exists in the chamber during film formation. In addition, the first substrate 100 is heated in the CVD method. Therefore, when silicon nitride is formed on the oxide semiconductor film OS2 in step S270, oxygen defects are generated in the oxide semiconductor film OS2, and hydrogen diffuses into the oxide semiconductor film OS2 and is captured by the oxygen defects. As a result, the oxide semiconductor film OS2 has a low resistance, forming a second gate electrode 210 (see Fig.35 ). It should be noted that, when the second gate electrode 210 is not sufficiently reduced in resistance only by forming the nitride layer 220, heat treatment may be performed after step S270. Since the second gate electrode 210 is in contact with the nitride layer 220, oxygen in the second gate electrode 210 is extracted to the nitride layer 220 by heat treatment, and oxygen defects are generated in the second gate electrode 210. In addition, hydrogen contained in the nitride layer 220 is diffused to the second gate electrode 210 by heat treatment. As a result, the second gate electrode 210 is further reduced in resistance.

[0189] Through the above steps, we can produce Fig.24The semiconductor device 11 shown. It should be noted that in the semiconductor device 11 involved in this modification, a nitride layer 220 is formed on the second gate electrode 210, but the nitride layer 220 can function as an interlayer insulating layer when forming a pixel electrode electrically connected to the drain electrode 160 of the semiconductor device 11. The semiconductor device 11 manufactured in this way also has a 30cm 2 / Vs or higher field effect mobility.

[0190] In the semiconductor device 11 manufactured in this modification, the second gate electrode 210 is configured with a gap between the source electrode 150 and the drain electrode 160, rather than overlapping with the source electrode 150 and the drain electrode 160 in a plan view, thereby suppressing the occurrence of short circuits between electrodes. In addition, since the second gate electrode 210 is light-transmissive, the aperture ratio of the pixel PX can be increased. In addition, since the oxide semiconductor layer 140 includes Poly-OS and has excellent etching resistance, it has a stable property not only during the manufacture of the semiconductor device 11 but also after the manufacture. Therefore, the semiconductor device 11 has high reliability.

[0191] <Third Embodiment>

[0192] In the semiconductor device 10 involved in the first embodiment, the second gate electrode 190 is directly connected to the connection electrode 170. That is, the second gate electrode 190 is directly electrically connected to the connection electrode 170. However, the second gate electrode can also be electrically connected to the connection electrode 170 via a connection electrode provided on the second gate electrode. Therefore, in this embodiment, a semiconductor device 12 including a connection electrode different from the connection electrode 170 is described. It should be noted that the description of the same structure as the semiconductor device 10 is sometimes omitted below. In addition, for the sake of convenience of description, the connection electrode 170 described in the first embodiment is described as the first connection electrode 170.

[0193] [1. Configuration of Semiconductor Device 12]

[0194] Reference Fig.36 and Fig.37 A semiconductor device 12 according to an embodiment of the present invention will be described.

[0195] Fig.36 It is a schematic plan view showing the structure of a semiconductor device 12 according to an embodiment of the present invention. Fig.37 It is a schematic cross-sectional view showing the structure of a semiconductor device 12 according to an embodiment of the present invention. Fig.37 It is used Fig.36 A cross-sectional view of the semiconductor device 12 taken along line B1 - B2 in FIG.

[0196] like Fig.37 As shown, the semiconductor device 12 includes a first substrate 100, a first gate electrode 110, a scan line 120, a first insulating layer 130, an oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a first connection electrode 170, a second insulating layer 180, a second gate electrode 230, a second connection electrode 240, a third insulating layer 250 and a third connection electrode 260. The second gate electrode 230 is disposed on the second insulating layer 180 in a manner overlapping with the oxide semiconductor layer 140. The second connection electrode 240 is disposed on the second insulating layer 180 and is in contact with the first connection electrode 170 via the second opening OP2. The third insulating layer 250 covers the upper surface and end surface of the second gate electrode 230 and the upper surface and end surface of the second connection electrode 240, and is disposed on the second insulating layer 180. The third insulating layer 250 has a third opening OP3 for exposing a portion of the upper surface of the second gate electrode 230 and a fourth opening OP4 for exposing a portion of the upper surface of the second connection electrode 240. The third connection electrode 260 is disposed on the third insulating layer 250. The third connection electrode 260 is in contact with the second gate electrode 230 via the third opening OP3, and is in contact with the second connection electrode 240 via the fourth opening OP4.

[0197] like Fig.36 As shown in FIG. 1 , the second gate electrode 230 and the second connection electrode 240 are provided separately from each other, but the second gate electrode 230 and the second connection electrode 240 are formed of the same layer. As described above, the third connection electrode 260 is in contact with the second gate electrode 230 and the second connection electrode 240. Therefore, the second gate electrode 230 is electrically connected to the first gate electrode 110 via the first connection electrode 170, the second connection electrode 240, and the third connection electrode 260. Therefore, the voltage included in the signal input to the scan line 120 is applied to both the first gate electrode 110 and the second gate electrode 230.

[0198] In a plan view, the second gate electrode 230 has a gap g with respect to the source electrode 150. s The configuration has a gap g with respect to the drain electrode 160. d Therefore, even if a voltage is applied to the second gate electrode 230, the occurrence of an inter-electrode short circuit between the second gate electrode 230 and the source electrode 150 or the drain electrode 160 can be suppressed. It should be noted that, in a top view, the third connecting electrode 260 overlaps with the drain electrode 160. However, since not only the second insulating layer 180 but also the third insulating layer 250 is provided between the third connecting electrode 260 and the drain electrode 160, an inter-electrode short circuit hardly occurs between the third connecting electrode 260 and the drain electrode 160.

[0199] The second gate electrode 230 and the second connection electrode 240 are conductive. As described above, the second gate electrode 230 and the second connection electrode 240 are formed of the same layer. That is, the second gate electrode 230 and the second connection electrode 240 are formed of the same material. The second gate electrode 230 and the second connection electrode 240 can use the same material as the first gate electrode 110 and the scanning line 120.

[0200] The third insulating layer 250 can function as an interlayer insulating layer. For example, as the third insulating layer 250, the same material as the first insulating layer 130 and the second insulating layer 180 can be used. In addition, the third insulating layer 250 can also function as a planarization layer. In this case, for example, as the third insulating layer 250, a resin such as polyimide or acrylic can be used. The resin can also be a photosensitive resin. In the case where a photosensitive resin is used as the third insulating layer 250, since the photosensitive resin can be directly exposed to light for etching without applying a resist, the process using the photolithography method is simplified. In addition, the third insulating layer 250 can have a single-layer structure or a stacked structure. In the case where the third insulating layer 250 has a stacked structure, the third insulating layer 250 can also have a structure in which a resin is stacked on an oxide or a nitride.

[0201] The third connection electrode 260 is conductive. As the third connection electrode 260, the same material as the first connection electrode 170 or the second connection electrode 240 can be used. In addition, as the third connection electrode 260, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) can also be used. Since the third connection electrode 260 is arranged to overlap with the source electrode 150 or the drain electrode 160, the aperture ratio of the pixel PX is hardly reduced. Therefore, as the third connection electrode 260, not only a light-transmitting material can be used, but also a non-light-transmitting material can be used.

[0202] [2. Method for manufacturing semiconductor device 12]

[0203] Reference Figures 38 to 40 A method for manufacturing the semiconductor device 12 will be described.

[0204] Fig.38 1 is a flowchart illustrating a method for manufacturing the semiconductor device 12 according to an embodiment of the present invention. Fig.39 and Fig.40 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device 12 according to an embodiment of the present invention. Fig.38 The steps of the flowchart shown.

[0205] Steps S100 to S200 are similar to those in the first embodiment. Figure 5The steps described above are the same, and thus description thereof is omitted here. In the manufacturing of the semiconductor device 12 , step S280 is performed after step S200 .

[0206] In step S280, a third conductive film CF3 is formed on the second insulating layer by sputtering (see Fig.17 ). In addition, the third conductive film CF3 is patterned by photolithography to form a second gate electrode 230 and a second connection electrode 240 (see Fig.39 ). The second gate electrode 230 is provided separately from the second connection electrode 240. The second connection electrode 240 is in contact with the first connection electrode 170 via the second opening OP2.

[0207] In step S290, a third insulating layer 250 is formed on the second insulating layer 180 by coating to cover the second gate electrode 230 and the second connecting electrode 240. In addition, a third opening OP3 and a fourth opening OP4 are formed in the third insulating layer 250 by photolithography (see FIG. 1 ). Fig.40 ). When the third insulating layer 250 is photosensitive, the third opening OP3 and the fourth opening OP4 can be formed without using a photoresist. In the third opening OP3, a portion of the second gate electrode 230 is exposed. In the fourth opening OP4, a portion of the second connection electrode 240 is exposed.

[0208] In step S300, a fourth conductive film is formed on the third insulating layer 250 by sputtering, and the fourth conductive film is patterned by photolithography to form a third connection electrode 260. The third connection electrode 260 is connected to the second gate electrode 230 via the third opening OP3, and is connected to the second connection electrode 240 via the fourth opening OP4.

[0209] Through the above steps, we can produce Fig.36 and Fig.37 The semiconductor device 12 shown in FIG. The semiconductor device 12 manufactured in this way has a 30 cm 2 / Vs or higher field effect mobility.

[0210] According to the semiconductor device 12, the second gate electrode 230 does not overlap with the source electrode 150 and the drain electrode 160 in a plan view, but is arranged with a gap between the source electrode 150 and the drain electrode 160, thereby suppressing the occurrence of short circuits between electrodes. In addition, since the oxide semiconductor layer 140 includes Poly-OS, it has excellent etching resistance, and thus has stable properties not only during the manufacture of the semiconductor device 12 but also after the manufacture. Therefore, the semiconductor device 12 has high reliability.

[0211] <Modification of the Third Embodiment>

[0212] Reference Fig.41 A semiconductor device 12A will be described as a modified example of the semiconductor device 12. In the following, description of the same configuration as that of the semiconductor device 12 may be omitted.

[0213] Fig.41 It is a schematic plan view showing the structure of a semiconductor device 12A according to one embodiment of the present invention.

[0214] The semiconductor device 12A includes a third connection electrode 260A. In a plan view, the third connection electrode 260A does not overlap with the source electrode 150 and the drain electrode 160. Fig.41 As shown, the third connection electrode 260A extends to surround the end of the drain electrode 160. It should be noted that the third connection electrode 260A is connected to the second gate electrode 230 via the third opening OP3 and is connected to the second connection electrode 240 via the fourth opening OP4.

[0215] As the third connection electrode 260A, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) can be used. The area surrounding the end of the drain electrode 160 in the third connection electrode 260A does not overlap with the first gate electrode 110 and the scan line 120. Therefore, when this area is not light-transmissive, the aperture ratio of the pixel PX is reduced. However, since the third connection electrode 260A is light-transmissive, the aperture ratio of the pixel PX is hardly reduced.

[0216] According to the semiconductor device 12A, the second gate electrode 230 does not overlap with the source electrode 150 and the drain electrode 160 in a plan view, but is arranged with a gap between the source electrode 150 and the drain electrode 160, thereby suppressing the occurrence of short circuit between electrodes. In addition, since the oxide semiconductor layer 140 includes Poly-OS, it has excellent etching resistance, and thus has a stable property not only during the manufacture of the semiconductor device 12A but also after the manufacture. Therefore, the semiconductor device 12A has high reliability.

[0217] The various embodiments and variations described above as embodiments of the present invention can be appropriately combined and implemented as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or designing components or adding, omitting or changing conditions of processes based on the various embodiments and variations by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0218] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

Claims

1. A semiconductor device comprising: a first gate electrode; an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode on the source electrode and the drain electrode and overlapping the first gate electrode and the oxide semiconductor layer; In a plan view, the second gate electrode is arranged with a gap between the source electrode and the drain electrode. The second gate electrode is electrically connected to the first gate electrode.

2. The semiconductor device according to claim 1, It also includes a scanning line formed of the same layer as the first gate electrode and arranged in a manner electrically connected to the first gate electrode, In the plan view, the second gate electrode extends so as to surround an end portion of one of the source electrode and the drain electrode. An end portion of the second gate electrode is in contact with the scanning line via the opening.

3. The semiconductor device according to claim 1, wherein The second gate electrode includes a second oxide semiconductor having a polycrystalline structure.

4. The semiconductor device according to claim 3, wherein: The second gate electrode has a sheet resistance of 1000 Ω / sq. or less.

5. The semiconductor device according to claim 1, wherein The oxide semiconductor layer includes: a first region connected to one of the source electrode and the drain electrode; and a second region overlapping with the second gate electrode, A difference between the film thickness of the first region and the film thickness of the second region is 3 nm or less.

6. The semiconductor device according to claim 1, wherein When the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C., the etching rate is less than 3 nm / min.

7. The semiconductor device according to claim 6, wherein: The etching solution includes nitric acid and acetic acid.

8. The semiconductor device according to claim 6, wherein: The oxide semiconductor layer is formed by heat treating an oxide semiconductor film having an amorphous structure. When the oxide semiconductor film is etched using the etching solution at 40° C., an etching rate is 100 nm / min or more.

9. The semiconductor device according to claim 1, wherein: When the oxide semiconductor layer is etched using a 0.5% hydrofluoric acid solution at room temperature, an etching rate is less than 5 nm / min.

10. The semiconductor device according to claim 1, wherein The oxide semiconductor layer contains a plurality of metal elements. One of the plurality of metal elements is indium, The atomic ratio of the indium to the plurality of metal elements is 50% or more.

11. A semiconductor device comprising: a first gate electrode; a scanning line formed of the same layer as the first gate electrode and arranged to be electrically connected to the first gate electrode; an oxide semiconductor layer including an oxide semiconductor having a polycrystalline structure over the first gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; a second gate electrode on the source electrode and the drain electrode and overlapping the first gate electrode and the oxide semiconductor layer; an insulating layer on the second gate electrode, the insulating layer comprising a first opening portion through which a portion of the second gate electrode is exposed; and a first connection electrode electrically connected to the second gate electrode via the first opening, In a plan view, the second gate electrode is arranged with a gap between the source electrode and the drain electrode. The first connection electrode is electrically connected to the scanning line via a second opening portion through which a part of the scanning line is exposed.

12. The semiconductor device according to claim 11, wherein In the plan view, the first connecting electrode overlaps with at least one of the source electrode and the drain electrode.

13. The semiconductor device according to claim 11, wherein In the plan view, the first connection electrode extends to surround an end of one of the source electrode and the drain electrode. The first connecting electrode is light-transmissive.

14. The semiconductor device according to claim 11, It also includes a second connection electrode formed of the same layer as the source electrode and the drain electrode and separated from the source electrode and the drain electrode, The first connection electrode is connected to the second connection electrode via a second opening portion through which a portion of the second connection electrode is exposed. The second connection electrode is in contact with the scanning line via a third opening that exposes a portion of the scanning line.

15. The semiconductor device according to claim 11, wherein The oxide semiconductor layer includes: a first region connected to one of the source electrode and the drain electrode; and a second region overlapping with the second gate electrode, A difference between the film thickness of the first region and the film thickness of the second region is 3 nm or less.

16. The semiconductor device according to claim 11, wherein When the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C., the etching rate is less than 3 nm / min.

17. The semiconductor device according to claim 16, wherein: The etching solution includes nitric acid and acetic acid.

18. The semiconductor device according to claim 16, wherein: The oxide semiconductor layer is formed by heat treating an oxide semiconductor film having an amorphous structure. When the oxide semiconductor film is etched using the etching solution at 40° C., an etching rate is 100 nm / min or more.

19. The semiconductor device according to claim 11, wherein When the oxide semiconductor layer is etched using a 0.5% hydrofluoric acid solution at room temperature, an etching rate is less than 5 nm / min.

20. The semiconductor device according to claim 11, wherein The oxide semiconductor layer contains a plurality of metal elements. One of the plurality of metal elements is indium, The atomic ratio of the indium to the plurality of metal elements is 50% or more.

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