Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a manufacturing method of the display device. Provided is a high-definition display device. The display device includes: an oxide semiconductor layer including a polycrystalline structure; a gate insulating layer disposed over the oxide semiconductor layer; a gate electrode over the gate insulating layer facing the oxide semiconductor layer; a first silicon nitride layer provided in contact with the gate electrode; a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer; a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer; a first transparent conductive layer electrically connected to the oxide semiconductor layer; and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer. The gate electrode has a channel length of 2.0 [mu] m or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device and a method for manufacturing the display device. In particular, one embodiment of the present invention relates to a display device using a transistor including an oxide semiconductor and a method for manufacturing the display device. Background Art

[0002] Recently, development of transistors using oxide semiconductors for channels instead of amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon is underway (e.g., Patent Document 1 and Patent Document 2). Like transistors using amorphous silicon for channels, transistors using oxide semiconductors for channels can be formed with a simple structure and a low-temperature process. It is known that transistors using oxide semiconductors for channels have higher mobility than transistors using amorphous silicon for channels, and have very low cutoff current.

[0003] In addition, in recent years, display devices have been required to be highly refined, and the pixel size has been continuously reduced. As the pixel size is reduced, the reduction of wiring width and transistor size is being studied. However, there is a limit to their reduction, and the configuration of the metal layer and semiconductor layer constituting the pixel circuit causes the aperture ratio to decrease. Therefore, the development of transistors that use the following transistors for pixel circuits is underway: the transistor is a transistor that uses an oxide semiconductor layer for the channel, which can obtain characteristics sufficient to drive the pixel circuit even if the transistor size is small.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2014-146819

[0007] Patent Document 2: Japanese Patent Application Publication No. 2015-159315 Summary of the invention

[0008] Problems to be solved by the invention

[0009] It is known that transistors using oxide semiconductors are greatly affected by hydrogen contained in the insulating film provided around the oxide semiconductor. As the pixel size of the display device is reduced, the size of the transistor (channel length L) also needs to be reduced. When the channel length L is less than 2.0 μm, hydrogen is also likely to invade the channel region, not just the source region and the drain region, so it may not work as a transistor.

[0010] One object of one embodiment of the present invention is to provide a high-definition display device.

[0011] Means for solving problems

[0012] A display device involved in one embodiment of the present invention comprises: an oxide semiconductor layer including a polycrystalline structure; a gate insulating layer arranged on the oxide semiconductor layer; a gate electrode on the gate insulating layer and opposite to the oxide semiconductor layer; a first silicon nitride layer provided in contact with the gate electrode; a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer; a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer; a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, wherein the channel length of the gate electrode is less than 2.0 μm.

[0013] A display device according to one embodiment of the present invention comprises: an oxide semiconductor layer including a polycrystalline structure; a gate insulating layer arranged on the oxide semiconductor layer; a gate electrode on the gate insulating layer and opposite to the oxide semiconductor layer; a first silicon nitride layer provided in contact with the gate electrode; a silicon oxide layer provided in contact with the first silicon nitride layer; a source wiring provided in contact with the silicon oxide layer and electrically connected to the oxide semiconductor layer; a second silicon nitride layer provided in contact with the source wiring and the silicon oxide layer; a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, wherein the channel length of the gate electrode is less than 2.0 μm, and the film thickness of the silicon oxide layer is smaller than the film thickness of the first silicon nitride layer, the film thickness of the second silicon nitride layer, and the film thickness of the third silicon nitride layer.

[0014] A method for manufacturing a display device involved in one embodiment of the present invention includes: forming an oxide semiconductor layer including a polycrystalline structure; forming a gate insulating layer on the oxide semiconductor layer; forming a gate electrode opposite to the oxide semiconductor layer on the gate insulating layer; forming a first silicon nitride layer in contact with the gate electrode; forming a source wiring electrically connected to the oxide semiconductor layer in contact with the first silicon nitride layer; forming a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer; forming a first transparent conductive layer electrically connected to the oxide semiconductor layer in contact with the second silicon nitride layer; and forming a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer, wherein, in the oxide semiconductor layer, a channel length of a channel region overlapping with the gate electrode is less than 2.0 μm, and the film formation temperatures of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are each greater than 150° C. and less than 250° C. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic plan view showing the structure of a display device according to one embodiment of the present invention.

[0016] Figure 2This is a schematic plan view showing a circuit configuration of a display device according to an embodiment of the present invention.

[0017] Figure 3 : is a circuit diagram showing a pixel circuit of a pixel of a display device according to one embodiment of the present invention.

[0018] Figure 4 This is a cross-sectional view schematically showing a display device according to one embodiment of the present invention.

[0019] Figure 5 It is a plan view showing the structure of a pixel of a display device according to one embodiment of the present invention.

[0020] Figure 6 It is a plan view showing the structure of a pixel of a display device according to one embodiment of the present invention.

[0021] Figure 7 It is a sequence diagram for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0022] Figure 8 It is a sequence diagram for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0023] Fig. 9 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0024] Fig.10 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0025] Fig.11 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0026] Fig.12 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0027] Fig.13 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0028] Fig.14 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0029] Fig.15 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0030] Fig.16 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0031] Fig.17 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0032] Fig.18 This is a cross-sectional view schematically showing a display device according to one embodiment of the present invention.

[0033] Fig.19 It is a sequence diagram for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0034] Fig. 20 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0035] Fig.21 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0036] Fig. 22 This is a cross-sectional view schematically showing a display device according to one embodiment of the present invention.

[0037] Fig.23 It is a cross-sectional view for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0038] Fig.24 This is a cross-sectional view schematically showing a display device according to one embodiment of the present invention.

[0039] Fig.25 It is a sequence diagram for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0040] Fig.26 It is a sequence diagram for explaining a method for manufacturing a display device according to one embodiment of the present invention.

[0041] Description of Reference Numerals

[0042] 10, 10A to 10C: display device, 100: array substrate, 110: first driving circuit, 111: multiplexing circuit, 112: analog switch, 115: wiring portion, 116: data signal supply line, 120: second driving circuit, 121: peripheral area, 122: display area, 124: sealing area, 126: exposed area, 129: scanning signal line, 131: data signal line, 141: connection wiring, 143: connection portion, 145: common wiring, 146: common electrode, 150: Terminal portion, 160: transistor, 161: first gate electrode, 163: first source electrode, 164: first drain electrode, 168: capacitor, 170: liquid crystal element, 180: pixel, 182: pixel circuit, 190: opposing substrate, 192: light shielding portion, 200: sealing portion, 300: flexible printed circuit substrate, 400: IC chip, AOS: oxide semiconductor layer, B: sub-pixel, BM: black matrix, CF: color filter, CMTL: common auxiliary electrode, CON1: contact area, CTCO: Common electrode, G: sub-pixel, GI1: first gate insulating layer, GI2: second gate insulating layer, GL1: gate wiring, GL2: gate electrode, IL1: first insulating layer, IL2: second insulating layer, IL3: third insulating layer, IL4: fourth insulating layer, LC: liquid crystal layer, LS: light shielding layer, MO1, MO2: metal oxide layer, OC: cover layer, OF1, OF2: alignment film, OS1: channel region, OS2: low resistance region, PAS1~PAS3: passivation layer, PCON: opening, POS: oxide semiconductor layer, PTCO: pixel electrode, R: sub-pixel, S: semiconductor layer, S1: semiconductor layer, S2: semiconductor layer, S3: semiconductor layer, SCON1: opening, SCON2: opening, SO: silicon oxide layer, SP: spacer, SUB1: substrate, SUB2: opposing substrate, Tr, Tr1, Tr2, Tr2-1, Tr2-2: transistor, W: wiring group, W1~W3: wiring, WC1, WC2: opening, ZCON: opening, ZTCO: connection electrode DETAILED DESCRIPTION

[0043] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is exemplary only. While maintaining the gist of the invention, those skilled in the art will be able to easily conceive of a configuration by appropriately changing the configuration of the embodiment, which is of course included within the scope of the present invention. In order to make the description clearer, the accompanying drawings sometimes schematically represent the width, film thickness, shape, etc. of each part compared to the actual method. However, the illustrated shape is only an example and does not limit the interpretation of the present invention. In this specification and the drawings, the same figure mark is used for the same configuration as that described above with respect to the existing drawings, and the detailed description is sometimes appropriately omitted.

[0044] "Semiconductor device" refers to a device as a whole that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one form of a semiconductor device. The semiconductor device of the embodiment shown below may be, for example, a transistor used in an integrated circuit (IC) such as a display device, a microprocessor (MPU), or a memory circuit.

[0045] A "display device" refers to a structure that uses an electro-optical layer to display an image. For example, the term display device sometimes refers to a display panel that includes an electro-optical layer, or sometimes refers to a structure in which other optical components (such as a polarization component, a backlight, a touch panel, etc.) are installed on a display unit. In the "electro-optical layer", as long as there is no technical contradiction, a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer may also be included. Therefore, in the embodiments described below, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to the above-mentioned other display devices including an electro-optical layer.

[0046] In various embodiments of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. On the contrary, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for the sake of convenience, the description is made using the phrases such as up or below, but, for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured to be different from the orientation shown in the figure. In the following description, for example, the description of the oxide semiconductor layer on the substrate is merely a description of the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Up or down refers to the stacking order in a structure having a plurality of layers stacked, and in the case of being expressed as a pixel electrode above a transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, when expressed as a pixel electrode vertically above a transistor, it refers to a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0047] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C. In addition, these expressions do not exclude the case where α includes other elements.

[0048] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0049] <First Embodiment>

[0050] Reference Figure 1 to Figure 26 A display device 10 according to one embodiment of the present invention will be described.

[0051] <1. Overview of Display Device>

[0052] Reference Figure 1 and Figure 2 The overview of the display device 10 will be described. Figure 1 It is a schematic plan view showing the configuration of the display device 10 . Figure 2 1 is a schematic plan view showing a circuit configuration of the display device 10. As an example, the display device 10 is a liquid crystal display device.

[0053] like Figure 1 or Figure 2 As shown, the display device 10 includes an array substrate 100, a sealing portion 200, an opposing substrate 190, a flexible printed circuit (FPC) 300, and an IC chip 400. The array substrate 100 and the opposing substrate 190 are bonded together by the sealing portion 200.

[0054] In addition, the display device 10 includes a display area 122 and a peripheral area 121 surrounding the display area 122. The peripheral area 121 includes a sealed area 124 and an outer side of the sealed area 124 surrounding the sealed area 124. The outer side of the sealed area 124 includes an exposed area 126.

[0055] A plurality of pixels 180 are arranged in a matrix in the first direction D1 and the second direction D2 in the display region 122. The display region 122 is a region overlapping a liquid crystal layer (not shown) including liquid crystal molecules in a plan view.

[0056] In the peripheral region 121, a light shielding portion 192 is disposed so as to overlap with the array substrate 100 and the counter substrate 190. In the sealing region 124, a sealing portion 200 is disposed. The sealing region 124 is a region overlapping with the sealing portion 200 in a plan view.

[0057] The exposed area 126 is an area where the array substrate 100 is exposed from the counter substrate 190. The FPC terminal portion 150 is arranged in the exposed area 126. In addition, the FPC 300, the IC chip 400, and a part of the routing wiring portion 115 are arranged in the exposed area 126.

[0058] In the display device 10 , the sealed area 124 , the outer side of the sealed area 124 , and the exposed area 126 may be collectively referred to as a frame area.

[0059] The FPC terminal portion 150 includes a plurality of FPC terminals. The routing wiring portion 115 includes a plurality of data signal supply lines 116. The light shielding portion 192 overlaps the sealing portion 200, the first driving circuit 110, the second driving circuit 120, a portion of the routing wiring portion 115, and the common wiring 145, and has a function of hiding the sealing portion 200, the first driving circuit 110, the second driving circuit 120, a portion of the routing wiring portion 115, the common wiring 145, and the like.

[0060] The case where the shape of the array substrate 100 of the display device 10 and the shape of the display area 122 are octagonal is described. It should be noted that the shape of the array substrate 100 of the display device 10 and the shape of the display area 122 are not limited to octagonal, and can be rectangular or circular.

[0061] <2. Circuit Configuration of Display Device 10>

[0062] Next, refer to Figure 2 The circuit configuration of the display device 10 will be described. Figure 1 The same or similar structures will be described as needed.

[0063] like Figure 2 As shown, the FPC terminal portion 150 connected to the FPC 300 is connected to the IC chip 400 and the second drive circuit 120 via the connection wiring 141. The IC chip 400 is connected to the first drive circuit 110 using a plurality of data signal supply lines 116.

[0064] The first driving circuit 110 is provided in parallel with the first direction D1 of the display region 122. In addition, the second driving circuit 120 is provided in parallel with the second direction D2 of the display region 122. The first driving circuit 110 and the second driving circuit 120 are parallel to the sealing region 124 ( Figure 1 The area where the sealing area 124 overlaps with the first driving circuit 110 and the second driving circuit 120 is an example and is not limited to Figure 1 The sealed region 124 shown in FIG. The region where the sealed region 124 overlaps with the first drive circuit 110 and the second drive circuit 120 is provided with a pixel circuit 182 (see FIG. 1 ) of a plurality of pixels 180. Figure 3 ) area outside the area.

[0065] The first driving circuit 110 is, for example, a source driver, and includes a plurality of multiplexing circuits 111 for selecting data signals. The multiplexing circuits 111 include a plurality of analog switches (ASWs) 112. The plurality of ASWs 112 are electrically connected between the plurality of data signal lines 131 and the plurality of data signal supply lines 116, and each of the ASWs 112 has a function of electrically connecting the corresponding data signal lines 131 to the data signal supply lines 116. For the sake of convenience, as an example, Figure 2 The multiplexer circuit 111 shown includes two ASWs 112. The number of ASWs 112 included in the multiplexer circuit 111 may be greater than two.

[0066] The second driving circuit 120 is, for example, a gate driver circuit. In addition, the IC chip 400 supplies a control signal for driving the pixel circuit 182 to at least one of the first driving circuit 110 and the second driving circuit 120 .

[0067] Each of the plurality of pixels 180 may correspond to, for example, a sub-pixel R, a sub-pixel G, and a sub-pixel B. The pixel 180 is a minimum unit constituting a portion of an image reproduced in the display area 122. Each of the pixels 180 includes a display element. Figure 1 In the example shown, the display element is a liquid crystal element 170 (see Figure 3 The color corresponding to the sub-pixel is determined by the characteristics of the liquid crystal element 170 or the color filter (not shown) disposed in the sub-pixel. It should be noted that the color filter can be disposed on the counter substrate 190 or on the array substrate 100.

[0068] For example, the sub-pixel R may include a red color filter that emits red, the sub-pixel G may include a green color filter that emits green, and the sub-pixel B may include a blue color filter that emits blue.

[0069] A plurality of data signal lines including the data signal lines 131 extend from the first driving circuit 110 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. A plurality of scanning signal lines including the scanning signal lines 129 extend from the second driving circuit 120 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0070] The common wiring 145 overlaps with the peripheral region 121, for example, and is provided inside the periphery of the peripheral region 121. A common voltage is supplied to the common wiring 145 from an external device. The common voltage may be, for example, a voltage between a voltage of a voltage amplitude on the positive side of a data signal and a voltage of a voltage amplitude on the negative side of a data signal, or may be a voltage that serves as a reference for the voltage amplitude, and may be 0 V, a ground voltage, or a ground voltage. The common wiring 145 may be electrically connected to a common electrode (not shown) formed on the opposing substrate 190 via a plurality of connection portions 143, or may be connected to the common electrode 146 (see FIG. 1 ) using various wiring layers. Figure 3 )Electrical connection.

[0071] The FPC 300 is connected to the FPC terminal portion 150, whereby the display device 10 is connected to an external device (not shown) connected to the FPC 300, and a signal from the external device is supplied to, for example, the IC chip 400, the first drive circuit 110, the second drive circuit 120, and each pixel 180. The display device 10 drives each pixel circuit 182 provided in the display device 10 using the signal from the external device and the control signal generated by the IC chip 400, the first drive circuit 110, and the second drive circuit 120.

[0072] <3. Configuration of Pixel Circuit 182 of Pixel 180>

[0073] Reference Figure 3 , describing the structure of the pixel circuit 182. Figure 3 1 is a schematic circuit diagram showing the configuration of a pixel circuit 182 of a pixel 180 in the display device 10. Figure 1 and Figure 2 The same or similar structures will be described as needed.

[0074] The pixel circuit 182 includes, for example, a transistor 160, a liquid crystal element 170, and a capacitor 168. Details will be described later. For example, the first electrode of the capacitor 168 is a pixel electrode PTCO, and the second electrode of the capacitor 168 is grounded. Similar to the capacitor 168, the first electrode of the liquid crystal element 170 is a pixel electrode PTCO, and the second electrode of the liquid crystal element 170 is a common electrode CTCO. It should be noted that the first electrode and the second electrode of the capacitor 168 are replaceable. The first electrode and the second electrode of the liquid crystal element 170 are replaceable. The second electrode of the liquid crystal element 170 is the common electrode 146. It should be noted that the second electrode of the capacitor 168 can be either the common electrode CTCO or the common electrode 146. The transistor 160 includes a first gate electrode 161, a first source electrode 163, and a first drain electrode 164. The first gate electrode 161 is connected to the scanning signal line 129. The first source electrode 163 is connected to the data signal line 131. The first drain electrode 164 is connected to the first electrode of the capacitor 168 and the first electrode of the liquid crystal element 170. It should be noted that, in this specification, for the sake of convenience, the first source electrode 163 is referred to as a source electrode, and the first drain electrode 164 is referred to as a drain electrode, but sometimes the function of each electrode as a source electrode and a function as a drain electrode are switched according to the voltage supplied (applied) to the source electrode and the drain electrode of the transistor 160.

[0075] The display device 10 can display an image by supplying an arbitrary signal (voltage or current) to the pixel circuit 182 of each of the three sub-pixels of the display device 10. For example, the IC chip 400, the first driving circuit 110, the second driving circuit 120, and the external device can change the alignment state of the liquid crystal molecules included in the liquid crystal element 170 by supplying a current or a voltage to each of the pixel electrodes and the common electrode 146 included in the pixel circuit 182. As a result, the display device 10 can display an image.

[0076] <4. Configuration of Display Device 10>

[0077] Reference Figures 4 to 6 The outline of a display device 10 according to one embodiment of the present invention will be described. Figure 4 It is a cross-sectional view showing the structure of a display device 10 according to one embodiment of the present invention. Figure 4 The cross-sectional view shown in FIG. 1 shows the transistor Tr2 in the peripheral region 121 and the transistor Tr1 in the pixel circuit 182 which are adjacent to each other. Actually, the pixel circuit 182 is included in the display region 122, and the peripheral circuit is included in the peripheral region 121. Therefore, it goes without saying that Figure 4 , the pixel circuit and the peripheral circuit shown adjacent to each other are separately provided in the display device 10. And, Figure 4The cross-sectional view shown in FIG. 1 shows the periphery of the opening of the pixel 180 and a portion of the transmissive region (opening region) that participates in image display. The transistor Tr2 and the transistor Tr1 are, for example, thin film transistors. Figure 1 to Figure 3 The same or similar structures will be described as needed.

[0078] also, Figure 5 and Figure 6 It is a plan view showing the structure of a pixel of the display device 10 according to one embodiment of the present invention. Figure 5 The layout from the light shielding layer LS to the passivation layer PAS3 is shown. Figure 6 The layout from the passivation layer PAS3 to the common electrode CTCO is shown.

[0079] like Figure 4 As shown, the layers included in the display device 10 are arranged above the substrate SUB1 (third direction D3). The display device 10 includes a transistor Tr1, a transistor Tr2, a wiring group W including a plurality of wirings, a connecting electrode ZTCO, a pixel electrode PTCO, a common auxiliary electrode CMTL, and a common electrode CTCO. TCO is an abbreviation of Transparent Conductive Oxide. The transistor Tr1 is a transistor included in the pixel circuit 182 of the pixel 180 of the display device 10. The transistor Tr2 is a transistor included in a peripheral circuit such as the first driving circuit 110 or the second driving circuit 120. The wiring group W includes, for example, a wiring W1, a wiring W2, and a wiring W3.

[0080] <4-1. Configuration of transistor Tr1>

[0081] like Figure 4 As shown, transistor Tr1 is arranged above substrate SUB1. Transistor Tr1 at least includes an oxide semiconductor layer POS, a first gate insulating layer GI1, a gate wiring GL1 (also called a gate electrode), a passivation layer PAS1, a wiring W3, a passivation layer PAS2 and a connecting electrode ZTCO (also called a connecting electrode). Transistor Tr1 may also have a passivation layer PAS3 on the connecting electrode ZTCO. Transistor Tr1 may also have a second insulating layer IL2 and a light shielding layer LS between the oxide semiconductor layer POS and the substrate SUB1. In addition, transistor Tr1 may also have a metal oxide layer MO1 with aluminum as a main component, which is arranged in contact with the oxide semiconductor layer POS between the oxide semiconductor layer POS and the second insulating layer IL2. Figure 4In the embodiment, an example in which the metal oxide layer MO1 is provided under the oxide semiconductor layer POS is described, but one embodiment of the present invention is not limited thereto, and the oxide semiconductor layer POS may also be in contact with the second insulating layer IL2 (see Fig.24 ).

[0082] The gate wiring GL1 is opposite to the oxide semiconductor layer POS. The first gate insulating layer GI1 is provided between the oxide semiconductor layer POS and the gate wiring GL1. In the present embodiment, as the transistor Tr1, a top-gate transistor in which the oxide semiconductor layer POS is provided on the substrate SUB1 side relative to the gate wiring GL1 is exemplified, but a bottom-gate transistor in which the positional relationship between the gate wiring GL1 and the oxide semiconductor layer POS is opposite may also be used. It should be noted that the structure from the substrate SUB1 to the passivation layer PAS3 is sometimes referred to as a semiconductor device.

[0083] The oxide semiconductor layer POS has a polycrystalline structure including a plurality of crystal grains. As will be described in detail later, the oxide semiconductor layer POS having a polycrystalline structure can be formed by using the Poly-OS (Poly-crystalline Oxide Semiconductor) technology. Hereinafter, an oxide semiconductor having a polycrystalline structure may be referred to as Poly-OS.

[0084] The oxide semiconductor layer POS contains two or more metal elements including indium, and the ratio of indium in the two or more metal elements is 50% or more, which will be described in detail later. As other metal elements besides indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr) and lanthanide elements can also be used. However, the oxide semiconductor layer POS only needs to contain Poly-OS, and sometimes contains other metal elements other than the above.

[0085] The oxide semiconductor layer POS includes a channel region OS1 and a low resistance region OS2. The channel region OS1 is a region of the oxide semiconductor layer that overlaps with the gate wiring GL1 in a plan view. The channel region OS1 switches between a conducting state and a non-conducting state in accordance with a voltage supplied to the gate wiring GL1. The low resistance region OS2 is a region with a lower resistance than the channel region OS1. The low resistance region OS2 functions as a source region or a drain region. For example, the low resistance region OS2 is made low-resistance by performing ion implantation of impurities into the oxide semiconductor layer POS.

[0086] like Figure 5As shown in FIG. 1 , the gate wiring GL1 is arranged along the first direction D1. The region of the gate wiring GL1 that overlaps with the oxide semiconductor layer POS is called a gate electrode. The oxide semiconductor layer POS is arranged to intersect the gate wiring GL1. In addition, the region of the oxide semiconductor layer POS that overlaps with the gate wiring GL1 is a channel region OS1. Figure 5 In the channel region OS1, the width of the gate wiring GL1 (the length in the second direction D2) corresponds to the channel length L. In addition, in the channel region OS1, the oxide semiconductor layer POS (the length in the first direction D1) corresponds to the channel width W. In the present embodiment, the width of the gate wiring GL1 (channel length L) is 2.0 μm or less, preferably 1.5 μm or less.

[0087] A first gate insulating layer GI1 is provided on the oxide semiconductor layer POS. A passivation layer PAS1 is provided on the first gate insulating layer GI1. A wiring W3 is provided on the passivation layer PAS1. Figure 5 As shown, in a plan view, the wiring W3 is arranged along the second direction D2 and functions as a source wiring. The wiring W3 is connected to the low resistance area OS2 via an opening SCON1 provided in the first gate insulating layer GI1 and the passivation layer PAS1. A passivation layer PAS2 is provided on the passivation layer PAS1 and the wiring W3. A connecting electrode ZTCO is provided on the passivation layer PAS2. The connecting electrode ZTCO is connected to the low resistance area OS2 via an opening ZCON provided in the first gate insulating layer GI1 and the passivation layers PAS1 and PAS2. The connecting electrode ZTCO is connected to the low resistance area OS2 at the bottom of the opening ZCON. The area where the connecting electrode ZTCO is connected to the low resistance area OS2 is called the contact area CON1.

[0088] A second insulating layer IL2 and a light shielding layer LS are provided between the oxide semiconductor layer POS and the substrate SUB1. Figure 5 As shown, when viewed from above, the light-shielding layer LS is arranged along the first direction D1 and is disposed in a region overlapping with the gate wiring GL1. In addition, the light-shielding layer LS is disposed in a manner intersecting with the oxide semiconductor layer POS. That is, when viewed from above, the light-shielding layer LS is disposed in a region overlapping with the channel region OS1. The light-shielding layer LS suppresses light incident from the substrate SUB1 side from reaching the channel region OS1. When a conductive layer is used as the light-shielding layer LS, a voltage may also be applied to the light-shielding layer LS to control the channel region OS1. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate wiring GL1 may also be electrically connected. When viewed from above, the above-mentioned contact region CON1 is disposed in a region that does not overlap with the light-shielding layer LS.

[0089] As a display device 10, when a high light transmittance is required, one of the source electrode and the drain electrode is sometimes formed with a metal conductive layer, and the other is formed with a transparent conductive layer. For example, if a transparent conductive layer such as ITO is formed in contact with a silicon layer, the surface of the silicon layer is oxidized due to the process gas and oxygen ions during the ITO film formation. Since the oxide layer formed on the surface of the silicon layer is high-resistance, the contact resistance between the silicon layer and the transparent conductive layer becomes high. As a result, the electrical contact between the silicon layer and the transparent conductive layer is poor. On the other hand, even if the above-mentioned transparent conductive layer is formed in contact with the oxide semiconductor layer, a high-resistance oxide layer such as the above-mentioned will not be formed on the surface of the oxide semiconductor layer. Therefore, no poor electrical contact between the oxide semiconductor layer and the transparent conductive layer will occur.

[0090] In order to realize a high-definition display device 10, the width (channel length L) of the gate electrode of a transistor using an oxide semiconductor layer needs to be 2 μm or less. Considering the deviation in the width of the gate electrode caused by the photolithography process and etching in the manufacturing process of the display device 10, it is necessary to be able to drive as a transistor even if it is less than 1.5 μm.

[0091] It is known that oxide semiconductors produce oxygen defects due to processing damage such as etching. If hydrogen is captured by the oxygen defect, the resistance of the oxide semiconductor can be reduced, so that it can function as a conductor. On the other hand, the resistance of the oxide semiconductor is increased by supplying oxygen to the oxygen defect, so that it can function as a semiconductor. That is, in order to make the transistor work well, in the channel region, it is preferred to increase the resistance of the oxide semiconductor by supplying oxygen to the oxygen defect, and in the source region or the drain region, it is preferred to supply hydrogen to the oxygen defect to reduce the resistance of the oxide semiconductor.

[0092] The characteristics of transistors using oxide semiconductors are greatly affected by the hydrogen and oxygen contained in the insulating film provided around the oxide semiconductor. When an excess of oxygen is supplied to the oxide semiconductor, a defect energy level different from an oxygen defect is formed due to the excess oxygen, thereby reducing the reliability of the transistor or causing a reduction in field effect mobility. In addition, when hydrogen is supplied to the oxide semiconductor in excess and hydrogen is supplied to the channel region, there is a problem of the transistor being depleted and no longer working.

[0093] Therefore, in order to miniaturize a transistor using an oxide semiconductor, it is necessary to appropriately supply oxygen and hydrogen to the channel region OS1 and the low-resistance region OS2 having a channel length of 2.0 μm or less.

[0094] In one embodiment of the present invention, by appropriately supplying hydrogen to the oxide semiconductor layer POS, the resistance of the low-resistance region OS2 functioning as a source region and a drain region is reduced, and diffusion of hydrogen into the channel region OS1 is suppressed.

[0095] In this embodiment, a silicon nitride layer is used as the passivation layer PAS1~PAS3. The silicon nitride layer contains more hydrogen than silicon oxide. When heat exceeding 250°C is applied, the hydrogen contained in the silicon nitride layer diffuses. Therefore, as the passivation layer PAS1~PAS3, the silicon nitride layer is formed at a temperature of 150°C to 250°C. Thus, the diffusion of a large amount of hydrogen contained in the silicon nitride layer can be suppressed, and excessive supply of hydrogen to the low resistance region OS2 can be suppressed. Thus, the depletion of the transistor Tr1 can be suppressed. The composition of the passivation layers PAS1~PAS3 will be described in detail later.

[0096] <4-2. Configuration of transistor Tr2>

[0097] The transistor Tr2 has a p-type transistor Tr2-1 and an n-type transistor Tr2-2. When the transistor Tr2 is not distinguished, the transistor included in the peripheral region 121 is expressed as the transistor Tr2. When the transistor Tr2 is distinguished, the transistor Tr2 is expressed as the p-type transistor Tr2-1, the n-type transistor Tr2-2, and the like.

[0098] The p-type transistor Tr2-1 and the n-type transistor Tr2-2 each have a gate electrode GL2, a second gate insulating layer GI2, and a semiconductor layer S. The gate electrode GL2 is opposite to the semiconductor layer S. The second gate insulating layer GI2 is disposed between the semiconductor layer S and the gate electrode GL2. As an example, the transistor Tr2 of the display device 10 is a top-gate transistor having a gate electrode GL2 disposed above the semiconductor layer S. The transistor Tr2 may also be a bottom-gate transistor having a positional relationship between the semiconductor layer S and the gate electrode GL2 reversed.

[0099] A first insulating layer IL1 is provided on the substrate SUB1. The first insulating layer IL1 functions as a base layer. By providing the first insulating layer IL1, it is possible to suppress impurities from entering the semiconductor layer S from the substrate SUB1.

[0100] The semiconductor region S of the p-type transistor Tr2-1 includes semiconductor regions S1 and S2. The semiconductor region S of the n-type transistor Tr2-2 includes semiconductor regions S1, S2, and S3. The semiconductor region S1 is a semiconductor in a region overlapping with the gate electrode GL2 in a plan view. The semiconductor region S1 functions as a channel region of the transistor Tr2-1. The semiconductor region S2 functions as a conductor. The semiconductor region S3 functions as a conductor with a higher resistance than the semiconductor region S2. The semiconductor region S3 suppresses hot carrier degradation by attenuating hot carriers invading the semiconductor region S1.

[0101] A second insulating layer IL2 and a first gate insulating layer GI1 are provided on the gate electrode GL2. A wiring W2 is provided on these insulating layers. The wiring W2 functions as a source electrode and a drain electrode of the transistor Tr2. The wiring W2 is connected to the semiconductor region S via an opening SCON2 provided in the second insulating layer IL2, the first gate insulating layer GI1, and the second gate insulating layer GI2. In addition, the wiring W2 is connected to the wiring W1 through an opening WC1 provided in the second insulating layer IL2 and the first gate insulating layer GI1. A passivation layer PAS1 is provided on the wiring W2. A wiring W3 is provided on the passivation layer PAS1. The wiring W3 is connected to the wiring W2 through an opening WC2 provided in the passivation layer PAS1.

[0102] The gate electrode GL2 is formed in the same layer as the wiring W1 and the light shielding layer LS. The wiring W2 is formed in the same layer as the gate wiring GL1. The same layer means that a plurality of components are formed by patterning one layer.

[0103] <4-3. Other Configurations of Display Device>

[0104] Next, the layer structure provided on the transistor Tr1 and the transistor Tr2 is described. In the display area 122, a color filter CF is provided on the passivation layer PAS3. By providing the color filter CF on the substrate SUB1 side, the positional displacement between the color filter CF and the pixel circuit can be suppressed. In addition, the third insulating layer IL3 is provided on the color filter CF and the passivation layer PAS3. Since the color filter CF is not provided in the peripheral area 121, the third insulating layer IL3 is provided on the passivation layer PAS3. The third insulating layer IL3 functions as a planarization film.

[0105] In the display region 122, a pixel electrode PTCO is provided on the third insulating layer IL3. The pixel electrode PTCO is connected to the connection electrode ZTCO via an opening PCON provided in the third insulating layer IL3. Figure 5 and Figure 6As shown, the pixel electrode PTCO overlaps the gate wiring GL1, the oxide semiconductor layer POS and the connection electrode ZTCO between two adjacent wirings W3 and the wiring W3. The pixel electrode PTCO is in contact with the connection electrode ZTCO in the opening PCON overlapping the gate wiring GL1.

[0106] The fourth insulating layer IL4 is provided in the display region 122 and the peripheral region 121. In the display region 122, the fourth insulating layer IL4 is provided in a manner covering the pixel electrode PTCO and the third insulating layer IL3. In addition, in the peripheral region 121, the fourth insulating layer IL4 is provided on the third insulating layer IL3. In addition, at the end of the peripheral region 121 (the end of the substrate SUB1), the fourth insulating layer IL4 is in contact with the third insulating layer IL3. Thus, the moisture contained in the third insulating layer IL3 can be sealed.

[0107] In the display region 122, a common auxiliary electrode CMTL and a common electrode CTCO are provided on the fourth insulating layer IL4. Figure 6 As shown, the common auxiliary electrode CMTL and the common electrode CTCO are arranged in a grid shape in a manner overlapping with the gate wiring GL and the wiring W3. That is, the common auxiliary electrode CMTL is provided in common with respect to a plurality of pixels. In other words, the common auxiliary electrode CMTL has an opening OP. The opening OP is provided in a manner exposing the pixel electrode PTCO. The pattern of the opening OP is provided on the inner side of the pattern of the pixel electrode PTCO. It should be noted that the area where the opening OP is provided is equivalent to the opening portion of the pixel. That is, the opening ZCON (first contact area CON1) is included in the opening portion of the pixel. It should be noted that the opening portion of the pixel refers to an area where the user can visually recognize the light from the pixel. For example, an area that is shielded by a metal layer and the user cannot visually recognize the light is not included in the opening portion of the pixel. That is, the opening portion of the above-mentioned pixel is sometimes referred to as a "light-transmitting area". In addition, the area of ​​the common auxiliary electrode CMTL extending along the D1 direction overlaps with the opening PCON. In the display area 122, the common auxiliary electrode CMTL also functions as a black matrix. It should be noted that the common auxiliary electrode CMTL and the common electrode CTCO are also provided in the opening portion PCON. Although in Figure 4 In the above description, the case where the common electrode CTCO is disposed on the common auxiliary electrode CMTL is described, but the common auxiliary electrode CMTL may also be disposed on the common electrode CTCO. Figure 4 As shown, the pixel electrode PTCO overlaps with the common electrode CTCO via the fourth insulating layer IL4. The region where the pixel electrode PTCO overlaps with the common electrode CTCO via the fourth insulating layer IL4 functions as a storage capacitor.

[0108] A spacer SP is provided on the common electrode CTCO so as to fill the opening PCON. The spacer SP protrudes toward the counter substrate SUB2. Due to the spacer SP, the spacer SP of the liquid crystal layer LC is provided not only in the display region 122 but also in the peripheral region 121. In the display region 122 and the peripheral region 121, an alignment film OF1 is provided on the third insulating layer IL3, the common electrode CTCO, and the spacer SP.

[0109] In the peripheral region 121, a black matrix BM is provided on the counter substrate SUB2. A cover layer OC is provided in the peripheral region 121 and the display region 122. An alignment film OF2 is provided in a manner covering the cover layer OC. The substrate SUB1 and the counter substrate SUB2 are configured such that the alignment film OF1 faces the alignment film OF2 and are bonded together by a sealing portion 200 provided in the peripheral region 121. The liquid crystal layer LC is provided in the region surrounded by the sealing portion 200.

[0110] <5. Method for Manufacturing Display Device 10>

[0111] A method for manufacturing the display device 10 according to one embodiment of the present invention will be described. Figure 7 and Figure 8 It is a sequence diagram for explaining a method for manufacturing the display device 10 according to one embodiment of the present invention. Figures 9 to 17 It is a cross-sectional view for explaining a method for manufacturing the display device 10 according to one embodiment of the present invention.

[0112] First, a first insulating layer IL1, a semiconductor region S, and a second gate insulating layer GI2 are formed on a substrate SUB1 (see Figure 7 Step S1001 and Fig. 9 ).

[0113] As the substrate SUB1, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate is used. When the substrate SUB1 needs to be flexible, a substrate containing organic resin such as a polyimide substrate, an acrylic resin substrate, a siloxane substrate, a fluororesin substrate or the like can be used as the substrate SUB1. When a substrate containing organic resin is used as the substrate SUB1, in order to improve the heat resistance of the substrate SUB1, impurity elements may be introduced into the organic resin.

[0114] The first insulating layer IL1 is formed by a CVD (Chemical Vapor Deposition) method or a sputtering method. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), Silicon Nitride (SiN x), silicon oxide nitride (SiN x O y ) and other inorganic insulating materials. The above-mentioned SiO x N y It is a silicon compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). SiN x O y It is a silicon compound containing oxygen at a ratio smaller than nitrogen (x>y). The first insulating layer IL1 may have a single-layer structure using the above-mentioned inorganic insulating material or a stacked structure.

[0115] In addition, polysilicon can be used as the semiconductor region S. In addition, as the second gate insulating layer GI2, the same film formation method and inorganic insulating material as those of the first insulating layer IL1 are used.

[0116] Next, a light shielding layer LS is formed on the gate insulating layer GI2 (see Figure 7 Step S1002 and Fig. 9 ).

[0117] The light shielding layer LS is formed by processing a conductive layer formed by sputtering, for example. As the light shielding layer LS, a general metal material can be used. As the light shielding layer LS, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used. In addition, the light shielding layer LS can be a single-layer structure using the above-mentioned materials or a stacked structure.

[0118] Next, a second insulating layer IL2 is formed on the light shielding layer LS (see Figure 7 Step S1003 and Fig. 9 ) As the second insulating layer IL2, the same film forming method and inorganic insulating material as those of the first insulating layer IL1 are used.

[0119] In addition, the second insulating layer IL2 may be a single-layer structure using the above-mentioned inorganic insulating material, or may be a stacked structure. In the case where the second insulating layer IL2 is set to a stacked structure, it is preferred to sequentially form a nitrogen-containing insulating material and an oxygen-containing insulating material starting from the substrate SUB1. By using a nitrogen-containing insulating material, for example, it is possible to block impurities that diffuse from the substrate SUB1 side to the oxide semiconductor layer POS. In addition, by using an oxygen-containing insulating material, oxygen can be released by heat treatment. The temperature of the heat treatment at which the oxygen-containing insulating material releases oxygen is, for example, below 600°C, below 500°C, below 450°C or below 400°C. That is, the oxygen-containing insulating material releases oxygen at a heat treatment temperature performed in a manufacturing process of a display device when, for example, a glass substrate is used as the substrate SUB1. In this embodiment, as a nitrogen-containing insulating material, for example, silicon nitride is formed. In addition, as an oxygen-containing insulating material, for example, silicon oxide is formed.

[0120] Next, a metal oxide layer MO1 (see FIG. 1 ) mainly composed of aluminum is formed on the second insulating layer IL2. Figure 7 Step S1004 and Fig.10 ).

[0121] The metal oxide layer MO1 is formed by sputtering. The metal oxide layer MO1 mainly composed of aluminum is formed by, for example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating materials. The above-mentioned AlO x N y It is an aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). AlN x O y It is an aluminum compound containing oxygen at a ratio less than nitrogen (x>y).

[0122] “A metal oxide layer mainly composed of aluminum” means that the ratio of aluminum contained in the metal oxide layer MO1 is greater than 1% of the entire metal oxide layer MO1. The ratio of aluminum contained in the metal oxide layer MO1 may be greater than 5% and less than 70%, greater than 10% and less than 60%, or greater than 30% and less than 50% of the entire metal oxide layer MO1. The above ratio may be a mass ratio or a weight ratio.

[0123] The thickness of the metal oxide layer MO1 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In the present embodiment, aluminum oxide is used as the metal oxide layer MO1. Aluminum oxide has a high barrier property against gases.

[0124] Next, an amorphous oxide semiconductor layer AOS is formed on the metal oxide layer MO1 (see Figure 7 Step S1005 and Fig.10 ).

[0125] The oxide semiconductor layer AOS is formed by sputtering or atomic layer deposition (ALD) and has a thickness of, for example, 5 nm to 50 nm, preferably 10 nm to 40 nm, and more preferably 10 nm to 30 nm.

[0126] As the oxide semiconductor layer AOS, a metal oxide having semiconductor properties can be used. As the oxide semiconductor layer AOS, for example, an oxide semiconductor containing two or more metals including indium (In) is used. In addition, the ratio of indium in the two or more metals is 50% or more. As the oxide semiconductor layer AOS, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr) or lanthanide elements can be used. As the oxide semiconductor layer AOS, other elements other than the above can also be used. In this embodiment, a metal oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer AOS.

[0127] In the case where the oxide semiconductor layer AOS is crystallized by the OS annealing treatment described later, it is preferred that the oxide semiconductor layer AOS after film formation and before the OS annealing treatment is amorphous (a state where the oxide semiconductor has a small amount of crystalline components). That is, the film formation method of the oxide semiconductor layer AOS is preferably a condition in which the oxide semiconductor layer AOS is not crystallized as much as possible just after film formation. For example, in the case of forming the oxide semiconductor layer AOS by sputtering, the oxide semiconductor layer AOS is formed while controlling the temperature of the film-forming object (substrate SUB1 and the structure formed thereon).

[0128] If a film is formed on a film-forming object by sputtering, the ions generated in the plasma and the atoms rebounded by the sputtering target collide with the film-forming object, so the temperature of the film-forming object rises as the film-forming process proceeds. If the temperature of the film-forming object rises during the film-forming process, the oxide semiconductor layer AOS contains microcrystals in the state just after the film is formed, which will hinder the crystallization based on the subsequent OS annealing process. As described above, in order to control the temperature of the film-forming object, for example, the film can be formed while the film is cooled. For example, the film-forming object is cooled from the surface opposite to the film-forming surface in such a manner that the temperature of the film-forming surface of the film-forming object (hereinafter referred to as the "film-forming temperature") is below 100°C, below 70°C, below 50°C or below 30°C. As described above, by forming the oxide semiconductor layer AOS while cooling the film-forming object, an oxide semiconductor layer AOS with a small amount of crystalline components in the state just after the film is formed can be formed.

[0129] Next, a pattern of the oxide semiconductor layer AOS is formed (see Figure 7 Although not shown in the figure, a resist mask is formed on the oxide semiconductor layer AOS, and the oxide semiconductor layer AOS is etched using the resist mask. As the etching of the oxide semiconductor layer AOS, wet etching can be used, or dry etching can be used. As wet etching, etching can also be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0130] The oxide semiconductor layer AOS is preferably patterned before the OS annealing treatment. If the oxide semiconductor layer AOS is crystallized by the OS annealing treatment, it tends to be difficult to etch. In addition, even if damage is caused in the oxide semiconductor layer AOS due to etching, the damage can be repaired by the OS annealing treatment, so it is preferred.

[0131] After the patterning of the oxide semiconductor layer AOS, the oxide semiconductor layer AOS is subjected to a heat treatment (OS annealing treatment) (see Figure 7 Step S1007 and Fig.11 ). In the OS annealing treatment, the oxide semiconductor layer AOS is maintained at a predetermined reaching temperature for a predetermined time. The predetermined reaching temperature is 300° C. to 500° C., preferably 350° C. to 450° C. In addition, the holding time at the reaching temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. By performing the OS annealing treatment, the oxide semiconductor layer AOS is crystallized to form an oxide semiconductor layer POS having a polycrystalline structure.

[0132] Next, the oxide semiconductor layer POS is used as a mask to form a pattern of the metal oxide layer MO1 (see Figure 7 Step S1008 and Fig.12 ). The metal oxide layer MO1 is etched using the crystallized oxide semiconductor layer POS as a mask. As the etching of the metal oxide layer MO1, wet etching or dry etching can be used. As the wet etching, for example, diluted hydrofluoric acid (DHF) is used. Compared with the amorphous oxide semiconductor layer AOS, the crystallized oxide semiconductor layer POS is resistant to etching by diluted hydrofluoric acid. Therefore, the metal oxide layer MO1 can be etched using the oxide semiconductor layer POS as a mask. As a result, the photolithography process can be omitted.

[0133] Next, a first gate insulating layer GI1 is formed on the oxide semiconductor layer POS (see Figure 7 Step S1009 and Fig.13 ).

[0134] The film forming method and insulating material of the first gate insulating layer GI1 may refer to the description of the second insulating layer IL2. The first gate insulating layer GI1 has a thickness of, for example, 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm.

[0135] As the first gate insulating layer GI1, an insulating material containing oxygen is preferably used. In addition, as the first gate insulating layer GI1, an insulating layer with fewer defects is preferably used. For example, when comparing the composition ratio of oxygen in the first gate insulating layer GI1 with the composition ratio of oxygen in an insulating layer having the same composition as the second gate insulating layer GI2 (hereinafter referred to as "the other insulating layer"), the composition ratio of oxygen in the first gate insulating layer GI1 is closer to the stoichiometric ratio relative to the insulating layer than the composition ratio of oxygen in the other insulating layer. For example, in the case where silicon oxide (SiO x ), the oxygen composition ratio of silicon oxide used as the first gate insulating layer GI1 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio of silicon oxide used as the second gate insulating layer GI2. For example, a layer in which no defects are observed when evaluated by the electron spin resonance method (ESR) may be used as the first gate insulating layer GI1.

[0136] In order to form an insulating layer with few defects as the first gate insulating layer GI1, the first gate insulating layer GI1 may be formed at a film forming temperature of 350° C. or higher. In addition, after the first gate insulating layer GI1 is formed, a process of injecting oxygen into a portion of the first gate insulating layer GI1 may be performed. In the present embodiment, in order to form an insulating layer with few defects as the first gate insulating layer GI1, silicon oxide is formed at a film forming temperature of 350° C. or higher.

[0137] Next, a metal oxide layer MO2 having aluminum as a main component is formed on the first gate insulating layer GI1 (see Figure 7 Step S1010 and Fig.13 ).

[0138] The film forming method and insulating material of the metal oxide layer MO2 may refer to the description of the metal oxide layer MO1. Oxygen is injected into the first gate insulating layer GI1 by forming the metal oxide layer MO2. The film thickness of the metal oxide layer MO2 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In the present embodiment, aluminum oxide is used as the metal oxide layer MO2. Aluminum oxide has a high barrier property to gases. In the present embodiment, aluminum oxide used as the metal oxide layer MO2 suppresses the outward diffusion of oxygen injected into the first gate insulating layer GI1 when the metal oxide layer MO2 is formed.

[0139] For example, when the metal oxide layer MO2 is formed by sputtering, the process gas used in sputtering may remain in the film of the first gate insulating layer GI1. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the first gate insulating layer GI1. The remaining Ar may be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the first gate insulating layer GI1.

[0140] A first gate insulating layer GI1 is formed on the oxide semiconductor layer POS, and a heat treatment (oxidation annealing treatment) is performed to supply oxygen to the oxide semiconductor layer POS while the metal oxide layer MO2 is formed on the first gate insulating layer GI1 (see Figure 7 Step S1011 shown).

[0141] In the process from the formation of the oxide semiconductor layer POS to the formation of the first gate insulating layer GI1 on the oxide semiconductor layer POS, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer POS. Therefore, the oxygen defects formed near the upper surface of the oxide semiconductor layer POS are more than the oxygen defects formed near the lower surface of the oxide semiconductor layer POS. That is, the oxygen defects in the oxide semiconductor layer POS are not uniformly present in the thickness direction of the oxide semiconductor layer POS, but are unevenly distributed in the thickness direction of the oxide semiconductor layer POS. Specifically, the oxygen defects in the oxide semiconductor layer POS are less as they are closer to the lower surface side of the oxide semiconductor layer POS, and more as they are closer to the upper surface side of the oxide semiconductor layer POS.

[0142] In the case where the oxide semiconductor layer POS having the above-mentioned oxygen defect distribution is uniformly subjected to oxygen supply treatment, if the amount of oxygen required to repair the oxygen defects formed on the upper surface side of the oxide semiconductor layer POS is supplied, oxygen is excessively supplied to the lower surface side of the oxide semiconductor layer POS. As a result, on the lower surface side, defect energy levels different from those of the oxygen defects are formed due to the excess oxygen. As a result, phenomena such as characteristic changes in reliability tests or reductions in field effect mobility occur. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface side of the oxide semiconductor layer POS while suppressing the oxygen supply to the lower surface side of the oxide semiconductor layer POS.

[0143] In a state where a metal oxide layer MO1 is provided below the oxide semiconductor layer POS and a metal oxide layer MO2 is provided above the oxide semiconductor layer POS, oxidation annealing is performed. Thus, in the above oxidation annealing process, since the oxygen injected into the first gate insulating layer GI1 is blocked by the metal oxide layer MO2, its release into the atmosphere is suppressed. In addition, the oxygen released from the second insulating layer IL2 is supplied to the upper surface and side surfaces of the oxide semiconductor layer POS. In addition, the metal oxide layer MO1 can suppress the excessive supply of oxygen to the bottom of the oxide semiconductor layer POS. Thus, the oxygen is efficiently supplied to the oxide semiconductor layer POS, and oxygen defects can be repaired.

[0144] Next, after the oxidation annealing treatment, the metal oxide layer MO2 is etched (removed) (see Figure 7 Step S1012 and Fig.14 ). As the etching of the metal oxide layer MO2, wet etching or dry etching can be used. As wet etching, for example, diluted hydrofluoric acid (DHF) is used. By this etching, the metal oxide layer MO2 formed on the entire surface is removed. In other words, the removal of the metal oxide layer MO2 is performed without using a mask. In other words, by this etching, at least the entire metal oxide layer MO2 in the area overlapping with the oxide semiconductor layer POS formed into a certain pattern when viewed from above is removed.

[0145] Next, a gate wiring GL1 (see Figure 7 Step S1013 and Fig.15 ) The film forming method and conductive material of the gate wiring GL may refer to the description of the light shielding layer LS.

[0146] Next, impurities are added to the oxide semiconductor layer POS using the gate wiring GL1 as a mask (see Figure 7 Step S1014 and Fig.15) In this embodiment, the case where impurities are added by ion implantation is described, but it may also be done by an ion doping method.

[0147] Specifically, by ion implantation, an impurity element is added from the first gate insulating layer GI1 to the oxide semiconductor layer POS, thereby forming a low resistance region OS2. In addition, in the oxide semiconductor layer POS, the region overlapping with the gate wiring GL1 becomes the channel region OS1. As the impurity element, argon (Ar), phosphorus (P) or boron (B) can be used, for example. In addition, when boron (B) is added by ion implantation, the acceleration energy is set to 20 keV or more and 40 keV or less, and the implantation amount of boron (B) is set to 1×10 14 cm -2 Above 1×10 16 cm -2 The following will do.

[0148] The concentration of the impurity element contained in the low resistance region OS2 is preferably 1×10 18 cm -3 Above 1×10 21 cm -3 In addition, the low resistance region OS2 contains 1×10 18 cm -3 Above 1×10 21 cm -3 In the following cases, it can be presumed that the impurity element is intentionally added by an ion implantation method or a doping method.

[0149] By ion implanting impurity elements into the oxide semiconductor layer POS, oxygen defects are formed in the low resistance region OS2, and defects are also formed in the metal oxide layer MO1 and the second insulating layer IL2 arranged below the low resistance region OS2. In the subsequent process, hydrogen is supplied to the oxygen defects, thereby further reducing the resistance of the low resistance region OS2. As a method of supplying hydrogen to the oxygen defects, for example, a method of using a silicon nitride layer as a passivation layer can be cited. Since the silicon nitride layer contains a large amount of hydrogen during film formation, the low resistance region OS2 can be further reduced in resistance by allowing the hydrogen contained in the silicon nitride layer to be captured by the oxygen defects in the low resistance region OS2. In addition, by allowing hydrogen to be captured by defects formed in the metal oxide layer MO1 and the second insulating layer IL2 by ion implantation, the supply of hydrogen to the channel region OS1 in a manner exceeding the necessary limit is suppressed. However, if a large amount of hydrogen is diffused during film formation of the silicon nitride layer, hydrogen cannot be completely captured in the oxygen defects in the low resistance region OS2 and the defects in the metal oxide layer MO1 and the second insulating layer IL2. When an excessive amount of hydrogen is supplied to the oxygen vacancies in the low-resistance region OS2 , hydrogen is supplied from the low-resistance region OS2 to the channel region OS1 , causing depletion of the transistor.

[0150] In order to prevent excessive supply of hydrogen to the low resistance region OS2, silicon oxide may be used in combination as a passivation layer, but when the silicon oxide is formed, film formation waste (particles) is sometimes generated due to the reaction gas. Since it is difficult to remove the film formation waste, it becomes an obstacle to the subsequent manufacturing process, so it is not desirable to use thick silicon oxide as a passivation layer.

[0151] Therefore, in this embodiment, a silicon nitride layer is used as the passivation layer PAS1 to PAS3 formed on the gate wiring GL1, and the silicon nitride layer is formed at 150° C. to 250° C. As a result, a large amount of hydrogen diffusion is suppressed during the formation of the silicon nitride layer, and excessive supply of hydrogen to the low resistance region OS2 is suppressed. As a result, depletion of the transistor Tr1 can be suppressed. The following is a detailed description of the film formation method of the passivation layers PAS1 to PAS3.

[0152] Next, a passivation layer PAS1 is formed on the first gate insulating layer GI1 and the gate wiring GL1 (see Figure 8 Step S1015 and Fig.16). The passivation layer PAS1 is formed using a silicon nitride layer. The film thickness of the passivation layer PAS1 is greater than 200nm and less than 600nm. In addition, the film thickness of the passivation layer PAS1 is preferably thicker than the film thickness of the passivation layers PAS2 and PAS3. In this way, the parasitic capacitance generated in the wiring W3 can be reduced. The raw material gas during the formation of the silicon nitride layer contains a large amount of hydrogen. Therefore, when the film formation temperature exceeds 250°C, hydrogen diffuses and invades the oxide semiconductor layer POS. Therefore, when forming a silicon nitride layer as the passivation layer PAS1, it is preferably formed at a film formation temperature of greater than 150°C and less than 250°C.

[0153] Next, an opening SCON1 is formed in the passivation layer PAS1 to reach the low resistance region OS2. Then, a wiring W3 is formed on the passivation layer PAS1, and the wiring W3 is connected to the low resistance region OS2 via the opening SCON1 (see FIG. 1 ). Figure 8 Step S1016 and Fig.16 ). The film forming method and conductive material of the wiring W3 refer to the description of the light shielding layer LS. The film forming temperature of the wiring W3 is preferably a temperature not exceeding the film forming temperature of the passivation layer PAS1. This is because when the film is formed at a temperature significantly exceeding the film forming temperature of the wiring W3, hydrogen is released from the passivation layer PAS1 and diffuses into the channel area OS1. In this way, the film forming temperature of the wiring, electrode, and insulating layer formed on the passivation layer PAS1 is preferably not higher than the film forming temperature of the passivation layer PAS1.

[0154] Next, a passivation layer PAS2 is formed on the passivation layer PAS1 and the wiring W3 (see Figure 8 Step S1017 and Fig.16 ). The passivation layer PAS2 is formed using a silicon nitride layer. The film thickness of the passivation layer PAS2 is not less than 50nm and not more than 350nm. Similar to the passivation layer PAS1, the silicon nitride layer of the passivation layer PAS2 is also preferably formed under the condition of a film forming temperature of not less than 150°C and not more than 250°C. Thus, when the passivation layer PAS2 is formed, the diffusion of hydrogen contained in the raw material gas can be suppressed, and the diffusion of hydrogen contained in the silicon nitride layer of the passivation layer PAS1 can be suppressed.

[0155] Next, an opening ZCON is formed in the passivation layer PAS2 to reach the low resistance region OS2. Then, a connection electrode ZTCO is formed on the passivation layer PAS2, and the connection electrode ZTCO is connected to the low resistance region OS2 via the opening ZCON (see FIG. 1 ). Figure 8 Step S1018 and Fig.16 ).

[0156] The connecting electrode ZTCO is formed by processing a translucent oxide conductive layer formed by sputtering. As the connecting electrode ZTCO, a transparent conductive material such as a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO) can be used. As the connecting electrode ZTCO, other transparent conductive materials other than the above can also be used.

[0157] Next, a passivation layer PAS3 is formed using a silicon nitride layer in contact with the connection electrode ZTCO (see Figure 8 Step S1019 and Fig.17 ). The passivation layer PAS3 is formed using a silicon nitride layer. The film thickness of the passivation layer PAS3 is not less than 50nm and not more than 300nm. Similar to the passivation layer PAS1, the silicon nitride layer of the passivation layer PAS3 is also preferably formed under the condition of a film forming temperature of not less than 150°C and not more than 250°C. Thus, when the passivation layer PAS3 is formed, the diffusion of hydrogen contained in the raw material gas can be suppressed, and the diffusion of hydrogen contained in the silicon nitride layers of the passivation layers PAS1 and PAS2 can be suppressed.

[0158] In addition, by forming a silicon nitride layer as the passivation layer PAS3 at a temperature of 150° C. to 250° C., it is possible to suppress the connection electrode ZTCO from being reduced during film formation. This can suppress the generation of unevenness on the surface of the connection electrode ZTCO. It is possible to suppress the short circuit of the connection electrode ZTCO and the reduction of light transmittance caused by the unevenness generated on the surface of the connection electrode ZTCO.

[0159] As described above, in the present embodiment, a silicon nitride layer is used as the passivation layer PAS1 to PAS3 formed on the gate wiring GL1, and the film forming temperature of the silicon nitride layer is set to be above 150°C and below 250°C. Thus, it is possible to suppress the excessive diffusion of hydrogen during the film forming of the passivation layers PAS1 to PAS3, so that hydrogen can be appropriately supplied to the low resistance region OS2. In addition, as the passivation layers PAS1 to PAS3, since silicon oxide is not used, the influence of film forming garbage can be reduced. In addition, as the passivation layers PAS1 to PAS3, since they are formed only by the silicon nitride layer, the adhesion between the passivation layers PAS1 to PAS3 can be improved. In addition, by forming the silicon nitride layer as the passivation layer PAS1 to PAS3 at a temperature above 150°C and below 250°C, the generation of compressive stress of the silicon nitride layer can be suppressed. Thus, it is possible to suppress the film peeling of the silicon nitride layer and the connecting electrode ZTCO and the warping of the substrate SUB1.

[0160] Next, a color filter CF is formed on the passivation layer PAS3 (see Figure 8 Step S1020 and Figure 4 In the present embodiment, the color filters CF include red, green, and blue. The color filters CF of each color are arranged along the second direction D2.

[0161] Next, a third insulating layer IL3 is formed on the color filter CF (see Figure 8 Step S1021 and Figure 4 The third insulating layer IL3 is formed using an organic resin material. By forming the third insulating layer IL3 on the color filter CF, it is possible to reduce unevenness caused by the color filter CF and the transistor Tr1 formed thereunder.

[0162] In a high-definition display device, it becomes difficult to align the color filter formed on the opposing substrate with the pixel circuit of the array substrate, so it is preferred to set the color filter on the array substrate side. In addition, in order to make the surface of the liquid crystal drive flat, a flattening film is set on the color filter. The color filter and the flattening film are made of organic insulating materials, but the organic insulating material contains a large amount of water. When this large amount of water invades the oxide semiconductor layer, it has a greater impact on the operation of the transistor, so it is necessary to suppress the intrusion of water into the oxide semiconductor layer.

[0163] In this embodiment, silicon nitride layers formed at 150° C. to 250° C. are used as the passivation layers PAS1 to PAS3 . The silicon nitride layers can suppress moisture contained in the color filter CF and the third insulating layer IL3 from entering the oxide semiconductor layer POS.

[0164] Next, an opening PCON that reaches the connection electrode ZTCO is formed in the third insulating layer IL3 and the color filter CF. Then, a pixel electrode PTCO is formed on the third insulating layer IL3, and the pixel electrode PTCO is connected to the connection electrode ZTCO via the opening PCON (see FIG. 1 ). Figure 8 Step S1022 and Figure 4 The pixel electrode PTCO is formed by using the inorganic insulating material and the film forming method described in the connection electrode ZTCO.

[0165] Next, a fourth insulating layer IL4 is formed on the third insulating layer IL3 and the pixel electrode PTCO (see Figure 8 Step S1023 and Figure 4 The fourth insulating layer IL4 is formed by using the inorganic insulating material and the film forming method described in the first insulating layer IL1. Since the fourth insulating layer IL4 functions as a capacitor of the capacitor 168, it is preferably formed using, for example, a silicon nitride layer.

[0166] Next, a common auxiliary electrode CMTL is formed on the fourth insulating layer IL4 (see Figure 8 Step S1024 and Figure 4The film forming method and conductive material of the common auxiliary electrode CMTL may refer to the description of the light shielding layer LS. After forming a conductive film on the fourth insulating layer IL4, the conductive film is processed in a manner to cover the gate wiring GL1 and the wiring W3, so that the common auxiliary electrode CMTL arranged in a grid shape can be formed.

[0167] Next, a common electrode CTCO is formed on the common auxiliary electrode CMTL (see Figure 8 Step S1025 and Figure 4 ). The film forming method and transparent conductive material of the common electrode CTCO can refer to the description of the connecting electrode ZTCO. After forming a transparent conductive film on the fourth insulating layer IL4 and the common auxiliary electrode CMTL, the common electrode CTCO configured in a grid shape can be formed by processing the transparent conductive film in a manner overlapping with the common auxiliary electrode CMTL. The common electrode CTCO and the common auxiliary electrode CMTL function as a common wiring. The common electrode CTCO is formed of a transparent conductive material, so the resistance is high, but by setting the common auxiliary electrode CMTL to be grounded, the resistance can be reduced. In addition, the common auxiliary electrode CMTL also functions as a black matrix by having a light-shielding property.

[0168] Next, a spacer SP is formed in the opening PCON (see Figure 8 Step S1026 and Figure 4 ). The spacer SP is formed using an organic resin so that the organic resin protrudes from the surface of the substrate. The spacer SP may not be formed in all the openings PCON. When the spacer SP is not formed, the organic resin may be embedded only in the openings PCON so that the organic resin does not protrude from the surface.

[0169] Next, an alignment film OF1 is formed on the substrate SUB1, a sealant 200 is applied to surround the display region 122, and liquid crystal is dropped. The counter substrate SUB2 on which a black matrix BM is formed is bonded to the substrate SUB1 to face each other, and the sealant 200 is cured. The display device 10 can be manufactured through the above steps.

[0170] In the present embodiment, a silicon nitride layer is used as the passivation layer PAS1 to PAS3 formed on the gate wiring GL1. Therefore, the passivation layer PAS2 is connected to the passivation layer PAS1 and the passivation layer PAS3. The wiring W3 is sandwiched between the passivation layer PAS1 and the passivation layer PAS2, and the connecting electrode ZTCO is sandwiched between the passivation layer PAS2 and the passivation layer PAS3. As a result, the adhesion of the passivation layers PAS1 to PAS3 is improved. In addition, the passivation layers PAS1 to PAS3 are formed at a low temperature of more than 150°C and less than 250°C. As a result, the hydrogen contained in the raw material gas and the hydrogen contained in the silicon nitride layer can be prevented from diffusing due to the heat applied when the passivation layers PAS1 to PAS3 are formed. In addition, since silicon oxide is not used as the passivation layers PAS1 to PAS3, film formation garbage during film formation can be suppressed.

[0171] <6. Crystal Structure of Oxide Semiconductor Layer>

[0172] The oxide semiconductor layer POS described in this embodiment includes Poly-OS. The crystal grain size of the crystal grains included in the Poly-OS observed from the upper surface of the oxide semiconductor layer POS (or the film thickness direction of the oxide semiconductor layer POS) is 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size of the crystal grain is obtained, for example, by cross-sectional SEM observation, cross-sectional TEM observation, or electron backscattered diffraction (EBSD) method.

[0173] In Poly-OS, a plurality of crystal grains may have one crystal structure or multiple crystal structures. The crystal structure of Poly-OS may be determined using electron beam diffraction or XRD. That is, the crystal structure of the oxide semiconductor layer POS may be determined using electron beam diffraction or XRD.

[0174] The crystal structure of the oxide semiconductor layer POS is preferably cubic. The symmetry of the cubic crystal structure is high, and even if oxygen defects are generated in the oxide semiconductor layer POS, it is not easy to cause structural relaxation, and the crystal structure is stable. As described above, by increasing the ratio of indium, the crystal structure of each of the plurality of crystal grains can be controlled to form an oxide semiconductor layer POS having a cubic crystal structure.

[0175] In the transistor Tr1 including the oxide semiconductor layer POS manufactured by the above manufacturing method, even if the channel length L of the channel region OS1 is set to 0.5 μm or more and 2.0 μm or less, good transistor characteristics can be obtained. Since a miniaturized transistor can be formed, the pixel circuit can also be miniaturized. Thus, a high-definition display device 10 can be provided.

[0176] In the transistor Tr including the oxide semiconductor layer POS manufactured by the above manufacturing method, when the channel length L of the channel region OS1 is in the range of 0.5 μm to 2 μm and the channel width of the channel region OS1 is in the range of 1 μm to 25 μm, a mobility of 50 cm 2 / Vs or above, 55cm 2 / Vs or above or 60cm 2 / Vs or above. The mobility in this embodiment refers to the field effect mobility in the saturation region of the transistor, and refers to the maximum value of the field effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the transistor from the voltage supplied to the gate electrode (Vg).

[0177] <7. Modification 1>

[0178] Next, refer to Figure 18 to Figure 21 Modification 1 of the display device 10 is described. In this embodiment, a configuration using only silicon nitride layers without using silicon oxide as the passivation layers PAS1 to PAS3 is described. In this modification, a case where a silicon oxide layer SO is formed on the passivation layer PAS1 is described.

[0179] Fig.18 This is a cross-sectional view schematically showing a display device 10A according to one embodiment of the present invention. Fig.18 The display device 10A shown in FIG. Figure 4 The configuration of the display device 10 shown is different in that a silicon oxide layer SO is provided between the passivation layer PAS1 and the wiring W3.

[0180] Fig.19 FIG. 1 is a flowchart for explaining a method for manufacturing a display device 10A according to an embodiment of the present invention. Figure 7 and Figure 8 The sequence diagram shown is different from step S1027 and step S1016.

[0181] A silicon oxide layer SO is formed on the passivation layer PAS1 (see Fig.19 Step S1027 and Fig. 20 ). As described above, since film formation waste is generated when the silicon oxide layer is formed, the film thickness T1 of the silicon oxide layer SO is preferably smaller than the film thickness of the passivation layers PAS1 to PAS3, and is preferably formed at a thickness of 10 nm to 50 nm, or 10 nm to 30 nm. Thus, the generation of film formation waste during film formation can be suppressed. In addition, by also setting the temperature for forming the silicon oxide layer SO to be 150° C. to 250° C., the diffusion of hydrogen contained in the passivation layer PAS1 can be suppressed.

[0182] Next, an opening SCON1 is formed in the passivation layer PAS1 to reach the low resistance region OS2. Then, a wiring W3 is formed on the passivation layer PAS1, and the wiring W3 is connected to the low resistance region OS2 via the opening SCON1 (see FIG. 1 ). Figure 8 Step S1016 and Fig.21 ). The film forming method and conductive material of the wiring W3 can refer to the description of the light shielding layer LS. The wiring W3 can be formed by processing a conductive film, but when processing the conductive film, the passivation layer PAS1 may also be etched. By forming a thin silicon oxide layer SO on the passivation layer PAS1, the silicon oxide layer SO can function as an etching stop layer.

[0183] In this modification, the silicon oxide layer SO exposed from the wiring W3 is completely removed by etching. Fig.21 As shown in FIG. 1 , a silicon oxide layer SO is provided between the passivation layer PAS1 and the wiring W3. Since the silicon oxide layer SO is masked by the wiring W3, the film thickness at the time of film formation is maintained. Fig.21 The film thickness T1 of the silicon oxide layer SO shown is 10 nm to 50 nm, or 10 nm to 30 nm. Then, a silicon nitride layer is formed on the passivation layer PAS1 as the passivation layer PAS2, thereby improving the adhesion between the passivation layer PAS1 and the passivation layer PAS2. Therefore, in this modification, in addition to being able to obtain Figure 7-Figure 8 In addition to the effects described in the manufacturing process, it is also possible to suppress the passivation layer PAS1 from being etched more than necessary when processing the wiring W3.

[0184] <8. Modification 2>

[0185] Next, refer to Fig. 22 and Fig.23 A second variation of the display device 10 is described. In the first variation, a case where the silicon oxide layer SO is formed on the passivation layer PAS1 and then the silicon oxide layer SO exposed from the wiring W3 when the wiring W3 is formed is completely removed. In this variation, a case where the wiring W3 is processed in such a way that the silicon oxide layer SO remains is described. Therefore, the sequence diagram for describing the manufacturing method of the display device 10B is the same as that of the first variation. Fig.19 About the same.

[0186] Fig. 22 1 is a cross-sectional view showing an overview of a display device 10B according to an embodiment of the present invention. In this variation, a silicon oxide layer SO is provided between the passivation layer PAS1 and the passivation layer PAS2. In the silicon oxide layer SO, a thickness T1 of a first region overlapping with the wiring W3 is greater than a thickness T2 of a second region not overlapping with the wiring W3.

[0187] In this modification, Fig.19 In the sequence diagram shown, the step S1016 is different from that of Modification 1. The silicon oxide layer SO is formed with a film thickness of 10 nm to 50 nm, preferably 10 nm to 30 nm, so the film thickness T1 is the film thickness of the silicon oxide layer SO after the film formation. On the other hand, the area exposed from the wiring W3 is removed by etching, so the film thickness T2 is smaller than the film thickness T1. The film thickness T2 may be greater than 0 nm and less than 10 nm. The conductive film is etched so that the silicon oxide layer SO remains to form the wiring W3.

[0188] By providing a thinner silicon oxide layer SO between the passivation layer PAS1 and the passivation layer PAS2, the diffusion of hydrogen contained in the layer above the passivation layer PAS2 can be suppressed. In addition, since the thickness of the silicon oxide layer SO is smaller than the thickness of the passivation layers PAS1 to PAS3, the influence of film formation garbage during film formation can also be reduced.

[0189] <9. Modification 3>

[0190] Next, refer to Fig.24 and Fig.25 A description will be given of a third modification of the display device 10. In this modification, a manufacturing method that is partially different from the manufacturing method of the display device 10 will be described.

[0191] Fig.24 1 is a cross-sectional view showing an overview of a display device 10C according to an embodiment of the present invention. Fig.24 As shown, the structure of transistor Tr1 is similar to Figure 4 The transistor Tr1 shown in FIG. 1 is constructed differently. Fig.24 , the metal oxide layer MO1 formed under the oxide semiconductor layer POS is omitted.

[0192] Fig.25 This is a sequence diagram for explaining a method for manufacturing the display device 10C according to one embodiment of the present invention. Fig.25 The sequence diagram shown is similar to Figure 7 The sequence diagram shown is partially different. Fig.25 As shown in FIG. 1 , the step of forming the metal oxide layer MO1 formed on the second insulating layer IL2 is omitted ( Figure 7 Step S1004) and the process of patterning the metal oxide layer MO1 ( Figure 7 Step S1008 shown). It should be noted that, Fig.25 The steps after step S1014 are shown in FIG. Figure 8The steps shown are the same, so detailed description is omitted. In this modification, the metal oxide layer MO1 is omitted, but the first gate insulating layer GI1 is capped by the metal oxide layer MO2. As a result, through the subsequent oxidation annealing, the oxygen released from the second insulating layer IL2 and the first gate insulating layer GI1 is capped by the metal oxide layer MO2, and is thus supplied to the upper and lower surfaces of the oxide semiconductor layer POS, and the oxygen defects are repaired. Therefore, the oxygen defects in the oxide semiconductor layer POS can be efficiently supplied.

[0193] <10. Modification 4>

[0194] Next, refer to Fig.26 A fourth variation of the display device 10 will be described. In this variation, a manufacturing method that is partially different from the manufacturing method of the display device 10 will be described. It should be noted that the cross-sectional structure of the display device of this variation is different from that of the display device 10. Fig.24 The cross-sectional structure of the display device 10C shown is the same, and thus illustration is omitted.

[0195] Fig.26 It is a sequence diagram for explaining a method for manufacturing a display device according to one embodiment of the present invention. Fig.26 The sequence diagram shown is similar to Figure 7 The sequence diagram shown is partially different. Fig.26 As shown, the step of forming the metal oxide layer MO2 formed on the first gate insulating layer GI1 is omitted ( Figure 7 Step S1010) and the process of removing the metal oxide layer MO2 ( Figure 7 Step S1012 shown). It should be noted that, Fig.26 The steps after step S1014 are shown in FIG. Figure 8 The steps shown are the same, so detailed description is omitted. In this modification, the metal oxide layer MO2 is omitted, but the lower side of the oxide semiconductor layer POS is covered with the metal oxide layer MO1. As a result, through the subsequent oxidation annealing, the oxygen released from the second insulating layer IL2 is supplied to the upper and lower surfaces of the oxide semiconductor layer POS, and the oxygen defects are repaired. In addition, the oxygen released from the second insulating layer IL2 is blocked by the metal oxide layer MO1 and is suppressed from being supplied to the lower surface of the oxide semiconductor layer POS in large quantities, so that the formation of defect energy levels can be suppressed. Therefore, the oxygen defects in the oxide semiconductor layer POS can be efficiently supplied.

[0196] As described in Modifications 3 and 4, by performing annealing in a state where the metal oxide layer MO1 or the metal oxide layer MO2 is formed on at least one of the lower surface or the upper surface of the oxide semiconductor layer POS, oxygen can be supplied to oxygen vacancies in the oxide semiconductor layer POS.

[0197] In the manufacturing method of the display device 10 of the present modification example 3 and modification example 4, in the transistor Tr1 including the oxide semiconductor layer POS, even if the channel length L of the channel region OS1 is set to 0.5 μm or more and 2 μm or less, good transistor characteristics can be obtained. Since a miniaturized transistor can be formed, the pixel circuit can also be miniaturized. Thus, a high-definition display device 10 can be provided.

[0198] In the manufacturing method of the display device 10C of the present modification example 3 and modification example 4, a good oxide semiconductor layer POS having a polycrystalline structure can also be formed. In the transistor Tr including the oxide semiconductor layer POS manufactured in modification example 3 and modification example 4, a mobility of 30 cm-1 can be obtained when the channel length L of the channel region OS1 is in the range of 0.5 μm to 2 μm and the channel width of the channel region OS1 is in the range of 1 μm to 25 μm. 2 / Vs or above, 35cm 2 / Vs or above or 40cm 2 / Vs and above electrical characteristics.

[0199] As the embodiments of the present invention, the above-mentioned embodiments can be implemented in appropriate combination as long as they are not contradictory. In addition, the methods obtained by appropriately adding, deleting or changing the design of the components or adding, omitting or changing the conditions of the processes based on the semiconductor devices and display devices of the various embodiments by those skilled in the art are included in the scope of the present invention as long as they have the gist of the present invention.

[0200] Even if there are other effects different from the effects brought about by the above-mentioned embodiments, it should be understood that the effects brought about by the present invention are obvious from the description of this specification or can be easily predicted by those skilled in the art.

Claims

1. A display device comprising: an oxide semiconductor layer including a polycrystalline structure; a gate insulating layer disposed on the oxide semiconductor layer; a gate electrode on the gate insulating layer and facing the oxide semiconductor layer; a first silicon nitride layer disposed in contact with the gate electrode; a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer; a second silicon nitride layer disposed in contact with the source wiring and the first silicon nitride layer; a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, Wherein, the channel length of the gate electrode is less than 2.0 μm.

2. The display device according to claim 1, wherein: A silicon oxide layer is further provided between the source wiring and the first silicon nitride layer.

3. The display device according to claim 2, wherein: The silicon oxide layer has a thickness of not less than 10 nm and not more than 50 nm.

4. The display device according to claim 1, wherein: An aluminum oxide layer is further provided between the gate insulating layer and the oxide semiconductor layer.

5. The display device according to claim 1, wherein: The oxide semiconductor layer contains two or more metal elements including indium, and a ratio of indium in the two or more metal elements is 50% or more.

6. A display device comprising: an oxide semiconductor layer including a polycrystalline structure; a gate insulating layer disposed on the oxide semiconductor layer; a gate electrode on the gate insulating layer and facing the oxide semiconductor layer; a first silicon nitride layer disposed in contact with the gate electrode; a silicon oxide layer disposed in contact with the first silicon nitride layer; a source wiring disposed in contact with the silicon oxide layer and electrically connected to the oxide semiconductor layer; a second silicon nitride layer disposed in contact with the source wiring and the silicon oxide layer; a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, Wherein, the channel length of the gate electrode is less than 2.0 μm, The film thickness of the silicon oxide layer is smaller than each of the film thickness of the first silicon nitride layer, the film thickness of the second silicon nitride layer, and the film thickness of the third silicon nitride layer.

7. The display device according to claim 6, wherein: In the silicon oxide layer, a first region overlapping with the source wiring has a greater thickness than a second region not overlapping with the source wiring.

8. The display device according to claim 7, wherein: The thickness of the first region of the silicon oxide layer is not less than 10 nm and not more than 50 nm.

9. The display device according to claim 7, wherein: The second region of the silicon oxide layer has a thickness greater than 0 nm and less than 10 nm.

10. The display device according to claim 6, wherein: An aluminum oxide layer is further provided between the gate insulating layer and the oxide semiconductor layer.

11. The display device according to claim 6, wherein: The oxide semiconductor layer contains two or more metal elements including indium, and a ratio of indium in the two or more metal elements is 50% or more.

12. A method for manufacturing a display device, comprising: forming an oxide semiconductor layer including a polycrystalline structure; forming a gate insulating layer on the oxide semiconductor layer; forming a gate electrode on the gate insulating layer and facing the oxide semiconductor layer; forming a first silicon nitride layer in contact with the gate electrode; forming a source wiring electrically connected to the oxide semiconductor layer in contact with the first silicon nitride layer; forming a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer; forming a first transparent conductive layer electrically connected to the oxide semiconductor layer in contact with the second silicon nitride layer; and forming a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer, wherein, in the oxide semiconductor layer, a channel length of a channel region overlapping with the gate electrode is less than 2.0 μm, The first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are each formed at a temperature of 150° C. or higher and 250° C. or lower.

Images