Display panel and manufacturing method thereof

Abstract

The present application provides a display panel and a method for manufacturing the same. The display panel includes a substrate; a buffer layer located on one side of the substrate; a plurality of fins arranged in an array on a side of the buffer layer away from the substrate; a semiconductor layer located on a side of the buffer layer away from the substrate and covering the fins; a first insulating layer located on a side of the semiconductor layer away from the substrate; a gate electrode located on a side of the first insulating layer away from the substrate; a second insulating layer located on a side of the gate away from the substrate; and a source electrode and a drain electrode, both located on a side of the second insulating layer away from the substrate and connected to the semiconductor layer. This application forms fin-shaped thin-film transistors without changing existing panel manufacturing equipment and processes, but by adding only one photomask process, effectively reducing transistor size and improving panel manufacturing capabilities.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Art

[0002] In related technologies, TFT device size reduction is difficult due to the limitations of exposure machine process capabilities and the narrow channel effect. In OLED pixels, the channel length must be lengthened to achieve the purpose of controlling switching characteristics, making it difficult to reduce pixel size and increase PPI. In the panel GOA circuit, the channel width must be lengthened to improve the drive capability of the scan line, making it difficult to reduce the panel frame. Summary of the Invention

[0003] Embodiments of the present application provide a display panel and a method for manufacturing the same, so as to solve the problem in the related art that it is difficult to reduce the frame of a display panel.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, the present application provides a display panel, comprising:

[0006] substrate;

[0007] a buffer layer, located on one side of the substrate;

[0008] a plurality of fins arranged in an array on a side of the buffer layer away from the substrate;

[0009] a semiconductor layer, located on a side of the buffer layer away from the substrate and covering the fin;

[0010] a first insulating layer, located on a side of the semiconductor layer away from the substrate;

[0011] a gate electrode, located on a side of the first insulating layer away from the substrate;

[0012] a second insulating layer, located on a side of the gate away from the substrate; and

[0013] a source electrode and a drain electrode, both located on a side of the second insulating layer away from the substrate and connected to the semiconductor layer;

[0014] The width of the fin is less than or equal to 1 μm, and the distance between adjacent fins is less than or equal to 8 μm.

[0015] In one embodiment, the height of the fin is less than or equal to 1 μm.

[0016] In one embodiment, the distance between adjacent fins is less than or equal to 2 μm.

[0017] In one embodiment, the distance between adjacent fins is greater than the width of the fins.

[0018] In one embodiment, the semiconductor layer includes a channel region and a source region and a drain region located on both sides of the channel region; the channel region of the semiconductor layer covers the fin, and the fin is located between the source region and the drain region.

[0019] In one embodiment, the fins are made of inorganic insulating material.

[0020] In a second aspect, the present application provides a method for manufacturing a display panel, comprising:

[0021] providing a substrate;

[0022] Using a mask to form a plurality of fins on a substrate, wherein the width of the fins is less than or equal to 1 μm, and the distance between adjacent fins is less than or equal to 8 μm;

[0023] A thin film transistor is formed on the fin, thereby completing the preparation of the display panel.

[0024] In one embodiment, forming a plurality of fins on a substrate using a mask includes:

[0025] depositing a buffer layer and a metal sacrificial layer on the substrate;

[0026] Patterning the metal sacrificial layer to form a plurality of sub-sacrificial layers, wherein the width of the sub-sacrificial layers is less than or equal to 8 μm, and the distance between adjacent sub-sacrificial layers is less than or equal to 10 μm;

[0027] depositing an inorganic layer entirely on the patterned metal sacrificial layer;

[0028] performing dry etching on the entire surface of the inorganic layer until the metal sacrificial layer is exposed;

[0029] The entire surface of the metal sacrificial layer is wet-etched to form a plurality of fins.

[0030] In one embodiment, the metal sacrificial layer includes Al material or Cu material.

[0031] In one embodiment, forming a thin film transistor on the fin includes:

[0032] Depositing a semiconductor layer on the entire surface of the plurality of fins so that the semiconductor layer is patterned;

[0033] depositing a first insulating layer on the patterned semiconductor layer to cover the semiconductor layer;

[0034] forming a gate electrode on the first insulating layer so that the gate electrode is patterned;

[0035] forming a second insulating layer on the gate electrode, and forming an opening in the second insulating layer to expose the semiconductor layer;

[0036] A source electrode and a gate electrode connected to the semiconductor layer are formed in the opening.

[0037] The display panel of the present application includes a substrate; a buffer layer located on one side of the substrate; a plurality of fins arranged in an array on the side of the buffer layer away from the substrate; a semiconductor layer located on the side of the buffer layer away from the substrate and covering the fins; a first insulating layer located on the side of the semiconductor layer away from the substrate; a gate electrode located on the side of the first insulating layer away from the substrate; a second insulating layer located on the side of the gate away from the substrate; and a source electrode and a drain electrode, both located on the side of the second insulating layer away from the substrate and connected to the semiconductor layer. Through the above solution, the present application uses fins to form a similar structure for thin-film transistors, effectively reducing transistor size and improving panel processing capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0039] Attachment Figure 1 Schematic diagram of the cross-sectional structure of the display panel in an embodiment of the present application;

[0040] Attachment Figure 2 Schematic diagram of the preparation process of the fin in the embodiment of the present application;

[0041] Attachment Figure 3 Schematic diagram of the fabrication process of a thin film transistor in an embodiment of the present application;

[0042] Attachment Figure 4 Schematic diagram for comparing the structures of display panels in the embodiments of the present application.

[0043] Description of reference numerals in the figures:

[0044] 100. Display panel;

[0045] 110 , substrate; 120 , buffer layer; 121 , metal sacrificial layer; 130 , fin; 140 , semiconductor layer; 150 , first insulating layer; 160 , gate electrode; 170 , second insulating layer; 180 , source electrode; 190 , drain electrode. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0047] Reference Figure 1 As shown, according to a first aspect of the present application, a display panel 100 is provided, comprising:

[0048] The substrate 110 supports the various layers provided on the substrate 110. When the organic light-emitting display device is a bottom-emitting organic light-emitting display device or a double-sided emission organic light-emitting display device, a transparent substrate 110 is used. When the organic light-emitting display device is a top-emitting organic light-emitting display device, a translucent or opaque substrate 110 as well as a transparent substrate 110 can be used. The substrate 110 is made of an insulating material such as glass, quartz or a polymer resin. Examples of polymer materials include polyethersulfone (PES), polyacrylate (PA), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP) or a combination thereof. The substrate 110 may include metal.

[0049] The substrate 110 may be a rigid substrate 110 or a flexible substrate 110 that can be bent, folded, rolled, etc. Examples of flexible materials for the flexible substrate 110 include polyimide (PI), but are not limited to polyimide (PI).

[0050] Buffer layer 120 is located on one side of substrate 110 and is disposed over the entire surface of substrate 110. Buffer layer 120 prevents the diffusion of impurity ions and the penetration of moisture and external air, and provides a flat surface. Buffer layer 120 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. Depending on the type of substrate 110, process conditions, and other factors, buffer layer 120 may be removed.

[0051] A plurality of fins 130 are arrayed on a side of the buffer layer 120 away from the substrate 110; wherein the width of the fins is less than or equal to 1 μm, and the distance between adjacent fins is less than or equal to 8 μm. In some embodiments, the height of the fins is less than or equal to 1 μm, and in more specific embodiments, the height of the fins can be 500 nm, and the distance between adjacent fins is less than or equal to 2 μm.

[0052] The distance between the plurality of fins 130 is greater than the width of the fin 130. The fin 130 is made of an inorganic insulating material.

[0053] The semiconductor layer 140 is located on the side of the buffer layer 120 away from the substrate 110 and covers the fin 130. The semiconductor is formed of polycrystalline silicon. The semiconductor layer 140 is divided into a channel region and a source region and a drain region formed on both sides of the channel region. The channel region of the semiconductor is polycrystalline silicon without doping impurities, that is, an intrinsic semiconductor. The source region and the drain region are polycrystalline silicon doped with conductive impurities, that is, impurity semiconductors. The impurities doped in the source region and the drain region can be either P-type impurities or N-type impurities. The semiconductor layer 140 includes a channel region and a source region and a drain region located on both sides of the channel region. In some embodiments of the present application, the channel region of the semiconductor layer 140 covers the fin 130, and the fin 130 is located between the source region and the drain region.

[0054] A first insulating layer 150 is located on a side of the semiconductor layer 140 away from the substrate 110. The first insulating layer 150, also known as a gate insulating layer, is formed on the semiconductor. The gate insulating layer may be a single layer or multiple layers comprising at least one of tetraethylorthosilicate (TEOS), silicon nitride, and silicon oxide.

[0055] The gate electrode 160 is located on a side of the first insulating layer 150 away from the substrate 110 and is formed on the gate insulating layer, and the gate electrode 160 overlaps the channel region. The gate electrode 160 can be formed as multiple layers or a single layer including a low-resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance.

[0056] The second insulating layer 170 is located on a side of the gate electrode away from the substrate 110 and is formed on the gate electrode 160. The first interlayer insulating layer can be formed as multiple layers or a single layer, for example, of tetraethylorthosilicate (TEOS), silicon nitride, or silicon oxide. The first interlayer insulating layer and the gate insulating layer include source contact holes and drain contact holes, through which the source region and the drain region are exposed, respectively.

[0057] It should be noted that to avoid increasing the thickness of the display panel, the height of the fins (also known as the thickness of the fin layer) and the thickness of the aforementioned semiconductor layer, first insulating layer, and gate electrode do not exceed the thickness of the second insulating layer before the display panel is improved. In some embodiments, the thickness of the second insulating layer is between 500nm and 2μm, and the maximum sum of the height of the fins and the thickness of the semiconductor layer, first insulating layer, and gate electrode does not exceed 2μm. The greater the height of the fins, the more beneficial it is for the equivalent shrinkage of the TFT device. The thickness of the semiconductor layer, first insulating layer, and gate electrode can be prepared at a smaller value while meeting functional requirements. Similarly, the smaller the distance between adjacent fins, the more it can improve the equivalent shrinkage of the TFT device. The aforementioned semiconductor layer, first insulating layer, gate electrode, and second insulating layer need to be formed between adjacent fins. When the thickness of the semiconductor layer, first insulating layer, and gate electrode is prepared at a smaller value while meeting functional requirements, it is also beneficial to shorten the distance between adjacent fins. In some embodiments, the distance between adjacent fins is less than 2μm and greater than 1.2μm. It should be noted that the actual thickness of each layer may vary due to different manufacturing processes and device requirements.

[0058] The source electrode 180 and the drain electrode are both located on the side of the second insulating layer 170 away from the substrate 110 and connected to the semiconductor layer 140. The source electrode 180 and the drain electrode are both formed on the second insulating layer 170. The source electrode 180176 is connected to the source region through the source contact hole, and the drain electrode is connected to the drain region through the drain contact hole. The source electrode 180 and the drain electrode can be formed as multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni or their alloys, or a material with high corrosion resistance. For example, the source electrode 180 and the drain electrode can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti or Mo / Al / Mo, and others.

[0059] In addition, the gate electrode 160, the source electrode 180, and the drain electrode are respectively the control electrode, the input electrode, and the output electrode of the thin film transistor in the display panel 100 driving circuit, and together with the semiconductor, form a thin film transistor. The channel of the thin film transistor is formed in the semiconductor between the source electrode 180 and the drain electrode.

[0060] It should be noted that the complete display panel 100 also includes an interlayer insulating layer, an anode, a pixel defining layer, an organic emission layer, a cathode and an encapsulation layer, etc., which are sequentially formed on the thin film transistor. These layers can be the same structure as in the related art, and this application will not go into details here. Each of the layers disclosed above can be composed of a single layer or multiple layers, and another layer can be further arranged between the layers.

[0061] Through the above scheme, refer to Figure 4 As shown, Figure 4 (a) is a planar space schematic diagram of a common TFT device. Figure 4 (b) is a TFT device with a reduced equivalent width in one embodiment of the present application. Figure 4 (c) is a TFT device with a reduced equivalent length in an embodiment of the present application. It can be clearly seen that the solution of the present application can greatly reduce the size of the planar space occupied by the TFT device, indirectly improving the panel PPI (Pixels Per Inch, which refers to the number of pixels per inch (1 inch = 2.54 cm) and is an important indicator for measuring screen resolution), achieving the effect of reducing the border. In a specific embodiment of the present application, the fin 130 is 500nm high and the distance between adjacent fins 130 is 2um. When the materials and manufacturing specifications of each layer remain unchanged, the planar space of the channel region in the display panel of the present application can be saved by approximately 33.3% compared to a display panel without fins.

[0062] Reference Figure 2 and Figure 3 As shown, according to the second aspect of the present application, the present application provides a method for preparing a display panel 100, comprising:

[0063] S100: providing a substrate 110;

[0064] S200 : forming a plurality of fins 130 on the substrate 110 using a mask, wherein the width of the fins 130 is less than or equal to 1 μm, and the distance between adjacent fins 130 is less than or equal to 8 μm.

[0065] In this step, refer to Figure 2 As shown, this step also includes:

[0066] S210: depositing a buffer layer 120 and a metal sacrificial layer 121 on the substrate 110;

[0067] The metal sacrificial layer 121 includes Al material or Cu material.

[0068] S220: Patterning the metal sacrificial layer 121. Specifically, the patterned metal sacrificial layer forms a plurality of sub-sacrificial layers, each having a width less than or equal to 8 μm, and a distance between adjacent sub-sacrificial layers less than or equal to 10 μm. The distance between adjacent sub-sacrificial layers needs to be greater than the width of the sub-sacrificial layer, and the difference between the distance between adjacent sub-sacrificial layers and the width of the sub-sacrificial layer is twice the width of the fin. It should be noted that the distance between the sub-sacrificial layers is the same as the distance between adjacent fins that are ultimately formed, i.e., the distance between the sub-sacrificial layers determines the distance between adjacent fins. To minimize the size of the display panel, in actual production processes, the sub-sacrificial layers should be designed to have the minimum line width and line spacing required for the process.

[0069] S230: depositing an inorganic layer on the entire surface of the patterned metal sacrificial layer 121;

[0070] S240: performing dry etching on the entire surface of the inorganic layer until the metal sacrificial layer 121 is exposed;

[0071] S250 : performing wet etching on the entire surface of the metal sacrificial layer 121 to form a plurality of fins 130 .

[0072] S300 : forming a thin film transistor on the fin 130 , thereby completing the preparation of the display panel 100 .

[0073] In this step, refer to Figure 3 As shown, this step also includes:

[0074] S310: Depositing a semiconductor layer 140 on the entire surface of the plurality of fins 130 to pattern the semiconductor layer 140;

[0075] S320: depositing a first insulating layer 150 on the patterned semiconductor layer 140 to cover the semiconductor layer 140;

[0076] S330: forming a gate electrode 160 on the first insulating layer 150 so that the gate electrode 160 is patterned;

[0077] S340 : forming a second insulating layer 170 on the gate electrode 160 , and forming an opening in the second insulating layer 170 to expose the semiconductor layer 140 ;

[0078] S350 : forming a source electrode 180 and a gate electrode 160 connected to the semiconductor layer 140 in the opening.

[0079] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A display panel, characterized in that: include: substrate; a buffer layer, located on one side of the substrate; a plurality of fins arranged in an array on a side of the buffer layer away from the substrate; a semiconductor layer, located on a side of the buffer layer away from the substrate and covering the fin; a first insulating layer, located on a side of the semiconductor layer away from the substrate; a gate electrode, located on a side of the first insulating layer away from the substrate; a second insulating layer, located on a side of the gate away from the substrate; as well as a source electrode and a drain electrode, both located on a side of the second insulating layer away from the substrate and connected to the semiconductor layer; The width of the fin is less than or equal to 1 μm, and the distance between adjacent fins is less than or equal to 8 μm.

2. The display panel according to claim 1, wherein: The height of the fin is less than or equal to 1 μm.

3. The display panel according to claim 1, wherein: The distance between adjacent fins is less than or equal to 2 μm.

4. The display panel according to claim 1, wherein: The distance between adjacent fins is greater than the width of the fins.

5. The display panel according to claim 1, wherein: The semiconductor layer includes a channel region and a source region and a drain region located on both sides of the channel region; The channel region of the semiconductor layer covers the fin, and the fin is located between the source region and the drain region.

6. The display panel according to claim 1, wherein: The fins are made of inorganic insulating material.

7. A method for preparing a display panel, characterized in that: include: providing a substrate; Using a mask to form a plurality of fins on a substrate, wherein the width of the fins is less than or equal to 1 μm, and the distance between adjacent fins is less than or equal to 8 μm; A thin film transistor is formed on the fin, thereby completing the preparation of the display panel.

8. The preparation method according to claim 7, characterized in that The forming of a plurality of fins on a substrate using a mask comprises: depositing a buffer layer and a metal sacrificial layer on the substrate; Patterning the metal sacrificial layer to form a plurality of sub-sacrificial layers, wherein the width of the sub-sacrificial layers is less than or equal to 8 μm, and the distance between adjacent sub-sacrificial layers is less than or equal to 10 μm; depositing an inorganic layer entirely on the patterned metal sacrificial layer; performing dry etching on the entire surface of the inorganic layer until the metal sacrificial layer is exposed; The entire surface of the metal sacrificial layer is wet-etched to form a plurality of fins.

9. The preparation method according to claim 8, characterized in that The metal sacrificial layer includes Al material or Cu material.

10. The preparation method according to claim 8, characterized in that forming a thin film transistor on the fin, comprising: Depositing a semiconductor layer on the entire surface of the plurality of fins so that the semiconductor layer is patterned; depositing a first insulating layer on the patterned semiconductor layer to cover the semiconductor layer; forming a gate electrode on the first insulating layer so that the gate electrode is patterned; forming a second insulating layer on the gate electrode, and forming an opening in the second insulating layer to expose the semiconductor layer; A source electrode and a gate electrode connected to the semiconductor layer are formed in the opening.

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