Array substrate, display panel and driving method thereof

Abstract

The present application provides an array substrate, a display panel and a driving method thereof, wherein the array substrate comprises a substrate and a plurality of conductive layers located on one side of the substrate. The plurality of conductive layers comprises a voltage stabilizing structure and at least one pixel circuit. The pixel circuit comprises a driving transistor and a first transistor, wherein the first transistor comprises a first electrode, a second electrode and a first control electrode, the driving transistor comprises a third electrode and a second control electrode, the second electrode and the second control electrode are connected, and the first electrode and the third electrode are connected; the orthographic projection of the first control electrode on the substrate substrate and the orthographic projection of the voltage stabilizing structure on the substrate substrate have an overlapping area, and the orthographic projection of the second electrode on the substrate substrate and the overlapping area are staggered. By staggering the orthographic projection of the second electrode on the substrate substrate and the overlapping area, the problem of uneven brightness of pixels caused by the difference in the area of ​​the above-mentioned overlapping area is solved, thereby improving the uniformity of the display brightness of the display panel and further improving the display effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a driving method thereof. Background Art

[0002] At present, organic light emitting diode (OLED) display devices are widely used due to their light weight, self-luminescence, wide viewing angle, low driving voltage, high luminous efficiency, low power consumption and fast response speed. OLED display devices widely use low temperature polysilicon oxide (LTPO) display technology.

[0003] However, due to the difference in parasitic capacitance of different thin film transistors in existing LTPO display products, and because the gate of the thin film transistor is more sensitive to parasitic capacitance coupling, the output current uniformity of different thin film transistors is poor, resulting in uneven brightness of different pixels. Therefore, the prior art has the problem of uneven display brightness of the display panel, which affects the display effect. Summary of the invention

[0004] In view of this, the embodiments of the present application are directed to providing an array substrate, a display panel and a driving method thereof, so as to solve the problem of uneven display brightness of the display panel, which affects the display effect.

[0005] In a first aspect, the present application provides an array substrate, comprising: a base substrate and a plurality of conductive layers, wherein the plurality of conductive layers are located on one side of the base substrate; wherein the plurality of conductive layers include a voltage stabilizing structure and at least one pixel circuit; the pixel circuit includes a driving transistor and a first transistor, wherein the first transistor includes a first electrode, a second electrode and a first control electrode, and the driving transistor includes a third electrode and a second control electrode, wherein the second electrode and the second control electrode are connected, and the first electrode and the third electrode are connected; an orthographic projection of the first control electrode on the base substrate and an orthographic projection of the voltage stabilizing structure on the base substrate have an overlapping area, and the orthographic projection of the second electrode on the base substrate and the overlapping area are staggered.

[0006] In one embodiment, in the first direction, the driving transistor and the second electrode are located on the same side of the overlapping region.

[0007] In one embodiment, in the first direction, the first pole and the second pole are respectively located on both sides of the overlapping area.

[0008] In one embodiment, the orthographic projection of the first pole on the substrate substrate and the overlap region at least partially overlap;

[0009] Preferably, in the first direction, the orthographic projection of the first pole on the substrate overlaps with the overlapping area.

[0010] In one embodiment, the overlapping area extends along a second direction, and the second direction intersects the first direction; preferably, the second direction is perpendicular to the first direction; preferably, the second control electrode extends along the second direction; preferably, the voltage stabilizing structure includes a voltage stabilizing line, and the voltage stabilizing line extends along the second direction.

[0011] In one embodiment, the plurality of conductive layers include a plurality of pixel circuits arranged along the second direction, and at least part of the first electrode is located between overlapping regions of adjacent pixel circuits; preferably, the first electrode includes a source electrode, and the second electrode includes a drain electrode.

[0012] In one embodiment, the first transistor comprises an indium gallium zinc oxide transistor.

[0013] In one embodiment, the pixel circuit comprises a 7T1C pixel circuit.

[0014] The second aspect of the present application provides a display panel, comprising: an array substrate as mentioned in the above embodiment; wherein the pixel circuit also includes a second transistor and an initialization signal line, the second transistor includes a fourth electrode and a fifth electrode, the fourth electrode is connected to the initialization signal line, and the fifth electrode is connected to the second electrode.

[0015] A third aspect of the present application provides a method for driving a display panel, which is suitable for driving the display panel mentioned in the above embodiment, and the driving method includes:

[0016] In the reset phase, the first transistor and the second transistor are controlled to be turned on, and an initialization signal is input to the initialization signal line to initialize the second control electrode.

[0017] The technical solution provided by the present application is to set the orthographic projection of the first control electrode of the first transistor on the substrate substrate and the orthographic projection of the voltage stabilizing structure on the substrate substrate to have an overlapping area, and to use the voltage stabilizing structure to improve the performance of the first transistor; and the orthographic projection of the second electrode of the first transistor on the substrate substrate and the overlapping area are staggered, so as to eliminate the influence of the difference in the area of ​​the overlapping area in each pixel circuit on the parasitic capacitance of the first transistor. In this way, the parasitic capacitance of the first transistor in each pixel circuit is consistent, and the second control electrode voltage of the driving transistor in different pixel circuits is also consistent, so that the output current of different pixel circuits is consistent, and further, the display brightness uniformity of the display panel is improved, and the display effect is improved.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 Shown is a structural schematic diagram of a pixel circuit in the related art.

[0021] Figure 2 The figure shows a control signal timing diagram of a pixel circuit in the related art.

[0022] Figure 3 Shown is a schematic diagram of a planar structure of an array substrate in the related art.

[0023] Figure 4 FIG. 1 is a schematic diagram of the structure of an array substrate provided in one embodiment of the present application.

[0024] Figure 5 Shown is a schematic diagram of the planar structure of an array substrate provided in one embodiment of the present application.

[0025] Figure 6 FIG. 1 is a schematic diagram of the structure of a pixel circuit provided in one embodiment of the present application.

[0026] Figure 7 Shown is a schematic structural diagram of a pixel circuit provided in another embodiment of the present application.

[0027] Figure 8 FIG. 1 is a flow chart of a method for driving a display panel according to an embodiment of the present application.

[0028] Fig. 9 FIG. 1 is a control signal timing diagram of a pixel circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0030] The LTPO display product includes an array substrate, which includes multiple pixel circuits. Figure 1 FIG. 1 is a schematic diagram showing a structure of a pixel circuit in the related art. Figure 1As shown, the pixel circuit includes a first switch element T01, a second switch element T02, a third switch element T03, a fourth switch element T04, a fifth switch element T05, a sixth switch element T06, a seventh switch element T07, a first capacitor C0 and a first light-emitting device OLED. Among them, the third switch element T03 is an indium gallium zinc oxide thin film transistor, and the first switch element T01 is a low-temperature polysilicon thin film transistor.

[0031] Figure 2 The figure shows a control signal timing diagram of a pixel circuit in the related art, see Figure 2 The pixel circuit includes three working stages, namely, a reset stage T10, a write stage T20 and a light emitting stage T30. The first control signal Scan01, the second control signal Scan02, the third control signal Scan03, the fourth control signal Scan04 and the fifth control signal EM respectively control the fourth switch element T04, the second switch element T02, the third switch element T03, the seventh switch element T07, the fifth switch element T05 and the sixth switch element T06 in the pixel circuit according to the respective level states shown in the timing diagram.

[0032] In the array substrate, each switch element is equipped with a plate 101 for stabilizing the gate voltage of the switch element. Figure 3 FIG. 1 is a schematic diagram of a planar structure of an array substrate in the related art. Figure 3 1 shows the electrode plate 101, the thin film layer constituting the third switch element T03, part of the thin film layer of the first switch element T01, and the connection relationship between the above-mentioned thin film layers. Figure 2 As shown, the first switch element T01 includes a first gate 102 and a first semiconductor layer 103, and the third switch element T03 includes a second gate 104, a first source 105, a first drain 106 and a second semiconductor layer 107. There is a first overlapping region between the second gate 104 and the plate 101, and part of the first drain 106 overlaps the first overlapping region.

[0033] However, in the prior art, in different pixel circuits, the area of ​​the first overlapping region is different, and the area of ​​the region where the first drain 106 overlaps with the first overlapping region is also different, resulting in a difference in the first parasitic capacitance Cgd between the first gate 102 and the first drain 106. When the pixel circuit is working, the voltage of the first gate 102 is affected by the coupling of the first parasitic capacitance Cgd, resulting in different voltages of the first gate 102 in different pixel circuits, thereby resulting in different brightness of multiple pixels in the display panel, causing clustered Mura.

[0034] In view of the above phenomenon, the inventors conducted simulation research, and the simulation results show that when there are differences in the first parasitic capacitance Cgd in different pixel circuits, the larger the first parasitic capacitance Cgd is, the smaller the voltage of the first gate 102 in the pixel circuit where the first parasitic capacitance Cgd is located.

[0035] Based on this, the embodiments of the present application provide an array substrate, a display panel and a driving method thereof to solve the above technical problems.

[0036] Figure 4 FIG. 1 is a schematic diagram of the structure of an array substrate provided in an embodiment of the present application. Figure 5 FIG. 1 is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present application. Figure 4 and Figure 5 The array substrate comprises: a base substrate 200 and a plurality of conductive layers 201, wherein the plurality of conductive layers 201 are located on one side of the base substrate 200; wherein the plurality of conductive layers 201 comprise a voltage stabilizing structure 202 and at least one pixel circuit 203; the pixel circuit comprises a driving transistor T1 and a first transistor T3, wherein the first transistor T3 comprises a first electrode 206, a second electrode 204 and a first control electrode 208, the driving transistor T1 comprises a third electrode 207 and a second control electrode, the second electrode 204 and the second control electrode 205 are connected, and the first electrode 206 and the third electrode 207 are connected; the orthographic projection of the first control electrode 208 on the base substrate 200 and the orthographic projection of the voltage stabilizing structure 202 on the base substrate 200 have an overlapping area, and the orthographic projection of the second electrode 204 on the base substrate 200 and the overlapping area are staggered.

[0037] Specifically, the base substrate 200 is used to carry multiple conductive layers 201. The types of the base substrate 200 include but are not limited to glass base substrates or polymer base substrates. Multiple conductive layers 201 are arranged on one side of the base substrate 200 to define pixel electrodes, establish circuit connections, and transmit signals. The voltage stabilizing structure 202 is used to keep the gate voltage of the transistor stable and unchanged, thereby improving the performance of the transistor. Some of the conductive layers 201 in the multiple conductive layers 201 form at least one pixel circuit 203.

[0038] Figure 6 FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention. Figure 4-Figure 6, the pixel circuit 203 includes an electrically connected driving transistor T1 and a first transistor T3. The orthographic projection of the first control electrode 208 on the substrate 200 and the orthographic projection of the voltage stabilizing structure 202 on the substrate 200 have an overlapping area, and the area of ​​the overlapping area is different in different pixel circuits 203. There is a parasitic capacitance C between the first control electrode 208 and the second electrode 204. The second electrode 204 is connected to the second control electrode 205. When the parasitic capacitance C is charged and discharged, the voltage of the second control electrode 205 changes due to the coupling effect. When the parasitic capacitance C of the first transistor T3 in different pixel circuits 203 is different, the voltage of the second control electrode 205 in different pixel circuits 203 is different, and the output current of different pixel circuits 203 will also be inconsistent, resulting in uneven brightness of the display panel. Therefore, staggering the orthographic projection of the second electrode 204 on the base substrate 200 and the overlapping area can eliminate the influence of the difference in the overlapping area area in each pixel circuit 203 on the parasitic capacitance C of the first transistor T3, thereby making the parasitic capacitance C of the first transistor T3 in each pixel circuit 203 consistent.

[0039] The technical solution of this embodiment is to arrange the orthographic projection of the first control electrode 208 of the first transistor T3 on the substrate 200 and the orthographic projection of the voltage stabilizing structure 202 on the substrate 200 to have an overlapping area, and to use the voltage stabilizing structure 202 to improve the performance of the first transistor T3; and the orthographic projection of the second electrode 204 of the first transistor T3 on the substrate 200 and the overlapping area are arranged in a staggered manner, so as to eliminate the influence of the difference in the area of ​​the overlapping area in each pixel circuit 203 on the parasitic capacitance C of the first transistor T3. In this way, the parasitic capacitance C of the first transistor T3 in each pixel circuit 203 is consistent, and the voltage of the second control electrode 205 of the driving transistor T1 in different pixel circuits 203 is also consistent, so that the output current of different pixel circuits 203 is consistent, and further, the display brightness uniformity of the display panel is improved, and the display effect is improved.

[0040] In one embodiment, in the first direction x, the driving transistor T1 and the second electrode 204 are located on the same side of the overlapping region.

[0041] Specifically, see Figure 5, in the first direction x, the second control electrode 205 is located on one side of the overlapping area. The second electrode 204 needs to be overlapped with the second control electrode 205 to realize the pixel circuit 203 structure. The second electrode 204 and the driving transistor T1 are overlapped on the same side of the overlapping area, so that the orthographic projection of the second electrode 204 on the substrate 200 is independent of the overlapping area, that is, the orthographic projection of the second electrode 204 on the substrate 200 and the overlapping area do not have an overlapping part. In this way, the parasitic capacitance C between the first control electrode 208 and the second electrode 204 will not be affected by the difference in the area of ​​the overlapping area in each pixel circuit 203, so that the parasitic capacitance C of the first transistor T3 of each pixel circuit 203 in the array substrate is consistent, and the parasitic capacitance C couples the voltage of the second control electrode 205, so that the output current of different pixel circuits 203 is consistent.

[0042] In this embodiment, by arranging the driving transistor T1 and the second electrode 204 on the same side of the overlapping region in the first direction x, the influence of the difference in the area of ​​the overlapping region on the parasitic capacitance C of the first transistor T3 is eliminated, further improving the display brightness uniformity of the display panel, which is beneficial to improving the display effect.

[0043] In one embodiment, in the first direction x, the first pole 206 and the second pole 204 are respectively located on both sides of the overlapping region.

[0044] Specifically, Figure 5 As shown, in the first direction x, the first electrode 206 is arranged on one side of the overlapping region away from the driving transistor T1, and the second electrode 204 is arranged on the other side of the overlapping region. The first transistor T3 also includes a semiconductor layer 209, and the orthographic projection of the semiconductor layer 209 on the substrate 200 passes through the orthographic projection of the overlapping region on the substrate 200. The first electrode 206 and the second electrode 204 are respectively overlapped with the semiconductor layer 209 on both sides of the overlapping region to form a channel structure of the first transistor T3. Exemplarily, when the first transistor T3 is working, the current flows from the first electrode 206 to the second electrode 204, and the path through which the current flows crosses the overlapping region, and the first control electrode 208 controls the current.

[0045] In this embodiment, by arranging the first electrode 206 and the second electrode 204 on both sides of the overlapping region in the first direction x, it is convenient for the first control electrode 208 to control the working current of the first transistor T3. This arrangement eliminates the influence of the difference in the area of ​​the overlapping region on the parasitic capacitance C of the first transistor T3, further improves the display brightness uniformity of the display panel, and is conducive to improving the display effect.

[0046] In one embodiment, the orthographic projection of the first pole 206 on the substrate 200 and the overlapping region at least partially overlap; preferably, in the first direction x, the orthographic projection of the first pole 206 on the substrate 200 overlaps with the overlapping region.

[0047] Specifically, see Figure 5 , the first electrode 206 is arranged on one side of the overlapping area, and the driving transistor T1 is arranged on the other side of the overlapping area. The driving transistor T1 includes a third electrode 207. In order to realize the pixel circuit structure, the first electrode 206 is overlapped with the third electrode 207, and the positive projection of the lead of the first electrode 206 on the substrate 200 extends from the side of the overlapping area away from the driving transistor T1 to the side of the overlapping area close to the driving transistor T1. Exemplarily, the first electrode 206 and the third electrode 207 are located in different metal layers, and the lead of the first electrode 206 extends from the metal layer where the first electrode 206 is located to the metal layer where the third electrode 207 is located through a via. In the first direction x, the first electrode 206 and the third electrode 207 of the driving transistor T1 are respectively located on both sides of the overlapping area, and the positive projection of the first electrode 206 on the substrate 200 is set to overlap with the overlapping area, then the first electrode 206 crosses the overlapping area and overlaps with the third electrode 207, connecting the first transistor T3 and the driving transistor T1, and realizing the pixel circuit structure. Exemplarily, the third electrode 207 of the driving transistor T1 is a source or a drain.

[0048] In this embodiment, the orthographic projection of the first electrode 206 on the base substrate 200 is set to overlap with the overlapping area at least partially, so that the first electrode 206 is connected to the driving transistor T1; in the first direction x, the orthographic projection of the first electrode 206 on the base substrate 200 is set to overlap with the overlapping area, so that the lead of the first electrode 206 crosses the overlapping area and overlaps with the third electrode 207, connecting the first transistor T3 and the driving transistor T1, and realizing the structure of the pixel circuit 203. On the basis of the above embodiments, the technical solution of this embodiment is conducive to further improving the display effect.

[0049] In one embodiment, the overlapping area extends along the second direction y, and the second direction y intersects with the first direction x; preferably, the second direction y is perpendicular to the first direction x; preferably, the second control electrode 205 extends along the second direction y; preferably, the voltage stabilizing structure 202 includes a voltage stabilizing line, and the voltage stabilizing line extends along the second direction y.

[0050] Specifically, see Figure 5, the overlapping area extends along the second direction y, and a plurality of first control electrodes 208 and voltage stabilizing structures 202 are formed in the second direction y. The second direction y intersects with the first direction x, so that the first control electrode 208 controls the current between the first electrode 206 and the second electrode 204 distributed in the first direction x. Preferably, the second direction y is set perpendicular to the first direction x, so that the shape design of the plurality of conductive layers 201 is more regular, the circuit design is simpler, and the electron flow and signal transmission are optimized. Preferably, the second control electrode 205 is set to extend along the second direction y to form a plurality of second control electrodes 205. Preferably, the voltage stabilizing structure 202 includes a voltage stabilizing line for keeping the voltage in the circuit stable. The voltage stabilizing line extends along the second direction y to connect the plurality of voltage stabilizing structures 202 arranged in the second direction y. Such a setting can ensure the uniformity of the pixel circuit 203, which is conducive to further realizing uniform display brightness, and such a design scheme makes the preparation process of the array substrate easier, which is conducive to reducing errors and defects in the preparation process.

[0051] In one embodiment, the plurality of conductive layers 201 include a plurality of pixel circuits 203 arranged along the second direction y, and at least part of the first electrodes 206 are located between overlapping regions of adjacent pixel circuits 203. Preferably, the first electrodes 206 include a source electrode, and the second electrodes 204 include a drain electrode.

[0052] Specifically, part of the conductive layers 201 in the plurality of conductive layers 201 constitute a plurality of pixel circuits 203, and the plurality of pixel circuits 203 are arranged along the second direction y. By setting at least part of the first electrode 206 of the first transistor T3 between the overlapping regions of adjacent pixel circuits 203, the layout of the signal line can be optimized, the crossing and overlapping of the signal line can be reduced, and the parasitic effect can be reduced. In other embodiments, by setting at least part of the first electrode 206 of the first transistor T3 between the overlapping regions of adjacent pixel circuits 203, the adjacent pixel circuits 203 can also share at least part of the first electrode 206. This arrangement can simplify the circuit design, and by sharing electrodes, the brightness of each pixel can be more accurately controlled, thereby improving the brightness uniformity of the entire display panel. Preferably, the first electrode 206 is a source electrode, and the second electrode 204 is a drain electrode. The control voltage of the driving transistor T1 is coupled by the parasitic capacitance C between the drain electrode and the gate electrode of the first transistor T3, so as to further improve the display brightness uniformity of the display panel, which is conducive to improving the display effect.

[0053] In one embodiment, the first transistor T3 is an InGaZnO transistor.

[0054] Exemplarily, the semiconductor layer 209 of the first transistor T3 is made of indium gallium zinc oxide semiconductor. The indium gallium zinc oxide thin film can be uniformly deposited on a large area by processes such as sputtering, and has good uniformity, which can further improve the performance of the thin film transistor, so that the manufactured display has good uniformity and stability. The embodiment of the present application does not specifically limit the material of the semiconductor layer 209 of the first transistor T3.

[0055] In one embodiment, the pixel circuit 203 includes a 7T1C pixel circuit.

[0056] Specifically, Figure 7 FIG. 1 is a schematic diagram of a pixel circuit provided in another embodiment of the present application. Based on the above embodiments, Figure 7 As shown, the pixel circuit 203 further includes a second transistor T4, a third transistor T2, a fourth transistor T5, a fifth transistor T6, a sixth transistor T7, a storage capacitor Cst and a second light emitting device OLED1. The first end of the fourth transistor T5 and the first end of the storage capacitor Cst are connected to the first power supply voltage signal ELVDD, the second end of the fourth transistor T5 is electrically connected to the first end of the driving transistor T1 and the second end of the third transistor T2, and the control end of the fourth transistor T5 is connected to the first switch signal EM1. The control end of the driving transistor T1 is electrically connected to the second end of the storage capacitor Cst and the first end of the first transistor T3, the second end of the driving transistor T1 is electrically connected to the second end of the first transistor T3, the first end of the second transistor T4 and the first end of the fifth transistor T6. The second end of the fifth transistor T6 is electrically connected to the first end of the sixth transistor T7 and the first end of the second light emitting device OLED1, and the second end of the second light emitting device OLED1 is connected to the second power supply voltage signal ELVSS. The first end of the third transistor T2 is connected to the data voltage signal Vdata1, the control end of the fifth transistor T6 is connected to the first switch signal EM1, the second end of the second transistor T4 is connected to the first reference signal Vref2, and the second end of the sixth transistor T7 is connected to the second reference signal Vref3. The control end of the second transistor T4 is connected to the first drive signal Scan1, the control end of the third transistor T2 is connected to the second drive signal Scan2, the control end of the first transistor T3 is connected to the third drive signal Scan3, and the control end of the sixth transistor T7 is connected to the fourth drive signal Scan4.

[0057] Exemplarily, the first electrode 206 serves as the second end of the first transistor T3, the second electrode 204 serves as the first end of the first transistor T3, and the second control electrode 205 serves as the control end of the driving transistor T1. In this embodiment, the pixel circuit 203 includes a 7T1C pixel circuit to improve the stability of the circuit. In combination with the above embodiments, the display brightness uniformity of the display panel is further improved, which is conducive to improving the display effect. It should be noted that the array substrate provided in the embodiment of the present application includes but is not limited to the 7T1C pixel circuit.

[0058] An embodiment of the present application also provides a display panel, including: an array substrate as mentioned in the above embodiment; wherein the pixel circuit 203 also includes a second transistor T4 and an initialization signal line, the second transistor T4 includes a fourth electrode and a fifth electrode, the fourth electrode is connected to the initialization signal line, and the fifth electrode is connected to the second electrode 204.

[0059] For example, see Figure 7 , the fourth electrode serves as the second end of the second transistor T4 , the fifth electrode serves as the first end of the second transistor T4 , and the first reference signal Vref2 is transmitted to the second transistor T4 through the initialization signal line.

[0060] The display panel provided in the embodiment of the present application has the beneficial effects of the array substrate mentioned in the above embodiment, and its technical principles and the effects produced are similar, which will not be repeated here.

[0061] Figure 8 FIG. 1 is a flow chart of a method for driving a display panel provided in an embodiment of the present application. The method is suitable for driving the display panel mentioned in the above embodiment. Figure 8 As shown, the driving method includes:

[0062] S110, a reset phase, controlling the first transistor and the second transistor to turn on, inputting an initialization signal to the initialization signal line to initialize the second control electrode.

[0063] Specifically, Fig. 9 FIG. 1 is a timing diagram of control signals of a pixel circuit provided by an embodiment of the present application, see Fig. 9 The pixel circuit 203 includes three working stages, namely, a reset stage T11, a data writing stage T21, and a light emitting stage T31. The first drive signal Scan1, the second drive signal Scan2, the third drive signal Scan3, the fourth drive signal Scan4, and the first switch signal EM1 drive the second transistor T4, the third transistor T2, the first transistor T3, the sixth transistor T7, the fourth transistor T5, and the fifth transistor T6 in the pixel circuit 203 according to the respective level states shown in the timing diagram.

[0064] Exemplarily, the first transistor T3 and the second transistor T4 are both N-type transistors, and the third transistor T2, the fourth transistor T5, the fifth transistor T6 and the sixth transistor T7 are all P-type transistors. In the reset stage, the first drive signal Scan1 and the third drive signal Scan3 are both high levels, controlling the first transistor T3 and the second transistor T4 to turn on, and inputting the initialization signal to the initialization signal line to initialize the second control electrode 205 of the drive transistor T1. In the data writing stage T21, the second drive signal Scan2 and the fourth drive signal Scan4 are both low levels, and the third drive signal Scan3 is high level, controlling the third transistor T2, the first transistor T3 and the second transistor T4 to turn on, and writing data to the pixel. In the light-emitting stage T31, the first switch signal EM1 is set low from a high level to control the fourth transistor T5 and the fifth transistor T6 to emit light.

[0065] The display panel driving method provided in the embodiment of the present application has the beneficial effects of the array substrate or display panel mentioned in the above embodiments, and its technical principles and the effects produced are similar, which will not be repeated here.

[0066] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution of this application can be achieved, and this document is not limited here.

[0067] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. An array substrate, characterized in that: include: substrate substrate; and A plurality of conductive layers are located on one side of the substrate; Among them, the multiple conductive layers include a voltage stabilizing structure and at least one pixel circuit; the pixel circuit includes a driving transistor and a first transistor, the first transistor includes a first electrode, a second electrode and a first control electrode, the driving transistor includes a third electrode and a second control electrode, the second electrode and the second control electrode are connected, and the first electrode and the third electrode are connected; the orthographic projection of the first control electrode on the substrate and the orthographic projection of the voltage stabilizing structure on the substrate have an overlapping area, and the orthographic projection of the second electrode on the substrate and the overlapping area are staggered.

2. The array substrate according to claim 1, characterized in that: In the first direction, the driving transistor and the second electrode are located on the same side of the overlapping region.

3. The array substrate according to claim 1, characterized in that: In a first direction, the first pole and the second pole are respectively located at two sides of the overlapping area.

4. The array substrate according to claim 1, characterized in that: The orthographic projection of the first pole on the substrate and the overlapping area at least partially overlap; Preferably, in the first direction, the orthographic projection of the first pole on the base substrate overlaps with the overlapping area.

5. The array substrate according to claim 4, characterized in that: The overlapping area extends along a second direction, and the second direction intersects the first direction; Preferably, the second direction is perpendicular to the first direction; Preferably, the second control electrode extends along the second direction; Preferably, the voltage stabilizing structure comprises a voltage stabilizing line, and the voltage stabilizing line extends along the second direction.

6. The array substrate according to claim 1, characterized in that: The plurality of conductive layers include a plurality of pixel circuits arranged along a second direction, and at least a portion of the first electrodes are located between the overlapping regions of adjacent pixel circuits; Preferably, the first electrode includes a source electrode, and the second electrode includes a drain electrode.

7. The array substrate according to claim 1, characterized in that: The first transistor comprises an indium gallium zinc oxide transistor.

8. The array substrate according to claim 1, characterized in that: The pixel circuit includes a 7T1C pixel circuit.

9. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 8; The pixel circuit further includes a second transistor and an initialization signal line, the second transistor includes a fourth electrode and a fifth electrode, the fourth electrode is connected to the initialization signal line, and the fifth electrode is connected to the second electrode.

10. A method for driving a display panel, characterized in that: Suitable for driving the display panel according to claim 9, the driving method comprising: In the reset phase, the first transistor and the second transistor are controlled to be turned on, and an initialization signal is input to the initialization signal line to initialize the second control electrode.

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