Semiconductor device, design method thereof and system including the same

Abstract

There is provided a semiconductor device including a first layout pattern including a first standard cell including: a plurality of first signal lines disposed parallel to each other and each having a center located on a corresponding first wiring track; the two first power lines are arranged on the two opposite sides of the first signal lines in parallel and have the same width; and the center line of the two first power lines is defined as the boundary of the first standard unit. The semiconductor device solves a wiring problem and electromigration by changing a wiring track, reducing a standard cell, and simultaneously increasing a width of a power line of the reduced standard cell. The invention also provides a design method of the semiconductor device and a system including the semiconductor device.

Description

[0001] This application is a divisional application with the application date of April 2, 2018, the name of which is “Semiconductor device, design method thereof and system comprising the same” and the patent application number is 201810284453.X. Technical Field

[0002] The present invention generally relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a design method thereof, and a system including the same. Background Art

[0003] The current trend of miniaturizing integrated circuits (ICs) has resulted in smaller devices that consume less power and provide more functionality at even higher speeds. The miniaturization process has also led to tighter design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits while ensuring that the standard cell layout design and manufacturing specifications are met.

[0004] In the prior art, the layout pattern of the second metal layer of the semiconductor device is designed on 16 routing tracks (routing tracks) 1-16. The signal line and the power lines VSS and VDD are designed as a whole, which will cause the following wiring and electromigration problems: when the centers of the signal line and the VSS and VDD power lines are placed on the routing tracks 1-16, if the layout pattern divides the boundaries or reduces the standard cell, some boundaries are located at the center of the power line VSS, but there are some boundaries located outside the VDD power line, so the reduction of the standard cell will cause wiring and electromigration problems. When the width of the power lines VDD and VSS increases, the center of the power line VSS is placed on the routing tracks 1 and 16, but the center of the power line cannot be placed on the routing tracks, and there will also be wiring problems. Among them, electromigration is a metal migration phenomenon caused by metal lines under the action of current and temperature, which may cause the metal lines to break, thereby affecting the normal operation of the chip.

[0005] For example, in the prior art, the VSS in the first metal layer and the second metal layer is 32nm, and the VDD is 64nm. The width of the power line VSS and the power line VDD in the same layer are different. For example, the gap between the power line VDD and the signal line is very large, and the gap between adjacent wires in the signal line and the power line VSS is small. The wiring is uneven, which is easy to cause electromigration problems and wiring problems when the standard unit is reduced. Moreover, it is difficult to ensure the accuracy and device performance of the uneven wiring during the manufacturing process of the semiconductor device.

[0006] In addition, when the difference between standard cell A and standard cell B is only the wiring VSS shape and pin position, two standard cells A and B need to be established in the library, and the layout pattern of the first metal layer can be designed according to the standard cell A and the standard cell B, thereby increasing the design cycle. In addition, in the prior art, since the pin position of the upside-down standard cell may deviate from the wiring track, it may also cause a layout pattern failure. Summary of the invention

[0007] In order to solve the defects existing in the prior art, according to one aspect of the present invention, a semiconductor device is provided, comprising a first layout pattern, wherein the first layout pattern comprises a first standard unit, wherein the first standard unit comprises: a plurality of first signal lines, which are arranged to be parallel to each other and the center of each first signal line is located on a corresponding first wiring track; and two first power lines, which are arranged in parallel on opposite sides of the plurality of first signal lines and have the same width; and wherein the center lines of the two first power lines are defined as the boundaries of the first standard unit.

[0008] In an embodiment, the gap between each first power line and an adjacent first signal line is the same first distance; the gap between two adjacent first signal lines among the plurality of first signal lines is the same second distance, and the first distance is greater than or equal to the second distance.

[0009] In an embodiment, a width of each first signal line is smaller than a width of the first power line.

[0010] In an embodiment, the semiconductor device further includes a second layout pattern, wherein the second layout pattern includes a modified first standard cell, and the modified first standard cell is formed by turning the first standard cell upside down.

[0011] In an embodiment, the first wiring tracks include an odd number of first wiring tracks, and the number of the first signal lines is the same as the number of the first wiring tracks.

[0012] In an embodiment, the semiconductor device also includes a third layout pattern, the third layout pattern includes a second standard cell, the second standard cell includes: an even number of second signal lines, which are arranged to be parallel to each other and the center of each second signal line is located on a corresponding second wiring track; two second power lines, which are respectively arranged on opposite sides of the even number of second signal lines and have the same width, wherein the width of the first power line is greater than the width of the second power line and the center line of the two second power lines is defined as the boundary of the second standard cell.

[0013] In an embodiment, the gap between each second power line and an adjacent second signal line is the same third distance; the gap between two adjacent second signal lines among the even number of second signal lines is the same fourth distance, wherein the third distance is greater than or equal to the fourth distance.

[0014] In an embodiment, the semiconductor device further includes the fourth layout pattern, wherein the fourth layout pattern includes a modified second standard cell, and the second standard cell turned upside down serves as the modified second standard cell.

[0015] In an embodiment, the semiconductor device also includes a fifth layout pattern located in the first metal layer, wherein the first layout pattern is located in a second metal layer above the first metal layer; the fifth layout pattern includes a third standard unit, and the third standard unit includes: a plurality of conductive components arranged on the first wiring track; two third power lines arranged on opposite sides of the plurality of conductive components in parallel with the first wiring track, wherein a width of the third power line is smaller than a width of the first power line and a center of the third power line overlaps with a center of the first power line.

[0016] In an embodiment, the semiconductor device further includes a sixth layout pattern located in the first metal layer, wherein the sixth layout pattern includes a modified third standard cell, and a third standard cell turned upside down is used as the modified third standard cell.

[0017] According to another aspect of the present invention, a method for designing a semiconductor device is provided, comprising: providing a plurality of first signal lines parallel to each other and arranging the centers of the plurality of first signal lines on corresponding first wiring tracks; arranging two first power lines in parallel on opposite sides of the plurality of first signal lines; and arranging the two first power lines to have the same width to form a first layout pattern, wherein the center lines of the two first power lines are defined as the boundaries of a first standard cell.

[0018] In an embodiment, the first standard cell is modified and a second layout pattern is set according to the modified first standard cell.

[0019] In an embodiment, modifying the first standard cell further includes turning the first standard cell upside down.

[0020] In an embodiment, the gap between each first power line and an adjacent first signal line is the same first distance; the multiple first signal lines are an odd number of first signal lines, and the gap between two adjacent first signal lines among the base number of first signal lines is the same second distance, wherein the first distance is greater than or equal to the second distance, and the number of the first wiring tracks is the same as the number of the first signal lines.

[0021] In an embodiment, the method for designing a semiconductor device also includes: providing an even number of second signal lines parallel to each other and setting the centers of the even number of second signal lines on a second wiring track; setting two second power lines in parallel on opposite sides of the even number of second signal lines, wherein the width of the first power line is greater than the width of the second power line, the width of the odd number of first signal lines is the same as the width of the even number of second signal lines, and setting the two second power lines to have the same width to form a third layout pattern, wherein the center lines of the two second power lines are defined as the boundaries of the second standard cells.

[0022] In an embodiment, the gap between each second power line and an adjacent second signal line is set to the same third distance; the gap between two adjacent second signal lines among the even number of second signal lines is set to the fourth distance, wherein the third distance is greater than or equal to the fourth distance.

[0023] In an embodiment, the second standard cell is turned upside down and a fourth layout pattern is set according to the turned-upside-down second standard cell.

[0024] In an embodiment, the two first power lines include a first VSS power line and a first VDD power line, and the widths of the first VSS power line and the first VDD power line are set to be greater than the widths of the plurality of first signal lines.

[0025] In an embodiment, the first VDD line in the modified first standard cell is arranged to overlap the first VDD line in the first standard cell.

[0026] According to another aspect of the present invention, there is provided a system including a semiconductor device, including: a substrate; a semiconductor device arranged above the substrate; a first metal layer located above the semiconductor device and including a first layout pattern, wherein the first layout pattern includes a first standard cell, the first standard cell including: a plurality of first signal lines arranged parallel to each other and with the center of each first signal line located on a corresponding wiring track; and two first power lines arranged in parallel on opposite sides of the plurality of first signal lines and having the same width, wherein center lines of the two first power lines are defined as boundaries of the first standard cell.

[0027] In an embodiment of the present invention, the wiring track of the standard cell is changed, and the reduced standard cell is designed according to the changed wiring track. By increasing the width of the power line in the reduced standard cell, the wiring offset wiring track and electromigration problems can be solved. In addition, during the design process, 5% to 10% of the design time can be saved by flipping the wiring cell, thereby shortening the design cycle, and when the difference between the cells is only the wiring shape and the pin position, the semiconductor device can be designed according to the standard cell and its variants, thereby avoiding wiring failures where the designed pins are inaccessible. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0029] Figure 1 is a diagram of a first layout pattern of a semiconductor device according to an embodiment of the present invention; and

[0030] Figure 2 is a diagram showing a layout pattern of a second metal layer of a semiconductor device according to an embodiment of the present invention;

[0031] Figure 3 is a diagram showing a layout pattern of a second metal layer of a semiconductor device according to another embodiment of the present invention;

[0032] Figure 4 is a diagram of a layout pattern of a first metal layer of a semiconductor device according to an embodiment of the present invention;

[0033] Figure 5 is a diagram of a layout pattern of a first metal layer of a semiconductor device according to another embodiment of the present invention; and

[0034] Figure 6 is a flowchart of a method for designing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0036] The embodiments of the present invention change the wiring track to reduce the standard cell, increase the width of the power line, and at the same time improve or avoid the problem of electrical migration of the wiring, thereby reducing the height of the standard cell. Among them, the standard cell is a functional unit pre-designed from the component library. These functional units are generally rectangular in shape, with equal or almost equal heights, and different widths. Track (T for short) is the layout rule of the cell library; as a unit of measurement. The cell height of the standard cell library is basically fixed, which is convenient for the layout of the layout; the height is usually measured in T, that is, expressed in M2 track pitch, including integer standard cells, such as 7T, 9T and 12T, etc.; and non-integer standard cells, such as 6.75T, etc. The standard cell of the non-integer wiring track usually has a wiring deviation from the wiring track after flipping during the wiring process, which will cause wiring failure. For example, the standard cell of 6.75T is used as an example for explanation below.

[0037] In an embodiment of the present invention, a semiconductor device is formed in or on a substrate, and then a first metal layer and a second metal layer are formed in a dielectric layer above the semiconductor device to connect with the semiconductor device. Herein, the first metal layer and the second metal layer of the semiconductor device are designed as standard cells to reduce the design cycle.

[0038] Figure 1 1 is a diagram of a first layout pattern of a semiconductor device according to an embodiment of the present invention. Figure 1 , the semiconductor device includes a first layout pattern, the first layout pattern includes a first standard cell 100, the first standard cell 100 includes: a plurality of first signal lines 120, 122, 124, 126 and 128, arranged to be parallel to each other and the center of each first signal line is located on the corresponding first wiring track 1-5, for example, the center line of the first signal line coincides with the corresponding first wiring track or is located on the first wiring track; and two first power lines VDD 118 and VSS116, arranged in parallel on opposite sides of the plurality of first signal lines 120-128 and having the same width; and wherein the center lines of the two first power lines VSS and VDD are defined as boundaries 116 and 118 of the first standard cell. In an embodiment, the first layout pattern is a layout pattern of a second metal layer of the semiconductor device, wherein the second metal layer is located above the substrate. For example, the height of the standard cell is 6.75T, wherein half of the height of the standard cell is 0.216μm.

[0039] In this embodiment, by changing the number of routing tracks (including routing tracks 1-5), the center of the signal line is set on the routing track, and the center of the power lines on both sides can be set as the boundary of the standard cell. This reduced standard cell can increase the power width and make the signal line routing uniform, which can overcome the electromigration problem and routing problem in the prior art.

[0040] In the following, refer to Figure 2 , the layout pattern of the second metal layer of the semiconductor device is described in detail. The semiconductor device 200 includes a first layout pattern 250, the first layout pattern 250 includes a first standard cell, and the first standard cell includes: a plurality of first signal lines 222, 224, 226, 228 and 230, which are arranged to be parallel to each other and the center of each first signal line is located on the corresponding first wiring track 1-5; and two first power lines VDD and VSS, which are arranged in parallel on opposite sides of the plurality of first signal lines 222-228 and have the same width, wherein the center lines of the two first power lines VSS and VDD are defined as the edges of the first standard cell. The gap between each first power line and the adjacent first signal line is the same first distance; the gap between the adjacent two first signal lines in the plurality of first signal lines is the same second distance, and the first distance is greater than or equal to the second distance. For example, the gap between the first signal line 228 and the first signal line 230 is the second distance 232, and the gap between the power line VDD and the first signal line 230 is the first distance 234. The width of each first signal line is less than the width of the first power line.

[0041] The semiconductor device 200 further includes a second layout pattern 222, wherein the second layout pattern 222 includes a modified first standard cell, and the modified first standard cell is formed by turning the first standard cell upside down. The first wiring tracks 1-5 include an odd number of first wiring tracks, and the number of first signal lines is the same as the number of first wiring tracks. Specifically, different numbers of first signal lines or first wiring tracks can be set according to the size of the standard cell, an odd number greater than or equal to 5, for example, 5, 7, 9, etc. In one embodiment, the number of first signal lines and the number of first wiring tracks are both 5. Different numbers of first signal lines and first wiring tracks may also be included depending on the size of the standard cell. The second layout pattern is a layout pattern of a second metal layer of the semiconductor device, wherein the second metal layer is located above the substrate. In an embodiment, the first power line and the first signal line include a conductive material such as a metal, a metal composite material or other suitable material, wherein the conductive material is formed in one or more metallization layers by one or more processes of a physical vapor deposition process, a chemical vapor deposition process, a plating process or other suitable processes.

[0042] The semiconductor device 200 also includes a third layout pattern 254, the third layout pattern includes a second standard cell, and the second standard cell includes: an even number of second signal lines 202, 204, 206, 208, 210, 212, which are arranged to be parallel to each other and the center of each second signal line is located on a corresponding second wiring track 1-6. The third layout pattern is a layout pattern of a second metal layer of the semiconductor device, wherein the second metal layer is located above the substrate. Specifically, different numbers of second signal lines or second wiring tracks can be set according to the size of the standard cell, an odd number greater than or equal to 6, for example, 6, 8, 10, etc. Figure 2 , six second signal lines or second wiring tracks are shown, and the number of signal lines or wiring tracks in the second standard cell is increased by one compared to the number of signal lines or wiring tracks in the first standard cell.

[0043] Two second power lines VDD and VSS are respectively arranged on opposite sides of the even-numbered second signal lines 202-212 and have the same width, wherein the width of the first power line is greater than the width of the second power line and the center lines of the two second power lines are defined as the boundaries 240 and 244 of the second standard cell. For example, the width of the power lines VDD and VSS in the second standard cell is less than the width of the power lines VDD and VSS in the first standard cell. The gap between each second power line VDD or VSS and the adjacent second signal line 212 or 202 is the same third distance; the gap between the adjacent two second signal lines between the even-numbered second signal lines is the same fourth distance, wherein the third distance is greater than or equal to the fourth distance. For example, the gap between the second power line VDD and the adjacent second signal line 212 is the third distance 214 and the gap between the second signal line 212 and the second signal line 210 is the fourth distance 216, wherein the third distance 214 can be greater than or equal to the fourth distance 216.

[0044] The semiconductor device 200 further includes a fourth layout pattern 256, wherein the fourth layout pattern 256 includes a modified second standard cell, and the second standard cell flipped upside down is used as the modified second standard cell. The fourth layout pattern is a layout pattern of a second metal layer of the semiconductor device, wherein the second metal layer is located above the substrate. In an embodiment, the second power line and the second signal line include a conductive material such as a metal, a metal composite material, or other suitable material, wherein the conductive material is formed in one or more metallization layers by one or more processes of a physical vapor deposition process, a chemical vapor deposition process, a plating process, or other suitable processes.

[0045] In the following, reference will be made to the Figure 3 A layout pattern of another embodiment of a semiconductor device is described in detail. To avoid repetition, detailed descriptions of the same structures are omitted.

[0046] See attached Figure 3 , attached Figure 3 The semiconductor device in the embodiment includes three identical standard cells, and the other structures are similar to those in the embodiment of the present invention. Figure 2 The first metal layer is located below the second metal layer and above the substrate, and the centers of the power lines VSS304 and VDD302 of the first metal layer coincide with the power lines VSS 314 and VDD 312 in the second metal layer. The width of the first power lines VSS and VDD in the second metal layer is 70nm, and the width of the first power lines VSS and VDD in the first metal layer is 52nm. Therefore, according to an embodiment of the present invention, the wiring problem and the electromigration problem can be solved by increasing the width of the power lines VDD and VSS in the second metal layer, while increasing the uniformity of the wiring, making it easier to manufacture the semiconductor device, and ensuring the manufacturing accuracy and performance during the manufacturing process of the semiconductor device.

[0047] refer to Figure 4 , the semiconductor device 400 further includes a fifth layout pattern 410 located in the first metal layer, wherein the first layout pattern, the second metal layout pattern, the third metal layout pattern and the fourth metal layout pattern are located in the second metal layer above the first metal layer; the fifth layout pattern 410 includes a third standard cell, and the third standard cell includes: a plurality of conductive components, arranged on the first wiring track; two third power lines VDD and VSS, arranged on opposite sides of the plurality of conductive components in parallel with the first wiring track, wherein the width of the third power line is less than the width of the first power line and the center of the third power line overlaps with the center of the first power line. In an embodiment, the first metal layer and the second metal layer are both located above the substrate, a semiconductor device may be arranged in or above the substrate, and the first metal layer and the second metal layer are successively arranged above the semiconductor device to be electrically connected to the semiconductor device. In an embodiment, the power line includes a conductive material such as a metal, a metal composite material or other suitable material, wherein the conductive material is formed in one or more metallization layers by one or more processes of a physical vapor deposition process, a chemical vapor deposition process, a plating process or other suitable processes. In one embodiment, the conductive component is an element that can be connected to the components in the substrate and the signal line in the second metal layer through vertical interconnects (e.g., through holes). In one embodiment, the conductive component is a functional element transistor, diode, resistor, inductor, capacitor, etc., or a combination of one or more such devices. In another embodiment, the conductive component is a logic device, for example, various logic gates.

[0048] For example, refer to Figure 3 The width of the first power lines VSS and VDD in the second metal layer is 70nm, and the width of the first power lines VSS and VDD in the first metal layer is 52nm. The centers of the power lines VSS 304 and VDD 302 in the first metal layer coincide with the power lines VSS 314 and VDD 312 in the second gold layer.

[0049] refer to Figure 4 , the semiconductor device 400 further includes a sixth layout pattern 412 located in the first metal layer, wherein the sixth layout pattern 412 includes a modified third standard cell, and the third standard cell turned upside down is used as the modified third standard cell. In one embodiment of the present invention, when the difference between the fifth layout pattern and the sixth conductive layout pattern is that the pin position 402 of a conductive component in the sixth conductive layout pattern (for example, Figure 4 In another embodiment of the present invention, when the pin positions ZN or I in the third standard cell are different, the third standard cell (the pin position of the conductive component is located on the wiring track) turned upside down is used as a modified third standard cell (the pin position of the conductive component is also located on the wiring track), without creating a new standard cell used alone for the sixth conductive layout pattern. In another embodiment of the present invention, signal lines or components other than power lines VDD and VSS are arranged through wiring tracks. When the pin positions of the signal lines or conductive components are set on the wiring track, the pin positions of the signal lines or conductive components of the modified standard cell formed by flipping the standard cell are also set on the wiring track. This solves the technical problem that the pin position of the modified standard cell deviates from the wiring track. In another embodiment of the present invention, the pin position in the third standard cell is located on the wiring track, and the pin position 404 in the deformed third standard cell is also located on the wiring track, thereby solving the wiring fault caused by the pin position deviating from the wiring track in the prior art.

[0050] According to an embodiment of the present invention, a system including a semiconductor device is provided, including: a substrate; a semiconductor device arranged above the substrate; a first metal layer located above the semiconductor device and including a first layout pattern, wherein the first layout pattern includes a first standard unit, and the first standard unit includes: a plurality of first signal lines arranged parallel to each other and the center of each first signal line is located on a corresponding wiring track; and two first power lines arranged in parallel on opposite sides of the plurality of first signal lines and having the same width, wherein the center lines of the two first power lines are defined as the boundaries of the first standard unit.

[0051] Figure 6 is a flow chart of a method for designing a semiconductor device according to an embodiment of the present invention. Figure 6 A method for designing a semiconductor device is described in detail.

[0052] According to an embodiment of the present invention, a method 600 for designing a semiconductor device includes: in step 602, providing a plurality of first signal lines parallel to each other and setting the centers of the plurality of first signal lines on corresponding first wiring tracks; in step 604, setting two first power lines in parallel on opposite sides of the plurality of first signal lines; and in step 606, setting the two first power lines to have the same width to form a first layout pattern, wherein the center lines of the two first power lines are defined as the boundaries of the first standard cells.

[0053] Next, the first standard cell is modified and a second layout pattern is set according to the modified first standard cell. Specifically, the first standard cell is further modified to flip the first standard cell upside down. The gap between each first power line and the adjacent first signal line is the same first distance; the plurality of first signal lines are odd-numbered first signal lines, and the gaps between two adjacent first signal lines in the cardinal number of first signal lines are the same second distance, wherein the first distance is greater than or equal to the second distance, and the number of first wiring tracks is the same as the number of first signal lines.

[0054] The method for designing a semiconductor device also includes: providing an even number of second signal lines parallel to each other and setting the center of the even number of second signal lines on a second wiring track; setting two second power lines in parallel on opposite sides of the even number of second signal lines, wherein the width of the first power line is greater than the width of the second power line, the width of the odd number of first signal lines is the same as the width of the even number of second signal lines, and setting the two second power lines to have the same width to form a third layout pattern, wherein the center lines of the two second power lines are defined as the boundaries of the second standard cell. Specifically, the gap between each second power line and the adjacent second signal line is the same third distance; the gap between two adjacent second signal lines in the even number of second signal lines is a fourth distance, wherein the third distance is greater than or equal to the fourth distance. Flipping the second standard cell upside down and setting a fourth layout pattern based on the flipped second standard cell.

[0055] The two first power lines include a first VSS power line and a first VDD power line, and the widths of the first VSS power line and the first VDD power line are set to be greater than the widths of the plurality of first signal lines. For example, the widths of the power lines VDD and VSS in the first metal layer and the second metal layer are increased by 10%-20%. This solves the wiring and electromigration problems of the standard cell. In one embodiment, the first VDD line in the modified first standard cell is set to overlap the first VDD line in the first standard cell. In another embodiment, for example, the standard cell 502 is flipped upside down, and in the standard cell 502, the pin positions A1, A2, and ZN are all located on the wiring track, generating a modified standard cell 504, and in the standard cell 504, the pin positions A1, A2, and ZN are all located on the wiring track. In order to facilitate wiring, the power lines VDD and VSS can be interchanged (see Figure 5 ). Therefore, the wiring pins of the original standard cell and the modified standard cell are all located on the wiring track without any wiring pins deviating from the wiring track. This upside-down flipping can save design time, for example, 5% to 10% of design time.

[0056] The height of the standard cell can be designed according to actual needs. For example, the design of non-integer standard cells of other sizes is the same as the 6.75T standard cell described in this article. To avoid repetition, detailed descriptions of other standard cells are omitted in this article.

[0057] In an embodiment of the present invention, the wiring track of the standard cell is changed, for example, it is changed to a non-integer wiring track, and the reduced standard cell is designed according to the changed wiring track, for example, the other components and wires except the power line are designed according to the wiring track. By increasing the width of the power line in the reduced standard cell, the wiring offset wiring track and electromigration problems can be solved. In addition, during the design process, 5% to 10% of the design time can be saved by flipping the wiring cell. Since the conductive components and signal lines located between the power lines are designed according to the wiring track, the pin positions in the flipped standard cell are still located on the wiring track. Therefore, this wiring method can shorten the design cycle, and when the difference between the cells is only the wiring shape and the pin position, the semiconductor device can be designed according to the standard cell and its variants, thereby avoiding wiring failures where the designed pins are inaccessible.

[0058] The basic principles of the present invention are described above in conjunction with specific embodiments. However, it should be pointed out that a person skilled in the art can understand that all or any steps or components of the method and apparatus of the present invention can be implemented in any computing device (including a processor, storage medium, etc.) or a network of computing devices in the form of hardware, firmware, software, or a combination thereof. This can be achieved by a person skilled in the art using their basic programming skills after reading the description of the present invention.

[0059] Therefore, the purpose of the present invention can also be achieved by running a program or a group of programs on any computing device. The computing device can be a well-known general-purpose device. Therefore, the purpose of the present invention can also be achieved by simply providing a program product containing a program code that implements the method or device. In other words, such a program product also constitutes the present invention, and a storage medium storing such a program product also constitutes the present invention. Obviously, the storage medium can be any well-known storage medium or any storage medium developed in the future.

[0060] It should also be noted that in the apparatus and method of the present invention, it is obvious that each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present invention. In addition, the steps of performing the above series of processes can naturally be performed in chronological order according to the order of description, but do not necessarily need to be performed in chronological order. Some steps can be performed in parallel or independently of each other.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: The method comprises a first layout pattern, wherein the first layout pattern comprises a first standard cell, and the first standard cell comprises: a plurality of first signal lines arranged parallel to each other and spaced equally in a first direction, and a center of each first signal line is located on a corresponding first wiring track; and two first power lines arranged in parallel on opposite sides of the plurality of first signal lines, and the two first power lines have the same width in the first direction, the width of each first power line is greater than the width of each first signal line, and the long axes of the plurality of first signal lines and the long axes of the two first power lines extend in a second direction, and the second direction is different from the first direction; and wherein the interval between the two first power lines has a center line in the second direction, the center line is one of the first wiring tracks, the center of a corresponding first signal line is located on the center line, and the plurality of first signal lines are uniformly arranged between the two first power lines relative to the center line in the first direction, the plurality of first signal lines completely overlap each other in the first direction, and the center line of the two first power lines is defined as a boundary of the first standard cell; The semiconductor device further includes a second layout pattern located in the first metal layer, wherein the first layout pattern is located in a second metal layer above the first metal layer, the second layout pattern includes a second standard cell, and the second standard cell includes: A plurality of conductive components are arranged below the first wiring track; Two second power lines are arranged parallel to the first wiring track on opposite sides of the plurality of conductive components, wherein the width of the second power line is smaller than the width of the first power line and the center of the second power line overlaps with the center of the first power line.

2. The semiconductor device according to claim 1, wherein: The gap between each first power line and the adjacent first signal line is the same first distance; The gaps between two adjacent first signal lines among the plurality of first signal lines are both the same second distance, and the first distance is greater than or equal to the second distance.

3. The semiconductor device according to claim 1, wherein: The width of the first signal line is the same as the width of the second signal line.

4. The semiconductor device according to claim 3, wherein: Also included is a third layout pattern, The third layout pattern includes a modified first standard cell, which is formed by turning the first standard cell upside down.

5. The semiconductor device according to claim 1, wherein: The first wiring tracks include an odd number of first wiring tracks.

6. The semiconductor device according to claim 5, wherein: The number of the first signal lines is the same as the number of the first wiring tracks.

7. The semiconductor device according to claim 1, wherein: Also included is a fourth layout pattern located in the second metal layer, the fourth layout pattern includes a third standard cell, and the third standard cell includes: an even number of second signal lines, arranged to be parallel to each other and with the center of each second signal line located on a corresponding second wiring track; Two third power lines are respectively arranged on opposite sides of the even-numbered second signal lines and have the same width, wherein the width of the first power line is greater than that of the third power line and the center lines of the two third power lines are defined as the boundaries of the third standard unit.

8. The semiconductor device according to claim 7, wherein: The gap between each third power line and the adjacent second signal line is the same third distance; The gaps between two adjacent second signal lines among the even number of second signal lines are both the same fourth distance, wherein the third distance is greater than or equal to the fourth distance.

9. A method for designing a semiconductor device, characterized in that include: Providing the first layout pattern including a first standard cell, comprising: Providing a plurality of first signal lines that are parallel to each other and equally spaced in a first direction, wherein the centers of the plurality of first signal lines are arranged on corresponding first wiring tracks, and the long axes of the plurality of first signal lines and the long axes of the two first power lines extend in a second direction, the second direction being different from the first direction; Disposing two first power lines in parallel on opposite sides of the plurality of first signal lines, wherein the interval between the two first power lines has a center line in the second direction, the center line is one of the first wiring tracks, the center of a corresponding first signal line is located on the center line, and the plurality of first signal lines are evenly arranged between the two first power lines relative to the center line in the first direction, and the plurality of first signal lines completely overlap each other in the first direction; and Arranging the two first power lines to have the same width in the first direction to form a first layout pattern, the width of each first power line being greater than the width of each first signal line, wherein a center line of the two first power lines is defined as a boundary of a first standard cell; Providing a second standard cell of a second layout pattern located in the first metal layer, wherein the first layout pattern is located in a second metal layer above the first metal layer, and providing the second standard cell comprises: disposing a plurality of conductive members below the first routing track; and Two second power lines are arranged parallel to the first wiring track on opposite sides of the plurality of conductive components, wherein the width of the second power line is smaller than that of the first power line and the center of the second power line overlaps with the center of the first power line.

10. A system comprising a semiconductor device, comprising: substrate; A semiconductor device is disposed above the substrate; A first metal layer is located above the semiconductor device and includes a first layout pattern, wherein the first layout pattern includes a first standard cell, and the first standard cell includes: a plurality of first signal lines arranged parallel to each other and spaced apart at equal intervals in a first direction, the number of the plurality of first signal lines being an odd number, and the center of each first signal line being located on a corresponding wiring track; and two first power lines, arranged in parallel on opposite sides of the plurality of first signal lines, and the two first power lines have the same width in the first direction, the long axes of the plurality of first signal lines and the long axes of the two first power lines extend in a second direction, the second direction is different from the first direction, and the width of each of the first power lines is greater than the width of each of the first signal lines; and The interval between the two first power lines has a center line in the second direction, the center line is one of the wiring tracks, the center of a corresponding first signal line is located on the center line, and the plurality of first signal lines are uniformly arranged between the two first power lines relative to the center line in the first direction, the plurality of first signal lines completely overlap each other in the first direction, and the center line of the two first power lines is defined as a boundary of the first standard cell; the semiconductor device further includes a second layout pattern located in the second metal layer, wherein the first metal layer is located above the second metal layer, the second layout pattern includes a second standard cell, and the second standard cell includes: A plurality of conductive components are arranged below the first wiring track; Two second power lines are arranged parallel to the first wiring track on opposite sides of the plurality of conductive components, wherein the width of the second power line is smaller than the width of the first power line and the center of the second power line overlaps with the center of the first power line.

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