Preparation method of copper electroplating back contact heterojunction cell and heterojunction cell

Abstract

The invention relates to the technical field of heterojunction solar cells, and particularly discloses a preparation method of a copper electroplating back contact heterojunction cell and a heterojunction cell, and the method comprises the steps: depositing a first intrinsic amorphous silicon layer, a first phosphorus-doped silicon layer, a protection layer and a laser sacrificial layer on a backlight surface of a silicon wafer substrate, and forming a first groove in the backlight surface; then texturing, rounding and cleaning are carried out; a second intrinsic amorphous silicon layer and a boron-doped silicon layer are deposited on the backlight surface, and a second groove is formed between the two first grooves; after a transparent conductive thin film layer and a copper seed layer are sequentially deposited on the backlight surface, an ink layer is prepared, exposure, development and patterning are carried out, a copper grid line electrode is electroplated on the backlight surface, the ink layer and a part of the copper alloy seed layer are removed, a third groove is formed between the first groove and the second groove to separate the transparent conductive thin film layer, and the copper grid line back contact heterojunction cell is obtained. According to the method, texturing and copper grid line manufacturing are combined, the process steps are few, the width of the copper grid line is flexible, adjustable and finer, and the photoelectric conversion efficiency and the production yield of the heterojunction solar cell are improved.

Description

Technical Field

[0001] The present application relates to the technical field of heterojunction solar cells, and in particular to a method for preparing a copper electroplated back-contact heterojunction cell and a heterojunction cell. Background Art

[0002] In recent years, back-contact heterojunction cells have the dual advantages of large short-circuit current and high open-circuit voltage due to the absence of metal grid lines on the front and the introduction of high-quality surface passivation of amorphous silicon thin films. This makes back-contact heterojunction solar cells have the dual advantages of large short-circuit current and high open-circuit voltage, representing the highest photoelectric conversion efficiency level of crystalline silicon solar cells. However, since the positive and negative electrodes of the battery are both on the back, the need to prepare positive and negative electrodes with interdigitated spacing has become a difficulty in the preparation process, and there is currently no unified solution.

[0003] At the same time, in the field of back-contact heterojunction batteries, copper paste has more advantages than silver paste in preparing gate lines (for example: the photogenerated carriers generated by the silicon wafer substrate, whether electrons or holes, are transported to the bottom electrode, which puts higher requirements on the contact and recombination of the silver paste, and the back alkaline polishing makes the suede surface flat and the contact resistance increases, which puts higher requirements on the conductivity of the silver paste. Secondly, the back gate line has lower requirements for light shielding. Considering that the larger the electrode area, the more conducive to current output, in this case, the silver paste consumption is large and the cost is high). Therefore, the use of copper paste to prepare gate lines in the preparation of back-contact heterojunction batteries has become a hot research topic in the industry.

[0004] However, compared with the preparation of silver grid lines by screen printing of silver paste, the preparation of copper grid lines in back-contact heterojunction cells requires multiple process steps and high requirements, and its preparation process is more complicated. In addition, due to the structural complexity of the back-contact heterojunction cell itself and the many preparation process steps, especially the positive and negative electrodes of the cell are both on the back, there is no good solution in the relevant technology for effectively combining the preparation of copper grid lines with other preparation processes of back-contact heterojunction cells to reduce the process steps, and to achieve flexible and adjustable copper grid line width and finer precision to improve the photoelectric conversion efficiency and production yield of heterojunction solar cells. Summary of the invention

[0005] The present application aims to at least solve the problems in the prior art of copper grid line back contact heterojunction cells, such as many process steps and high requirements, difficulty in controlling the copper grid line width, low photoelectric conversion efficiency and production yield of heterojunction solar cells, and high production cost. Therefore, the present application proposes a preparation method for a copper electroplated back contact heterojunction cell and a heterojunction cell.

[0006] In order to achieve the above objectives, in a first aspect, the present application provides a method for preparing a copper electroplated back-contact heterojunction battery, comprising: Obtaining a silicon wafer substrate, and sequentially depositing a first intrinsic amorphous silicon layer, a first phosphorus-doped silicon layer, a protective layer, and a laser sacrificial layer on a backlight surface of the silicon wafer substrate to form an N-type conductive region; A first segmented laser is used to ablate the surface of the N-type conductive region until a portion of the surface of the silicon wafer substrate is exposed to form a first groove; Using potassium hydroxide solutions of the first concentration, potassium hydroxide solutions of the second concentration and hydrofluoric acid aqueous solution of the first concentration in sequence to texturize, round and clean the slotted silicon wafer to obtain a first silicon wafer intermediate; Depositing a second intrinsic amorphous silicon layer and a boron-doped silicon layer on the backlight surface of the first silicon wafer intermediate in sequence, and using a second laser to ablate the area between every two of the first grooves after deposition until the surface of the protective layer is partially exposed to form a second groove; The silicon wafer after the second groove is formed is cleaned with a hydrofluoric acid aqueous solution of a second concentration, and a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer are sequentially deposited on the light-receiving surface of the silicon wafer after cleaning to obtain a third silicon wafer intermediate; Depositing a transparent conductive film layer and a copper alloy seed layer on the backlight surface of the third silicon wafer intermediate in sequence, exposing and developing the metal grid lines to pattern them, and then using the remaining ink as a mask to electroplate copper grid line electrodes in the metal grid line patterning areas in the first groove and the second groove adjacent to the backlight surface to obtain a fourth silicon wafer intermediate; Using a wet solution to remove the remaining ink layer and the copper alloy seed layer from the fourth silicon wafer intermediate to obtain a fifth silicon wafer intermediate; ablating the area between the first groove and the second groove of the fifth silicon wafer intermediate by a third laser until the surface of the boron-doped silicon layer is partially exposed to form a third groove, thereby obtaining a copper grid line back contact heterojunction battery; In some possible embodiments, the silicon wafer substrate is a clean N-type doped single crystal or polycrystalline silicon wafer after cleaning, with a thickness of 80um-160um, the first intrinsic amorphous silicon thin film layer has a thickness of 2nm-12nm and a refractive index of 3.2-4.8, and the first phosphorus-doped silicon layer has a thickness of 4nm-30nm and a refractive index of 1.8-4.

[0007] In some possible embodiments, the protective layer is one of a silicon oxide film layer, a silicon nitride film layer, a silicon oxynitride film layer or an aluminum oxide film layer, the protective layer has a film thickness of 20nm-150nm, a refractive index of 1.4-3.5, and the laser sacrificial layer has a thickness of 5nm-50nm, and a refractive index of 3-5. In some possible embodiments, the first laser is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser; the second laser is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser; the third laser is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser; wherein the laser wavelength is 200nm-500nm, the frequency is 10 12 HZ-10 19 HZ.

[0008] In some possible embodiments, the first concentration potassium hydroxide solution, the second concentration potassium hydroxide solution and the first concentration hydrofluoric acid aqueous solution are used to texturize, round and clean the slotted silicon wafer in sequence to obtain the first silicon wafer intermediate, including: Using a potassium hydroxide solution with a concentration of 1%-10% to perform a texturing treatment on the silicon wafer substrate after the deposition and grooving; The silicon wafer substrate after texturing is cleaned again with a potassium hydroxide solution having a concentration of 0.5% to 5%, so that the top and bottom of the velvet pyramid are rounded; The rounded silicon wafer substrate is cleaned and dried with a hydrofluoric acid aqueous solution having a concentration of 1% to 8% to obtain a first silicon wafer intermediate.

[0009] In some possible embodiments, a second intrinsic amorphous silicon layer and a boron-doped silicon layer are sequentially deposited on the backlight surface of the first silicon wafer intermediate, and a second laser is used to ablate the area between every two of the first grooves after deposition until the surface of the protective layer is exposed to form a second groove, including: the second intrinsic amorphous silicon layer has a thickness of 3 nm-17 nm and a refractive index of 3.2-4.8; the boron-doped silicon layer has a thickness of 5nm-40 nm and a refractive index of 2-5, and the boron-doped silicon layer is one of an amorphous silicon thin film layer, a microcrystalline silicon thin film layer or an oxygen-doped microcrystalline silicon thin film layer.

[0010] In some possible embodiments, the method of using a hydrofluoric acid aqueous solution of a second concentration to clean the silicon wafer after the second groove is formed, and sequentially depositing a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer on the light-receiving surface of the silicon wafer after cleaning to obtain a third silicon wafer intermediate includes: Using a hydrofluoric acid aqueous solution with a concentration of 1% to 10% to clean the silicon wafer after the second groove is formed, so as to remove silicon oxide generated on the silicon wafer substrate and a protective layer in the second groove; A third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer are sequentially deposited on the light-receiving surface of the cleaned silicon wafer, wherein the third intrinsic amorphous silicon layer has a thickness of 3nm-15nm and a refractive index of 3-5, the second phosphorus-doped silicon layer has a thickness of 4nm-30nm and a refractive index of 2.2-4.5, and the anti-reflection layer has a thickness of 70nm-150nm and a refractive index of 1.2-3.

[0011] In some possible embodiments, the step of sequentially depositing a transparent conductive film layer and a copper alloy seed layer on the backlight surface of the third silicon wafer intermediate, preparing an ink layer based on the area between the first groove and the second groove adjacent to the backlight surface after deposition, and electroplating a copper grid line electrode on the backlight surface to obtain a fourth silicon wafer intermediate includes: Anti-electroplating ink is screen-printed on the surface of the copper alloy seed layer, and the ink in the first groove and the second groove is removed by exposure and development until the copper alloy seed layer is partially exposed, so that an ink layer is formed in the area between the first groove and the second groove, thereby achieving preliminary patterning of the copper metal grid line.

[0012] In some possible embodiments, the transparent conductive film layer and the copper alloy seed layer are sequentially deposited on the backlight surface of the third silicon wafer intermediate, an ink layer is prepared based on the area between the first groove and the second groove adjacent to the backlight surface after deposition, and a copper grid line electrode is electroplated on the backlight surface to obtain a fourth silicon wafer intermediate, further comprising: The ink layer between the first groove and the second groove has a width of 5um-15um and a height of 5um-15um; Using the ink layer as a mask, copper grid line electrodes with a width of 10um-30um and a height of 5um-15um are generated in the first groove and the second groove based on an electroplating process.

[0013] The above technical solution has at least the following advantages or beneficial effects compared with the prior art: 1) When preparing a copper grid line back contact heterojunction battery, a laser sacrificial layer and a protective layer are prepared in advance. The laser sacrificial layer and the protective layer are selected from specific refractive index materials and are set to a specific thickness. The laser sacrificial layer can absorb the laser and reduce the damage of the laser to the N-type conductive area. It can also serve as a wet etching mask for the subsequent insulating protective layer. By selecting a laser with a specific wavelength and frequency, the copper grid line width can be flexibly adjusted and finer during the grooving process. At the same time, the problem of laser penetrating the protective layer and damaging the passivation effect of the intrinsic amorphous silicon layer is avoided, thereby improving the photoelectric conversion efficiency and production yield of the heterojunction solar cell.

[0014] 2) In order to improve the quality and photoelectric conversion efficiency of copper grid line back contact heterojunction solar cells, before the third intrinsic amorphous silicon layer, the second phosphorus-doped silicon layer and the anti-reflection layer are deposited on the light-receiving surface of the silicon wafer substrate by PECVD, the silicon oxide on the light-receiving surface of the silicon wafer substrate is removed by using a hydrofluoric acid aqueous solution in a concentration range of 1%-10%. At the same time, due to the special setting of the step, the protective layer in the second groove is exposed in this step, and the preparation material of the protective layer will react with the hydrofluoric acid aqueous solution. In this way, the protective layer in the second groove can be removed while cleaning, which reduces the process steps of the back contact heterojunction solar cell and improves the production efficiency of the back contact heterojunction cell.

[0015] 3) A third groove is opened in the transparent conductive film layer between the first groove and the second groove using a laser process. The third groove directly blocks the lateral conduction between the N conductive area and the P conductive area, avoiding the generation of leakage current and the result of lower battery photoelectric conversion efficiency, thereby improving the production yield of copper electroplated back-contact heterojunction solar cells.

[0016] 4) An intrinsic amorphous silicon layer is deposited on the silicon wafer substrate to passivate the dangling bonds on the silicon wafer surface, reduce the surface defect state density, and improve the photoelectric conversion efficiency of the battery; secondly, the laser sacrificial layer can absorb the laser, reduce the damage of the laser to the N-type conductive area, and can also serve as a wet etching mask for the subsequent insulating protective layer; and the existence of the protective layer can isolate the N-type conductive area and the P-type conductive area to prevent battery leakage; at the same time, the protective layer can protect the bottom layer from subsequent etching by alkaline solution; secondly, it can also effectively reflect the laser in this band to avoid laser damage to the passivation performance of the intrinsic amorphous silicon, resulting in lower battery efficiency.

[0017] In a second aspect, the present application also provides a copper electroplating back-contact heterojunction battery, which is prepared by the preparation method of the copper electroplating back-contact heterojunction battery provided in any one of the first aspects above.

[0018] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0019] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flow chart of a method for preparing a copper electroplated back-contact heterojunction battery according to an embodiment of the present application; Figure 2 It is a schematic diagram of the first cell structure in the preparation process of the copper grid back contact heterojunction solar cell according to the embodiment of the present application; Figure 3 It is a schematic diagram of the second cell structure in the preparation process of the copper grid line back contact heterojunction solar cell according to the embodiment of the present application; Figure 4 It is a schematic diagram of the third cell structure in the preparation process of the copper grid line back contact heterojunction solar cell according to the embodiment of the present application; Figure 5 It is a schematic diagram of the fourth cell structure in the preparation process of the copper grid line back contact heterojunction solar cell according to the embodiment of the present application; Figure 6 It is a schematic diagram of the fifth cell structure in the preparation process of the copper grid line back contact heterojunction solar cell according to the embodiment of the present application; Figure 7 It is a schematic diagram of the sixth cell structure in the preparation process of the copper grid back contact heterojunction solar cell according to an embodiment of the present application; Figure 8 It is a schematic diagram of the seventh cell structure in the preparation process of the copper grid line back contact heterojunction solar cell according to the embodiment of the present application; Fig. 9 It is a schematic diagram of the eighth cell structure in the preparation process of the copper grid back contact heterojunction solar cell according to the embodiment of the present application; Fig.10 It is a schematic diagram of the ninth cell structure in the preparation process of the copper grid back contact heterojunction solar cell according to an embodiment of the present application; Fig.11 It is a schematic diagram of the tenth cell structure in the preparation process of the copper grid line back contact heterojunction solar cell according to the embodiment of the present application; Fig.12 It is a schematic diagram of the eleventh cell structure in the preparation process of the copper grid line back contact heterojunction solar cell according to the embodiment of the present application; Fig.13 It is a schematic diagram of the twelfth cell structure in the preparation process of the copper grid back contact heterojunction solar cell according to an embodiment of the present application; Fig.14 is a schematic diagram of the thirteenth cell structure in the preparation process of the copper grid back contact heterojunction solar cell according to an embodiment of the present application; Fig.15 It is a schematic diagram of the structure of the fourteenth cell in the preparation process of the copper grid line back contact heterojunction solar cell according to the embodiment of the present application; Reference numerals: 00, silicon wafer substrate; 11, first intrinsic amorphous silicon layer; 12, first phosphorus-doped silicon layer; 13, protective layer; 14. laser sacrificial layer; 15. first trench; 21. second intrinsic amorphous silicon layer; 22. boron-doped silicon layer; 23. second trench; 24. a third intrinsic amorphous silicon layer; 25. a second phosphorus-doped silicon layer; 26. an anti-reflection layer; 31. Transparent conductive film layer; 32. Copper alloy seed layer; 33. Ink layer; 41. Copper grid electrode; 42. Anti-oxidation layer; 43. Third groove. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0025] See also Figures 1 to 15 This embodiment provides a method for preparing a copper electroplating back contact heterojunction battery, comprising: Step S100: obtaining a silicon wafer substrate, and sequentially depositing a first intrinsic amorphous silicon layer, a first phosphorus-doped silicon layer, a protective layer, and a laser sacrificial layer on the backlight surface of the silicon wafer substrate to form an N-type conductive region; like Figure 2 As shown, in this step, since the rough silicon wafer substrate surface is often accompanied by contamination and cutting damage, it must first undergo a tank solution pre-cleaning before use to remove organic contamination and large particles on the surface, and then use alkaline solution for double-sided polishing to remove the surface cutting damage layer, and then perform RCA cleaning (or other solution formulas equivalent to RCA cleaning), and finally use HF solution to remove the surface oxide layer, and then clean with deionized water and dry to obtain a silicon wafer substrate 00 with a clean surface.

[0026] It should be noted that, in the process of double-sided polishing and cleaning the rough silicon wafer substrate in sequence, the acid or alkaline solution used, if the alkaline solution is used, can be a sodium hydroxide solution or a potassium hydroxide solution, etc., if the acid solution is used, it can be an acid mixture, such as a mixture of citric acid, sulfuric acid, etc. The specific selection and concentration setting can be considered according to actual needs and are not limited here; Optionally, the thickness of the clean silicon wafer substrate 00 after cleaning is in the range of 80um-160um, and the specific thickness can be selected according to actual needs; After the silicon wafer substrate is cleaned, the first intrinsic amorphous silicon layer 11, the first phosphorus-doped silicon layer 12 and the protective layer 13 are prepared by PECVD, wherein the power supply of the PECVD equipment adopts one of 13.56 MHz, 26 MHz or 40 MHz, preferably 13.56 MHz.

[0027] Optionally, the process gas of the first intrinsic amorphous silicon layer 11 is a combination of silane (SiH4), hydrogen (H2), and carbon dioxide (CO2), with a thickness of 2-12 nm and a refractive index of 3.2-4.8. The first intrinsic amorphous silicon layer 11 can passivate dangling bonds on the surface of the silicon wafer and reduce the surface defect state density.

[0028] Optionally, the first phosphorus-doped silicon layer 12 is one or more of an amorphous layer, an oxygen-doped microcrystalline layer and a non-oxygen-doped microcrystalline layer, and its process gas includes several combinations of silane (SiH4), hydrogen (H2), carbon dioxide (CO2), and phosphine (PH3), with a thickness of 4-30 nm and a refractive index of 1.8-4. The presence of the first doped silicon layer 12 can provide a field passivation effect for the surface and improve the conversion efficiency of the battery.

[0029] In some embodiments, the protective layer 13 is made of one of a silicon oxide film layer, a silicon nitride film layer, a silicon oxynitride film layer or an aluminum oxide film layer. The protective layer has a film thickness of 20-150 nm and a refractive index of 1.4-3.5. The protective layer 13 can isolate the N-type conductive area and the P-type conductive area to prevent leakage of the battery. At the same time, the protective layer 13 can protect the bottom layer from subsequent etching with alkaline solution. Secondly, the protective layer 13 can reflect excess laser energy without being etched by the laser, thereby avoiding damage to the first intrinsic amorphous silicon layer 11 and the first phosphorus-doped silicon layer 12 of the silicon wafer substrate.

[0030] In some embodiments, the laser sacrificial layer 14 is an amorphous silicon layer with a thickness of 5nm-50nm and a refractive index of 3-5. The laser sacrificial layer can absorb the laser and reduce the damage of the laser to the N-type conductive region. It can also serve as a wet etching mask for the subsequent insulating protective layer. It can be understood that an N-type conductive region is formed after the first intrinsic amorphous silicon layer 11, the first phosphorus-doped silicon layer 12, the protective layer 13 and the laser sacrificial layer 14 are deposited on the backlight surface of the silicon wafer substrate 00; the above-mentioned deposition conditions and principles of each layer can be realized by the prior art and will not be elaborated here, and the selection of the thickness and refractive index of each layer and the number of deposition layers and the material setting of each layer are the key points of the technical solution of this embodiment. For example, the setting of the first intrinsic amorphous silicon layer 11 passivates the dangling bonds on the surface of the silicon wafer substrate and reduces the surface defect state density. The setting of the first phosphorus-doped silicon layer 12 further provides a field passivation effect on the surface to improve the battery conversion efficiency. By setting the protective layer 13 and combining the subsequent steps with a wavelength of 200nm-500nm and a frequency of 10 12 HZ-10 19 When the laser ablates a groove in the HZ band, the protective layer 112 can effectively reflect the laser in this band, thereby preventing the laser from damaging the intrinsic amorphous silicon and causing the passivation effect to reduce the cell conversion efficiency.

[0031] Step S200: using a segmented first laser to ablate the surface of the N-type conductive region until a portion of the surface of the silicon wafer substrate is exposed to form a first groove; In this step, if Figure 2 As shown, the first laser process is used to vertically remove the amorphous silicon layer 11, the first phosphorus-doped silicon layer 12, the protective layer 13 and the laser sacrificial layer 14 part of the structure to form the first trench 15, that is, to form the opening area of ​​the P-type conductive region, wherein the multiple laser processes can effectively reduce the edge passivation loss. The first intrinsic amorphous silicon layer 11 and the first phosphorus-doped silicon layer 12 covered under the protective layer 13 constitute the N-type conductive region.

[0032] It should be noted that the first laser can be one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser, and the specific selection can be made according to actual needs.

[0033] It should also be noted that the laser wavelength selection range is 200nm-500nm, and the frequency is 10 12 Hz-10 19 Hz, the reason for choosing this wavelength and frequency of laser is that it is selected by comprehensively considering the properties of the three-layer thin film deposited on the silicon wafer substrate; if other types of lasers are used, they will penetrate the protective layer 13 and damage the passivation effect of the intrinsic amorphous silicon, which will lead to a decrease in the battery conversion efficiency. In addition, if other types of lasers are used, they may penetrate the silicon nitride and damage the passivation effect of the intrinsic amorphous silicon, which will lead to a decrease in the battery conversion efficiency. That is, choosing this wavelength and frequency of laser can avoid the problem of the laser penetrating the protective layer and then damaging the passivation effect of the intrinsic amorphous silicon layer.

[0034] Optionally, the opening width of the first groove 15 is 30um-300um, and the interval between every two adjacent first grooves is 10um-100um. The specific values ​​can be selected according to actual needs and are not limited here.

[0035] Step S300: using potassium hydroxide solutions of the first concentration, potassium hydroxide solutions of the second concentration and hydrofluoric acid aqueous solution of the first concentration to sequentially texturize, rounden and clean the slotted silicon wafer to obtain a first silicon wafer intermediate; In this step, if Figure 4 As shown, the silicon wafer after the first groove 15 is opened is wet cleaned, and the process is as follows: Step S310: Use a potassium hydroxide solution with a concentration of 1%-10% to perform a texturing treatment on the light-receiving surface of the silicon wafer substrate 00 and the silicon wafer substrate 00 under the first groove 15. The silicon wafer is formed into a velvet surface with a pyramid structure from the polished surface, which can reduce the reflectivity of the silicon wafer. The design of the velvet pyramid can increase the area of ​​the light-receiving surface, thereby achieving the purpose of improving battery efficiency.

[0036] Step S320: Use a potassium hydroxide solution with a concentration of 0.5%-5% to clean the silicon wafer after texturing, so that the top and bottom of the velvet pyramid are rounded; the pyramid is etched slightly rounded due to the effect of the diluted alkali solution, which is more conducive to subsequent surface passivation and improves battery efficiency.

[0037] Step S330: Clean with a hydrofluoric acid aqueous solution having a concentration of 1%-8% and then dry. The hydrofluoric acid aqueous solution removes trace silicon oxide generated on the surface. It should be noted that the above steps are all carried out in the same wet cleaning equipment to simplify the battery process.

[0038] It can be understood that the first concentration of potassium hydroxide solution and the second concentration of potassium hydroxide solution are one of the concentrations in the above concentration range, and the first concentration of hydrofluoric acid aqueous solution is one of the concentrations in the above concentration range. The specific concentrations can be selected according to actual needs and will not be elaborated here.

[0039] Step S400: sequentially depositing a second intrinsic amorphous silicon layer and a boron-doped silicon layer on the backlight surface of the first silicon wafer intermediate, and using a second laser to ablate the area between every two of the first grooves after deposition until the surface of the protective layer is partially exposed to form a second groove; In this step, see Figures 5 to 7 A second intrinsic amorphous silicon layer 21 and a boron-doped silicon layer 22 are deposited on the backlight surface in the middle of the first silicon wafer by PECVD to form a P-type conductive area, wherein the power supply of the PECVD equipment adopts one of 13.56MHz, 26MHz or 40MHz, preferably 13.56MHz.

[0040] Optionally, the purpose of the second intrinsic amorphous silicon layer 21 is to passivate the surface dangling bonds of the silicon wafer in the first groove 15 and reduce the surface defect state density. The process gas includes all or several combinations of silane (SiH4), hydrogen (H2), and carbon dioxide (CO2). The thickness of the second intrinsic amorphous silicon layer 21 is 3nm-15nm, and the refractive index is between 3-5, which can be selected according to actual needs.

[0041] Optionally, the boron-doped silicon layer 22 can be one of an amorphous silicon thin film layer, a microcrystalline silicon thin film layer or an oxygen-doped microcrystalline silicon thin film layer, and its process gas is a combination of silane (SiH4), hydrogen (H2), carbon dioxide (CO2), and borane (B2H6). The boron-doped silicon layer 22 forms a PN junction with the N-type silicon wafer substrate and serves as the emitter of the battery. The thickness of this film is 5nm-60nm, and the refractive index is between 2.5-4.5.

[0042] In some embodiments, a second laser etching process is used between every two first trenches on the backlight side of the silicon wafer to remove the boron-doped silicon layer 22 , the second intrinsic amorphous silicon layer 21 , and the laser sacrificial layer 14 to expose the N-type conductive region.

[0043] It should be noted that the wavelength range of the laser is 200nm-500nm, the laser is a flat-top laser, and the type is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser, preferably ultraviolet picosecond laser; due to the presence of the protective layer 13, the laser etching depth can reach the surface of the protective layer 13.

[0044] Optionally, there is a non-grooved area of ​​15um-50um between the first groove 15 and the second groove 23 opened by the laser, and the specific value can be selected according to actual needs.

[0045] After deposition and grooving, the second trench 23 and the silicon wafer substrate 00 are cleaned with a hydrofluoric acid aqueous solution in a concentration range of 1%-10% to remove the protective layer 13 in the second trench 23 and the silicon oxide generated by the silicon wafer substrate 00, so that the N-type conductive area in the second trench 23 leaks out.

[0046] Step S500: using a hydrofluoric acid aqueous solution of a second concentration to clean the silicon wafer after the second groove is formed, and after cleaning, sequentially depositing a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer on the light-receiving surface of the silicon wafer to obtain a third silicon wafer intermediate; In this step, if Figure 8 As shown, a third intrinsic amorphous silicon layer 24, a second phosphorus-doped silicon layer 25 and an anti-reflection layer 26 are deposited on the light-receiving surface of the silicon wafer by PECVD. The power supply of the PECVD equipment adopts one of 13.56 MHz, 26 MHz or 40 MHz, preferably 13.56 MHz.

[0047] Optionally, the purpose of the third intrinsic amorphous silicon layer 24 is to passivate the dangling bonds on the light-receiving surface of the silicon wafer and reduce the surface defect state density. The process gas includes all or several combinations of silane (SiH4), hydrogen (H2), and carbon dioxide (CO2). The thickness of the third intrinsic amorphous silicon layer 24 is 3nm-15nm, and the refractive index is between 3-5. The specific selection can be made according to actual needs.

[0048] Optionally, the second phosphorus-doped silicon layer 25 is one or more of an amorphous layer, an oxygen-doped microcrystalline layer and a non-oxygen-doped microcrystalline layer, and its process gas includes several combinations of silane (SiH4), hydrogen (H2), carbon dioxide (CO2), and phosphine (PH3). The thickness is 4-30 nm, and the refractive index is between 2.2-4.5. The specific selection can be made according to actual needs. The presence of the second doped silicon layer 25 can provide a field passivation effect for the surface and improve the conversion efficiency of the battery.

[0049] Optionally, the anti-reflection layer 26 may be one or more of silicon nitride, silicon oxide, silicon oxynitride and aluminum oxide, and is not limited here. Preferably, it is a silicon nitride film with a thickness of 70-150 nm and a refractive index of 1.2-3.

[0050] Step S600: depositing a transparent conductive film layer and a copper alloy seed layer on the backlight surface of the third silicon wafer intermediate in sequence, preparing ink on the backlight surface after deposition, exposing and developing to remove the ink on the first groove and the second groove, exposing the gate electrode pattern and then electroplating to generate a copper gate electrode, thereby obtaining a fourth silicon wafer intermediate; In this step, if Figures 9 to 12 As shown, magnetron sputtering or reactive plasma is used to deposit the transparent conductive film layer 31 and the copper alloy seed layer 32. The material of the transparent conductive film 31 can be an indium oxide film doped with tin oxide, tungsten oxide, titanium oxide, thallium oxide, and gallium oxide, wherein indium oxide is the main material, with a weight ratio of more than 90%, preferably an indium oxide (ITO) film doped with tin oxide, and the main material of the target material used can also be an indium-free oxide target such as tin oxide and zinc oxide.

[0051] Optionally, the transparent conductive film 31 has a thickness of 50-150 nm and a refractive index of 1.5-3.0. The main material of the copper alloy seed layer 32 is copper, and the doping element can be one or more of manganese, zirconium, tungsten, aluminum, silver, titanium, and gold, which can be selected according to actual needs.

[0052] In some embodiments, ink with a width of 5-40 um and a height of 3-20 um is added between the first groove 15 and the second groove 23 by screen printing and exposure and development, anti-plating ink is screen printed on the surface of the copper alloy seed layer 32, and the ink in the first groove 15 and the second groove 23 is removed by exposure and development until part of the copper alloy seed layer 32 is leaked, so that an ink layer 33 is formed in the area between the first groove 15 and the second groove 32. like Fig.14 As shown, with the ink layer 33 as a mask, a copper grid electrode 41 is grown on the back of the battery by electroplating, wherein the copper grid width is 10-30 um, the height is 5-15 um, the grid width is 35%-45%, and the grid shape is a positive trapezoid.

[0053] Step S700: removing the remaining ink layer and the copper alloy seed layer from the fourth silicon wafer intermediate using a wet solution to obtain a fifth silicon wafer intermediate; In this step, if Fig.14 As shown, an alkaline solution is used to remove the electroplated ink layer 33 on the back, and the copper grid electrode 41 is used as a mask to remove the remaining copper alloy seed layer 32 on the back. The concentration of sulfuric acid in the copper removal solution is 0.1-10%, and the concentration of potassium persulfate solution is 0.1-10%. In order to avoid oxidation of metallic copper, a tin anti-oxidation layer 42 with a thickness of 0.1um-5um is formed on the surface of the copper electrode by chemical replacement reaction, and finally a copper grid back contact heterojunction battery is obtained, wherein the concentration of divalent tin ions in the tin solution is 0-40g / L.

[0054] Step S800: ablating the area between the first groove and the second groove of the fifth silicon wafer intermediate by a third laser until the surface of the boron-doped silicon layer is partially exposed to form a third groove, thereby obtaining a copper grid line back contact heterojunction battery; In this step, if Fig.15 As shown, wet etching and laser process are used between the first groove 15 and the second groove 23 to remove the transparent conductive film layer 31, and a third groove 43 is opened; the third groove 43 directly cuts off the lateral conduction between the N conductive area and the P conductive area, avoiding the generation of leakage current and the result of lower cell photoelectric conversion efficiency, thereby improving the production yield of copper electroplating back contact heterojunction solar cells. It should be noted that the third laser is: the wavelength range of the laser is 200nm-500nm, the laser is a flat-top laser, and the type is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser, preferably ultraviolet femtosecond laser.

[0055] In the above method steps, when preparing a copper grid line back contact heterojunction battery, a laser sacrificial layer and a protective layer are prepared in advance. The laser sacrificial layer and the protective layer select specific refractive index materials and are set to a specific thickness. The presence of the laser sacrificial layer can reduce the damage of the laser to the N-type conductive area, and can also serve as a wet etching mask for the subsequent insulating protective layer. By selecting a laser with a specific wavelength and frequency, during the grooving process, the copper grid line width can be flexibly adjusted and more refined, and at the same time, the problem of laser penetrating the protective layer and then damaging the passivation effect of the intrinsic amorphous silicon layer is avoided, thereby improving the photoelectric conversion efficiency and production yield of the heterojunction solar cell.

[0056] Furthermore, in order to improve the quality and photoelectric conversion efficiency of copper grid line back contact heterojunction solar cells, before depositing the third intrinsic amorphous silicon layer, the second phosphorus-doped silicon layer and the anti-reflection layer on the light-receiving surface of the silicon wafer substrate by PECVD, the silicon oxide on the light-receiving surface of the silicon wafer substrate is removed by using a hydrofluoric acid aqueous solution in a concentration range of 1%-10%. At the same time, due to the special setting of the step, the step just exposes the protective layer in the second groove, and the preparation material of the protective layer will react with the hydrofluoric acid aqueous solution. In this way, the protective layer in the second groove can be removed while cleaning, thereby reducing the process steps of the back contact heterojunction solar cell and improving the production efficiency of the back contact heterojunction cell.

[0057] At the same time, a third groove is opened between the first groove and the second groove by using a laser process to remove the transparent conductive film layer. The third groove directly blocks the lateral conduction between the N conductive area and the P conductive area, avoiding the generation of leakage current and the result of lower battery photoelectric conversion efficiency, thereby improving the production yield of copper electroplated back-contact heterojunction solar cells.

[0058] In addition, an intrinsic amorphous silicon layer is deposited on the silicon wafer substrate to passivate the dangling bonds on the silicon wafer surface, reduce the surface defect state density, and improve the photoelectric conversion efficiency of the battery; secondly, the laser sacrificial layer can absorb the laser, reduce the damage of the laser to the N-type conductive area, and can also serve as a wet etching mask for the subsequent insulating protective layer; and the existence of the protective layer can isolate the N-type conductive area and the P-type conductive area, which can prevent battery leakage, and can also effectively reflect the laser in this band, avoiding laser damage to the passivation performance of the intrinsic amorphous silicon, resulting in lower battery efficiency.

[0059] In some embodiments, a copper grid line back contact heterojunction battery is further provided. The copper grid line back contact heterojunction battery is prepared by the preparation method of a copper electroplating back contact heterojunction battery described in any of the above embodiments. The back contact heterojunction battery comprises: The silicon wafer substrate 00 comprises a first intrinsic amorphous silicon layer 11 and a first phosphorus-doped silicon layer 12 arranged on the backlight side of the silicon wafer substrate to form an N-type conductive region; a protective layer 13 and a sacrificial layer 14 arranged on the N-type conductive region; a second intrinsic amorphous silicon layer 21 and a boron-doped silicon layer 22 arranged on the backlight side of the silicon wafer substrate to form a P-type conductive region; a transparent conductive film layer 31, a copper alloy seed layer 32 and a copper gate electrode 41 arranged on the N-type conductive region and the P-type conductive region; and a third intrinsic amorphous silicon layer 23, a second phosphorus-doped silicon layer 24 and an anti-reflection layer 25 arranged on the light-receiving side of the silicon wafer substrate.

[0060] Optionally, the silicon wafer substrate 00 is an N-type doped single crystal or polycrystalline silicon wafer with a thickness of 80um-160um.

[0061] Optionally, the protective layer 13 is made of one of a silicon oxide thin film layer, a silicon nitride thin film layer, a silicon oxynitride thin film layer or an aluminum oxide thin film layer, the sacrificial layer 14 is an intrinsic amorphous silicon thin film, and the anti-reflection layer 25 is made of one of a silicon oxide thin film layer, a silicon nitride thin film layer, a silicon oxynitride thin film layer or an aluminum oxide thin film layer.

[0062] Optionally, the junction between the N-type conductive region and the silicon wafer substrate 00 is a heterojunction, and the junction between the P-type conductive region and the silicon wafer substrate 00 is a heterojunction.

[0063] It can be understood that the beneficial effects of the technical solution of this embodiment can be found in the relevant description of the corresponding beneficial effects of the above-mentioned method for preparing a copper electroplating back-contact heterojunction battery, and will not be repeated here.

[0064] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the invention.

[0065] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0066] Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Mentioning "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present embodiment application. The appearance of this phrase in various positions in the specification is not necessarily the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It can be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0067] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a copper electroplated back contact heterojunction battery, characterized in that: include: Obtaining a silicon wafer substrate, and sequentially depositing a first intrinsic amorphous silicon layer, a first phosphorus-doped silicon layer, a protective layer, and a laser sacrificial layer on a backlight surface of the silicon wafer substrate to form an N-type conductive region; A first segmented laser is used to ablate the surface of the N-type conductive region until a portion of the surface of the silicon wafer substrate is exposed to form a first groove; Using potassium hydroxide solutions of the first concentration, potassium hydroxide solutions of the second concentration and hydrofluoric acid aqueous solution of the first concentration in sequence to texturize, round and clean the slotted silicon wafer to obtain a first silicon wafer intermediate; Depositing a second intrinsic amorphous silicon layer and a boron-doped silicon layer on the backlight surface of the first silicon wafer intermediate in sequence, and using a second laser to ablate the area between every two of the first grooves after deposition until the surface of the protective layer is partially exposed to form a second groove; The silicon wafer after the second groove is formed is cleaned with a hydrofluoric acid aqueous solution of a second concentration, and a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer are sequentially deposited on the light-receiving surface of the silicon wafer after cleaning to obtain a third silicon wafer intermediate; Depositing a transparent conductive film layer and a copper alloy seed layer on the backlight surface of the third silicon wafer intermediate in sequence, preparing ink on the backlight surface after deposition, removing the ink on the first groove and the second groove by exposure and development, exposing the gate electrode pattern, and then electroplating to generate a copper gate electrode, to obtain a fourth silicon wafer intermediate; Using a wet solution to remove the remaining ink layer and the copper alloy seed layer from the fourth silicon wafer intermediate to obtain a fifth silicon wafer intermediate; A third laser is used to ablate the area between the first groove and the second groove of the fifth silicon wafer intermediate until the surface of the boron-doped silicon layer is partially exposed to form a third groove, thereby obtaining a copper grid line back contact heterojunction battery.

2. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The silicon wafer substrate is a clean N-type doped single crystal or polycrystalline silicon wafer after cleaning, with a thickness of 80um-160um, the first intrinsic amorphous silicon film layer has a thickness of 2nm-12nm and a refractive index of 3.2-4.8, and the first phosphorus-doped silicon layer has a thickness of 4nm-30nm and a refractive index of 1.8-4.

3. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The protective layer is one of a silicon oxide film layer, a silicon nitride film layer, a silicon oxynitride film layer or an aluminum oxide film layer. The protective layer has a film thickness of 20nm-150nm and a refractive index of 1.4-3.

5. The laser sacrificial layer has a thickness of 5nm-50nm and a refractive index of 3-5.

4. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The first laser is a segmented laser, and the type is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser; the second laser is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser; the third laser is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser; wherein the laser wavelength is 200nm-500nm, and the frequency is 10 12 HZ-10 19 HZ.

5. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The method of using potassium hydroxide solutions of the first concentration, potassium hydroxide solutions of the second concentration and hydrofluoric acid aqueous solution of the first concentration to sequentially texturize, round and clean the slotted silicon wafer to obtain a first silicon wafer intermediate comprises: Using a potassium hydroxide solution with a concentration of 1%-10% to perform a texturing treatment on the silicon wafer substrate after the deposition and grooving; The silicon wafer substrate after texturing is cleaned again with a potassium hydroxide solution having a concentration of 0.5% to 5%, so that the top and bottom of the velvet pyramid are rounded; The rounded silicon wafer substrate is cleaned and dried with a hydrofluoric acid aqueous solution having a concentration of 1% to 8% to obtain a first silicon wafer intermediate.

6. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The second intrinsic amorphous silicon layer and the boron-doped silicon layer are sequentially deposited on the backlight surface of the first silicon wafer intermediate, and a second laser is used to ablate the area between every two of the first grooves after deposition until the surface of the protective layer is exposed to form a second groove, including: the second intrinsic amorphous silicon layer has a thickness of 3 nm-17 nm and a refractive index of 3.2-4.8; the boron-doped silicon layer has a thickness of 5 nm-40 nm and a refractive index of 2-5, and the boron-doped silicon layer is one of an amorphous silicon thin film layer, a microcrystalline silicon thin film layer or an oxygen-doped microcrystalline silicon thin film layer.

7. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The method uses a hydrofluoric acid aqueous solution of a second concentration to clean the silicon wafer after the second groove is formed, and after cleaning, sequentially deposits a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer on the light-receiving surface of the silicon wafer to obtain a third silicon wafer intermediate, including: Using a hydrofluoric acid aqueous solution with a concentration of 1% to 10% to clean the silicon wafer after the second groove is formed, so as to remove silicon oxide generated on the silicon wafer substrate and a protective layer in the second groove; A third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer are sequentially deposited on the light-receiving surface of the cleaned silicon wafer, wherein the third intrinsic amorphous silicon layer has a thickness of 3nm-15nm and a refractive index of 3-5, the second phosphorus-doped silicon layer has a thickness of 4nm-30nm and a refractive index of 2.2-4.5, and the anti-reflection layer has a thickness of 70nm-150nm and a refractive index of 1.2-3.

8. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The method comprises depositing a transparent conductive film layer and a copper alloy seed layer on the backlight surface of the third silicon wafer intermediate in sequence, preparing an ink layer based on the area between the first groove and the second groove adjacent to the backlight surface after deposition, and electroplating a copper grid line electrode on the backlight surface to obtain a fourth silicon wafer intermediate, including: The surface of the copper alloy seed layer is screen-printed with anti-electroplating ink, and the metal grid lines are patterned by exposure and development. The ink in the first groove and the second groove leaks out of the copper alloy seed layer, so that an ink layer is formed in the area between the first groove and the second groove.

9. The method for preparing a copper electroplating back contact heterojunction battery according to claim 8, characterized in that: The transparent conductive film layer and the copper alloy seed layer are sequentially deposited on the backlight surface of the third silicon wafer intermediate, ink is prepared on the backlight surface after deposition, and the ink on the first groove and the second groove is removed by exposure and development, and a copper gate electrode is formed by electroplating after the gate electrode pattern is exposed to obtain a fourth silicon wafer intermediate, and further includes: The ink layer between the first groove and the second groove has a width of 5um-15um and a height of 5um-15um; Using the ink layer as a mask, copper grid line electrodes with a width of 10um-30um and a height of 5um-15um are generated in the first groove and the second groove based on an electroplating process.

10. A copper electroplating back contact heterojunction battery, characterized in that: The battery is prepared by the method for preparing a copper electroplated back-contact heterojunction battery as described in any one of claims 1 to 9.

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