Method for preparing copper electroplated back contact heterojunction cell and heterojunction cell

Abstract

The application relates to the technical field of heterojunction solar cells, and particularly discloses a preparation method of a copper-plated back contact heterojunction cell and the heterojunction cell, which comprises the following steps: depositing a first intrinsic amorphous silicon layer, a first phosphorus-doped silicon layer, a protective layer and a laser sacrifice layer on the back light surface of a silicon wafer substrate, and setting a first groove on the back light surface; then performing texturing, rounding and cleaning; depositing a second intrinsic amorphous silicon layer and a boron-doped silicon layer on the back light surface, and setting a second groove between the two first grooves; sequentially depositing a transparent conductive film layer and a copper seed layer on the back light surface, preparing an ink layer, removing the ink layer and part of the copper alloy seed layer after exposure and development patterning, and setting a third groove between the first groove and the second groove to separate the transparent conductive film layer, so as to obtain a copper grid line back contact heterojunction cell. The method combines texturing and copper grid line preparation, has fewer process steps, can realize flexible and more fine adjustment of the copper grid line width, and improves the photoelectric conversion efficiency and production yield of the heterojunction solar cell.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of heterojunction solar cells, in particular to a preparation method of a copper electroplating back contact heterojunction cell and a heterojunction cell. BACKGROUND

[0002] In recent years, the back contact heterojunction cell has the dual advantages of large short-circuit current and high open-circuit voltage due to no metal grid line shielding on the front surface and the introduction of high-quality amorphous silicon film surface passivation, which represents the highest level of photoelectric conversion efficiency of crystalline silicon solar cells. However, since the positive and negative electrodes of the cell are both on the back surface, it is difficult to prepare the interdigitated positive and negative electrodes, and there is no unified solution at present.

[0003] Meanwhile, in the field of back contact heterojunction cells, copper paste has more advantages than silver paste in preparing grid lines (for example, the photo-generated carriers, whether electrons or holes, generated by the silicon substrate are transported to the bottom electrode, which puts higher requirements on the contact and recombination of silver paste, and the back surface alkali etching makes the textured surface flat, increasing the contact resistance, which puts higher requirements on the conductivity of silver paste. In addition, the back surface grid line has lower requirements for light shielding, and the larger the electrode area, the more conducive to current output. In this case, the consumption and cost of silver paste are high), so the use of copper paste to prepare grid lines in the preparation of back contact heterojunction cells has become a research hotspot in the industry.

[0004] However, compared with the screen printing of silver paste to prepare silver grid lines, the preparation of copper grid lines in back contact heterojunction cells requires multiple process steps and high requirements, and the preparation process is more complex. In addition, due to the complexity of the structure of the back contact heterojunction cell and the multiple preparation process steps, especially since the positive and negative electrodes of the cell are both on the back surface, how to effectively combine the preparation of copper grid lines with other preparation processes of the back contact heterojunction cell to reduce the process steps, and realize flexible and more precise line width of the copper grid lines to improve the photoelectric conversion efficiency and production yield of the heterojunction solar cell, there is no good solution in the related art. SUMMARY

[0005] The present application aims to at least solve the problems in the prior art that the process steps of the copper grid line back contact heterojunction cell are multiple and require high requirements, the line width of the copper grid line is difficult to control, the photoelectric conversion efficiency and production yield of the heterojunction solar cell are low, and the production cost is high. Therefore, the present application provides a preparation method of a copper electroplating back contact heterojunction cell and a heterojunction cell.

[0006] To achieve the above-mentioned purpose, in a first aspect, the present application provides a preparation method of a copper electroplating back contact heterojunction cell, comprising:

[0007] A silicon wafer substrate is obtained, and a first intrinsic amorphous silicon layer, a first phosphorus-doped silicon layer, a protective layer and a laser sacrificial layer are sequentially deposited on the back surface of the silicon wafer substrate to form an N-type conductive region.

[0008] A first laser is used to ablate the surface of the N-type conductive region to partially expose the surface of the silicon wafer substrate to form a first groove.

[0009] A first concentration of potassium hydroxide solution, a second concentration of potassium hydroxide solution and a first concentration of hydrofluoric acid solution are sequentially used to etch, round and clean the grooved silicon wafer to obtain a first silicon wafer intermediate.

[0010] A second intrinsic amorphous silicon layer and a boron-doped silicon layer are sequentially deposited on the back surface of the first silicon wafer intermediate, and a second laser is used to ablate the region between every two first grooves to partially expose the surface of the protective layer to form a second groove.

[0011] A second concentration of hydrofluoric acid solution is used to clean the silicon wafer after the second groove is formed, and a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer are sequentially deposited on the light-receiving surface of the silicon wafer to obtain a third silicon wafer intermediate.

[0012] A transparent conductive film layer and a copper alloy seed layer are sequentially deposited on the back surface of the third silicon wafer intermediate, and after the metal gate line pattern is exposed and developed, the remaining ink is used as a mask to electroplate copper gate line electrodes in the metal gate line patterned area between the first groove and the second groove on the back surface to obtain a fourth silicon wafer intermediate.

[0013] The remaining ink layer and the copper alloy seed layer are removed from the fourth silicon wafer intermediate by using a wet solution to obtain a fifth silicon wafer intermediate.

[0014] A third laser is used to ablate the region between the first groove and the second groove of the fifth silicon wafer intermediate to partially expose the surface of the boron-doped silicon layer to form a third groove to obtain a copper gate line back contact heterojunction solar cell.

[0015] In some embodiments that can be implemented, the silicon wafer substrate is a clean N-type doped single crystal or polycrystalline silicon wafer after cleaning, the thickness is 80-160 um, the first intrinsic amorphous silicon film layer has a thickness of 2-12 nm and a refractive index of 3.2-4.8, and the first phosphorus-doped silicon layer has a thickness of 4-30 nm and a refractive index of 1.8-4.

[0016] In some embodiments that can be implemented, the protective layer is one of a silicon oxide film layer, a silicon nitride film layer, a silicon oxynitride film layer or an aluminum oxide film layer, the protective layer has a thickness of 20-150 nm and a refractive index of 1.4-3.5, and the laser sacrificial layer has a thickness of 5-50 nm and a refractive index of 3-5.

[0017] In some embodiments, the first laser is one of a nanosecond pulsed laser, a femtosecond pulsed laser, or a picosecond pulsed laser; the second laser is one of a nanosecond pulsed laser, a femtosecond pulsed laser, or a picosecond pulsed laser; the third laser is one of a nanosecond pulsed laser, a femtosecond pulsed laser, or a picosecond pulsed laser; wherein the laser wavelength is 200 nm-500 nm, and the frequency is 10 12 HZ-10 19 HZ.

[0018] In some embodiments, the first concentration, the second concentration of potassium hydroxide solution, and the first concentration of hydrofluoric acid aqueous solution are sequentially used to perform texturing, rounding, and cleaning on the grooved silicon wafer to obtain a first silicon wafer intermediate, comprising:

[0019] The grooved silicon wafer substrate is subjected to texturing treatment using a potassium hydroxide solution with a concentration of 1%-10%;

[0020] The grooved silicon wafer substrate is subjected to texturing treatment using a potassium hydroxide solution with a concentration of 1%-10%;

[0021] The grooved silicon wafer substrate is subjected to texturing treatment using a potassium hydroxide solution with a concentration of 1%-10%;

[0022] In some embodiments, the second intrinsic amorphous silicon layer and the boron-doped silicon layer are sequentially deposited on the back light surface of the first silicon wafer intermediate, and a second laser is used to ablate the area between every two first grooves to expose the surface of the protective layer to form a second groove, comprising: the second intrinsic amorphous silicon layer has a thickness of 3 nm-17 nm and a refractive index of 3.2-4.8; the boron-doped silicon layer has a thickness of 5 nm-40 nm and a refractive index of 2-5, and the boron-doped silicon layer is one of an amorphous silicon thin film layer, a microcrystalline silicon thin film layer, or an oxygen-doped microcrystalline silicon thin film layer.

[0023] In some embodiments, the second concentration of hydrofluoric acid aqueous solution is used to clean the silicon wafer after the second groove is formed, and a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer, and an anti-reflection layer are sequentially deposited on the light-receiving surface of the silicon wafer to obtain a third silicon wafer intermediate, comprising:

[0024] The silicon wafer after the second groove is formed is cleaned using a hydrofluoric acid aqueous solution with a concentration of 1%-10% to remove the generated silicon oxide on the silicon wafer substrate and the protective layer in the second groove;

[0025] A third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer are sequentially deposited on the light-receiving surface of the cleaned silicon wafer, wherein the third intrinsic amorphous silicon layer has a thickness of 3-15 nm and a refractive index of 3-5, the second phosphorus-doped silicon layer has a thickness of 4-30 nm and a refractive index of 2.2-4.5, and the anti-reflection layer has a thickness of 70-150 nm and a refractive index of 1.2-3.

[0026] In some embodiments, a transparent conductive film layer and a copper alloy seed layer are sequentially deposited on the back surface of the third silicon wafer intermediate, an ink layer is prepared based on the area between the first groove and the second groove adjacent to the back surface after deposition, and a copper grid line electrode is formed by electroplating on the back surface to obtain a fourth silicon wafer intermediate, which comprises:

[0027] The surface of the copper alloy seed layer is screen printed with an anti-electroplating ink, and the ink in the first groove and the second groove is removed by exposure and development to expose part of the copper alloy seed layer, so that an ink layer is formed between the first groove and the second groove, that is, the copper metal grid line is initially patterned.

[0028] In some embodiments, a transparent conductive film layer and a copper alloy seed layer are sequentially deposited on the back surface of the third silicon wafer intermediate, an ink layer is prepared based on the area between the first groove and the second groove adjacent to the back surface after deposition, and a copper grid line electrode is formed by electroplating on the back surface to obtain a fourth silicon wafer intermediate, which further comprises:

[0029] The width of part of the ink layer between the first groove and the second groove is 5-15 um, and the height is 5-15 um;

[0030] The ink layer is used as a mask, and a copper grid line electrode with a width of 10-30 um and a height of 5-15 um is formed in the first groove and the second groove based on the electroplating process.

[0031] In the above-mentioned technical solutions, compared with the prior art, at least the following advantages or beneficial effects are achieved:

[0032] 1) In the preparation of copper grid line back contact heterojunction solar cells, the laser sacrificial layer and the protective layer are prepared in advance, the laser sacrificial layer and the protective layer are selected from specific refractive index materials and have a specific thickness, the laser sacrificial layer can absorb the laser, reducing the damage of the laser to the N-type conductive region, and can also act as a wet etching mask for the subsequent insulating protective layer, and a laser with a specific wavelength and frequency is selected, so that in the slotting process, the copper grid line width is flexible and more precise, and the problem of damage to the passivation effect of the intrinsic amorphous silicon layer caused by the laser penetrating the protective layer is avoided, thereby improving the photoelectric conversion efficiency and production yield of the heterojunction solar cell.

[0033] 2) In order to improve the quality and photoelectric conversion efficiency of the copper grid line back contact heterojunction solar cell, before depositing a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer on the light-receiving surface of the silicon substrate, the silicon oxide on the light-receiving surface of the silicon substrate is removed by using a 1%-10% concentration range of hydrofluoric acid aqueous solution. At the same time, due to the special setting of the step, the protective layer in the second groove is exposed, and the protective layer is prepared from a material that reacts with the hydrofluoric acid aqueous solution. In this way, the protective layer in the second groove can be removed while cleaning, reducing the process steps of the back contact heterojunction solar cell and improving the production efficiency of the back contact heterojunction solar cell.

[0034] 3) A third groove is opened in the transparent conductive film layer between the first groove and the second groove using a laser process, which directly separates the N conductive region and the P conductive region, avoiding the generation of leakage current and the resulting low photoelectric conversion efficiency of the cell, thereby improving the production yield of the copper-plated back contact heterojunction solar cell.

[0035] 4) The silicon substrate is deposited with an intrinsic amorphous silicon layer, which passivates the dangling bonds on the surface of the silicon substrate, reduces the surface defect state density, and improves the photoelectric conversion efficiency of the cell. Secondly, the laser sacrificial layer can absorb laser, reducing the damage of the laser to the N-type conductive region, and also can act as a wet etching mask for the subsequent insulating protective layer. The presence of the protective layer can isolate the N-type conductive region and the P-type conductive region, preventing the cell from leaking. At the same time, the protective layer can protect the bottom layer from subsequent etching by alkali solution. Secondly, it can also effectively reflect the laser of this wavelength band, avoiding the damage of the laser to the passivation performance of the intrinsic amorphous silicon, which makes the cell efficiency lower.

[0036] In a second aspect, the application also provides a copper-plated back contact heterojunction solar cell prepared by the preparation method of the copper-plated back contact heterojunction solar cell according to any one of the first aspect.

[0037] It can be understood that the beneficial effects of the second aspect described above can be referred to the related description in the first aspect, which will not be repeated here.

[0038] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description, or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creating any inventive labor.

[0040] Figure 1 is a flow chart of a preparation method of a copper electroplating back contact heterojunction cell according to an embodiment of the present application;

[0041] Figure 2 is a first cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0042] Figure 3 is a second cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0043] Figure 4 is a third cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0044] Figure 5 is a fourth cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0045] Figure 6 is a fifth cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0046] Figure 7 is a sixth cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0047] Figure 8 is a seventh cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0048] Figure 9 is an eighth cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0049] Figure 10 is a ninth cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0050] Figure 11 is a tenth cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0051] Figure 12 is an eleventh cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0052] Figure 13 is a twelfth cell structure schematic diagram in a preparation flow of a copper grid line back contact heterojunction solar cell according to an embodiment of the present application;

[0053] Figure 14 Fig. 13 is a schematic diagram of a thirteenth cell structure in a preparation process of a copper grid back contact heterojunction solar cell according to an embodiment of the present application;

[0054] Figure 15 Fig. 14 is a schematic diagram of a fourteenth cell structure in a preparation process of a copper grid back contact heterojunction solar cell according to an embodiment of the present application;

[0055] Reference Signs:

[0056] 00, silicon wafer substrate; 11, first intrinsic amorphous silicon layer; 12, first phosphorus-doped silicon layer; 13, protective layer;

[0057] 14, laser sacrifice layer; 15, first groove; 21, second intrinsic amorphous silicon layer; 22, boron-doped silicon layer; 23, second groove;

[0058] 24, third intrinsic amorphous silicon layer; 25, second phosphorus-doped silicon layer; 26, anti-reflection layer;

[0059] 31, transparent conductive film layer; 32, copper alloy seed layer; 33, ink layer;

[0060] 41, copper grid electrode; 42, anti-oxidation layer; 43, third groove. DETAILED DESCRIPTION

[0061] The embodiments of the present application will be described in detail with reference to the drawings, and the embodiments described herein are examples for explaining the present application and should not be used in a limiting sense.

[0062] It should be noted that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can also be present.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this description, the terms "may" and "can" include any one of, or all of, possible combination of the items that they introduce.

[0064] Referring to Figures 1 to 15 The embodiment provides a preparation method of a copper electroplating back contact heterojunction solar cell, comprising:

[0065] Step S100: Obtain a silicon wafer substrate, and deposit, on the back surface of the silicon wafer substrate, a first intrinsic amorphous silicon layer, a first phosphorus-doped silicon layer, a protective layer, and a laser-sacrificial layer in sequence to form an N-type conductive region.

[0066] As shown in the figure, in this step, since the rough silicon wafer substrate surface is often accompanied by contamination and cutting damage, therefore, before use, it first needs to undergo tank solution pre-cleaning to remove the surface organic contamination and large particles, and then use lye to polish both sides to remove the surface cutting damage layer, and then perform RCA cleaning (or other solution formula equivalent to RCA cleaning), and finally, HF solution is used to remove the surface oxide layer, and after deionized water cleaning, the silicon wafer substrate 00 is obtained. Figure 2 It should be noted that, during the double-side polishing and cleaning process of the rough silicon wafer substrate, the acid or alkali solution used can be sodium hydroxide solution or potassium hydroxide solution, etc., and the acid solution can be an acid mixture such as citric acid and sulfuric acid, and the specific selection and concentration can be considered according to actual needs, which is not limited here.

[0067] Optionally, the thickness of the cleaned silicon wafer substrate 00 after cleaning is 80-160 um, and the specific thickness can be selected according to actual needs.

[0068] After cleaning the silicon wafer substrate, the first intrinsic amorphous silicon layer 11, the first phosphorus-doped silicon layer 12, and the protective layer 13 are prepared by PECVD, wherein the PECVD equipment power source adopts one of 13.56 MHz, 26 MHz or 40 MHz, and preferably 13.56 MHz.

[0069] Optionally, the process gas of the first intrinsic amorphous silicon layer 11 is a combination of silane (SiH4), hydrogen (H2), and carbon dioxide (CO2), the thickness is 2-12 nm, and the refractive index is 3.2-4.8. The first intrinsic amorphous silicon layer 11 can passivate the silicon wafer surface dangling bond and reduce the surface defect state density.

[0070] Optionally, the first phosphorus-doped silicon layer 12 adopts one or more of amorphous layer, oxygen-doped microcrystalline layer, and non-oxygen-doped microcrystalline layer, and the process gas includes a combination of silane (SiH4), hydrogen (H2), carbon dioxide (CO2), and phosphine (PH3), the thickness is 4-30 nm, and the refractive index is 1.8-4. The presence of the first doped silicon layer 12 can provide field passivation effect for the surface and improve the conversion efficiency of the battery.

[0071]

[0072] ​In some embodiments, the protective layer 13 is made of one of a silicon oxide thin film layer, a silicon nitride thin film layer, a silicon oxynitride thin film layer or an aluminum oxide thin film layer. The thickness of the protective layer is 20-150 nm and the refractive index is 1.4-3.5. The protective layer 13 can isolate the N-type conductive area and the P-type conductive area, thereby preventing leakage of the battery. At the same time, the protective layer 13 can protect the bottom layer from subsequent etching by alkaline solution. Secondly, the protective layer 13 can reflect excess laser energy while not being etched by the laser, thereby avoiding damage to the first intrinsic amorphous silicon layer 11 and the first phosphorus-doped silicon layer 12 of the silicon wafer substrate.

[0073] In some embodiments, the laser sacrificial layer 14 is an amorphous silicon layer with a thickness of 5 nm to 50 nm and a refractive index of 3 to 5. The laser sacrificial layer can absorb the laser light and reduce the damage of the laser light to the N-type conductive region. It can also serve as a wet etching mask for the subsequent insulating protective layer.

[0074] It can be understood that an N-type conductive region is formed after depositing a first intrinsic amorphous silicon layer 11, a first phosphorus-doped silicon layer 12, a protective layer 13 and a laser sacrificial layer 14 on the backlight surface of the silicon wafer substrate 00; the above-mentioned deposition conditions and principles of each layer can be achieved by the existing technology and will not be elaborated here. The selection of the thickness and refractive index of each layer and the number of deposition layers and the material setting of each layer are the key points of the technical solution of this embodiment. For example, the setting of the first intrinsic amorphous silicon layer 11 passivates the dangling bonds on the surface of the silicon wafer substrate and reduces the surface defect state density. The setting of the first phosphorus-doped silicon layer 12 further provides a field passivation effect on the surface, thereby improving the battery conversion efficiency. By setting the protective layer 13 and combining the subsequent steps with a wavelength of 200nm-500nm and a frequency of 10 12 HZ-10 19 When the laser ablates a groove in the HZ laser band, the protective layer 112 can effectively reflect the laser beam in this wavelength band, thereby preventing the laser beam from damaging the intrinsic amorphous silicon and causing a decrease in the cell conversion efficiency.

[0075] Step S200: using a segmented first laser to ablate the surface of the N-type conductive region until a portion of the surface of the silicon wafer substrate is exposed to form a first trench;

[0076] In this step, if Figure 2 As shown, a first laser process is used on a silicon wafer substrate 00 to vertically remove portions of the amorphous silicon layer 11, first phosphorus-doped silicon layer 12, protective layer 13, and laser sacrificial layer 14 in multiple steps to form a first trench 15, thereby forming an opening for the P-type conductive region. This multiple laser process effectively reduces edge passivation losses. The first intrinsic amorphous silicon layer 11 and first phosphorus-doped silicon layer 12, covering protective layer 13, form the N-type conductive region.

[0077] It should be noted that the first laser can be one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser, and the specific selection can be made according to actual needs.

[0078] It should also be noted that the laser wavelength is selected in the range of 200nm-500nm, and the frequency is 10 12 Hz-10 19 Hz, the selection of the wavelength and the frequency of the laser is made by comprehensively considering the properties of the three-layer film deposited on the silicon substrate; if other types of laser are used, the passivation effect of the intrinsic amorphous silicon will be damaged by penetrating the protective layer 13, thereby causing the conversion efficiency of the battery to decrease. Moreover, if other types of laser are used, the passivation effect of the intrinsic amorphous silicon can be damaged by penetrating the silicon nitride, thereby causing the conversion efficiency of the battery to decrease, that is, the selection of the wavelength and the frequency of the laser can avoid the problem of the passivation effect of the intrinsic amorphous silicon layer being damaged by the laser penetrating the protective layer.

[0079] Optionally, the first groove 15 has a width of 30um-300um, and the interval between every two adjacent first grooves is 10um-100um, and the specific value can be selected according to actual needs, which is not limited herein.

[0080] Step S300: using the first concentration, the second concentration of potassium hydroxide solution and the first concentration of hydrofluoric acid aqueous solution to sequentially etch, round and clean the grooved silicon wafer to obtain a first silicon wafer intermediate;

[0081] In this step, as shown in Figure 4 , the silicon wafer after the first groove 15 is opened is subjected to wet cleaning, and the process is as follows:

[0082] Step S310: using a potassium hydroxide solution with a concentration of 1%-10% to etch the light-receiving surface of the silicon substrate 00 and the silicon substrate 00 under the first groove 15, the silicon wafer is formed with a pyramidal structure from the polished surface, which can reduce the reflectivity of the silicon wafer, and the design of the pyramidal surface can increase the area of the light-receiving surface to achieve the purpose of improving the battery efficiency.

[0083] Step S320: using a potassium hydroxide solution with a concentration of 0.5%-5% to clean the etched silicon wafer, so as to round the pyramidal tower top and the pyramidal tower bottom; the pyramidal tower top and the pyramidal tower bottom are slightly rounded and etched by the dilute alkali solution, which is more conducive to the subsequent surface passivation and improves the battery efficiency.

[0084] Step S330: using a hydrofluoric acid aqueous solution with a concentration of 1%-8% to clean and then dry, the hydrofluoric acid aqueous solution removes the trace amount of silicon oxide generated on the surface, and it should be noted that the above steps are all carried out in the same wet cleaning equipment, which simplifies the process flow of the battery.

[0085] It can be understood that the first concentration of potassium hydroxide solution, the second concentration of potassium hydroxide solution is one of the above concentration range, the first concentration of hydrofluoric acid aqueous solution is one of the above concentration range, and the specific selection can be made according to the actual demand, which is not described here.

[0086] Step S400: sequentially depositing a second intrinsic amorphous silicon layer and a boron-doped silicon layer on the back surface of the first silicon wafer intermediate, and using a second laser to ablate the area between every two first grooves to expose part of the surface of the protective layer to form a second groove;

[0087] In this step, please refer to Figures 5 to 7 In this step, please refer to

[0088] Optionally, the purpose of the second intrinsic amorphous silicon layer 21 is to passivate the surface dangling bonds of the silicon wafer in the first groove 15 and reduce the surface defect state density, and the process gas includes all or a combination of silane (SiH4), hydrogen (H2), and carbon dioxide (CO2), wherein the thickness of the second intrinsic amorphous silicon layer 21 is 3-15 nm, and the refractive index is 3-5, which can be selected according to actual needs.

[0089] Optionally, the boron-doped silicon layer 22 can be one of an amorphous silicon thin film layer, a microcrystalline silicon thin film layer, or an oxygen-doped microcrystalline silicon thin film layer, and the process gas is a combination of silane (SiH4), hydrogen (H2), carbon dioxide (CO2), and diborane (B2H6). The boron-doped silicon layer 22 forms a PN junction with the N-type silicon wafer substrate, which is the emitter of the cell, and the thickness of the thin film layer is 5-60 nm, and the refractive index is 2.5-4.5.

[0090] In some embodiments, the boron-doped silicon layer 22, the second intrinsic amorphous silicon layer 21, and the laser sacrifice layer 14 are removed between every two first grooves on the back surface of the silicon wafer using a second laser etching process, and the N-type conductive region is exposed.

[0091] It should be noted that the wavelength of the laser is in the range of 200-500 nm, the laser is a flat-top laser, and the type is one of nanosecond pulse laser, femtosecond pulse laser, or picosecond pulse laser, preferably ultraviolet picosecond laser; due to the presence of the protective layer 13, the laser etching depth can reach the surface of the protective layer 13.

[0092] Optionally, there is a non-grooving area between the first groove 15 and the second groove 23, and the specific value can be selected according to actual needs.

[0093] After the deposition and grooving, the second groove 23 and the silicon wafer substrate 00 are cleaned with a hydrofluoric acid aqueous solution in a concentration range of 1%-10% to remove the protective layer 13 in the second groove 23 and the generated silicon oxide of the silicon wafer substrate 00, so that the N-type conductive region in the second groove 23 is exposed.

[0094] Step S500: The silicon wafer after the second groove is opened is cleaned with a second concentration of hydrofluoric acid aqueous solution, and a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer, and an anti-reflection layer are sequentially deposited on the light-receiving surface of the silicon wafer after cleaning, to obtain a third silicon wafer intermediate;

[0095] In this step, as shown in FIG. 4, a third intrinsic amorphous silicon layer 24, a second phosphorus-doped silicon layer 25, and an anti-reflection layer 26 are deposited on the light-receiving surface of the silicon wafer by PECVD. The PECVD equipment power source uses one of 13.56 MHz, 26 MHz, or 40 MHz, and preferably 13.56 MHz. Figure 8 Optionally, the purpose of the third intrinsic amorphous silicon layer 24 is to passivate the dangling bonds on the surface of the light-receiving surface of the silicon wafer and reduce the surface defect state density. The process gas includes all or a combination of silane (SiH4), hydrogen (H2), and carbon dioxide (CO2). The thickness of the third intrinsic amorphous silicon layer 24 is 3-15 nm, and the refractive index is 3-5, which can be selected according to actual needs.

[0096] Optionally, the second phosphorus-doped silicon layer 25 is one or a combination of an amorphous layer, an oxygen-doped microcrystalline layer, and a non-oxygen-doped microcrystalline layer. The process gas includes a combination of silane (SiH4), hydrogen (H2), carbon dioxide (CO2), and phosphine (PH3). The thickness is 4-30 nm, and the refractive index is 2.2-4.5. The second doped silicon layer 25 can provide field passivation effects for the surface and improve the conversion efficiency of the battery.

[0097] Optionally, the anti-reflection layer 26 can be one or a combination of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide, which is not limited here, and is preferably a silicon nitride film. The thickness is 70-150 nm, and the refractive index is 1.2-3.

[0098] Step S600: A transparent conductive film layer and a copper alloy seed layer are sequentially deposited on the non-light-receiving surface of the third silicon wafer intermediate. After deposition, ink is prepared on the non-light-receiving surface, the ink on the first groove and the second groove is removed by exposure and development, the grid line electrode pattern is exposed, and a copper grid line electrode is generated by electroplating to obtain a fourth silicon wafer intermediate;

[0099] In this step, as shown in FIG. 5, a transparent conductive film layer 27 and a copper alloy seed layer 28 are sequentially deposited on the non-light-receiving surface of the third silicon wafer intermediate. The transparent conductive film layer 27 is prepared by PECVD, and the copper alloy seed layer 28 is prepared by sputtering. The PECVD equipment power source uses one of 13.56 MHz, 26 MHz, or 40 MHz, and preferably 13.56 MHz.

[0100] Figures 9 to 12 ​As shown, magnetron sputtering or reactive plasma is used to deposit a transparent conductive film layer 31 and a copper alloy seed layer 32. The material of the transparent conductive film 31 can be an indium oxide film doped with tin oxide, tungsten oxide, titanium oxide, thallium oxide, or gallium oxide, wherein indium oxide is the main material, accounting for more than 90% by weight, and a tin oxide-doped indium oxide (ITO) film is preferred. The main material of the target material can also be an indium-free oxide target such as tin oxide and zinc oxide.

[0101] Optionally, the transparent conductive film 31 has a thickness of 50-150 nm and a refractive index of 1.5-3.0. The copper alloy seed layer 32 is mainly made of copper, and the doping element can be one or more of manganese, zirconium, tungsten, aluminum, silver, titanium, and gold, which can be selected according to actual needs.

[0102] In some embodiments, ink with a width of 5-40 μm and a height of 3-20 μm is added between the first groove 15 and the second groove 23 by screen printing and exposure and development, and anti-plating ink is screen printed on the surface of the copper alloy seed layer 32. The ink in the first groove 15 and the second groove 23 is removed by exposure and development until a portion of the copper alloy seed layer 32 is exposed, so that an ink layer 33 is formed in the area between the first groove 15 and the second groove 32.

[0103] like Figure 14 As shown, the ink layer 33 is used as a mask and a copper grid electrode 41 is grown on the back of the battery by electroplating process, wherein the copper grid line width is 10-30 um, the height is 5-15 um, the grid line height width is 35%-45%, and the grid line morphology is a positive trapezoid.

[0104] Step S700: removing the remaining ink layer and the copper alloy seed layer from the fourth silicon wafer intermediate using a wet solution to obtain a fifth silicon wafer intermediate;

[0105] In this step, if Figure 14 As shown, an alkaline solution is used to remove the electroplated ink layer 33 on the back surface, and the copper grid electrode 41 is used as a mask to remove the remaining copper alloy seed layer 32 on the back surface. The sulfuric acid concentration in the copper removal solution is 0.1-10%, and the potassium persulfate solution concentration is 0.1-10%. To prevent oxidation of metallic copper, a tin anti-oxidation layer 42 with a thickness of 0.1μm-5μm is formed on the surface of the copper electrode through a chemical replacement reaction, ultimately resulting in a copper grid back-contact heterojunction battery. The divalent tin ion concentration in the tin solution is 0-40g / L.

[0106] Step S800: ablating the area between the first trench and the second trench of the fifth silicon wafer intermediate by a third laser until the surface of the boron-doped silicon layer is partially exposed to form a third trench, thereby obtaining a copper grid line back contact heterojunction battery;

[0107] In this step, as shown in Figure 15 The third trench 43 is opened by using a wet etching and a laser process to the transparent conductive thin film layer 31 between the first trench 15 and the second trench 23; the third trench 43 directly cuts off the lateral conduction between the N conductive region and the P conductive region, avoids the generation of leakage current and the result of lower battery photoelectric conversion efficiency, and improves the production yield of the copper-plated back contact heterojunction solar cell. It should be noted that the third laser is: the wavelength range of the laser is 200-500 nm, the laser is a flat-top laser, and the type is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser, preferably ultraviolet femtosecond laser.

[0108] In the above method steps, when preparing the copper grid line back contact heterojunction solar cell, the laser sacrifice layer and the protective layer are prepared in advance, the laser sacrifice layer and the protective layer are selected from a specific refractive index material and set to a specific thickness, the existence of the laser sacrifice layer can reduce the damage of the laser to the N-type conductive region, and also can act as a wet etching mask of the subsequent insulating protective layer, and the laser with a specific wavelength and frequency is selected, in the slotting process, the line width of the copper grid line is flexibly adjustable and more fine, and the problem of damaging the passivation effect of the intrinsic amorphous silicon layer caused by the laser penetrating the protective layer is avoided, thereby improving the photoelectric conversion efficiency and production yield of the heterojunction solar cell.

[0109] In addition, in order to improve the quality and photoelectric conversion efficiency of the copper grid line back contact heterojunction solar cell, before the third intrinsic amorphous silicon layer, the second phosphorus-doped silicon layer and the anti-reflection layer are deposited on the light-receiving surface of the silicon wafer substrate by PECVD, the silicon wafer substrate light-receiving surface is removed by using a 1%-10% concentration range of hydrofluoric acid aqueous solution, and at the same time, due to the special setting of the step, the protective layer in the second trench is exposed, and the protective layer is prepared from a material that reacts with the hydrofluoric acid aqueous solution, so that the protective layer in the second trench can be removed while cleaning, thereby reducing the process steps of the back contact heterojunction solar cell and improving the production efficiency of the back contact heterojunction solar cell.

[0110] Meanwhile, the third trench is opened by using a laser process to remove the transparent conductive thin film layer between the first trench and the second trench, the third trench directly cuts off the lateral conduction between the N conductive region and the P conductive region, avoids the generation of leakage current and the result of lower battery photoelectric conversion efficiency, and improves the production yield of the copper-plated back contact heterojunction solar cell.

[0111] And, the intrinsic amorphous silicon layer deposited on the silicon substrate can passivate the dangling bonds on the surface of the silicon substrate, reduce the surface defect state density, and improve the photoelectric conversion efficiency of the battery; secondly, the laser sacrifice layer can absorb the laser, reduce the damage of the laser to the N-type conductive region, and also can act as a wet etching mask of the subsequent insulating protective layer; and the presence of the protective layer can isolate the N-type conductive region and the P-type conductive region, can prevent the battery from leaking, and can also effectively reflect the laser of this wave band to avoid the laser from damaging the passivation performance of the intrinsic amorphous silicon, so that the battery efficiency is low.

[0112] In some embodiments, a copper grid back contact heterojunction battery is also provided, which is prepared by the preparation method of the copper grid back contact heterojunction battery described in any of the above embodiments, and the back contact heterojunction battery comprises:

[0113] The silicon substrate 00 is provided with a first intrinsic amorphous silicon layer 11 and a first phosphorus-doped silicon layer 12 on the back light surface of the silicon substrate, forming an N-type conductive region; a protective layer 13 and a sacrifice layer 14 are arranged on the N-type conductive region; a second intrinsic amorphous silicon layer 21 and a boron-doped silicon layer 22 are arranged on the back light surface of the silicon substrate, forming a P-type conductive region; a transparent conductive thin film layer 31, a copper alloy seed layer 32 and a copper grid electrode 41 are arranged on the N-type conductive region and the P-type conductive region; a third intrinsic amorphous silicon layer 23, a second phosphorus-doped silicon layer 24 and an anti-reflection layer 25 are arranged on the light receiving surface of the silicon substrate.

[0114] Optionally, the silicon substrate 00 is an N-type doped single crystal or polycrystalline silicon wafer, and the thickness is 80-160um.

[0115] Optionally, the protective layer 13 is one of a silicon oxide thin film layer, a silicon nitride thin film layer, a silicon oxynitride thin film layer or an aluminum oxide thin film layer, the sacrifice layer 14 is an intrinsic amorphous silicon thin film, and the anti-reflection layer 25 is one of a silicon oxide thin film layer, a silicon nitride thin film layer, a silicon oxynitride thin film layer or an aluminum oxide thin film layer.

[0116] Optionally, the junction between the N-type conductive region and the silicon substrate 00 is a heterojunction, and the junction between the P-type conductive region and the silicon substrate 00 is a heterojunction.

[0117] It can be understood that the beneficial effects of the technical solutions of the present embodiment can be referred to the above-mentioned corresponding beneficial effects of the preparation method of the copper grid back contact heterojunction battery, which will not be described here in detail.

[0118] In the description of the application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0119] In the description of the application, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the application. In the description of the application, the exemplary description of the above terms does not necessarily mean the same embodiment or example, but can mean different embodiments or examples.

[0120] Obviously, the described embodiments are only a part of the embodiments of the application, not all the embodiments. In this paper, "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the application. The phrase appears at various places in the specification is not necessarily the same embodiment, nor is it an independent or alternative embodiment or a separate embodiment. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0121] Although the embodiments of the application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and purposes of the application, and the scope of the application is defined by the claims and their equivalents.

Claims

1. A method for preparing a copper electroplated back contact heterojunction battery, characterized in that: include: Obtaining a silicon wafer substrate, and sequentially depositing a first intrinsic amorphous silicon layer, a first phosphorus-doped silicon layer, a protective layer, and a laser sacrificial layer on a backlight surface of the silicon wafer substrate to form an N-type conductive region; A first segmented laser is used to ablate the surface of the N-type conductive region until a portion of the surface of the silicon wafer substrate is exposed to form a first trench; Using a first concentration potassium hydroxide solution, a second concentration potassium hydroxide solution and a first concentration hydrofluoric acid aqueous solution in sequence to texturize, round and clean the slotted silicon wafer to obtain a first silicon wafer intermediate; Depositing a second intrinsic amorphous silicon layer and a boron-doped silicon layer in sequence on the backlight surface of the first silicon wafer intermediate, and using a second laser to ablate the area between every two of the first grooves after deposition until the surface of the protective layer is partially exposed to form a second groove; cleaning the silicon wafer after the second groove is formed with a hydrofluoric acid aqueous solution of a second concentration to remove silicon oxide generated on the silicon wafer substrate and a protective layer in the second groove; and sequentially depositing a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer, and an anti-reflection layer on the light-receiving surface of the silicon wafer after cleaning to obtain a third silicon wafer intermediate; Depositing a transparent conductive thin film layer and a copper alloy seed layer on the backlight surface of the third silicon wafer intermediate in sequence, preparing ink on the backlight surface after deposition, exposing and developing to remove the ink on the first groove and the second groove, exposing the gate electrode pattern, and then electroplating to form a copper gate electrode to obtain a fourth silicon wafer intermediate; removing the remaining ink layer and the copper alloy seed layer from the fourth silicon wafer intermediate using a wet solution to obtain a fifth silicon wafer intermediate; A third laser is used to ablate the area between the first trench and the second trench of the fifth silicon wafer intermediate until the surface of the boron-doped silicon layer is partially exposed to form a third trench, thereby obtaining a copper grid line back contact heterojunction battery.

2. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The silicon wafer substrate is a clean N-type doped single crystal or polycrystalline silicon wafer after cleaning, with a thickness of 80um-160um, the first intrinsic amorphous silicon layer has a thickness of 2nm-12nm and a refractive index of 3.2-4.8, and the first phosphorus-doped silicon layer has a thickness of 4nm-30nm and a refractive index of 1.8-4.

3. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The protective layer is one of a silicon oxide film layer, a silicon nitride film layer, a silicon oxynitride film layer or an aluminum oxide film layer. The thickness of the protective layer is 20nm-150nm, and the refractive index is 1.4-3.

5. The thickness of the laser sacrificial layer is 5nm-50nm, and the refractive index is 3-5.

4. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The first laser is a segmented laser, and the type is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser; the second laser is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser; the third laser is one of nanosecond pulse laser, femtosecond pulse laser or picosecond pulse laser; wherein the laser wavelength is 200nm-500nm, and the frequency is 10 12 HZ-10 19 HZ.

5. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The method of sequentially texturing, rounding, and cleaning the slotted silicon wafer using a potassium hydroxide solution of a first concentration, a potassium hydroxide solution of a second concentration, and a hydrofluoric acid aqueous solution of a first concentration to obtain a first silicon wafer intermediate comprises: Using a potassium hydroxide solution with a concentration of 1% to 10% to perform a texturing treatment on the silicon wafer substrate after the deposition and grooving; The silicon wafer substrate after texturing is cleaned again with a potassium hydroxide solution having a concentration of 0.5% to 5%, so that the top and bottom of the velvet pyramid are rounded; The rounded silicon wafer substrate is cleaned with a hydrofluoric acid aqueous solution having a concentration of 1%-8% and dried to obtain a first silicon wafer intermediate.

6. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The second intrinsic amorphous silicon layer and the boron-doped silicon layer are sequentially deposited on the backlight surface of the first silicon wafer intermediate, and a second laser is used to ablate the area between every two of the first grooves after deposition until the surface of the protective layer is partially exposed to form a second groove, including: the second intrinsic amorphous silicon layer has a thickness of 3 nm-17 nm and a refractive index of 3.2-4.8; the boron-doped silicon layer has a thickness of 5 nm-40 nm and a refractive index of 2-5, and the boron-doped silicon layer is one of an amorphous silicon thin film layer, a microcrystalline silicon thin film layer or an oxygen-doped microcrystalline silicon thin film layer.

7. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The silicon wafer after the second groove is formed is cleaned with a hydrofluoric acid aqueous solution of a second concentration to remove silicon oxide generated on the silicon wafer substrate and a protective layer in the second groove, and after cleaning, a third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer, and an anti-reflection layer are sequentially deposited on the light-receiving surface of the silicon wafer to obtain a third silicon wafer intermediate, comprising: Cleaning the silicon wafer after the second groove is formed using a hydrofluoric acid aqueous solution with a concentration of 1% to 10% to remove silicon oxide generated on the silicon wafer substrate and a protective layer in the second groove; A third intrinsic amorphous silicon layer, a second phosphorus-doped silicon layer and an anti-reflection layer are sequentially deposited on the light-receiving surface of the cleaned silicon wafer, wherein the third intrinsic amorphous silicon layer has a thickness of 3nm-15nm and a refractive index of 3-5, the second phosphorus-doped silicon layer has a thickness of 4nm-30nm and a refractive index of 2.2-4.5, and the anti-reflection layer has a thickness of 70nm-150nm and a refractive index of 1.2-3.

8. The method for preparing a copper electroplating back contact heterojunction battery according to claim 1, characterized in that: The method comprises depositing a transparent conductive film layer and a copper alloy seed layer on the backlight surface of the third silicon wafer intermediate in sequence, preparing an ink layer based on the area between the first groove and the second groove adjacent to the backlight surface after the deposition, and electroplating a copper grid electrode on the backlight surface to obtain a fourth silicon wafer intermediate, comprising: Anti-electroplating ink is screen-printed on the surface of the copper alloy seed layer, and metal grid lines are patterned by exposure and development. The ink in the first groove and the second groove leaks out of the copper alloy seed layer, so that an ink layer is formed in the area between the first groove and the second groove.

9. The method for preparing a copper electroplating back contact heterojunction battery according to claim 8, characterized in that: The method further comprises depositing a transparent conductive film layer and a copper alloy seed layer on the backlight surface of the third silicon wafer intermediate in sequence, preparing ink on the backlight surface after the deposition, exposing and developing the ink to remove the first groove and the second groove, exposing the gate electrode pattern, and then electroplating to form a copper gate electrode to obtain a fourth silicon wafer intermediate. The ink layer between the first groove and the second groove has a width of 5um-15um and a height of 5um-15um; Using the ink layer as a mask, copper grid electrodes with a width of 10um-30um and a height of 5um-15um are generated in the first groove and the second groove based on an electroplating process.

10. A copper electroplating back contact heterojunction battery, characterized in that: The battery is prepared by the method for preparing a copper electroplated back-contact heterojunction battery as described in any one of claims 1 to 9.

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