Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display, at least one driving circuit is arranged in a display area, so that the display panel can be a display panel with an extremely narrow frame or even without a frame; a display area is divided into a plurality of sub-display areas, and at least two alignment marks are arranged in each sub-display area, so that alignment is carried out when a light-emitting element is transferred to an array substrate of the display panel by utilizing the alignment marks located in the sub-display areas; moreover, the alignment mark is arranged in one metal layer in the multiple metal layers located on the side, away from the substrate, of the active layer, a clearance area is arranged on the periphery of the alignment mark, the alignment mark and the clearance area on the periphery of the alignment mark are exposed out of the multiple metal layers located on the side, away from the substrate, of the active layer, and therefore it is ensured that the alignment mark is accurately recognized; the light-emitting element can be accurately transferred to the array substrate of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, Micro LED display panels are increasingly used in display devices such as smartphones, tablets and laptops due to their excellent brightness, lifespan, contrast, response time, energy consumption, viewing angle and resolution.

[0003] When transferring micro-LEDs to the display area of ​​the array substrate through mass transfer technology, alignment marks are required for alignment. In existing micro-LED display panels, alignment marks are usually set in the non-display area. With the development of display technology, display panels with extremely narrow borders or even borderless ones have gradually become mainstream. Therefore, how to set alignment marks has become a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a display panel and a display device, so as to set an alignment mark in a display area of ​​a display panel with an extremely narrow frame or even no frame.

[0005] To achieve the above objectives, the present application provides the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a display panel, the display panel includes a display area, the display area includes a plurality of light-emitting elements, a plurality of pixel circuits and at least one driving circuit, the driving circuit includes a shift register circuit arranged in a multi-stage cascade, the shift register circuit is used to transmit a driving signal to the pixel circuit, and the pixel circuit is used to drive the light-emitting element;

[0007] The display panel includes an array substrate, the array substrate includes a pixel circuit and a driving circuit, and the light emitting element is located on the array substrate;

[0008] The array substrate comprises:

[0009] substrate substrate;

[0010] An active layer located on one side of the substrate base;

[0011] A multi-layer metal layer located on the side of the active layer facing away from the substrate;

[0012] The display area includes multiple sub-display areas, each of which includes at least two alignment marks. The alignment marks are used for alignment when the light-emitting element is transferred to the array substrate. The alignment marks are located in a metal layer among the multiple metal layers. A clearance area is arranged around the alignment marks. The multiple metal layers expose the alignment marks and the clearance area around the alignment marks.

[0013] In a second aspect, an embodiment of the present application provides a display device, comprising the above-mentioned display panel.

[0014] Compared with the prior art, the above technical solution has the following advantages:

[0015] In the display panel provided in the embodiment of the present application, the display area includes not only a plurality of light-emitting elements and a plurality of pixel circuits, but also at least one driving circuit, that is, by arranging at least one driving circuit in the display area, the display panel can be a display panel with an extremely narrow frame or even a frameless frame; and, by dividing the display area into a plurality of sub-display areas and arranging at least two alignment marks in the sub-display areas, the alignment marks located in the sub-display areas are used to align the light-emitting elements when they are transferred to the array substrate of the display panel; at the same time, the alignment mark is arranged in a metal layer among the multi-layer metal layers located on the side of the active layer away from the base substrate, and a clearance area is arranged around the alignment mark, and the multi-layer metal layers located on the side of the active layer away from the base substrate expose the alignment mark and the clearance area around the alignment mark, thereby ensuring that the alignment mark is accurately identified; and finally, the light-emitting elements are accurately transferred to the array substrate of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic top view of a display panel provided in an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of a circuit structure of a pixel circuit;

[0019] Figure 3 A schematic diagram of the electrical connection relationship between a pixel circuit and a driving circuit in a display area of ​​a display panel provided in an embodiment of the present application;

[0020] Figure 4 A partial top view schematic diagram of a display panel provided in an embodiment of the present application;

[0021] Figure 5 A schematic top view of another display panel provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of a partial cross-sectional structure of a display panel provided in an embodiment of the present application;

[0023] Figure 7 A schematic top view of another display panel provided in an embodiment of the present application

[0024] Figure 8 A schematic diagram of a partial cross-sectional structure of an array substrate in a display panel provided in an embodiment of the present application;

[0025] Fig. 9 for Figure 7 A schematic diagram of a local layout structure of the A1 area in the middle display area of ​​the display panel shown;

[0026] Fig.10 for Fig. 9 Schematic diagram of the layout structure of the active layer q;

[0027] Fig.11 for Fig. 9 Schematic diagram of the layout structure of the first metal layer M3;

[0028] Fig.12 for Fig. 9 A schematic diagram of the layout structure of the second metal layer M4;

[0029] Fig.13 for Fig. 9 A schematic diagram of the stacking layout structure of the first metal layer M3 and the second metal layer M4;

[0030] Fig.14 A schematic diagram of a partial cross-sectional structure of an array substrate in another display panel provided in an embodiment of the present application;

[0031] Fig.15 for Figure 7 Another schematic diagram of a partial layout structure of the A1 area in the middle display area of ​​the display panel shown;

[0032] Fig.16 for Fig.15 Schematic diagram of the layout structure of the active layer q;

[0033] Fig.17 for Fig.15 Schematic diagram of the layout structure of the first metal layer M3;

[0034] Fig.18 for Fig.15 A schematic diagram of the layout structure of the second metal layer M4;

[0035] Fig.19 for Figure 7 A schematic diagram of the layout structure of the first metal layer M3 in the A2 area of ​​the display area close to the edge of the display panel shown;

[0036] Fig. 20 for Figure 7 A schematic diagram of the layout structure of the second metal layer M4 in the area A2 in the display area close to the edge of the display panel shown;

[0037] Fig.21 A partial enlarged schematic diagram of the first metal layer M3 and the second metal layer M4 in the routing area FF;

[0038] Fig. 22 A schematic diagram of a partial layout structure of a second metal layer M4 located in a wiring area in a display panel provided in an embodiment of the present application;

[0039] Fig.23 for Fig. 22 A schematic diagram of a stacked layout structure of a first metal layer M3 and a second metal layer M4 in the area shown;

[0040] Fig.24 for Fig. 22 A schematic diagram of another stacking layout structure of the first metal layer M3 and the second metal layer M4 in the shown area;

[0041] Fig.25 Another partial enlarged schematic diagram of the first metal layer M3 and the second metal layer M4 in the routing area FF;

[0042] Fig.26 for Fig. 22 A schematic diagram of another stacking layout structure of the first metal layer M3 and the second metal layer M4 in the shown area;

[0043] Fig. 27 A schematic diagram of a partial layout structure of a second metal layer M4 in a wiring area in another display panel provided in an embodiment of the present application;

[0044] Fig.28 for Fig. 27 A schematic diagram of a stacked layout structure of a first metal layer M3 and a second metal layer M4 in the area shown;

[0045] Fig.29 Another partial enlarged schematic diagram of the first metal layer M3 and the second metal layer M4 in the routing area FF;

[0046] Fig.30 It is another partial enlarged schematic diagram of the first metal layer M3 and the second metal layer M4 in the routing area FF;

[0047] Fig.31 A partial enlarged schematic diagram of the third metal layer M2, the first metal layer M3 and the second metal layer M4 in the routing area FF;

[0048] Fig.32is another partial enlarged schematic diagram of the third metal layer M2, the first metal layer M3 and the second metal layer M4 in the routing area FF;

[0049] Fig.33 A schematic top view of another display panel provided in an embodiment of the present application;

[0050] Fig.34 A schematic top view of another display panel provided in an embodiment of the present application;

[0051] Fig.35 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0052] Fig.36 A schematic diagram of the structure of another display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0055] Figure 1 A schematic top view of a display panel provided in an embodiment of the present application is shown. Figure 1 As shown, the display panel includes a display area AA, the display panel includes a plurality of pixel circuits 10 and at least one driving circuit 20, the driving circuit 20 includes a shift register circuit 21 with a multi-stage cascade arrangement, and the shift register circuit 21 is used to transmit a driving signal to the pixel circuit 10.

[0056] In order to better understand this application, Figure 2 A circuit structure diagram of a pixel circuit 10 is shown. Figure 2As shown, the pixel circuit 10 can be a 13T2C structure, and the pixel circuit 10 can include a pulse width module PWM controlled by pulse width modulation (Pulse Width Modulation) and an amplitude module PAM controlled by pulse amplitude modulation (Pulse Amplitude Modulation), so that the luminous efficiency and viewing angle color bias of the driven light-emitting element 30 (micro light-emitting diode) can reach the optimal state. Among them, the pulse width module PWM in the pixel circuit 10 may include 6 thin film transistors (G1-G6) and a capacitor (C1), the pulse width module PWM can receive the scanning signal SN1-PWM, the scanning signal SN2-PWM, the light control signal EM-PWM, the reference voltage signal Vref-PWM, the data signal data-PWM, the shutdown voltage signal VDD-PWM and the pulse width control voltage signal Sweep, and the pulse width module PWM is used to control the light emission duration of the light emitting element 30 (such as a light emitting diode); the amplitude module PAM in the pixel circuit 10 may include 7 thin film transistors (G7-G13) and a capacitor (C2), the amplitude module PAM can receive the scanning signal SN1-PWM, the scanning signal SN2-PWM, the light control signal EM-PWM, the reference voltage signal Vref-PWM, the data signal data-PWM and the first power supply voltage signal VPVDD, the amplitude module PAM is electrically connected to one electrode of the light emitting element 30, and the other electrode of the light emitting element 30 is electrically connected to receive the second power supply voltage signal VPVEE, and the amplitude module PAM is used to control the light emission intensity of the light emitting element 30 (such as a light emitting diode). The electrical connection relationship between the transistors in the 13T2C pixel circuit and the electrical connection relationship between the transistors and the signal lines are as follows: Figure 2 As shown, no further details are given.

[0057] Figure 3 A schematic diagram showing the electrical connection relationship between the pixel circuit 10 and the driving circuit 20 in the display area AA of a display panel provided by an embodiment of the present application is shown. Figure 1-Figure 3As shown, the driving circuit 20 may include a scanning circuit STV1, a scanning circuit STV2, a scanning circuit STV3 and a scanning circuit STV4; wherein the scanning circuit STV1 includes a multi-stage cascaded shift register circuit Scan1, and the shift register circuit Scan1 provides a scanning signal SN1-PAM to the amplitude module PAM in the pixel circuit 10; the scanning circuit STV2 includes a multi-stage cascaded shift register circuit Scan2, and the shift register circuit Scan2 provides a scanning signal SN2-PAM to the amplitude module PAM in the pixel circuit 10; the scanning circuit STV3 includes a multi-stage cascaded shift register circuit Scan3, and the shift register circuit Scan3 provides a scanning signal SN1-PWM to the pulse width module PWM in the pixel circuit 10; the scanning circuit STV4 includes a multi-stage cascaded shift register circuit Scan4, and the shift register circuit Scan4 provides a scanning signal line SN2-PWM to the amplitude module PWM in the pixel circuit 10. In addition, Figure 3 It is also shown in the figure that the amplitude module PWM in the pixel circuit 10 also receives the light emitting control signal EM-PWM and the pulse width control voltage signal Sweep, and the amplitude module PAM in the pixel circuit 10 also receives the light emitting control signal line EM-PAM.

[0058] Figure 4 A partial top view of a display panel provided in an embodiment of the present application is shown. Figure 4 As shown, the display panel includes a plurality of light emitting elements 30, and is combined with Figure 2 As shown, the pixel circuit 10 is electrically connected to the light emitting element 30, and the pixel circuit 10 is used to drive the light emitting element 30 to emit light. The light emitting element 30 can be a micro light emitting diode such as a sub-millimeter light emitting diode (Mini-LED) or a micro light emitting diode (Micro-LED).

[0059] like Figure 4 As shown, the display panel may include a pixel circuit group 100, the pixel circuit group 100 may include at least two pixel circuits 10, the pixel circuit group 100 is arranged in a row along a first direction X, and multiple rows of pixel circuit groups 100 are arranged along a second direction Y, the first direction X and the second direction Y intersect, and the first direction X and the second direction Y are parallel to the plane where the display panel is located. Accordingly, as Figure 4 As shown, the display panel may also include a light emitting element group 300, which may include at least two light emitting elements 30, and the light emitting element group 300 is also arranged in a row along the first direction X, and multiple rows of light emitting element groups 300 are also arranged along the second direction Y. The pixel circuit group 100 and the light emitting element group 300 are electrically connected accordingly.

[0060] Optional, such as Figure 4As shown, the light emitting element 30 includes a first light emitting element 31, a second light emitting element 32 and a third light emitting element 33. The first light emitting element 31 can be used to emit red light, the second light emitting element 32 can be used to emit green light, and the third light emitting element 33 can be used to emit blue light. A light emitting element group 300 includes a first light emitting element 31, a second light emitting element 32 and a third light emitting element 33. Accordingly, as Figure 4 As shown, a pixel circuit group 100 includes a first pixel circuit 11 driving a first light emitting element 31 to emit light, a second pixel circuit 12 driving a second light emitting element 32 to emit light, and a third pixel circuit 13 driving a third light emitting element 33 to emit light.

[0061] In order to arrange at least one driving circuit 20 in the display area AA, and considering that a certain distance is required between the pixel circuit 10 and the frame of the display panel, Figure 4 As shown, in the edge area of ​​the display area AA (such as Figure 4 The pixel circuit 10 and the corresponding electrically connected light emitting element 30 at least partially do not overlap in the direction perpendicular to the plane where the display panel is located, and in the middle area of ​​the display area AA (such as Figure 4 In other words, in the edge area of ​​the display area AA1, the pixel circuit 10 and the corresponding electrically connected light emitting element 30 at least partially overlap in a direction perpendicular to the plane where the display panel is located. Figure 4 The pixel circuit group 100 and the corresponding electrically connected light emitting element group 300 at least partially do not overlap in the direction perpendicular to the plane where the display panel is located, and in the middle area of ​​the display area AA (such as Figure 4 In the middle area AA1), the pixel circuit group 100 and the corresponding electrically connected light emitting element group 300 at least partially overlap in a direction perpendicular to the plane where the display panel is located, so that a display panel with an extremely narrow frame or even no frame is realized.

[0062] Optional, such as Figure 1 As shown, the shift register circuit 21 may be located between pixel circuits 10 in different columns, or in other words, the shift register circuit 21 may be located between pixel circuit groups 100 in different columns.

[0063] Figure 5 FIG. 4 shows a top view of another display panel provided in an embodiment of the present application. Figure 5 As shown, alternatively, the shift register circuit 21 may also be located between pixel circuits 10 in different rows, or in other words, the shift register circuit 21 may be located between pixel circuit groups 100 in different rows.

[0064] Figure 6 A partial cross-sectional structure diagram of a display panel provided in an embodiment of the present application is shown. Figure 6As shown, the display panel includes an array substrate 200 , the array substrate 200 includes a pixel circuit 10 and a driving circuit 20 , and the light emitting element 30 is located on the array substrate 200 , that is, the light emitting element 30 is transferred to the array substrate 200 .

[0065] like Figure 6 As shown, the array substrate 200 includes a base substrate sub, an active layer q located on one side of the base substrate sub, and a multi-layer metal layer located on the side of the active layer q away from the base substrate sub. The multi-layer metal layer includes, for example, a metal layer M1, a metal layer M2, a metal layer M3 and a metal layer M4 arranged in sequence along a direction away from the base substrate sub.

[0066] like Figure 6 As shown, the light-emitting element 30 includes a first semiconductor layer 301, an active layer 302 and a second semiconductor layer 303 which are stacked, the first semiconductor layer 301 is electrically connected to the first electrode D1, the second semiconductor layer 303 is electrically connected to the second electrode D, the first electrode D1 and the second electrode D2 of the light-emitting element 30 are bonded to the array substrate 200 through the bonding layer J1, and the light-emitting element 30 is electrically connected to the pixel circuit 10.

[0067] like Figure 6 As shown, the thin film transistor Gx (eg Figure 2 The thin film transistor Gx includes an active portion b1, a gate g1, a source electrode s1, and a drain electrode d1. The active portion b1 of the thin film transistor Gx is located in the active layer q. Similarly, the thin film transistor Gy in the driving circuit 20 also includes an active portion b2, a gate g2, a source electrode s2, and a drain electrode d2. The active portion b2 of the thin film transistor Gy is located in the active layer q.

[0068] Figure 7 A schematic top view of another display panel provided in an embodiment of the present application is shown. Figure 7 As shown, the display area AA of the display panel includes multiple sub-display areas AA0, and the sub-display area AA0 includes at least two alignment marks R, which are used for alignment when the light-emitting element 30 is transferred to the array substrate 200, and a clearance area H is arranged around the alignment mark R.

[0069] Figure 8 A partial cross-sectional structure diagram of an array substrate 200 in a display panel provided in an embodiment of the present application is shown. Figure 6-Figure 8 As shown, the alignment mark R may be located in a metal layer of the multi-layer metal layers on the side of the active layer q away from the substrate sub, and the multi-layer metal layers located on the side of the active layer q away from the substrate sub expose the alignment mark R and the clearance area H around the alignment mark R. Figure 8In the array substrate 200 shown, the multi-layer metal layers located on the side of the active layer q away from the base substrate sub further include a metal layer MC located between the metal layer M1 and the metal layer M2.

[0070] It is understandable that when the light emitting element 30 is transferred to the array substrate 200, the alignment mark R needs to be accurately identified. In order to accurately identify the alignment mark R, a clearance area H needs to be set around the alignment mark R, so that when the array substrate 200 is viewed from above in the direction toward the base substrate sub, only the alignment mark R can be seen within the alignment mark R and the clearance area H around the alignment mark R, and no other graphics. It is also understandable that the multi-layer metal layer located on the side of the active layer q away from the base substrate sub needs to expose the alignment mark R and the clearance area H around the alignment mark R so that the alignment mark R can be identified.

[0071] It can also be understood that the display area AA is divided into multiple sub-display areas AA0, and each sub-display area AA0 is provided with at least two alignment marks R. In this way, when the light-emitting element 30 is transferred to the array substrate 200, the accuracy of identifying the alignment mark R and the alignment accuracy of transferring the light-emitting element 30 to the array substrate 200 can be improved.

[0072] It can be seen that the display panel provided in the embodiment of the present application can be an extremely narrow frame or even a frameless display panel by setting at least one driving circuit 20 in the display area AA; and, by dividing the display area AA into multiple sub-display areas AA0, and setting at least two alignment marks R in the sub-display area AA0, the alignment mark R located in the sub-display area AA0 is used to align the light-emitting element 30 when it is transferred to the array substrate 200 of the display panel; at the same time, the alignment mark R is set in a metal layer in the multi-layer metal layer located on the side of the active layer q away from the base substrate sub, and a clearance area H is set around the alignment mark R, and the multi-layer metal layer located on the side of the active layer py away from the base substrate sub exposes the alignment mark R and the clearance area H around the alignment mark R, thereby ensuring that the alignment mark R is accurately identified; ultimately, the light-emitting element 30 is accurately transferred to the array substrate 200 of the display panel.

[0073] As known above, the multi-layer metal layer located on the side of the active layer q away from the substrate sub includes a first metal layer M3 and a second metal layer M4. The second metal layer M4 is located on the side of the first metal layer M3 away from the substrate sub. Fig. 9 Shows Figure 7 A schematic diagram of a local layout structure of the A1 area in the middle display area of ​​the display panel is shown. For the sake of clarity, Fig. 9Only the layout structure of the active layer q, the layout structure of the first metal layer M3 and the layout structure of the second metal layer M4 are shown. Fig.10 It further shows Fig. 9 Schematic diagram of the layout structure of the active layer q, Fig.11 It further shows Fig. 9 Schematic diagram of the layout structure of the first metal layer M3, Fig.12 It further shows Fig. 9 Schematic diagram of the layout structure of the second metal layer M4.

[0074] Combination Fig. 9 and Fig.11 As shown, the first metal layer M3 includes a solid portion T1 and a plurality of openings T2 . The solid portion T1 of the first metal layer M3 includes a first power structure PVDD. The first power structure PVDD is used to provide a first power voltage signal VPVDD.

[0075] Combination Fig. 9 and Fig.12 As shown, the second metal layer M4 includes a solid portion U1 and a plurality of openings U2 . The solid portion U1 of the second metal layer M4 includes a second power structure PVEE. The second power structure PVEE is used to provide a second power voltage signal VPVEE.

[0076] Combination Figure 2 and Figure 6 As shown, the first power structure PVDD is electrically connected to the pixel circuit 10 , the pixel circuit 10 is electrically connected to the first electrode D1 of the light emitting element 30 , and the second power structure PVEE is electrically connected to the second electrode D2 of the light emitting element 30 .

[0077] Corresponding to the layout structure, such as Fig. 9 and Fig.10 As shown, the active layer q of the display panel includes a first active portion q1, and the pixel circuit 10 includes the first active portion q1, the first active portion q1 includes the active portion of each thin film transistor in the pixel circuit 10, in the present application, for clarity of the diagram, the first active portion q1 in the pixel circuit 10 represents the pixel circuit 10, it can be understood that the pixel circuit 10 also includes other film layer structures.

[0078] Fig. 9 and Fig.12 The bonding position of the first electrode D1 and the second electrode D2 of the light emitting element 30 is also shown. For the convenience of marking, the bonding position of the first electrode D1 and the second electrode D2 of the light emitting element 30 represents the light emitting element 30.

[0079] Combination Figure 6 , Figure 9-12 It can be seen that the second power structure PVEE is electrically connected to the second electrode D2 of the light emitting element 30 .

[0080] Combination Figure 6 , Figure 9-12 It can be seen that the first power structure PVDD includes a first connection portion L1, and the first power structure PVDD is electrically connected to the pixel circuit 10 through the first connection portion L1; Figure 6 , Figure 9-12 It can also be seen that the physical part U1 of the second metal layer M4 also includes a first auxiliary electrode I1, and an opening V1 is provided between the first auxiliary electrode I1 and the second power structure PVEE, so that the first auxiliary electrode I1 and the second power structure PVEE are insulated from each other, and the physical part T1 of the first metal layer M3 also includes a second auxiliary electrode I2, and an opening V2 is provided between the second auxiliary electrode I2 and the first power structure PVDD, so that the second auxiliary electrode I2 and the first power structure PVDD are insulated from each other, so that the pixel circuit 10 is electrically connected in sequence through the second auxiliary electrode I2, the first auxiliary electrode I1 and the first electrode D1 of the light-emitting element 30.

[0081] Optionally, in some embodiments of the present application, the first power structure PVDD located in the first metal layer M3 and the second power structure PVEE located in the second metal layer M4 adopt a grid design, and the first metal layer M3 and the second metal layer M4 have hollow areas, and the alignment mark R and the clearance area H around the alignment mark R can be set in the hollow area of ​​the second metal layer M4, or in the hollow area of ​​the first metal layer M3.

[0082] However, when the first power structure PVDD located on the first metal layer M3 and the second power structure PVEE located on the second metal layer M4 adopt a grid design, due to process limitations, the thickness of the first metal layer M3 is limited to a certain extent, resulting in a large impedance of the first power structure PVDD, and a large difference in IR drop across the entire surface of the first power structure PVDD, which can easily affect the brightness uniformity of the display panel; similarly, the thickness of the second metal layer M4 is also limited to a certain extent, resulting in a large impedance of the second power structure PVEE, and a large difference in IR drop across the entire surface of the second power structure PVEE, which can easily affect the brightness uniformity of the display panel.

[0083] To this end, if the area of ​​the first power structure PVDD is increased, the impedance of the first power structure PVDD can be reduced, thereby improving the uniformity of the display brightness of the display panel. If the area of ​​the second power structure PVEE is increased, the impedance of the second power structure PVEE can be reduced, thereby improving the uniformity of the display brightness of the display panel. If the area of ​​the first power structure PVDD and the area of ​​the second power structure PVEE are increased at the same time, the impedance of the first power structure PVDD can be reduced, and the impedance of the second power structure PVEE can also be reduced, thereby improving the uniformity of the display brightness of the display panel.

[0084] like Figure 9-12 As shown, the display panel includes a pixel circuit group 100, the pixel circuit group 100 includes at least two pixel circuits 10, the pixel circuit group 100 is arranged in a row along a first direction X, and multiple rows of pixel circuit groups 100 are arranged along a second direction Y; accordingly, the display panel also includes a light emitting element group 300, the light emitting element group 300 includes at least two light emitting elements 30, the light emitting element group 300 is also arranged in a row along the first direction X, and multiple rows of light emitting element groups 300 are also arranged along the second direction Y; the pixel circuit group 100 and the light emitting element group 300 are electrically connected accordingly.

[0085] Optional, such as Figure 9-12 As shown, the light emitting element 30 includes a first light emitting element 31, a second light emitting element 32 and a third light emitting element 33. The first light emitting element 31 can be used to emit red light, the second light emitting element 32 can be used to emit green light, and the third light emitting element 33 can be used to emit blue light. A light emitting element group 300 includes a first light emitting element 31, a second light emitting element 32 and a third light emitting element 33. Accordingly, as Figure 9-12 As shown, a pixel circuit group 100 includes a first pixel circuit 11 driving a first light emitting element 31 to emit light, a second pixel circuit 12 driving a second light emitting element 32 to emit light, and a third pixel circuit 13 driving a third light emitting element 33 to emit light.

[0086] In order to increase the area of ​​the first power structure PVDD and the second power structure PVEE, it is optional, such as Figure 9-12 As shown, in a direction perpendicular to the plane where the substrate sub is located, the first power structure PVDD at least partially overlaps with a group of pixel circuit groups 100, and the second power structure PVEE at least partially overlaps with a group of pixel circuit groups 100. Further optionally, as Figure 9-12 As shown, in the direction perpendicular to the plane where the substrate sub is located, the first power structure PVDD covers the orthographic projection area of ​​a group of pixel circuit groups 100 in the plane where the substrate sub is located in the orthographic projection area of ​​the plane where the substrate sub is located, and the second power structure PVEE covers the orthographic projection area of ​​a group of pixel circuit groups 100 in the plane where the substrate sub is located in the orthographic projection area of ​​the plane where the substrate sub is located.

[0087] Considering that in the actual process, arc discharge is prone to occur when a large area of ​​metal is patterned in a vacuum machine, the area of ​​the entity part T1 of the first metal layer M3 and the area of ​​the entity part U1 of the second metal layer M4 are subject to certain restrictions; furthermore, considering that in the direction perpendicular to the plane where the substrate sub is located, if the overlapping area of ​​the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4 is large, the insulation layer between the first metal layer M3 and the second metal layer M4 is damaged, which easily causes a short circuit between the two metal layers; therefore, if Figure 9-12 As shown, a plurality of openings T2 are opened in the first metal layer M3 to reduce the area of ​​the entity part T1 of the first metal layer M3, and a plurality of openings U2 are opened in the second metal layer M4 to reduce the area of ​​the entity part U1 of the second metal layer M4, thereby reducing the risk of arc discharge when the first metal layer M3 and the second metal layer M4 are subjected to patterning in a vacuum machine, and can also reduce the overlapping area of ​​the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4 in a direction perpendicular to the plane where the substrate sub is located, thereby reducing the risk of short circuit between the first metal layer M3 and the second metal layer M4 when the insulating layer between the first metal layer M3 and the second metal layer M4 is damaged.

[0088] Different metal layers in the display panel are isolated by an insulating layer, which not only isolates but also protects and supports them. Figure 6 As shown, there is an insulating layer PLN between the first metal layer M3 and the second metal layer M4, and the insulating layer PLN is an organic material layer, that is, the insulating layer PLN is an organic insulating layer. Alternatively, the insulating layer PLN may also be an inorganic material layer.

[0089] Compared with an inorganic material layer as an insulating layer, an organic material layer as an insulating layer usually has a lower manufacturing cost; moreover, the organic material layer usually has good chemical stability and physical properties, can resist the erosion of environmental factors such as moisture and oxygen, and is beneficial to extending the service life of the display panel; the organic material layer also has good flexibility and customization. However, the organic insulating layer will volatilize gas in some high-temperature processes, and exhaust design is required. In the display panel provided in the embodiment of the present application, a plurality of openings T2 are opened in the first metal layer M3, and a plurality of openings U2 are opened in the second metal layer M4, which is beneficial to the exhaust of the organic insulating layer between the first metal layer M3 and the second metal layer M4.

[0090] like Figure 9-12 As shown, the display panel includes a first blocking area CC, and as is known above, the active layer q of the display panel includes a first active portion q1, and the pixel circuit 10 includes the first active portion q1, the first active portion q1 includes the active portion of each thin film transistor in the pixel circuit 10, and the first active portion q1 is located in the first blocking area CC, that is, the active portion of each thin film transistor in the pixel circuit 10 is located in the first blocking area CC.

[0091] like Figure 9-12 As shown, combined with Fig.13 As shown, Fig.13 Shows Fig. 9Schematic diagram of the stacked layout structure of the first metal layer M3 and the second metal layer M4, in the direction perpendicular to the plane of the substrate, at least one of the solid part T1 of the first metal layer M3 and the solid part U1 of the second metal layer M4 covers the first shielding area CC, that is, covers the first active part q1, so as to avoid affecting the active part of each thin film transistor in the pixel circuit 10 when the laser bonding of the light-emitting element is performed, thereby avoiding affecting the performance of the pixel circuit 10 and ensuring the normal light emission of the light-emitting element.

[0092] It can be understood from this that Figure 9-13 As shown, combined with Fig.14 As shown, Fig.14 A schematic diagram of the partial cross-sectional structure of an array substrate 200 in another display panel provided in an embodiment of the present application is shown. In the first shielding area CC, in a direction perpendicular to the plane where the base substrate is located, the opening T2 in the first metal layer M3 and the opening U2 in the second metal layer M4 do not overlap each other, or in other words, the opening T2 in the first metal layer M3 and the opening U2 in the second metal layer M4 are arranged in an alternating and complementary manner, the opening T2 in the first metal layer M3 is shielded by the entity portion U1 in the second metal layer M4, and the opening U2 in the second metal layer M4 is shielded by the entity portion T1 in the first metal layer M3, thereby avoiding affecting the first active layer q1 in the first shielding area CC when laser bonding the light-emitting element, thereby avoiding affecting the performance of the pixel circuit 10 and ensuring normal light emission of the light-emitting element.

[0093] It can be further understood that the active layer q also includes a second active portion, the shift register circuit 21 includes the second active portion, and in a direction perpendicular to the plane of the substrate, at least one of the physical portion T1 of the first metal layer M3 and the physical portion U1 of the second metal layer M4 also covers the second active portion, thereby avoiding affecting the second active portion of the shift register circuit 21 when laser bonding the light-emitting element, thereby avoiding affecting the performance of the shift register circuit 21 and the driving circuit 20.

[0094] From the above analysis, it can be known that while increasing the area of ​​the first power structure PVDD, it is also necessary to open a plurality of openings T2 in the first power structure PVDD; similarly, while increasing the area of ​​the second power structure PVEE, it is also necessary to open a plurality of openings U2 in the second power structure PVEE; in this way, on the one hand, the area of ​​the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4 can be reduced, which is convenient for patterning in a vacuum machine; on the other hand, the overlapping area of ​​the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4 in the direction perpendicular to the plane where the substrate is located can be reduced, reducing the risk of short circuit between the two; on the other hand, it is conducive to sufficient exhaust. In addition, in order to avoid affecting the thin film transistors in the pixel circuit 10 and the thin film transistors in the shift register circuit 21 when laser bonding the light-emitting element, at least one of the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4 needs to cover the first active part q1 of the corresponding pixel circuit 10 and the second active part of the corresponding shift register circuit 21.

[0095] On this basis, Fig.15 Shows Figure 7 Another partial layout structure diagram of the A1 area in the middle display area of ​​the display panel is shown in FIG. Fig.15 Only the layout structure of the active layer q, the layout structure of the first metal layer M3 and the layout structure of the second metal layer M4 are shown. Fig.16 It further shows Fig.15 Schematic diagram of the layout structure of the active layer q, Fig.17 It further shows Fig.15 Schematic diagram of the layout structure of the first metal layer M3, Fig.18 It further shows Fig.15 Schematic diagram of the layout structure of the second metal layer M4.

[0096] like Figure 15-18 As shown, in a direction perpendicular to the plane where the substrate sub is located, the first power structure PVDD overlaps at least partially with four pixel circuit groups 100 overlapping two adjacent rows of pixel circuit groups 100 and two adjacent columns of pixel circuit groups 100; further optionally, as Figure 15-18 As shown, the orthographic projection area of ​​the first power structure PVDD on the plane where the substrate sub is located covers the orthographic projection area of ​​the 2*2 pixel circuit group 100 on the plane where the substrate sub is located.

[0097] like Figure 15-18 As shown, in a direction perpendicular to the plane where the substrate sub is located, the second power structure PVEE overlaps at least partially with four groups of pixel circuit groups 100 overlapping two adjacent rows of pixel circuit groups 100 and two adjacent columns of pixel circuit groups 100; further optionally, as Figure 15-18 As shown, the orthographic projection area of ​​the second power structure PVEE on the plane where the substrate sub is located covers the orthographic projection area of ​​the 2*2 pixel circuit group 100 on the plane where the substrate sub is located.

[0098] By analogy, the orthographic projection area of ​​the first power structure PVDD on the plane where the substrate sub is located can also cover 3*3, 3*4, 4*3, 4*4... and other different matrix pixel circuit groups 100 and the orthographic projection areas of all pixel circuit groups 100 on the plane where the substrate sub is located, and even the orthographic projection area of ​​the first power structure PVDD on the plane where the substrate sub is located can cover the entire display area AA of the display panel; and, as the orthographic projection area of ​​the first power structure PVDD on the plane where the substrate sub is located increases, the area of ​​the first power structure PVDD increases, and the impedance of the first power structure PVDD decreases, the more conducive it is to improving the display brightness uniformity of the display panel.

[0099] Similarly, the orthographic projection area of ​​the second power supply structure PVEE on the plane where the substrate sub is located can also cover different matrix pixel circuit groups 100 such as 3*3, 3*4, 4*3, 4*4... and the orthographic projection areas of all pixel circuit groups 100 on the plane where the substrate sub is located, and even the orthographic projection area of ​​the second power supply structure PVEE on the plane where the substrate sub is located can cover the entire display area AA of the display panel; and, as the orthographic projection area of ​​the second power supply structure PVEE on the plane where the substrate sub is located increases, the area of ​​the second power supply structure PVEE increases, and the impedance of the second power supply structure PVEE decreases, which is more conducive to improving the display brightness uniformity of the display panel.

[0100] It should be noted that a group of pixel circuits 100 and a group of light emitting elements 300 form a pixel unit pixel. Figure 9-13 It shows a pixel unit. Figure 15-18 Four pixel units are shown schematically, and the four pixel units form a matrix of two rows and two columns (ie, 2*2) along a first direction X and a second direction Y. In order to clearly distinguish different pixel units, Figure 15-18 In the figure, horizontal lines and vertical lines are used to indicate the boundaries of adjacent pixel unit regions along the first direction X and the second direction Y. It can be understood that the boundaries are only for the convenience of explanation and are not intended to limit the present invention.

[0101] like Figure 2As shown, the pixel circuit 100 includes a pulse width module PWM and an amplitude module PAM. Although the pulse width module PWM in the pixel circuit 100 is also connected to the off voltage signal VDD-PWM, and the off voltage signal VDD-PWM is similar to the first power supply voltage signal VPVDD, since the amplitude module PAM directly drives the light-emitting element 30, the first power supply structure PVDD is electrically connected to the amplitude module PAM of the pixel circuit 100, that is, the first power supply structure PVDD provides the first power supply voltage signal VPVDD to the amplitude module PAM of the pixel circuit 100. In this way, by increasing the area of ​​the first power supply structure PVDD, the brightness uniformity of the display panel can be more directly improved.

[0102] Fig.19 Shows Figure 7 The schematic diagram of the layout structure of the first metal layer M3 in the A2 area of ​​the display area near the edge of the display panel is shown, Fig. 20 Shows Figure 7 The schematic diagram of the layout structure of the second metal layer M4 in the A2 area of ​​the display area near the edge of the display panel is shown in FIG. Figure 4 , Fig.19 and Fig. 20 As shown, the display area AA of the display panel includes a first display area AA1 and a second display area AA2, and the second display area AA2 at least partially surrounds the first display area AA1; the second display area AA2 includes a plurality of light-emitting element groups 300, a plurality of pixel circuit groups 100 and a driving circuit 20, and in the second display area AA2, in a direction perpendicular to the plane where the substrate is located, the pixel circuit group 100 and the electrically connected light-emitting element group 300 at least partially do not overlap; the first display area AA1 includes a plurality of light-emitting element groups 300 and a plurality of pixel circuit groups 100, and in the first display area AA1, in a direction perpendicular to the plane where the substrate is located, the pixel circuit group 100 and the electrically connected light-emitting element group 300 at least partially overlap.

[0103] It is understandable that, combined with Figure 4 , Fig.19 and Fig. 20 As shown, normally, in the first display area AA1, in the direction perpendicular to the plane where the substrate is located, the pixel circuit group 100 and the electrically connected light emitting element group 300 at least partially overlap, so that the pixel circuit group 100 is electrically connected to the corresponding light emitting element group 300. In the second display area AA2, due to the addition of the driving circuit 20, and considering that there needs to be a certain distance between the pixel circuit 10 and the frame of the display panel, the pixel circuit group 100 and the electrically connected light emitting element group 300 are arranged in the direction perpendicular to the plane where the substrate is located, and at least partially do not overlap.

[0104] It is also understandable that, combined with Figure 4 , Fig.19 and Fig. 20 As shown, in the second display area AA2, since the pixel circuit group 100 and the electrically connected light emitting element group 300 do not overlap at least partially in the direction perpendicular to the plane of the substrate, in order for the pixel circuit group 100 to be electrically connected to the corresponding light emitting element group 300, some flying wires F1 need to be set, for example, a plurality of flying wires F1 are set in the first metal layer M3, so that the pixel circuit group 100 can be electrically connected to the corresponding light emitting element group 300.

[0105] Therefore, if Fig. 20 As shown, in the second display area AA2, the openings of the second metal layer M4 include a plurality of second openings K2; in the first display area AA1, the openings of the second metal layer M4 include a plurality of second openings K2 and a plurality of third openings K3, and the area of ​​the third openings K3 is greater than the area of ​​the second openings K2. In other words, the second metal layer M4 is only provided with a plurality of small openings in the second display area AA2, while a large opening and a small opening can be provided in the first display area AA1. This is because the flying wires provided in the second display area AA2 will cut the corresponding metal layer, and in order to maintain the integrity of the metal as much as possible so as to provide a better power supply capability, the second metal layer M4 is only designed with a small opening in the second display area AA2 close to the edge of the display panel, while a combination of a large opening and a small opening can be provided in the first display area AA1 in the middle of the display panel.

[0106] Combination Figure 9-13 as well as Figure 15-Figure 20 As shown, in the first display area AA1, a wiring area FF is provided on at least one side of the pixel circuit group 100 along the first direction X. Optionally, a wiring area FF is provided on both sides of the pixel circuit group 100 along the first direction X. The wiring area FF includes signal lines extending along the second direction Y, for example, data signal lines for transmitting data signals to the pixel circuit 10, and signal lines for transmitting driving signals to the driving circuit 20 (such as the shift register circuit 21 in the driving circuit 20); since the wiring area FF is not provided with an active layer q, the wiring area FF does not have the requirement to be completely covered by the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4. In the first display area AA1, the second metal layer M4 can be provided with a third opening K3 with a larger area in the wiring area FF, that is, the third opening K3 can be located in the wiring area FF, and the third opening K3 is arranged along the second direction Y in the wiring area FF.

[0107] In addition, the second metal layer M4 is provided with some third openings K3 with larger areas in the routing area FF, which can reduce the area of ​​the physical part U1 of the second metal layer M4, facilitate patterning in a vacuum machine, and reduce the overlapping area between the physical part T1 of the first metal layer M3 and the physical part U1 of the second metal layer M4, thereby reducing the risk of short circuit between the two. Moreover, it can also reduce the coupling between the physical part U1 of the second metal layer M4 (such as the second power structure PVFF) and the signal line in the routing area FF.

[0108] In this way, the sub-display area AA0 may at least partially overlap with the first display area AA1 , so that the alignment mark R and the clearance area H around the alignment mark R may be located in the third opening K3 with a larger area in the second metal layer M4 .

[0109] Combination Figure 9-13 as well as Figure 15-Figure 20 As shown, in the second metal layer M4, except for the third opening K3 located in the routing area FF and the opening V1 between the second power structure PVEE and the first auxiliary electrode I1, the other areas are basically set as the second opening K2, that is, the second opening K2 is evenly arranged in the entire display area AA, which is conducive to improving the etching uniformity and the uniformity of the reflection effect of the display panel. In addition, the first auxiliary electrode I1 may be provided with a second opening K2 with a relatively small area.

[0110] Combination Figure 9-13 as well as Figure 15-Figure 20 As shown, in the first display area AA1, along the second direction Y, the third opening K3 and the plurality of second openings K2 are alternately arranged, that is, the second metal layer M4 is in the routing area FF, and a plurality of second openings K2 are also provided between the third openings K3 adjacent to each other along the second direction Y. In this way, not only are some third openings K3 having an area larger than the second openings K2 provided in the routing area FF, but the plurality of second openings K2 are also retained, so that the pattern density of the second metal layer M4 in the routing area FF is relatively uniform with that in the first shielding area CC, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0111] It should be noted that, combined with Figure 9-13 as well as Figure 15-Figure 20As shown, the third opening K3 is larger than the area of ​​the second opening K2. Optionally, the length of the third opening K3 along the first direction X is larger than the length of the second opening K2 along the first direction X. Thus, along the first direction X, the third opening K3 overlaps with multiple second openings K2. Alternatively, the width of the third opening K3 along the second direction Y is larger than the width of the second opening K2 along the second direction Y. Thus, along the second direction Y, the third opening K3 overlaps with multiple second openings K2. Alternatively, the length of the third opening K3 along the first direction X is larger than the length of the second opening K2 along the first direction X, and the width of the third opening K3 along the second direction Y is larger than the width of the second opening K2 along the second direction Y. Thus, along the first direction X and the second direction Y, the third opening K3 overlaps with multiple second openings K2. In summary, along the first direction X and / or the second direction Y, the third opening K3 overlaps with multiple second openings K2.

[0112] Similarly, if Fig.19 As shown, in the second display area AA2, the openings of the first metal layer M3 include a plurality of fourth openings K4; in the first display area AA1, the openings of the first metal layer M3 include a plurality of fourth openings K4 and a plurality of fifth openings K5, and the area of ​​the fifth openings K5 is greater than the area of ​​the fourth openings K4. In other words, the first metal layer M3 is only provided with a plurality of small openings in the second display area AA2, while a large opening and a small opening can be provided in the first display area AA1. This is because the flying wires provided in the second display area AA2 will cut the corresponding metal layer, and in order to maintain the integrity of the metal as much as possible so as to provide a better power supply capability, the first metal layer M3 is only designed with a small opening in the second display area AA2 close to the edge of the display panel, while a combination of a large opening and a small opening can be provided in the first display area AA1 in the middle of the display panel.

[0113] Combination Figure 9-13 as well as Figure 15-Figure 20 As shown, in the first display area AA1, a wiring area FF is provided on at least one side of the pixel circuit group 100 along the first direction X. Optionally, a wiring area FF is provided on both sides of the pixel circuit group 100 along the first direction X. The wiring area FF includes signal lines extending along the second direction Y, for example, data signal lines for transmitting data signals to the pixel circuit 10, and signal lines for transmitting driving signals to the driving circuit 20 (such as the shift register circuit 21 in the driving circuit 20); since the wiring area FF is not provided with an active layer q, the wiring area FF does not have the requirement to be completely covered by the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4. In the first display area AA1, the first metal layer M3 can be provided with a fifth opening K5 with a larger area in the wiring area FF, that is, the fifth opening K5 can be located in the wiring area FF, and the fifth opening K5 is arranged along the second direction Y in the wiring area FF.

[0114] In addition, the first metal layer M3 sets some larger fifth openings K5 in the routing area FF, which can reduce the area of ​​the physical part T1 of the first metal layer M3, facilitate patterning in the vacuum machine, and reduce the overlapping area of ​​the physical part T1 of the first metal layer M3 and the physical part U1 of the second metal layer M4, thereby reducing the risk of short circuit between the two. Moreover, it can also reduce the coupling between the physical part T1 of the first metal layer M3 (such as the first power structure PVDD) and the signal line in the routing area FF.

[0115] In this way, the sub-display area AA0 may at least partially overlap with the first display area AA1 , so that the alignment mark R and the clearance area H around the alignment mark R may be located at the fifth opening K5 with a larger area in the first metal layer M3 .

[0116] Combination Figure 9-13 as well as Figure 15-Figure 20 As shown, in the first metal layer M3, except for the fifth opening K5 located in the routing area FF and the opening V2 between the first power structure PVDD and the second auxiliary electrode I2, other areas are basically set to the fourth opening K4, that is, the fourth opening K4 is evenly arranged in the entire display area AA, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0117] Combination Figure 9-13 as well as Figure 15-Figure 20 As shown, in the first display area AA1, along the second direction Y, the fifth opening K5 and the plurality of fourth openings K4 are alternately arranged, that is, the first metal layer M3 is in the routing area FF, and a plurality of fourth openings K4 are also provided between the fifth openings K5 adjacent to each other along the second direction Y. Thus, not only are some fifth openings K5 having an area larger than the fourth openings K4 provided on the first metal layer M3 in the routing area FF, but a plurality of fourth openings K4 are also retained, so that the pattern density of the first metal layer M3 in the routing area FF is relatively uniform with that in the first shielding area CC, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0118] It should be noted that, combined with Figure 9-13 as well as Figure 15-Figure 20As shown, the area of ​​the fifth opening K5 is larger than that of the fourth opening K4. Optionally, the length of the fifth opening K5 along the first direction X is larger than the length of the fourth opening K4 along the first direction X. Thus, along the first direction X, the fifth opening K5 overlaps with a plurality of fourth openings K4. Alternatively, the width of the fifth opening K5 along the second direction Y is larger than the width of the fourth opening K4 along the second direction Y. Thus, along the second direction Y, the fifth opening K5 overlaps with a plurality of fourth openings K4. Alternatively, the length of the fifth opening K5 along the first direction X is larger than the length of the fourth opening K4 along the first direction X, and the width of the fifth opening K5 along the second direction Y is larger than the width of the fourth opening K4 along the second direction Y. Thus, along the first direction X and the second direction Y, the fifth opening K5 overlaps with a plurality of fourth openings K4. In summary, along the first direction X and / or the second direction Y, the fifth opening K5 overlaps with a plurality of fourth openings K4.

[0119] Optional, combined Figure 9-13 as well as Figure 15-Figure 20 As shown, the opening designs of the first metal layer M3 and the second metal layer M4 can be combined. Specifically, in the second display area AA2, the openings of the second metal layer M4 include multiple second openings K2; in the first display area AA1, the openings of the second metal layer M4 include multiple second openings K2 and multiple third openings K3, and the area of ​​the third openings K3 is larger than the area of ​​the second openings K2, that is, the second metal layer M4 is only designed with a small opening in the second display area AA2 close to the edge of the display panel, while the first display area AA1 in the middle of the display panel can be designed with a combination of large openings and small openings.

[0120] At the same time, in the second display area AA2, the openings of the first metal layer M3 include multiple fourth openings K4; in the first display area AA1, the openings of the first metal layer M3 include multiple fourth openings K4 and multiple fifth openings K5, and the area of ​​the fifth openings K5 is larger than the area of ​​the fourth openings K4, that is, the first metal layer M3 is only designed with small openings in the second display area AA2 close to the edge of the display panel, while the first display area AA1 in the middle of the display panel can be designed with a combination of large and small openings.

[0121] Combination Figure 9-13 as well as Figure 15-Figure 20As shown, in the first display area AA1, a wiring area FF is provided on at least one side of the pixel circuit group 100 along the first direction X. Optionally, a wiring area FF is provided on both sides of the pixel circuit group 100 along the first direction X. The wiring area FF includes signal lines extending along the second direction Y, for example, data signal lines for transmitting data signals to the pixel circuit 10, and signal lines for transmitting driving signals to the driving circuit 20 (such as the shift register circuit 21 in the driving circuit 20); since the wiring area FF is not provided with an active layer q, the wiring area FF does not have the requirement to be completely covered by the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4. In the first display area AA1, the second metal layer M4 can be provided with a third opening K3 with a larger area in the wiring area FF, that is, the third opening K3 can be located in the wiring area FF, and the third opening K3 is arranged along the second direction Y in the wiring area FF.

[0122] Meanwhile, in the first display area AA1 , the first metal layer M3 may be provided with a fifth opening K5 with a larger area in the routing area FF, that is, the fifth opening K5 may be located in the routing area FF, and the fifth opening K5 is arranged along the second direction Y in the routing area FF.

[0123] Combination Figure 9-13 as well as Figure 15-Figure 20 As shown, the orthographic projection of the third opening K3 in the second metal layer M4 on the first metal layer M3 and the fifth opening K5 in the first metal layer M3 are arranged alternately along the second direction Y. In this way, the area of ​​the entity part T1 of the first metal layer M3 and the area of ​​the entity part U1 of the second metal layer M4 can be reduced at the same time, which is convenient for patterning in a vacuum machine, and the overlapping area of ​​the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4 can be reduced, reducing the risk of short circuit between the two, and can also reduce the coupling between the entity part T1 of the first metal layer M3 (such as the first power structure PVDD) and the signal line in the routing area FF, and the coupling between the entity part U1 of the second metal layer M4 (such as the second power structure PVEE) and the signal line in the routing area FF.

[0124] In this way, the sub-display area AA0 can at least partially overlap with the first display area AA1, so that the alignment mark R and the clearance area H around the alignment mark R can be located in the third opening K3 with a larger area in the second metal layer M4, or in the fifth opening K5 with a larger area in the first metal layer M3.

[0125] Combination Figure 9-13 as well as Figure 15-Figure 20As shown, in the second metal layer M4, except for the third opening K3 located in the routing area FF and the opening V1 between the second power structure PVEE and the first auxiliary electrode I1, the other areas are basically set as the second opening K2, that is, the second opening K2 is evenly arranged in the entire display area AA, which is conducive to improving the etching uniformity and the uniformity of the reflection effect of the display panel. In addition, the first auxiliary electrode I1 may be provided with a second opening K2 with a relatively small area.

[0126] Combination Figure 9-13 as well as Figure 15-Figure 20 As shown, in the first metal layer M3, except for the fifth opening K5 located in the routing area FF and the opening V2 between the first power structure PVDD and the second auxiliary electrode I2, other areas are basically set to the fourth opening K4, that is, the fourth opening K4 is evenly arranged in the entire display area AA, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0127] Further optional, combined Figure 9-13 as well as Figure 15-Figure 20 As shown, in the first display area AA1, along the second direction Y, the third opening K3 and the plurality of second openings K2 are alternately arranged, that is, the second metal layer M4 is in the routing area FF, and a plurality of second openings K2 are also provided between the third openings K3 adjacent to each other along the second direction Y. In this way, not only are some third openings K3 having an area larger than the second openings K2 provided in the routing area FF, but the plurality of second openings K2 are also retained, so that the pattern density of the second metal layer M4 in the routing area FF is relatively uniform with that in the first shielding area CC, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0128] At the same time, combined Figure 9-13 as well as Figure 15-Figure 20 As shown, in the first display area AA1, along the second direction Y, the fifth opening K5 and the plurality of fourth openings K4 are alternately arranged, that is, the first metal layer M3 is in the routing area FF, and a plurality of fourth openings K4 are also provided between the fifth openings K5 adjacent to each other along the second direction Y. Thus, not only are some fifth openings K5 having an area larger than the fourth openings K4 provided on the first metal layer M3 in the routing area FF, but a plurality of fourth openings K4 are also retained, so that the pattern density of the first metal layer M3 in the routing area FF is relatively uniform with that in the first shielding area CC, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0129] Combination Figure 9-13 as well as Figure 15-Figure 20As shown, optionally, the orthographic projection of the third opening K3 on the first metal layer M3 overlaps with the multiple fourth openings K4 between two adjacent fifth openings K5; another optional option, the orthographic projection of the fifth opening K5 on the second metal layer M4 overlaps with the multiple second openings K2 between two adjacent third openings K3; yet another optional option, the orthographic projection of the third opening K3 on the first metal layer M3 overlaps with the multiple fourth openings K4 between two adjacent fifth openings K5, and the orthographic projection of the fifth opening K5 on the second metal layer M4 overlaps with the multiple second openings K2 between two adjacent third openings K3.

[0130] For better understanding, Fig.21 A local enlarged schematic diagram of the first metal layer M3 and the second metal layer M4 in the routing area FF is shown. It can be seen that in the routing area FF, the orthographic projection of the third opening K3 on the first metal layer M3 and the fifth opening K5 are arranged in an alternating and complementary manner, the orthographic projection of the third opening K3 on the first metal layer M3 overlaps with the multiple fourth openings K4 between two adjacent fifth openings K5, and the orthographic projection of the fifth opening K5 on the second metal layer M4 overlaps with the multiple second openings K2 between two adjacent third openings K3.

[0131] It can be understood that the orthographic projection of the third opening K3 on the first metal layer M3 overlaps with the multiple fourth openings K4 between two adjacent fifth openings K5, and / or the orthographic projection of the fifth opening K5 on the second metal layer M4 overlaps with the multiple second openings K2 between two adjacent third openings K3, which can further reduce the overlapping area between the entity part T1 of the first metal layer M3 and the entity part U1 of the second metal layer M4, which is beneficial to exhaust, and can also further reduce the coupling between the entity part T1 of the first metal layer M3 (such as the first power structure PVDD) and the signal line in the routing area FF, and the coupling between the entity part U1 of the second metal layer M4 (such as the second power structure PVEE) and the signal line in the routing area FF; and the pattern density of the first metal layer M3 in the routing area FF is relatively uniform with the pattern density in the first shielding area CC, and the pattern density of the second metal layer M4 in the routing area FF is also relatively uniform with the pattern density in the first shielding area CC, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0132] And, combined with Figure 9-Figure 21As shown, in the first shielding area CC, in order to shield the first active portion q1, the second opening K2 of the second metal layer M4 and the fourth opening K4 of the first metal layer M3 are not overlapped in the direction perpendicular to the plane where the substrate is located, and the second opening K2 of the second metal layer M4 is uniformly arranged as a whole in the display area AA, and the fourth opening K4 of the first metal layer M3 is also uniformly arranged as a whole. Therefore, in the overall display area AA, in the direction perpendicular to the plane where the substrate is located, the second opening K2 of the second metal layer M4 and the fourth opening K4 of the first metal layer M3 do not overlap, so that the second active portion of the driving circuit and the active portions of other thin film transistors can also be shielded.

[0133] As known above, the sub-display area AA0 can at least partially overlap with the first display area AA1, so that the alignment mark R and the clearance area H around the alignment mark R can be located in the third opening K3 with a larger area in the second metal layer M4, or in the fifth opening K5 with a larger area in the first metal layer M3, which is explained in detail below.

[0134] Fig. 22 FIG. 1 shows a schematic diagram of a partial layout structure of a second metal layer M4 located in a wiring area FF in a display panel provided by an embodiment of the present application. Fig.23 Shows Fig. 22 A schematic diagram of a stacked layout structure of the first metal layer M3 and the second metal layer M4 in the region shown in FIG. Figure 22-Figure 23 As shown, the alignment mark R is located in the second metal layer M4, and the opening U2 of the second metal layer M4 includes a clearance area H.

[0135] Combination Fig. 22 and Fig.23 As shown, optionally, the third opening K3 of the second metal layer M4 may include a clearance area H, that is, the alignment mark R and the clearance area H around the alignment mark R are located in the third opening K3 of the second metal layer M4.

[0136] Combination Fig. 22 and Fig.23 As shown, optionally, the alignment mark R and the clearance area H around the alignment mark R are located within the solid portion T1 of the first metal layer M3 in the orthographic projection of the first metal layer M3, that is, no opening is set between the alignment mark R and the clearance area H around the alignment mark R within the orthographic projection range of the first metal layer M3.

[0137] Combination Fig. 22 and Fig.24 As shown, Fig.24 Shows Fig. 22Schematic diagram of another stacked layout structure of the first metal layer M3 and the second metal layer M4 in the area shown. Alternatively, the orthographic projection of the alignment mark R and the clearance area H around the alignment mark R on the first metal layer M3 is located within the opening T2 of the first metal layer M3. Specifically, the opening T2 of the first metal layer M3 may also include a sixth opening K6, and the orthographic projection of the alignment mark R and the clearance area H around the alignment mark R on the first metal layer M3 is located within the sixth opening K6 of the first metal layer M3. The sixth opening K6 may be an opening different from the fourth opening K4 and the fifth opening K5.

[0138] Fig.25 Another partial enlarged schematic diagram of the first metal layer M3 and the second metal layer M4 in the routing area FF is shown, as shown in FIG. Fig.25 As shown, the alignment mark R is located in the second metal layer M4, but the alignment mark R is not located in the third opening K3. At this time, the opening U2 of the second metal layer M4 may also include a seventh opening K7, the alignment mark R and the clearance area H around the alignment mark R are located in the seventh opening K7, the alignment mark R and the clearance area H around the alignment mark R are projected in the first metal layer M3 in the fifth opening K5, and the seventh opening K7 may be an opening different from the second opening K2 and the third opening K3.

[0139] It can be understood that, since there is an organic insulating layer between the first metal layer M3 and the second metal layer M4, Fig.24 and Fig.25 In the embodiment, there is an organic insulating layer between the first metal layer M3 and the second metal layer M4 to support the alignment mark R. However, the alignment mark R and the clearance area H around the alignment mark R are located in the solid portion T1 of the first metal layer M3 when the orthographic projection of the first metal layer M3 is located, rather than in the opening T2 of the first metal layer M3, so that the alignment mark R is more stable.

[0140] It can also be understood that the alignment mark R and the clearance area H around the alignment mark R are located in the solid portion T1 of the first metal layer M3, or in the opening U2 of the first metal layer M3, when the orthographic projection of the alignment mark R and the clearance area H around the alignment mark R is on the first metal layer M3. This is to ensure that when the second metal layer M4 is viewed from the side of the second metal layer M4 away from the base substrate, there is only one alignment mark R within the range of the alignment mark R and the clearance area H around the alignment mark R, thereby accurately identifying the alignment mark R.

[0141] Combination Fig. 22 and Fig.26 As shown, Fig.26 Shows Fig. 22A schematic diagram of another stacked layout structure of the first metal layer M3 and the second metal layer M4 in the area shown, and optionally, the clearance area H around the alignment mark R is located in the solid part T1 of the first metal layer M3 in the orthographic projection of the first metal layer M3; the opening of the first metal layer M3 includes a first opening K1, and the first opening K1 is covered by the alignment mark R in a direction perpendicular to the plane of the substrate.

[0142] This is because, as is known above, in the first metal layer M3, the fourth openings K4 are uniformly arranged in the display area AA as a whole, and the third opening K3 in the second metal layer M4 overlaps with the plurality of fourth openings K4 between the orthographic projection of the first metal layer M3 and two adjacent fifth openings K5, so as to reduce the overlapping area between the entity portion T1 of the first metal layer M3 and the entity portion U1 of the second metal layer M4, which is beneficial to exhaust. After the alignment mark R is set in the third opening K3 of the second metal layer M4, since a clearance area H needs to be set around the alignment mark R, if the clearance area H around the alignment mark R is The orthographic projection of the first metal layer M3 is located within the entity portion T1 of the first metal layer M3, so at least the portion of the first metal layer M3 corresponding to the clearance area H cannot be set with an opening; furthermore, if the clearance area H around the alignment mark R is small, it may cause difficulty in identifying and misjudgment of the alignment mark R, and if the clearance area H around the alignment mark R is large, the alignment mark R and the portion of the first metal layer M3 corresponding to the clearance area H around the alignment mark R are a continuous metal covering area, and this part of the continuous metal covering area may have a peeling problem due to insufficient exhaust.

[0143] Based on this, the opening of the first metal layer M3 is set to include a first opening K1, and in the direction perpendicular to the plane of the substrate, the first opening K1 is covered by the alignment mark R. In this way, when looking at the second metal layer M4 from the side of the second metal layer M4 away from the substrate, there is only one alignment mark R within the range of the alignment mark R and the clearance area H around the alignment mark R, so as to accurately identify the alignment mark R, and the portion of the first metal layer M3 corresponding to the alignment mark R and the clearance area H around the alignment mark R has the first opening K1, so as to avoid metal peeling problems and facilitate sufficient exhaust.

[0144] Further optionally, in some embodiments of the present application, the geometric center of the first opening K1 coincides with the geometric center of the orthographic projection of the alignment mark R on the first metal layer M3. This is because, if the geometric center of the first opening K1 does not coincide with the geometric center of the orthographic projection of the alignment mark R on the first metal layer M3, the organic insulating layer PLN between the alignment mark R and the first opening K1 is not flat due to the presence of the organic insulating layer PLN between the first metal layer M3 and the second metal layer M4, which will cause the alignment mark R to be uneven, resulting in insufficient stability and accuracy of the alignment mark R. However, by setting the geometric center of the first opening K1 to coincide with the geometric center of the orthographic projection of the alignment mark R on the first metal layer M3, the alignment mark R can be made flat, the stability of the alignment mark R can be improved, and it is conducive to accurate identification of the alignment mark R.

[0145] Fig. 27 FIG. 4 shows a schematic diagram of a partial layout structure of a second metal layer M4 in a wiring area FF in another display panel provided in an embodiment of the present application. Fig.28 Shows Fig. 27 A schematic diagram of a stacked layout structure of a first metal layer M3 and a second metal layer M4 in the region shown in FIG. Fig. 22 and Fig.26 The difference between the alignment mark R in the figure and the rectangular one is that Fig. 27 and Fig.28 In the figure, the alignment mark R is a circle, and other parts can refer to Fig. 22 and Fig.26 The description is not repeated here.

[0146] Fig.29 and Fig.30 Two other partial enlarged schematic diagrams of the first metal layer M3 and the second metal layer M4 in the routing area FF are shown, such as Fig.29 and Fig.30 As shown, the alignment mark R may also be located in the first metal layer M3, the opening U2 of the first metal layer M3 includes a clearance area H, and the opening of the second metal layer M4 exposes the alignment mark R and the clearance area H around the alignment mark R in a direction perpendicular to the plane of the substrate.

[0147] Optional, such as Fig.29 As shown, the alignment mark R and the clearance area H around the alignment mark R can be located in the fifth opening K5 of the first metal layer M3. At this time, the opening U2 of the second metal layer M4 can also include an eighth opening K8. In the direction perpendicular to the plane of the substrate, the eighth opening K8 of the second metal layer M4 exposes the alignment mark R and the clearance area H around the alignment mark R. The eighth opening K8 can be an opening different from the second opening K2 and the third opening K3.

[0148] Another option, such as Fig.30As shown, the opening T2 of the first metal layer M3 may also include a ninth opening K9, the alignment mark R and the clearance area H around the alignment mark R may be located within the ninth opening K9 of the first metal layer M3, and the alignment mark R and the clearance area H around the alignment mark R may be located within the third opening K3 as their orthographic projections on the second metal layer M4, and the ninth opening K9 may be an opening different from the fourth opening K4 and the fifth opening K5.

[0149] like Figure 6 As shown, the multi-layer metal layer located on the side of the active layer q away from the substrate sub further includes a third metal layer M2, and the third metal layer M2 is located on the side of the first metal layer M3 facing the substrate sub. Fig.31 and Fig.32 Two partial enlarged schematic diagrams of the third metal layer M2, the first metal layer M3 and the second metal layer M4 in the routing area FF are shown, such as Fig.31 and Fig.32 As shown, the third metal layer M3 also includes a solid portion Z1 and a plurality of openings Z2 , the alignment mark R may also be located in the third metal layer M3 , and the opening Z2 of the third metal layer M3 may include a clearance area H.

[0150] Optional, such as Fig.31 As shown, the alignment mark R located on the third metal layer M2 and the clearance area H around the alignment mark R are located within the fifth opening K5 of the first metal layer M3 as their orthographic projection on the first metal layer M3, and the opening U2 of the second metal layer M4 also includes an eighth opening K8. In a direction perpendicular to the plane of the substrate, the eighth opening K8 of the second metal layer M4 and the fifth opening K5 of the first metal layer M3 expose the alignment mark R located on the third metal layer M2 and the clearance area H around the alignment mark R.

[0151] Another option, such as Fig.32 As shown, the opening T2 of the first metal layer M3 also includes a ninth opening K9. In a direction perpendicular to the plane of the substrate, the ninth opening K9 of the first metal layer M3 and the third opening K3 of the second metal layer M4 expose the alignment mark R located in the third metal layer M2 and the clearance area H around the alignment mark R.

[0152] It should be noted that the above embodiments describe the situation where the alignment mark R and the clearance area H around the alignment mark R are respectively located in the opening U2 of the second metal layer M4, in the opening T2 of the first metal layer M3, and in the opening Z2 of the third metal layer M3, thereby providing a variety of designs for the setting of the alignment mark R and the clearance area H around the alignment mark R to adapt to various actual situations.

[0153] It should also be noted that, since the first metal layer M3 and the second metal layer M4 are provided with a relatively large opening in the routing area FF, the above-mentioned embodiment is mainly introduced by taking the alignment mark R and the clearance area H around the alignment mark R as an example in which the alignment mark R and the clearance area H around the alignment mark R are located in the routing area FF. It can be understood that, since the routing area FF is not provided with the active layer q, when the alignment mark R and the clearance area H around the alignment mark R are located in the routing area FF, in the direction perpendicular to the plane where the substrate is located, the alignment mark R and the clearance area H do not overlap with the active layer q, and the clearance area H can be prevented from exposing the active layer q, but the present application is not limited to this, such as Figure 8 As shown, when the multi-layer metal layers located on the side of the active layer q facing away from the substrate sub can cover the active layer q, that is, when the active layer q will not be damaged by the laser bonding of the light-emitting element, the alignment mark R and the clearance area H may also overlap with the active layer q in the direction perpendicular to the plane of the substrate sub, depending on the specific situation.

[0154] It should be further explained that, the above-mentioned embodiment is mainly introduced by taking the example that the alignment mark R and the clearance area H around the alignment mark R are located in the first display area AA1, but the present application is not limited to this. Optionally, the alignment mark R and the clearance area H around the alignment mark R may also be set in the second display area AA2 except the area where the flying line F1 is set.

[0155] Based on any of the above embodiments, optionally, in some embodiments of the present application, such as Figure 7 As shown, the at least two alignment marks R in the sub-display area AA0 include at least one group of alignment marks R10 , and the alignment mark group R10 includes two alignment marks R.

[0156] Optional, such as Figure 7 As shown, when the at least two alignment marks R in the sub-display area AA0 include a group of alignment mark groups R10, the line connecting the geometric centers of the two alignment marks R in the alignment mark group R10 intersects with the first direction X and the second direction Y; that is, the line connecting the geometric centers of the two alignment marks R in the alignment mark group R10 needs to be able to construct an XY coordinate system so as to accurately identify the bonding positions of each light-emitting element according to the alignment situation.

[0157] Further optional, such as Figure 7 As shown in FIG. 1 , when at least two alignment marks R in the sub-display area AA0 include an alignment mark group R10, a line connecting the geometric centers of the two alignment marks R in the alignment mark group R10 coincides with a diagonal line of the sub-display area AA0, thereby improving the alignment accuracy of the alignment marks R. Figure 7As shown, the shapes of the two alignment marks R in the alignment mark group R10 can be different. For example, one alignment mark R in the alignment mark group R10 is rectangular and the other alignment mark R is circular. In this way, not only the alignment accuracy of the alignment mark R can be improved, but also the front and back of the alignment can be identified during alignment.

[0158] Fig.33 and Fig.34 Schematic diagrams of top views of two other display panels provided in the embodiments of the present application are shown. Fig.33 and Fig.34 As shown, when the at least two alignment marks R in the sub-display area AA0 include at least two alignment mark groups R10, taking the at least two alignment mark groups R10 including the first alignment mark group R11 and the second alignment mark group R12 as an example, the lines connecting the geometric centers of the two alignment marks R in the at least two alignment mark groups R10 intersect, for example, the lines connecting the geometric centers of the two alignment marks R in the first alignment mark group R11 intersect with the lines connecting the geometric centers of the two alignment marks R in the second alignment mark group R12. In this way, the alignment accuracy of the alignment marks R can be further improved.

[0159] Optional, such as Fig.33 As shown, at least two alignment marks R in the sub-display area AA0 include two groups of alignment mark groups R10, and the two groups of alignment marks R10 include a first group of alignment mark group R11 and a second group of alignment mark group R12. The line connecting the geometric centers of the two alignment marks R in any group of alignment mark group R10 passes through the geometric center of the sub-display area AA0, and the lines connecting the geometric centers of the two alignment marks R in the two groups of alignment mark groups R10 form a cross.

[0160] Another option, such as Fig.34 As shown, at least two alignment marks R in the sub-display area AA0 include two groups of alignment mark groups R10, and the two groups of alignment marks R10 include a first group of alignment mark group R11 and a second group of alignment mark group R12. The line connecting the geometric centers of two alignment marks R in any group of alignment mark group R10 passes through the geometric center of the sub-display area AA0, and the lines connecting the geometric centers of two alignment marks R in the two groups of alignment mark groups R10 form a cross shape.

[0161] like Fig.33 and Fig.34 As shown, in the alignment mark group R10, like the first alignment mark group R11 and the second alignment mark group R12, the shapes of the two alignment marks R are different. For example, one alignment mark R is rectangular and the other alignment mark R is circular. This not only improves the alignment accuracy of the alignment mark R, but also allows identification of the front and back sides during alignment.

[0162] In the embodiment of the present application, the shape and size of the alignment mark R are not limited, and the shape and size of the clearance area H are not limited either. However, in order to better identify the alignment mark R, the alignment mark R is surrounded by no other graphic boundaries that affect the identification of the alignment mark R, such as Figure 7 As shown, the minimum spacing between the boundary of the alignment mark R and the boundary of the clearance area around the alignment mark R can be set to be greater than 5 μm, so as to ensure better identification of the alignment mark R. For example, the alignment mark R is rectangular, and the length and width of the alignment mark R can be 30 μm×30 μm; for another example, the alignment mark R is circular, and the diameter of the alignment mark R can be 30 μm; the clearance area H can be rectangular, and the length and width of the clearance area H can be 40 μm.

[0163] Accordingly, the embodiment of the present application further provides a display device, such as Fig.35 and Fig.36 As shown, the display device 500 includes the display panel 400 provided in any of the above embodiments. Since the display panel 400 has been described in detail in the above embodiments, it will not be described again here.

[0164] The display device 500 can be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a notebook computer, an e-reader, or a television.

[0165] It should be noted that, since the driving circuit can be set in the display area in the aforementioned embodiment to achieve a display panel with extremely narrow bezels or even no bezels and a full-screen design, the display device provided in the embodiment of the present application can be a spliced ​​display device, including multiple bezel-less display units (i.e., display panel 400).

[0166] The various parts in this manual are described in a combination of parallel and progressive ways. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0167] With respect to the above description of the disclosed embodiments, the features described in the embodiments in this specification may be replaced or combined with each other, so that professionals in the field can implement or use the present application. Various modifications to these embodiments will be apparent to professionals in the field, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel comprises a display area, the display area comprises a plurality of light emitting elements, a plurality of pixel circuits and at least one driving circuit, the driving circuit comprises a shift register circuit arranged in a multi-stage cascade, the shift register circuit is used to transmit a driving signal to the pixel circuit, and the pixel circuit is used to drive the light emitting element; The display panel comprises an array substrate, the array substrate comprises the pixel circuit and the driving circuit, and the light emitting element is located on the array substrate; The array substrate comprises: substrate substrate; An active layer located on one side of the substrate; A multi-layer metal layer located on a side of the active layer away from the substrate; The display area includes multiple sub-display areas, each of which includes at least two alignment marks. The alignment marks are used for alignment when the light-emitting element is transferred to the array substrate. The alignment marks are located in a metal layer among the multiple metal layers. A clearance area is arranged around the alignment marks. The multiple metal layers expose the alignment marks and the clearance area around the alignment marks.

2. The display panel according to claim 1, characterized in that: In a direction perpendicular to the plane where the substrate is located, the alignment mark and the clearance area do not overlap with the active layer.

3. The display panel according to claim 1, characterized in that: The multi-layer metal layer includes a first metal layer, the first metal layer includes a solid portion and a plurality of openings, the solid portion of the first metal layer includes a first power supply structure, and the first power supply structure is used to provide a first power supply voltage signal; The multi-layer metal layer further includes a second metal layer, the second metal layer includes a solid portion and a plurality of openings, the solid portion of the second metal layer includes a second power supply structure, and the second power supply structure is used to provide a second power supply voltage signal; The first power supply structure is electrically connected to the pixel circuit, the pixel circuit is electrically connected to the first electrode of the light emitting element, and the second power supply structure is electrically connected to the second electrode of the light emitting element; The second metal layer is located on a side of the first metal layer away from the base substrate, the alignment mark is located on the second metal layer, and the opening of the second metal layer includes the clearance area.

4. The display panel according to claim 3, characterized in that: The orthographic projections of the alignment mark and the clearance area around the alignment mark on the first metal layer are located within the opening of the first metal layer, or within the solid portion of the first metal layer.

5. The display panel according to claim 3, characterized in that: The orthographic projection of the clearance area around the alignment mark on the first metal layer is located within the solid part of the first metal layer; The opening of the first metal layer includes a first opening, and the first opening is covered by the alignment mark in a direction perpendicular to the plane where the substrate is located.

6. The display panel according to claim 5, characterized in that: The geometric center of the first opening coincides with the geometric center of the orthographic projection of the alignment mark on the first metal layer.

7. The display panel according to claim 1, characterized in that: The multi-layer metal layer includes a first metal layer, the first metal layer includes a solid portion and a plurality of openings, the solid portion of the first metal layer includes a first power supply structure, and the first power supply structure is used to provide a first power supply voltage signal; The multi-layer metal layer further includes a second metal layer, the second metal layer includes a solid portion and a plurality of openings, the solid portion of the second metal layer includes a second power supply structure, and the second power supply structure is used to provide a second power supply voltage signal; The first power supply structure is electrically connected to the pixel circuit, the pixel circuit is electrically connected to the first electrode of the light emitting element, and the second power supply structure is electrically connected to the second electrode of the light emitting element; The second metal layer is located on a side of the first metal layer away from the substrate, the alignment mark is located on the first metal layer, and the opening of the first metal layer includes the clearance area; In a direction perpendicular to the plane where the substrate is located, the opening of the second metal layer exposes the alignment mark and the clearance area around the alignment mark.

8. The display panel according to claim 1, characterized in that: The multi-layer metal layer includes a first metal layer, the first metal layer includes a solid portion and a plurality of openings, the solid portion of the first metal layer includes a first power supply structure, and the first power supply structure is used to provide a first power supply voltage signal; The multi-layer metal layer further includes a second metal layer, the second metal layer is located on a side of the first metal layer away from the substrate, the second metal layer includes a solid portion and a plurality of openings, the solid portion of the second metal layer includes a second power supply structure, and the second power supply structure is used to provide a second power supply voltage signal; The first power supply structure is electrically connected to the pixel circuit, the pixel circuit is electrically connected to the first electrode of the light emitting element, and the second power supply structure is electrically connected to the second electrode of the light emitting element; The multi-layer metal layer further includes a third metal layer, the third metal layer is located on a side of the first metal layer facing the substrate, and the third metal layer includes a solid portion and a plurality of openings; The alignment mark is located in the third metal layer, the opening of the third metal layer includes the clearance area, and in a direction perpendicular to the plane where the substrate is located, the opening of the first metal layer and the opening of the second metal layer expose the alignment mark and the clearance area around the alignment mark.

9. The display panel according to any one of claims 3 to 8, characterized in that: The display panel includes a pixel circuit group, the pixel circuit group includes at least two pixel circuits, the pixel circuit group is arranged in a row along a first direction, and a plurality of rows of pixel circuit groups are arranged along a second direction, the first direction and the second direction intersect, and the first direction and the second direction are parallel to the plane where the substrate is located; In a direction perpendicular to the plane where the substrate is located, the first power supply structure at least partially overlaps with four groups of pixel circuit groups overlapping two adjacent rows of pixel circuit groups and two adjacent columns of pixel circuit groups; In a direction perpendicular to the plane where the substrate is located, the second power supply structure at least partially overlaps with four groups of pixel circuit groups overlapping two adjacent rows of pixel circuit groups and two adjacent columns of pixel circuit groups; The active layer includes a first active portion, the pixel circuit includes the first active portion, and in a direction perpendicular to the plane where the substrate is located, at least one of the entity portion of the first metal layer and the entity portion of the second metal layer covers the first active portion.

10. The display panel according to claim 9, characterized in that: The active layer also includes a second active portion, the shift register circuit includes the second active portion, and in a direction perpendicular to the plane where the substrate is located, at least one of the physical portion of the first metal layer and the physical portion of the second metal layer also covers the second active portion.

11. The display panel according to claim 9, characterized in that: The first power supply structure covers the entire display area in the orthographic projection area of ​​the plane where the base substrate is located; The second power supply structure covers the entire display area in an orthographic projection area on the plane where the base substrate is located.

12. The display panel according to claim 9, characterized in that: The pixel circuit includes a pulse width module and an amplitude module, and the first power supply structure is electrically connected to the amplitude module of the pixel circuit.

13. The display panel according to claim 9, characterized in that: The display panel includes a light emitting element group, the light emitting element group includes at least two light emitting elements, and a group of the pixel circuit groups is electrically connected to a group of the light emitting element groups; The display area includes a first display area and a second display area, wherein the second display area at least partially surrounds the first display area; The second display area includes a plurality of the light emitting element groups, a plurality of the pixel circuit groups and the driving circuit. In the second display area, in a direction perpendicular to the plane where the base substrate is located, the pixel circuit groups and the light emitting element groups electrically connected thereto at least partially do not overlap; The first display area includes a plurality of the light emitting element groups and a plurality of the pixel circuit groups. In the first display area, in a direction perpendicular to the plane where the base substrate is located, the pixel circuit groups at least partially overlap with the electrically connected light emitting element groups.

14. The display panel according to claim 13, characterized in that: In the second display area, the opening of the second metal layer includes a plurality of second openings; In the first display area, the openings of the second metal layer include a plurality of the second openings and a plurality of third openings, and the area of ​​the third openings is greater than the area of ​​the second openings; In the first display area, a wiring area is provided on at least one side of the pixel circuit group along the first direction, the wiring area includes a signal line extending along the second direction, the third opening is located in the wiring area, and the third openings are arranged in the wiring area along the second direction; The sub-display area at least partially overlaps with the first display area, and the alignment mark and the clearance area around the alignment mark are located in the third opening.

15. The display panel according to claim 14, characterized in that: In the first display area, along the second direction, the third opening and a plurality of the second openings are arranged alternately.

16. The display panel according to claim 15, characterized in that: In the first display area, along the first direction and / or the second direction, the third opening overlaps with a plurality of the second openings.

17. The display panel according to claim 13, characterized in that: In the second display area, the openings of the first metal layer include a plurality of fourth openings; In the first display area, the openings of the first metal layer include a plurality of fourth openings and a plurality of fifth openings, and the area of ​​the fifth openings is greater than the area of ​​the fourth openings; In the first display area, a wiring area is provided on at least one side of the pixel circuit group along the first direction, the wiring area includes a signal line extending along the second direction, the fifth opening is located in the wiring area, and the fifth openings are arranged in the wiring area along the second direction; The sub-display area at least partially overlaps with the first display area, and the alignment mark and the clearance area around the alignment mark are located in the fifth opening.

18. The display panel according to claim 17, characterized in that: In the first display area, along the second direction, the fifth opening and the plurality of fourth openings are arranged alternately.

19. The display panel according to claim 18, characterized in that: In the first display area, along the first direction and / or the second direction, the fifth opening and the plurality of fourth openings overlap.

20. The display panel according to claim 13, characterized in that: In the second display area, the opening of the second metal layer includes a plurality of second openings; In the first display area, the openings of the second metal layer include a plurality of the second openings and a plurality of third openings, and the area of ​​the third openings is greater than the area of ​​the second openings; In the first display area, a wiring area is provided on at least one side of the pixel circuit group along the first direction, the wiring area includes a signal line extending along the second direction, the third opening is located in the wiring area, and the third openings are arranged in the wiring area along the second direction; In the second display area, the openings of the first metal layer include a plurality of fourth openings; In the first display area, the openings of the first metal layer include a plurality of fourth openings and a plurality of fifth openings, and the area of ​​the fifth openings is greater than the area of ​​the fourth openings; In the first display area, the fifth opening is located in the wiring area, and the fifth opening is arranged along the second direction in the wiring area; The orthographic projection of the third opening on the first metal layer and the fifth opening are alternately arranged along the second direction; The sub-display area at least partially overlaps with the first display area, and the alignment mark and the clearance area around the alignment mark are located in the third opening or in the fifth opening.

21. The display panel according to claim 20, characterized in that: In the first display area, along the second direction, the third opening and a plurality of the second openings are arranged alternately; In the first display area, along the second direction, the fifth opening and the plurality of fourth openings are arranged alternately; The orthographic projection of the third opening on the first metal layer overlaps with the plurality of fourth openings between two adjacent fifth openings, and / or the orthographic projection of the fifth opening on the second metal layer overlaps with the plurality of second openings between two adjacent third openings.

22. The display panel according to claim 20, characterized in that: In a direction perpendicular to a plane where the substrate is located, the second opening and the fourth opening do not overlap.

23. The display panel according to claim 1, characterized in that: The display panel includes a pixel circuit group, the pixel circuit group includes at least two pixel circuits, the pixel circuit group is arranged in a row along a first direction, and a plurality of rows of pixel circuit groups are arranged along a second direction, the first direction and the second direction intersect, and the first direction and the second direction are parallel to the plane where the substrate is located; In the sub-display area, the at least two alignment marks include at least one alignment mark group, and the alignment mark group includes two alignment marks; When the at least two alignment marks include a group of the alignment mark group, a line connecting geometric centers of two alignment marks in the alignment mark group intersects the first direction and the second direction; When the at least two alignment marks include at least two groups of alignment mark groups, lines connecting geometric centers of two alignment marks in the at least two groups of alignment mark groups intersect.

24. The display panel according to claim 23, characterized in that: In the sub-display area, the at least two alignment marks include a group of alignment marks, and a line connecting geometric centers of two alignment marks in the group of alignment marks coincides with a diagonal line of the sub-display area.

25. The display panel according to claim 23, characterized in that: In the sub-display area, the at least two alignment marks include two groups of alignment mark groups, a line connecting the geometric centers of two alignment marks in any one group of alignment mark groups passes through the geometric center of the sub-display area, and a line connecting the geometric centers of two alignment marks in two groups of alignment mark groups forms a cross shape or a fork shape.

26. The display panel according to any one of claims 23 to 25, characterized in that: The shapes of the two alignment marks in the alignment mark group are different.

27. The display panel according to claim 26, characterized in that: One alignment mark in the alignment mark group is rectangular, and another alignment mark is circular.

28. The display panel according to claim 1, characterized in that: A minimum distance between a boundary of the alignment mark and a boundary of the clearance area around the alignment mark is greater than 5 μm.

29. A display device, characterized in that: A display panel comprising any one of claims 1-28.

Images