Display panel, manufacturing method thereof and display device

Abstract

The present disclosure relates to the technical field of display, and relates to a display panel, a manufacturing method thereof, and a display device. The display panel comprises a substrate, a first pixel definition layer, a second pixel definition layer, an emitting layer, and a cathode layer. A first opening of the first pixel definition layer exposes part of an anode. A second opening of the second pixel definition layer at least partially overlaps with the first opening in the orthographic projection of the substrate. Between two adjacent sub-pixels, the display panel comprises at least one partition port. The partition port comprises a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least part of the first pixel definition layer. At the junction of the first sub-partition and the second sub-partition, the second sub-partition protrudes towards the sub-pixel relative to the first sub-partition. The manufacturing method is used to manufacture the display panel. The display device comprises the display panel. The present disclosure can avoid color crosstalk between adjacent sub-pixels, improve electrical light leakage, and improve display effect.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays are widely used in various fields due to their lightweight, wide viewing angle, fast response, low-temperature resistance, high luminous efficiency, and the ability to fabricate flexible displays. OLED displays use a vapor deposition process to form organic light-emitting materials, and pixel definition layers define the light-emitting areas. When current flows through them, these organic light-emitting materials emit light in the light-emitting areas, thus achieving the display.

[0003] In existing technologies, when a sub-pixel (target sub-pixel) is lit, due to the lateral leakage current problem in the display panel, adjacent sub-pixels are easily affected by this sub-pixel and may also be illuminated, resulting in light leakage and color crosstalk. This electrical light leakage phenomenon is particularly noticeable in full-color OLED display panels, especially in low grayscale displays, where color shift is particularly severe, thereby reducing the display quality of the OLED display panel.

[0004] Therefore, providing a display panel and its manufacturing method and display device that can avoid color crosstalk between adjacent sub-pixels, improve electrical light leakage, and at the same time not affect the normal light emission of pixels and ensure low grayscale display effect is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned technical problems, this disclosure provides a display panel and its manufacturing method, as well as a display device, to solve the problem that display devices in the prior art are prone to color distortion due to lateral leakage current, which affects display quality.

[0006] This disclosure provides a display panel including a plurality of sub-pixels, the sub-pixels including an anode;

[0007] The display panel also includes:

[0008] The substrate has the anode located on one side.

[0009] The first pixel defining layer is located on the side of the anode away from the substrate. The first pixel defining layer includes a plurality of first openings, and the first openings expose a portion of the anode.

[0010] The second pixel definition layer is located on the side of the first pixel definition layer away from the substrate. The second pixel definition layer includes a plurality of second openings. The orthographic projection of the second openings onto the substrate at least partially overlaps with the orthographic projection of the first openings onto the substrate.

[0011] a light-emitting layer, at least part of the light-emitting layer being located in the first opening;

[0012] a cathode layer, the cathode layer being located on a side of the light-emitting layer away from the substrate;

[0013] The display panel comprises at least one partition opening between two adjacent sub-pixels, the partition opening comprising a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least part of the first pixel definition layer in a direction perpendicular to a plane in which the substrate lies, the first sub-partition and the second sub-partition being in communication;

[0014] At a junction of the first sub-partition and the second sub-partition, the second sub-partition protrudes relative to the first sub-partition in a direction closer to the sub-pixel in a direction in which one sub-pixel points to another sub-pixel adjacent thereto.

[0015] Based on the same inventive concept, the present disclosure also provides a manufacturing method of a display panel, the manufacturing method comprising:

[0016] providing a substrate;

[0017] manufacturing a plurality of anodes, the anodes corresponding to sub-pixels;

[0018] manufacturing a first pixel definition layer, the first pixel definition layer being patterned to form a plurality of first openings, the first openings exposing part of the anodes;

[0019] manufacturing a second pixel definition layer, the second pixel definition layer being patterned to form a plurality of second openings, a projection of the second openings on the substrate at least partially overlapping a projection of the first openings on the substrate;

[0020] manufacturing a partition opening between two adjacent sub-pixels, the partition opening comprising a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least part of the first pixel definition layer in a direction perpendicular to a plane in which the substrate lies, the first sub-partition and the second sub-partition being in communication to form the partition opening;

[0021] At a junction of the first sub-partition and the second sub-partition, the second sub-partition protrudes relative to the first sub-partition in a direction closer to the sub-pixel in a direction in which one sub-pixel points to another sub-pixel adjacent thereto.

[0022] manufacturing a light-emitting layer, at least part of the light-emitting layer being located in the first opening on a side of the second pixel definition layer away from the substrate; the light-emitting layer comprising a common layer, the common layer being partitioned at the partition opening;

[0023] manufacturing a cathode layer, the cathode layer being partitioned at the partition opening.

[0024] Based on the same inventive concept, the present disclosure also provides a display device, the display device comprising the display panel described above.

[0025] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0026] The display panel disclosed herein is disposed between two adjacent sub-pixels. The display panel includes at least one partition opening along a direction perpendicular to the plane of the substrate. The partition opening includes a first sub-partition penetrating a second pixel definition layer and a second sub-partition penetrating at least a portion of the first pixel definition layer. The first sub-partition and the second sub-partition are connected. The partition opening is located between two adjacent sub-pixels, which is also located between two adjacent second openings. The partition opening structure disclosed herein is such that, at the junction of the first and second sub-partitions, along a direction from one sub-pixel to another adjacent sub-pixel, the second sub-partition protrudes relative to the first sub-partition in a direction closer to the sub-pixel. Thus, the structure of the double-layered first and second pixel definition layers can form a single-sided undercut structure on one side of the second sub-partition at the junction of the first and second sub-partitions. Therefore, when the various layers of the light-emitting layer are deposited, the organic light-emitting material can form a light-emitting layer corresponding to the anode of the sub-pixel in the first and second openings. Moreover, due to the single-sided undercut structure of the formed second sub-partition, the common layer of the light-emitting layer can be effectively isolated at the second sub-partition position of the partition, which is equivalent to the leakage current path being isolated. This can effectively improve the color crosstalk between adjacent sub-pixels. Especially when the display panel is displaying at low grayscale, it can avoid color crosstalk between adjacent sub-pixels, improve electrical light leakage, and at the same time, it does not affect the normal light emission of the pixel, ensuring the low grayscale display effect. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0028] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this disclosure;

[0030] Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure along the A-A' direction;

[0031] Figure 3 yes Figure 2 A schematic diagram of a structure in which the light-emitting layer is located between the anode and cathode layers;

[0032] Figure 4 is Figure 1 Another cross-sectional structure schematic view in the direction of A-A' in FIG. 7;

[0033] Figure 5 is Figure 2 Another structure schematic view in FIG. 7 in which the light-emitting layer is located between the anode layer and the cathode layer;

[0034] Figure 6 is Figure 1 Another cross-sectional structure schematic view in the direction of A-A' in FIG. 8;

[0035] Figure 7 is a structure schematic view of a partitioning port in the related art;

[0036] Figure 8 is Figure 2 An enlarged structure schematic view of a partitioning port position in FIG. 8;

[0037] Figure 9 is a schematic view of a combination of a sub-pixel arrangement and a partitioning port arrangement provided by an embodiment of the present disclosure;

[0038] Figure 10 is a schematic view of another combination of a sub-pixel arrangement and a partitioning port arrangement provided by an embodiment of the present disclosure;

[0039] Figure 11 is Figure 1 Another cross-sectional structure schematic view in the direction of A-A' in FIG. 9;

[0040] Figure 12 is Figure 1 Another cross-sectional structure schematic view in the direction of A-A' in FIG. 10;

[0041] Figure 13 is Figure 1 Another cross-sectional structure schematic view in the direction of A-A' in FIG. 11;

[0042] Figure 14 is Figure 1 Another cross-sectional structure schematic view in the direction of A-A' in FIG. 12;

[0043] Figure 15 is Figure 1 Another cross-sectional structure schematic view in the direction of A-A' in FIG. 13;

[0044] Figure 16 is another planar structure schematic view of a display panel provided by an embodiment of the present disclosure;

[0045] Figure 17 is Figure 16 A cross-sectional structure schematic view in the direction of B-B' in FIG. 14;

[0046] Figure 18 is a flow chart of a manufacturing method of a display panel provided by an embodiment of the present disclosure;

[0047] Figure 19 is Figure 18 a schematic structural diagram of the manufacturing method of the display panel after the anode is completed;

[0048] Figure 20 is Figure 18 a schematic structural diagram of the manufacturing method of the display panel after the patterned first pixel definition layer is completed;

[0049] Figure 21 is Figure 18 a schematic structural diagram of the manufacturing method of the display panel after the second opening of the second pixel definition layer is completed;

[0050] Figure 22 is Figure 18 a schematic structural diagram of the manufacturing method of the display panel after the partition port is completed;

[0051] Figure 23 is Figure 18 a schematic structural diagram of the manufacturing method of the display panel after the light-emitting layer is completed;

[0052] Figure 24 is Figure 18 a schematic structural diagram of the manufacturing method of the display panel after the cathode layer is completed;

[0053] Figure 25 is another flow chart of a manufacturing method of a display panel provided by an embodiment of the present disclosure;

[0054] Figure 26 is Figure 25 a schematic structural diagram of the manufacturing method of the display panel after the patterned first pixel definition layer is completed;

[0055] Figure 27 is Figure 25 a schematic structural diagram of the manufacturing method of the display panel after the second opening of the second pixel definition layer is completed;

[0056] Figure 28 is Figure 25 a schematic diagram of the position of a mask plate when a partition port is manufactured in the manufacturing method of the display panel;

[0057] Figure 29 is Figure 25 a schematic diagram of the position of another mask plate when a partition port is manufactured in the manufacturing method of the display panel;

[0058] Figure 30 is Figure 25 a schematic structural diagram of the manufacturing method of the display panel after the light-emitting layer is completed;

[0059] Figure 31 is Figure 25A schematic diagram of a structure after a cathode layer is completed in a manufacturing method of the display panel 000;

[0060] Figure 32 A schematic diagram of a planar structure of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to enable a person skilled in the art to more clearly understand the above-mentioned purposes, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0062] In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the present disclosure, but the present disclosure can also be implemented in other ways different from those described herein; obviously, the embodiments in the description are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0063] Please refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, Figure 2 is Figure 1 A schematic diagram of a cross-sectional structure in the direction of A-A' in the display panel 000 provided by the embodiment, the display panel 000 includes a plurality of sub-pixels 000, and each sub-pixel 000 includes an anode 20.

[0064] The display panel 000 further includes:

[0065] A substrate 10, the anode 20 is located on one side of the substrate 10;

[0066] A first pixel definition layer 30, located on a side of the anode 20 away from the substrate 10, the first pixel definition layer 30 includes a plurality of first openings 30K1, and the first openings 30K1 expose part of the anode 20;

[0067] A second pixel definition layer 40, located on a side of the first pixel definition layer 30 away from the substrate 10, the second pixel definition layer 40 includes a plurality of second openings 40K1, and a projection of the second openings 40K1 on the substrate 10 at least partially overlaps a projection of the first openings 30K1 on the substrate 10;

[0068] A light-emitting layer 50, at least part of the light-emitting layer 50 is located in the first openings 30K1; it can be understood that the light-emitting layer 50 can include a light-emitting common layer, such as a hole transport layer, an electron transport layer, a charge generation layer, etc.

[0069] A cathode layer 60, the cathode layer 60 is located on a side of the light-emitting layer 50 away from the substrate 10;

[0070] Between two adjacent sub-pixels 00, the display panel 000 includes at least one partition port JK, which includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least part of the first pixel definition layer 30 along a direction Z perpendicular to a plane in which the substrate 10 is located, and the first sub-partition JK1 and the second sub-partition JK2 are in communication;

[0071] At the junction of the first sub-partition JK1 and the second sub-partition JK2, the second sub-partition JK2 protrudes in a direction close to the sub-pixel 00 relative to the first sub-partition JK1 along a direction in which one sub-pixel 00 points to another sub-pixel 00 adjacent thereto.

[0072] Specifically, the display panel 000 provided in the embodiment can be an organic light-emitting diode display panel, and the display panel 000 includes a substrate 10 (not filled in the figure), Figure 2 The substrate 10 is used as a bearing substrate and is used to arrange other film layer structures of the display panel 000. Optionally, the substrate 10 of the display panel 000 in the embodiment can be a hard material such as glass, ceramic, etc., or can be formed of a flexible material such as a polymer material such as polyimide (PI), polycarbonate (PC), polyether sulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), etc. The substrate 10 can be any one of a transparent substrate, a translucent substrate, or an opaque substrate, which is not limited in the embodiment. The sub-pixel 00 of the display panel 000 includes an anode 20, which can be located on one side of the substrate 10. Optionally, along a direction Z perpendicular to a plane in which the substrate 10 is located, the substrate 10 and the anode 20 can further include a driving array layer 70, and the driving array layer 70 can be arranged with a plurality of conductive films to form a thin film transistor 70T. The plurality of thin film transistors 70T are used to form a driving circuit such as a pixel circuit, etc., to provide a driving signal for the display panel 000. The driving array layer 70 can also be used to arrange a driving trace, and the arrangement structure of the driving array layer 70 is not described in the embodiment, and can be understood with reference to the film layer structure of an OLED display panel in related technologies. The anode 20 corresponding to the sub-pixel 00 can be electrically connected with the thin film transistor 70T, for transmitting the driving signal of the pixel circuit to the anode 20. Optionally, the anode 20 can be formed of various conductive materials, such as the anode 20 which can be formed into a transparent anode or a reflective anode according to its own purpose. When the anode 20 is formed into a transparent anode, the material of the anode 20 can include indium tin oxide (ITO), indium zinc oxide (IZO), etc. When the anode 20 is formed into a reflective anode, the material of the anode 20 can include silver, magnesium, aluminum, etc. or other metal mixtures, which are not specifically limited in the embodiment.

[0073] The anode 20 far from the substrate 10 side in the embodiment includes a first pixel definition layer 30 and a second pixel definition layer 40, which can be stacked, that is, the surface of the first pixel definition layer 30 far from the substrate 10 side can be in contact with the surface of the second pixel definition layer 40 toward the substrate 10 side. The first pixel definition layer 30 includes a plurality of first openings 30K1 exposing part of the anode 20, and the second pixel definition layer 40 includes a plurality of second openings 40K1, the orthographic projection of which on the substrate 10 at least partially overlaps the orthographic projection of the first openings 30K1 on the substrate 10, that is, the first openings 30K1 and the second openings 40K1 at least partially overlap together to form an opening exposing part of the anode 20 for subsequent organic light-emitting material setting. The second pixel definition layer 40 far from the substrate 10 side includes a light-emitting layer 50, at least part of which is located in the first opening 30K1, and optionally, at least part of which is located in the second opening 40K1. The light-emitting layer 50 can be formed by evaporation of organic light-emitting material, and the first openings 30K1 and the second openings 40K1 provided by the first pixel definition layer 30 and the second pixel definition layer 40 are used to prevent color mixing and color mixing between the light-emitting layers 50 of adjacent two sub-pixels 00, that is, the first openings 30K1 and the second openings 40K1 provided by the first pixel definition layer 30 and the second pixel definition layer 40 are used to define the light-emitting layer 50 of the organic light-emitting material of the adjacent sub-pixel 00, so as to correspondingly separate the light-emitting layer 50 of various colors into a relatively independent structure.

[0074] Optionally, the display panel 000 includes a plurality of sub-pixels 00, one sub-pixel 00 can be correspondingly provided with a light-emitting layer 50 provided by one first opening 30K1, and the plurality of sub-pixels 00 can include a plurality of different colors Figure 1 represented by different filling patterns, such as at least red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels; the plurality of sub-pixels 00 can be arranged in an array on the display panel 000, or the plurality of sub-pixels 00 can be arranged in other ways, which can be understood with reference to the pixel arrangement structure of the OLED display panel in the related art. The Figure 1 of the embodiment is Figure 1 only an example and does not represent the actual arrangement of the sub-pixels 00. The Figure 1 of the embodiment is

[0075] The side of the light-emitting layer 50 away from the substrate 10 further comprises a cathode layer 60 in the embodiment. The cathode layer 60 on the light-emitting layer 50 can make the anode 20, the light-emitting layer 50, and the cathode layer 60 form a stacked arrangement. By applying a voltage between the anode 20 and the cathode layer 60, the light-emitting layer 50 of different sub-pixels 00 emits visible light, thereby realizing an image that can be recognized by a user.

[0076] It can be understood that the display panel 000 in the embodiment includes but is not limited to the above-mentioned film layer structure, and can further include other film layer structures. For example, a thin film encapsulation layer 80 can be further arranged on the side of the cathode layer 60 away from the substrate 10. The thin film encapsulation layer 80 can be used to isolate water and oxygen, prevent water vapor and oxygen in the air from entering the light-emitting layer 50 and the driving array layer 70, thereby causing damage to the components therein. The display panel 000 can further include other film layer structures, such as a planarization layer, and the like. The embodiment will not be described here in detail, and can be understood with reference to the structure of an organic light-emitting display panel in related technologies. Optionally, the thin film encapsulation layer 80 in the embodiment can include a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer is used to block the organic layer, prevent water vapor and oxygen in the organic layer from penetrating into the light-emitting layer 50 of the organic light-emitting material and reacting to damage the organic light-emitting material and cause the display panel to fail. The organic layer is used to relieve stress and avoid the inorganic layer from being broken due to stress and causing water vapor and oxygen to invade. The second inorganic layer is used to avoid water vapor and oxygen in the external environment from invading the display panel 000. The first inorganic layer and the second inorganic layer of the thin film encapsulation layer 80 form a double protection, which can further reduce the probability of invasion.

[0077] Optionally, as shown in Figure 1 、 Figure 2 and Figure 3 , Figure 3 is Figure 2 a structure schematic diagram in which the light-emitting layer in the embodiment is located between the anode and the cathode layer. The light-emitting layer 50 in the embodiment can include a hole injection layer 501, a hole transport layer 502, an organic light-emitting layer 503, a hole blocking layer 504, an electron transport layer 505, and an electron injection layer 506 stacked in a direction Z perpendicular to the plane in which the substrate 10 is located. The hole injection layer 501 and the hole transport layer 502 are located between the organic light-emitting layer 503 and the anode 20, and the hole blocking layer 504, the electron transport layer 505, and the electron injection layer 506 are located between the organic light-emitting layer 503 and the cathode layer 60, and sequentially close to the cathode layer 60. The light-emitting layer 50 includes a common layer. The common layer includes one or more of the hole injection layer 501, the hole transport layer 502, the hole blocking layer 504, the electron transport layer 505, and the electron injection layer 506.

[0078] In the prior art, the mask plate for OLED evaporation is mainly evaporated by an open mask plate. That is, the hole injection layer, the hole transport layer, the organic light-emitting layer, the hole blocking layer, the electron transport layer, the electron injection layer, and the common layer of the hole injection layer and the hole transport layer of the light-emitting layer of the organic light-emitting material are formed by full-area evaporation. The common layer can be understood as the film layer corresponding to at least three color sub-pixels being evaporated by the open mask plate. The film layer covers all the sub-pixel regions and the interval regions between the sub-pixels. When the OELD device works, because the common layers of the sub-pixels are connected, the carriers will conduct laterally in the common layers, causing the common layers to generate a lateral leakage current, which causes the adjacent sub-pixel to be affected by the target sub-pixel and to be lightened when the target sub-pixel is lightened, thereby causing the light leakage and color mixing phenomenon. This electrical light leakage phenomenon is particularly obvious in the full-color OLED display panel, especially in low gray-scale display, and the color deviation problem is particularly serious, thereby reducing the display quality of the OLED display panel.

[0079] To solve the above problems, the embodiment is provided between two adjacent sub-pixels 00, and the display panel 000 includes at least one partition port JK, as shown in Figure 2 and Figure 4 Figure 4 is Figure 1 Another cross-sectional structure diagram of A-A' direction in Figure 4 (not showing the film layer above the second pixel definition layer in order to clearly show the structure of the partition port of the embodiment), Figure 4 in the direction Z perpendicular to the plane of the substrate 10, the partition port JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least part of the first pixel definition layer 30. The first sub-partition JK1 and the second sub-partition JK2 are communicated, that is, by opening the second sub-partition JK2 and the first sub-partition JK1 in the first pixel definition layer 30 and the second pixel definition layer 40 respectively, and the first sub-partition JK1 and the second sub-partition JK2 are communicated in the direction Z perpendicular to the plane of the substrate 10 to form a partition port JK. The partition port JK is located between two adjacent sub-pixels 00, and the partition port JK is located between two adjacent second openings 40K1. The structure of the partition port JK provided in the embodiment is that the first sub-partition JK1 and the second sub-partition JK2 are communicated at the junction of the first sub-partition JK1 and the second sub-partition JK2 (as shown in Figure 4At the position marked by the dashed circle J1, along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, the second sub-block JK2 protrudes towards the sub-pixel 00 relative to the first sub-block JK1. Thus, the structure of the double-layered first pixel definition layer 30 and the second pixel definition layer 40 can form at least one side of the second sub-block JK2 as a single-sided undercut structure at the position marked by the dashed circle J1. Therefore, when the above-mentioned film layers of the light-emitting layer 50 are deposited, the organic light-emitting material can form a light-emitting layer 50 corresponding to the anode 20 of the sub-pixel 00 in the first opening 30K1 and the second opening 40K1. Moreover, due to the single-sided undercut structure of the second sub-segment JK2 formed at the J1 position, the common layer of the light-emitting layer 50 can be effectively isolated at the J1 position, which is equivalent to the leakage current path being isolated. This can effectively improve the color crosstalk between adjacent sub-pixels. Especially when the display panel 000 performs low grayscale display, it can avoid color crosstalk between adjacent sub-pixels, improve electrical light leakage, and at the same time, it does not affect the normal light emission of the pixel, ensuring the low grayscale display effect.

[0080] In this embodiment, the first pixel definition layer 30 and the second pixel definition layer 40 are different film layers, and the materials used to manufacture the first pixel definition layer 30 and the second pixel definition layer 40 can be different. Because they are stacked and made of different materials, it is more convenient and faster to form a single-sided undercut structure of the second sub-segment JK2 at the junction of the first sub-segment JK1 and the second sub-segment JK2, so that... Figure 2 and Figure 4 The formation of the partition opening JK shown is made possible, thereby in this embodiment, at least the common layer in the light-emitting layer 50 can be effectively blocked at the partition opening JK, i.e., as shown... Figure 2 and Figure 4 The partition JK shown in the diagram can ensure the isolation of lateral leakage current, which helps to simplify the manufacturing process, improve process efficiency, improve color distortion, and enhance display quality.

[0081] It should be noted that in this embodiment... Figure 2 and Figure 4The first sub-separation JK1 and the second sub-separation JK2 are only exemplary drawings of the single-side undercut structure of the second sub-separation JK2 formed at the junction of the first sub-separation JK1 and the second sub-separation JK2. In actual implementation, the single-side undercut structure of the second sub-separation JK2 formed at the junction of the first sub-separation JK1 and the second sub-separation JK2 includes but is not limited to the above, and can also include other forms. As long as the second sub-separation JK2 protrudes towards the sub-pixel 00 at the junction of the first sub-separation JK1 and the second sub-separation JK2 in the direction of the sub-pixel 00 adjacent to the sub-pixel 00, at least the common layer in the light-emitting layer 50 or other film layers with the possibility of horizontal leakage current transmission can be separated at the single-side undercut structure, the embodiment does not make redundant description on the form of the single-side undercut structure of the second sub-separation JK2 formed at the junction of the first sub-separation JK1 and the second sub-separation JK2.

[0082] Optionally, as shown in Figure 1 、 Figure 2 and Figure 4 , the sub-pixel 00 includes adjacent first sub-pixel 00A and second sub-pixel 00B, the colors of the first sub-pixel 00A and the second sub-pixel 00B can be different, in the direction X of the first sub-pixel 00A pointing to the second sub-pixel 00B, the second sub-separation JK2 includes opposite first end JK2A and second end JK2B, the first end JK2A is located between the second end JK2B and the first sub-pixel 00A;

[0083] At the junction of the first sub-separation JK1 and the second sub-separation JK2 (such as the J1 position in Figure 4 ), the first end JK2A of the second sub-separation JK2 protrudes towards the first sub-pixel 00A relative to the first sub-separation JK1, thereby forming the form of the single-side undercut structure of the second sub-separation JK2.

[0084] Alternatively, as shown in Figure 1 、 Figure 2 and Figure 4 , the second pixel definition layer 40 includes a first surface 40A in contact with the first pixel definition layer 30;

[0085] In the direction X of the first sub-pixel 00A pointing to the second sub-pixel 00B, at the first end JK2A, the second sub-separation JK2 exposes part of the first surface 40A;

[0086] At the second end portion JK2B, the first surface 40A of the second pixel definition layer 40 is not exposed in the partition port JK, thereby forming a single-side undercut structure of the second sub-partition JK2 on the side close to the first sub-pixel 00A, and the second sub-partition JK2 on the side close to the second sub-pixel 00B is still smooth or continuous, thereby ensuring that the common layer or the cathode layer 60 included in the light-emitting layer 50 will not be left at the partition port JK. The structure is explained and described in detail in the subsequent embodiments, which will not be described here.

[0087] Optionally, the cathode layer 60 and the thin film packaging layer 80 of the present embodiment can further include other film layers, such as a cathode capping layer (CPL) located on the cathode layer 60 and a lithium fluoride (LiF) layer located on the planar layer. The cathode capping layer can improve light extraction efficiency, increase light-emitting refractive index, thereby improving the efficiency and service life of the light-emitting layer 50, and can also inhibit light absorption and reduce energy loss, thereby further enhancing the performance of the display panel. The lithium fluoride layer can isolate ions to improve light extraction efficiency. The film layer structure of the display panel 000 will not be described here. In specific implementation, the film layer structure of the display panel includes but is not limited to the above, and can also include other film layer structures that can realize display function and improve display quality. The film layer structure of the OLED display panel in the related art can be referred to for understanding.

[0088] Optionally, as shown in Figures 1-2 and Figure 5 , the Figure 5 is another structure diagram of the light-emitting layer located between the anode and the cathode layer in the Figure 2 . The light-emitting layer 50 in the present embodiment can include a hole injection layer 5011, a hole transport layer 5012, a first organic light-emitting layer 5013, a charge generation layer 5014, a second organic light-emitting layer 5015, a hole blocking layer 5016, an electron transport layer 5017, and an electron injection layer 5018 arranged in a stacking manner along the direction Z perpendicular to the plane in which the substrate 10 is located.

[0089] The light-emitting layer 50 includes a common layer.

[0090] The common layer includes one or more of the hole injection layer 5011, the hole transport layer 5012, the charge generation layer 5014, the hole blocking layer 5016, the electron transport layer 5017, and the electron injection layer 5018.

[0091] The embodiment explains that the light-emitting layer 50 of the display panel 000 can include at least two organic light-emitting layers, that is, the light-emitting layer 50 can include a hole injection layer 5011, a hole transport layer 5012, a first organic light-emitting layer 5013, a charge generation layer 5014, a second organic light-emitting layer 5015, a hole blocking layer 5016, an electron transport layer 5017, and an electron injection layer 5018 stacked along the direction Z perpendicular to the plane where the substrate 10 is located, the hole injection layer 5011 and the hole transport layer 5012 are located between the anode 20 and the first organic light-emitting layer 5013, the hole blocking layer 5016, the electron transport layer 5017, and the electron injection layer 5018 are located between the second organic light-emitting layer 5015 and the cathode layer 60, and sequentially close to the cathode layer 60.

[0092] In the display panel 000 of the embodiment, the light-emitting layer 50 adopts the structure of at least two organic light-emitting layers, which can be understood as more organic light-emitting layers connected in series, and the light-emitting efficiency can be effectively improved. Under the same current density, the brightness is also higher. Therefore, the display panel 000 adopting the structure has better light-emitting efficiency and higher brightness, which is beneficial to improving the display effect.

[0093] The embodiment further includes the charge generation layer 5014 between the first organic light-emitting layer 5013 and the second organic light-emitting layer 5015. The charge generation layer can also be called a secondary electron-hole pair generation layer. The charge generation layer 5014 can include an electron secondary generation layer 5014A and a hole secondary generation layer 5014B. Although the charge generation layer 5014 does not need to be connected to an electrical signal and relies on the electric field to generate electrons and holes, the charge generation layer 5014 is doped and has better conductivity. Once the common layer of the light-emitting layer 50 includes the charge generation layer 5014, the influence of the lateral leakage current is greater. Therefore, as shown in Figure 2 and Figure 4 The single-side undercut structure of the second sub-isolation JK2 formed at the junction of the first sub-isolation JK1 and the second sub-isolation JK2 (at the J1 position) can more effectively isolate the common layer of the light-emitting layer 50 at the J1 position when the common layer of the light-emitting layer 50 includes the charge generation layer 5014. The leakage current path is completely isolated, and the color crosstalk of adjacent sub-pixels can be effectively improved, especially when the display panel 000 displays low gray scale, to ensure the low gray scale display effect.

[0094] Optionally, as shown in Figure 1 and Figure 6 Figure 6 is Figure 1 Another cross-sectional structure schematic view in the direction of A-A' in FIG. 9. The display panel 000 provided by the embodiment further includes a touch layer 90 located on the side of the cathode layer 60 away from the substrate 10. Further optionally, the touch layer 90 is located on the side of the thin film encapsulation layer 80 away from the substrate 10. ​

[0095] The touch layer 90 includes a touch electrode 901, which is a mesh structure surrounding the light-emitting layer 50. The orthogonal projection of the touch electrode 901 onto the substrate 10 is located between two adjacent sub-pixels 00.

[0096] This embodiment explains that the display panel 000 can achieve touch function by setting a touch layer 90. The touch layer 90 is located on the side of the cathode layer 60 away from the substrate 10. The touch electrodes 901 set in the touch layer 90 are generally metal mesh structures. The touch electrodes 901 with metal mesh structures are routed around the sub-pixels 00. The area enclosed by the touch electrodes 901 with mesh structures corresponds to the location of the light-emitting layer 50. That is, the touch electrodes 901 with mesh routes are located between adjacent sub-pixels 00.

[0097] It is understood that the structure of the touch electrode 901 of the touch layer 90 will not be described in detail in this embodiment. The touch layer 90 may include a double layer or a single layer of conductive layer to form a grid-like touch electrode 901. The touch electrode 901 may include a touch driving electrode and a touch sensing electrode to realize the touch detection function. In specific implementation, the structure of the display touch panel in related technologies can be referred to for understanding. This embodiment will not be described in detail here.

[0098] like Figure 7 As shown, Figure 7 This is a schematic diagram of a partition structure in related technologies. Since the thin-film encapsulation layer 80' is generally thin, and the distance between the touch layer 90' and the cathode layer 60' is relatively close, when the touch electrode 901' of the touch layer 90' is located between adjacent sub-pixels 00', and a partition JK' is provided between adjacent sub-pixels 00', if the forming shape of the partition JK' is as follows... Figure 7 As shown, although the cathode layer 60' can be isolated at the partition JK' position, it is very likely that... Figure 7 The presence of the morphologically defined partition JK' results in the formation of cathode material residue within the partition JK', i.e. Figure 7 The cathode layer material 601' remaining in the partition JK' shown is in a floating state. The floating cathode layer material 601' is relatively close to the touch layer 90', so it will interfere with touch detection and affect touch accuracy.

[0099] Therefore, in this embodiment, it is set at the junction of the first sub-partition JK1 and the second sub-partition JK2 (e.g. Figure 4At the position circled by the dotted line J1, the second sub-isolation JK2 protrudes in the direction close to the sub-pixel 00 along the direction in which one sub-pixel 00 points to another sub-pixel 00 adjacent to it, such as the direction X in which the first sub-pixel 00A points to the second sub-pixel 00B. Thus, the structure of the double-layered first pixel definition layer 30 and the second pixel definition layer 40 can form a single-side undercut structure of the second sub-isolation JK2 at only one side of the second sub-isolation JK2 at the position circled by the dotted line J1. Thus, not only can the organic light-emitting material be located in the first opening 30K1 and the second opening 40K1 to form the light-emitting layer 50 corresponding to the anode 20 of the sub-pixel 00 when the above-mentioned film layers of the light-emitting layer 50 are deposited, but also due to the single-side undercut structure of the second sub-isolation JK2 at the position J1, the common layer of the light-emitting layer 50 can be effectively isolated at the position J1, which is equivalent to that the leakage current path is isolated, and the color crosstalk between adjacent sub-pixels can be effectively improved, especially when the display panel 000 displays a low gray scale to ensure the low gray scale display effect. Moreover, the cathode layer 60 can also be isolated in the isolation port JK with the single-side undercut structure of the second sub-isolation JK2 at only one side, and no cathode layer material can be left in the isolation port JK.

[0100] Specifically, as shown in FIG. 1, the display panel 000 includes a first pixel definition layer 30 and a second pixel definition layer 40. Figure 4 The second pixel definition layer 40 includes a first surface 40A in contact with the first pixel definition layer 30. In the isolation port JK between two adjacent sub-pixels 00, the second sub-isolation JK2 exposes the first surface 40A at the first end JK2A of the second sub-isolation JK2 in the direction X in which the first sub-pixel 00A points to the second sub-pixel 00B. The first surface 40A of the second pixel definition layer 40 is not exposed in the isolation port JK at the second end JK2B of the second sub-isolation JK2, thereby forming a single-side undercut structure of the second sub-isolation JK2 at only one side close to the first sub-pixel 00A, while the second sub-isolation JK2 at the side close to the second sub-pixel 00B is still smooth. The cathode layer 60 can still form a continuous structure at the second end JK2A of the second sub-isolation JK2 in the smooth form, thereby not only ensuring that the common layer of the light-emitting layer 50 is isolated at the isolation port JK, but also ensuring that the cathode layer 60 will not be left at the isolation port JK, which is conducive to improving the touch performance of the display panel 000 and ensuring the touch accuracy.

[0101] In some optional embodiments, please refer to Figure 1 , Figure 2 , Figure 4 and Figure 8 , Figure 8 is Figure 2An enlarged schematic view of the position of the partitioning port, in this embodiment, along the direction of the first sub-pixel 00A pointing to the second sub-pixel 00B, the cathode layer 60 only includes one slit 60K in the partitioning port JK.

[0102] This embodiment explains that in the partitioning port JK arranged between the two adjacent sub-pixels 00, along the direction of the first sub-pixel 00A pointing to the second sub-pixel 00B, the second sub-partition JK2 exposes the first surface 40A at the first end JK2A of the second sub-partition JK2; at the second end JK2B of the second sub-partition JK2, the first surface 40A of the second pixel definition layer 40 is not exposed in the partitioning port JK, thereby forming a form that the second sub-partition JK2 is a single-side undercut structure only on the side close to the first sub-pixel 00A, while the second sub-partition JK2 is still a smooth form on the side close to the second sub-pixel 00B. The cathode layer 60 can still form a continuous structure at the second end JK2A of the second sub-partition JK2 in the smooth form, which can also be understood that along the direction of the first sub-pixel 00A pointing to the second sub-pixel 00B, the cathode layer 60 only includes one slit 60K in the partitioning port JK, that is, one partitioning port JK corresponds to one slit 60K of the cathode layer 60, so as to more effectively prevent the cathode layer 60 material from remaining at the partitioning port JK and improve the touch sensitivity.

[0103] Optionally, in the structure of the cathode layer 60 provided in this embodiment, the cathode layer 60 except the slit 60K is a continuous structure, that is, the cathode 60 in the display panel 000 is still understood as a whole surface, and only at the position of the partitioning port JK, the cathode layer 60 is partitioned to form a slit 60K with limited size, and the slit 60K is still continuous. Therefore, the cathode layer 60 corresponding to different sub-pixels 00 does not need to be controlled separately, which is conducive to simplifying the driving.

[0104] Optionally, as shown in Figure 1 , Figure 2 , Figure 4 , Figure 8 and Figure 9 , Figure 10 , Figure 9 is a schematic view of the combination of the sub-pixel arrangement and the partitioning port arrangement provided by the embodiment of the present disclosure, Figure 10 is another schematic view of the combination of the sub-pixel arrangement and the partitioning port arrangement provided by the embodiment of the present disclosure, in this embodiment, as shown in Figure 9 , the arrangement mode of the plurality of sub-pixels 00 of the display panel 000 is taken as an example of diamond pentile arrangement, and one partitioning port JK can be arranged between the two adjacent sub-pixels 00; as shown in Figure 10As shown, the arrangement mode of the plurality of sub-pixels 00 of the display panel 000 is taken as an example to schematically show a diamond pentile arrangement, and two partition openings JK can be arranged between the two adjacent sub-pixels 00. The two partition openings JK arranged between the two adjacent sub-pixels 00 can more completely cut off the current leakage path, and the current leakage improvement effect is better, but the space between the two adjacent sub-pixels 00 is limited, and the more the number of partition openings JK between the two adjacent sub-pixels 00, the more difficult the current flow of the cathode layer 60, and the pressure drop will increase, which will cause the power consumption to rise. Therefore, in the embodiment, the number of partition openings JK between the two adjacent sub-pixels 00 can be 1-2, which can improve the color crosstalk problem, and can also improve the influence of the residual cathode material on the touch performance, and can also improve the problem of high power consumption of the cathode layer, that is, the embodiment can improve the color cast problem, improve the display quality, improve the touch sensitivity, and ensure the current flow of the cathode layer 60 and reduce the power consumption.

[0105] In some optional embodiments, please continue to refer to Figure 1 , Figure 2 and Figure 4 In the embodiment, the width W1 of the partition opening JK in the direction X from the first sub-pixel 00A to the second sub-pixel 00B ranges from 2-8um.

[0106] The embodiment explains that the width W1 of the partition opening JK in the direction X from the first sub-pixel 00A to the second sub-pixel 00B ranges from 2-8um, the width W1 of the partition opening JK cannot be too small, and too small is easy to cause the common layer of the light-emitting layer 50 and the cathode layer 60 not to be easily cut off at the partition opening JK; the width W1 of the partition opening JK also cannot be too large, and too large is easy to affect the current flow transmission of the cathode layer 60, cause the current pressure drop on the cathode layer 60 to increase, and cause the power consumption to rise. The width W1 of the partition opening JK in the direction X from the first sub-pixel 00A to the second sub-pixel 00B is set in the range of 2-8um in the embodiment, which can improve the color crosstalk, color cast problem, improve the display quality, improve the touch sensitivity, and reduce the power consumption.

[0107] In some optional embodiments, please refer to Figure 1 and Figure 11 , Figure 11 is Figure 1 another cross-sectional structure schematic view in the direction A-A' of

[0108] The color film layer 100 includes a black matrix 1001 and a color resistance 1002 arranged between the black matrix 1001;

[0109] The color resist 1002 corresponds to the light-emitting layer 50 in the direction Z perpendicular to the plane on which the substrate 10 is located.

[0110] The display panel 000 can also include a color film layer 100, which can be arranged on the side of the cathode layer 60 away from the substrate 10. Specifically, the color film layer 100 can be arranged on the side of the thin film encapsulation layer 80 away from the substrate 10, or the color film layer 100 can be arranged between the thin film encapsulation layer 80 and the touch layer 90. In related technologies, in order to prevent the light-emitting layer 50 from reflecting ambient light and affecting the display quality, an anti-reflection polarizing sheet is generally attached to the display panel. The polarizing sheet can cause a certain loss of outgoing light, which can reduce the brightness of the display panel. Moreover, the thickness of the polarizing sheet is relatively large, which is not conducive to the design of a flexible display panel. In this embodiment, the color film layer 100 is used instead of the polarizing sheet. The color film layer 100 includes a black matrix 1001 and color resist 1002 arranged between the black matrix 1001. In the direction Z perpendicular to the plane on which the substrate 10 is located, the color resist 1002 corresponds to the light-emitting layer 50. The black matrix 1001 has a relatively small transmittance. The black matrix 1001 has a plurality of openings, which are light transmission regions of the black matrix 1001. The color resist 1002 is arranged in the plurality of openings of the black matrix 1001, i.e., each color resist 1002 is arranged in the corresponding opening of the black matrix 1001. The color resist 1002 is used to absorb light of a color different from its own color and to allow light of the same color to pass through, thereby achieving light filtering of the display panel 000. Through the arrangement of the color film layer 100, the color gamut of the display panel can be compensated when the reflection of ambient light is reduced, and the display quality is improved.

[0111] Optionally, please continue to refer to Figure 1 and Figure 11 In this embodiment, the transmittance of the first pixel definition layer 30 is less than the transmittance of the second pixel definition layer 40.

[0112] Further optionally, the first pixel definition layer 30 includes a black material.

[0113] In this embodiment, when the display panel 000 includes the color film layer 100, the light transmittance of the material of the first pixel definition layer 30 can be less than the light transmittance of the second pixel definition layer 40, i.e., the material of the first pixel definition layer 30 can be a light-blocking material such as a black material. The first pixel definition layer 30 can block external light, thereby reducing the reflectivity of light irradiating the surface of the first pixel definition layer 30, and preventing external light from irradiating the thin film transistor 70T of the drive array layer 70, which is conducive to improving the stability of the thin film transistor 70T. Moreover, the first pixel definition layer 30 made of a black material can block crosstalk between adjacent sub-pixels 00, thereby improving the contrast of the display panel 000.

[0114] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 In the embodiment, the first opening 30K1 of the first pixel definition layer 30 in the orthographic projection of the substrate 10 is located within the second opening 40K1 of the second pixel definition layer 40 in the orthographic projection of the substrate 10.

[0115] The embodiment explains that the size of the first opening 30K1 can be slightly smaller than the size of the second opening 40K1, that is, the first opening 30K1 of the first pixel definition layer 30 in the orthographic projection of the substrate 10 is located within the second opening 40K1 of the second pixel definition layer 40 in the orthographic projection of the substrate 10, so that the first opening 30K1 and the second opening 40K1 overlap each other to form a containing space of the light-emitting layer 50, and the first opening 30K1 and the second opening 40K1 overlap each other to form the light-emitting region of the sub-pixel 00.

[0116] In some optional embodiments, please continue to refer to Figure 1 and Figure 12 , Figure 12 is Figure 1 Another cross-sectional structure schematic view in the direction of A-A' in In the embodiment, the second opening 40K1 of the second pixel definition layer 40 in the orthographic projection of the substrate 10 is located within the first opening 30K1 of the first pixel definition layer 30 in the orthographic projection of the substrate 10;

[0117] At the first opening 30K1, the second pixel definition layer 40 covers the first pixel definition layer 30.

[0118] The embodiment explains that the size of the first opening 30K1 can be slightly larger than the size of the second opening 40K1, that is, the second opening 40K1 of the second pixel definition layer 40 in the orthographic projection of the substrate 10 is located within the first opening 30K1 of the first pixel definition layer 30 in the orthographic projection of the substrate 10, so that when the first pixel definition layer 20 is patterned and the second pixel definition layer 40 is manufactured, at the first opening 30K1, the second pixel definition layer 40 can cover the first pixel definition layer 30 at the first opening 30K1, avoiding that foreign matter residues at the first opening 30K1 may affect the evaporation of the light-emitting layer 50, and then abnormal light emission occurs, which is beneficial to guarantee the light-emitting quality. In the embodiment, the second pixel definition layer 40 can cover the first pixel definition layer 30 at the first opening 30K1, and since the second pixel definition layer 40 can adopt a coating process, the ability to fill the gap of foreign matter is stronger, and the second pixel definition layer 40 is not easy to break, so that the foreign matter residues at the first opening 30K1 can be effectively covered, which is beneficial to improve the display and light-emitting quality.

[0119] In some optional embodiments, please continue to refer to Figure 1 , Figure 2, Figure 4 and Figure 6 In this embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, the second sub-partition JK2 penetrates the thickness of the first pixel definition layer 30, and the first sub-partition JK1 penetrates the thickness of the second pixel definition layer 40.

[0120] This embodiment explains that along the direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating a portion of the first pixel definition layer 30. The first sub-partition JK1 and the second sub-partition JK2 are connected, that is, by opening the second sub-partition JK2 and the first sub-partition JK1 in the first pixel definition layer 30 and the second pixel definition layer 40 respectively, and the first sub-partition JK1 and the second sub-partition JK2 are connected in the direction Z perpendicular to the plane where the substrate 10 is located to form a partition opening JK. The partition opening JK is located between two adjacent sub-pixels 00, and the partition opening JK is also located between two adjacent second openings 40K1. Therefore, along the direction X pointing from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-block JK2 protrudes towards the first sub-pixel 00A relative to the first sub-block JK1, forming a single-sided undercut structure on one side of the second sub-block JK2. Not only can the common layer of the light-emitting layer 50 be effectively blocked at the position J1 circled in the dashed circle, but the cathode layer 50 is also effectively blocked at the position J1 circled in the dashed circle, and there will be no cathode layer material residue. This can effectively improve the color crosstalk between adjacent sub-pixels and also improve touch performance.

[0121] In some alternative embodiments, please refer to the references. Figure 1 and Figure 13 , Figure 14 , Figure 13 yes Figure 1 Another cross-sectional structural diagram along the A-A' direction. Figure 14 yes Figure 1 Another cross-sectional structural diagram along the A-A' direction (to clearly illustrate the structure of the partition in this embodiment, Figure 14 (The film layers above the second pixel definition layer are not shown in the figure). In this embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, the second sub-segment JK2 penetrates the thickness of the first pixel definition layer 30, and the first sub-segment JK1 penetrates the thickness of the second pixel definition layer 40.

[0122] The embodiment explains that the partition port JK includes the first sub-partition JK1 penetrating the second pixel definition layer 40 and the second sub-partition JK2 penetrating the first pixel definition layer 30 in the direction Z perpendicular to the plane where the substrate 10 is located, the first sub-partition JK1 and the second sub-partition JK2 are communicated, that is, the second sub-partition JK2 and the first sub-partition JK1 are respectively opened in the first pixel definition layer 30 and the second pixel definition layer 40, and the first sub-partition JK1 and the second sub-partition JK2 are communicated in the direction Z perpendicular to the plane where the substrate 10 is located to form a partition port JK, the partition port JK is located between the adjacent two sub-pixels 00, and the partition port JK is located between the adjacent two second openings 40K1. Thus, in the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-partition JK2 protrudes relative to the first sub-partition JK1 in the direction close to the first sub-pixel 00A, and forms a single-side undercut structure on one side of the second sub-partition JK2. The common layer of the light-emitting layer 50 can be in the undercut structure not only on the side of the second sub-partition JK2 but also on the side of the first sub-partition JK1, and the light-emitting layer 50 can be effectively partitioned in the direction X perpendicular to the plane where the substrate 10 is located. Thus, the color crosstalk between the adjacent sub-pixels can be effectively improved, and the touch performance can be improved. Figure 14 The position J2 circled by the dotted line is effectively partitioned, and the cathode layer 50 is effectively partitioned at the position J2 circled by the dotted line, and no cathode layer material is left, which can effectively improve the color crosstalk between the adjacent sub-pixels and improve the touch performance.

[0123] The partition port JK of the embodiment is composed of the first sub-partition JK1 penetrating the entire thickness of the second pixel definition layer 40 and the second sub-partition JK2 penetrating the entire thickness of the first pixel definition layer 30, and the undercut amount of the side of the second sub-partition JK2 formed in the single-side undercut structure can be larger, and the partition effect is better.

[0124] In some optional embodiments, please continue to refer to Figure 1 , Figure 2 , Figure 4 , Figure 6 , Figure 13 and Figure 14 In the embodiment, the first pixel definition layer 30 further includes a plurality of third openings 30K2, the third openings 30K2 are located between the adjacent two first openings 30K1, and the third openings 30K2 penetrate the first pixel definition layer 30.

[0125] In the direction Z perpendicular to the plane where the substrate 10 is located, the partition port JK at least partially overlaps the third opening 30K2, and at least part of the second pixel definition layer 40 is filled in the third opening 30K2.

[0126] The embodiment explains that in order to make the double-layered first pixel definition layer 30 and the second pixel definition layer 40, Figure 4 the position J1 circled by the dotted line, Figure 14The second sub-segment JK2, formed at the position circled by the dashed line, has a single-sided undercut structure on only one side. When fabricating and patterning the first pixel definition layer 30, the first pixel definition layer 30 can include multiple first openings 30K1 corresponding to the anode 20, as well as multiple third openings 30K2. The third openings 30K2 are located between two adjacent first openings 30K1, that is, between two adjacent sub-pixels 00. The third openings 30K2 penetrate the entire thickness of the first pixel definition layer 30. In this embodiment, by setting the third openings 30K2 in the first pixel definition layer 30, the second pixel definition layer 40, after coating, can fill the third opening 30K2 and cover one side of the first pixel definition layer 30 (e.g., ...). Figure 4 and Figure 14 At position J3 circled in the diagram, the second pixel definition layer 40 can fill the third opening 30K2 and cover the first pixel definition layer 30 on one side. After the first pixel definition layer 30 and the second pixel definition layer 40 are fabricated, when the partition opening JK is fabricated, the first pixel definition layer 30 on one side of the third opening 30K2 is protected. This allows the second sub-partition JK2 to be formed on only one side near the first sub-pixel 00A. This makes the shape of the partition opening JK required in this embodiment possible during the manufacturing process, ensuring that the common layer of the light-emitting layer 50 can be effectively isolated, the cathode layer 50 can also be effectively isolated, and there will be no cathode layer material residue. This effectively improves color crosstalk between adjacent sub-pixels and enhances touch performance.

[0127] It is understood that the figures in this embodiment are only illustrative examples of the third opening 30K2 penetrating the entire thickness of the first pixel definition layer 30. In actual implementation, such as Figure 1 and Figure 15 As shown, Figure 15 yes Figure 1 Another cross-sectional structure diagram along the A-A' direction shows that the third opening 30K2 can also only penetrate part of the thickness of the first pixel definition layer 30. Since the single-sided undercut structure of the second sub-partition JK2 is relatively shallow, the area of ​​the first pixel definition layer 30 that needs to be covered and protected by the second pixel definition layer 40 at the third opening 30K2 can also be relatively shallow. Therefore, the first pixel definition layer 30 at the third opening 30K2 does not need to be completely removed. It is only necessary to ensure that one side of the first pixel definition layer 30 at the third opening 30K2 can be covered by the second pixel definition layer 40 without being side-cut. In specific implementation, the shape of the third opening 30K2 can be set according to actual needs.

[0128] In some alternative embodiments, please refer to the references. Figure 16 and Figure 17 , Figure 16is another planar structure schematic diagram of the display panel provided by the embodiment of the present disclosure, Figure 17 is Figure 16 is a cross-sectional structure schematic diagram in the direction of B-B' in the above-mentioned display panel 000, in the embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, the third opening 30K2 penetrates the thickness of the first pixel definition layer 30.

[0129] The display panel 000 further includes a photosensitive element 00X, in the direction Z perpendicular to the plane where the substrate 10 is located, the photosensitive element 00X at least partially overlaps with the third opening 30K2.

[0130] With the development of display technology, various display devices with fingerprint recognition function have appeared in the market, such as mobile phones, tablet computers, smart wearable devices, etc. Common fingerprint recognition methods mainly include under-screen optical fingerprint recognition and under-screen ultrasonic fingerprint recognition, among which under-screen optical fingerprint recognition becomes the market mainstream due to its price advantage. When the under-screen optical fingerprint recognition is applied to the OLED display panel, the photosensitive element 00X such as the under-screen fingerprint recognition element or the distance sensor can be set at the opening of the pixel definition layer by opening the pixel definition layer with poor light transmission. The third opening 30K2 penetrating the first pixel definition layer 30 is provided between the two adjacent sub-pixels 00 in the embodiment, and when the display panel 000 includes the photosensitive element 00X, the third opening 30K2 can be reused as the light transmission port of the photosensitive element 00X, and the photosensitive element 00X at least partially overlaps with the third opening 30K2 in the direction Z perpendicular to the plane where the substrate 10 is located, so as to ensure that the photosensitive element 00X can be normally used, and realize the photosensitive detection functions such as fingerprint recognition, palmprint recognition and distance detection of the display panel 000.

[0131] It can be understood that in the display panel 000 of the embodiment, the photosensitive element 00X can be provided between the two adjacent sub-pixels 00, and the photosensitive element 00X can be a fingerprint recognition element. By integrating the photosensitive element 00X in the entire plane of the display panel 000, large-area fingerprint recognition or full-screen fingerprint recognition can be realized.

[0132] Optionally, the setting film layer of the photosensitive element 00X in the embodiment can be arranged in the same layer as part of the film layer of the driving array layer 70, so that the thin film transistor 70T or the signal trace in the photosensitive element 00X and the driving array layer 70 are formed under the same process condition, which is conducive to simplifying the process flow. Further optionally, the photosensitive element 00X can include a lower electrode 00X1, an upper electrode 00X2, and an intrinsic semiconductor layer 00X3 arranged between the lower electrode 00X1 and the upper electrode 00X2. It can be understood that the arrangement structure of the photosensitive element 00X in the embodiment is only illustrative, and in specific implementation, the structure of the photosensitive element 00X can also be other structures, and the embodiment is only used to explain that the setting film layer of the photosensitive element 00X can be arranged in the same layer as part of the film layer of the driving array layer 70.

[0133] It can be understood that the photosensitive element 00X in the embodiment Figure 16 is only illustrative of the arrangement mode of the sub-pixel 00 and the arrangement position of the photosensitive element 00X, and in specific implementation, the arrangement mode of the sub-pixel 00 can also be other pixel arrangement structures, which can be selected according to actual needs. The number of the third openings 30K2 in the embodiment can be different from the number of the photosensitive elements 00X, that is, the photosensitive elements 00X can be arranged directly below part of the third openings 30K2, that is, part of the third openings 30K2 can be reused as the light transmission port of the photosensitive element 00X.

[0134] Optionally, the manufacturing materials of the first pixel definition layer 30 and the second pixel definition layer 40 in the embodiment can be different, and under the same etching condition, the etching rate of the first pixel definition layer 30 is greater than the etching rate of the second pixel definition layer 40. The etching rate of the first pixel definition layer 30 with low light transmittance can be about three times the etching rate of the second pixel definition layer 40 with high light transmittance. For example, the first pixel definition layer 30 is a negative material, and the second pixel definition layer 40 is a positive material. When the same mask is used to manufacture the isolation port JK, the exposure position of the mask opening of the positive material second pixel definition layer 40 will be removed, and the mask shielding position will be left. The exposure position of the mask opening of the negative material first pixel definition layer 30 will be left, and the mask shielding position will be removed, so that the isolation port JK is formed at the junction of the first sub-isolation JK1 and the second sub-isolation JK2, the second sub-isolation JK2 has only one side as a single undercut structure, the common layer of the light-emitting layer 50 can be effectively isolated, the cathode layer 50 can also be effectively isolated, and there is no residual cathode layer material, which effectively improves the color crosstalk of adjacent sub-pixels and improves the touch performance.

[0135] In some optional embodiments, please refer to Figures 1-5 , Figure 18is a flow chart of a manufacturing method of a display panel provided by the embodiments of the present disclosure, the embodiments provide a manufacturing method of a display panel, the manufacturing method is used for manufacturing the display panel 000 in any of the above embodiments; the manufacturing method of the embodiments comprises:

[0136] S10: providing a substrate 10;

[0137] S11: manufacturing a plurality of anodes 20, the anodes 20 correspond to sub-pixels 00; optionally, manufacturing the anodes 20 can also complete the manufacturing of the driving array layer 70; as shown in Figure 19 , Figure 19 is a structural schematic diagram after the manufacturing of the anodes in the manufacturing method of Figure 18 ;

[0138] S12: manufacturing a first pixel definition layer 30, patterning the first pixel definition layer 30 to form a plurality of first openings 30K1, the first openings 30K1 expose part of the anodes 20; as shown in Figure 20 , Figure 20 is a structural schematic diagram after the patterning of the first pixel definition layer in the manufacturing method of Figure 18 ;

[0139] S13: manufacturing a second pixel definition layer 40, patterning the second pixel definition layer 40 to form a plurality of second openings 40K1, the second openings 40K1 in the orthographic projection of the substrate 10 at least partially overlap with the first openings 30K1 in the orthographic projection of the substrate 10; as shown in Figure 21 , Figure 21 is a structural schematic diagram after the second openings of the second pixel definition layer in the manufacturing method of Figure 18 ;

[0140] S14: manufacturing a partition port JK, the partition port JK is located between two adjacent sub-pixels 00, and in a direction Z perpendicular to the plane where the substrate 10 is located, the partition port JK comprises a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least part of the first pixel definition layer 30, the first sub-partition JK1 and the second sub-partition JK2 are communicated to form the partition port JK; in the partition port JK formed in this step, at the junction of the first sub-partition JK1 and the second sub-partition JK2, in a direction pointing from one sub-pixel 00 to another sub-pixel 00 adjacent to it, such as a direction X pointing from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-partition JK2 protrudes relative to the first sub-partition JK1 in a direction close to the first sub-pixel 00A; as shown in Figure 22 , Figure 22 is a structural schematic diagram after the manufacturing of the partition port in the manufacturing method of Figure 18 ;

[0141] S15: manufacturing the light-emitting layer 50, at least part of the light-emitting layer 50 is located in the first opening 30K1 on the side of the second pixel definition layer 40 away from the substrate 10; the light-emitting layer 50 comprises a common layer, the common layer is blocked at the blocking port JK; as shown in Figure 3 , the common layer can be one or more of the hole injection layer 501, the hole transport layer 502, the hole blocking layer 504, the electron transport layer 505, and the electron injection layer 506, as shown in Figure 5 , the common layer can be one or more of the hole injection layer 5011, the hole transport layer 5012, the charge generation layer 5014, the hole blocking layer 5016, the electron transport layer 5017, and the electron injection layer 5018; as shown in Figure 23 , Figure 23 , the common layer can be one or more of the hole injection layer 5011, the hole transport layer 5012, the charge generation layer 5014, the hole blocking layer 5016, the electron transport layer 5017, and the electron injection layer 5018; as shown in Figure 18 , the structure after the light-emitting layer is completed in the manufacturing method of

[0142] S16: manufacturing the cathode layer 60, the cathode layer 60 is blocked at the blocking port JK; as shown in Figure 24 , Figure 24 , the structure after the cathode layer is completed in the manufacturing method of Figure 18 .

[0143] The manufacturing method of the display panel provided in the embodiment can form at least one blocking port JK between two adjacent sub-pixels 00 by manufacturing the structure of the first pixel definition layer 30 and the second pixel definition layer 40 which are double-layered and have different materials, the blocking port JK comprises the first sub-blocking JK1 penetrating the second pixel definition layer 40 and the second sub-blocking JK2 penetrating at least part of the first pixel definition layer 30 in the direction Z perpendicular to the plane where the substrate 10 is located, the second sub-blocking JK2 is formed when the first pixel definition layer 30 is patterned, the first sub-blocking JK1 is formed when the second pixel definition layer 40 is patterned, and finally the first sub-blocking JK1 and the second sub-blocking JK2 are communicated, that is, by opening the second sub-blocking JK2 and the first sub-blocking JK1 in the first pixel definition layer 30 and the second pixel definition layer 40 respectively, and the first sub-blocking JK1 and the second sub-blocking JK2 are communicated in the direction Z perpendicular to the plane where the substrate 10 is located to form a blocking port JK, the blocking port JK is located between two adjacent sub-pixels 00, and the blocking port JK is located between two adjacent second openings 40K1. The form of the blocking port JK is at the junction of the first sub-blocking JK1 and the second sub-blocking JK2 (as shown in Figure 4In the J1 position circled by the dashed line, a second sub-barrier JK2 protrudes in a direction close to the sub-pixel 00 relative to a first sub-barrier JK1 in a direction in which the sub-pixel 00 points to another sub-pixel 00 adjacent to the sub-pixel 00, so that a single-side undercut structure of the second sub-barrier JK2 can be formed at the J1 position circled by the dashed line. When film layers of the subsequent light-emitting layer 50 are deposited to form films, the organic light-emitting material can be located in the first opening 30K1 and the second opening 40K1 to form the light-emitting layer 50 corresponding to the anode 20 of the sub-pixel 00, and because of the single-side undercut structure of the second sub-barrier JK2 formed at the J1 position, the common layer of the light-emitting layer 50 can be effectively blocked at the J1 position (as shown in Figure 23 The equivalent leakage current path is blocked, the color crosstalk between adjacent sub-pixels can be effectively improved, and the cathode layer 60 can also be blocked at the blocking port JK (as shown in Figure 24 Especially when the display panel 000 displays in a low gray scale, the color crosstalk between adjacent sub-pixels can be avoided, the electrical light leakage can be improved, the normal light emission of the pixel is not affected, the low gray scale display effect is ensured, and the touch performance can be improved.

[0144] It can be understood that the manufacturing method of the embodiment can also include manufacturing other film layer structures of the display panel 000, such as a thin film encapsulation layer 80, a touch layer 90, and a color film layer 100. The embodiment will not be described here, and the process technology of the OLED display panel in the related art can be referred to for understanding.

[0145] Optionally, when the cathode layer 60 is manufactured, because of the existence of the blocking port JK, in a direction in which one sub-pixel 00 points to another sub-pixel 00 adjacent to the sub-pixel 00, that is, in a direction X in which the first sub-pixel 00A points to the second sub-pixel 00B, the cathode layer 60 only includes a slit 60K in the blocking port JK, so that the material of the cathode layer 60 can be more effectively prevented from remaining at the blocking port JK, and the touch sensitivity can be improved.

[0146] Optionally, the first pixel definition layer 30 and the second pixel definition layer 40 of the embodiment are different film layers, the manufacturing materials of the first pixel definition layer 30 and the second pixel definition layer 40 can be different, the first pixel definition layer 30 includes a negative material, the second pixel definition layer 40 includes a positive material, the transmittance of the first pixel definition layer 30 is less than the transmittance of the second pixel definition layer 40, and the etching rate of the first pixel definition layer 30 is greater than the etching rate of the second pixel definition layer 40 under the same etching condition. Because the two layers are stacked and the materials are different, the single-side undercut structure of the second sub-barrier JK2 can be more conveniently and quickly formed at the junction of the first sub-barrier JK1 and the second sub-barrier JK2 in the manufacturing process, so that Figure 2 and Figure 4The formation of the partitioning port JK shown is possible, so in this embodiment, at least the common layer in the light-emitting layer 50 can be effectively partitioned at the partitioning port JK, i.e., as shown in the mode of the partitioning port JK shown in Figure 2 and Figure 4 The arrangement of the partitioning port JK in the mode shown can ensure partitioning of the lateral leakage current, is conducive to simplifying the process technology, improving process efficiency, and also can improve the color cast problem and improve the display quality.

[0147] In some optional embodiments, please refer to Figures 1-5 , Figure 25 is another flowchart of a manufacturing method of a display panel provided by the embodiments of the present disclosure. The manufacturing method of the present embodiment is a manufacturing method of a display panel, and is used for manufacturing the display panel 000 in any of the above embodiments. The manufacturing method of the present embodiment includes the following steps:

[0148] S20: providing a substrate 10;

[0149] S21: manufacturing a plurality of anodes 20, the anodes 20 corresponding to sub-pixels 00; optionally, manufacturing the anodes 20 can also complete the manufacturing of the driving array layer 70, as shown in Figure 19 ;

[0150] S22: manufacturing a first pixel definition layer 30, patterning the first pixel definition layer 30 to form a plurality of first openings 30K1 and a plurality of third openings 30K2, the third openings 30K2 being located between two adjacent first openings 30K1, the third openings 30K2 penetrating the thickness of the first pixel definition layer 30, and the first openings 30K1 exposing part of the anodes 20, as shown in Figure 20 ; or the third openings 30K2 penetrating part of the thickness of the first pixel definition layer 30, as shown in Figure 26 , Figure 26 is a structural schematic diagram of the first pixel definition layer after the patterning in the manufacturing method of Figure 25 ; optionally, the third openings 30K2 and the first openings 30K1 can be completed in one patterning process, or can also be completed by two patterning processes, and the present embodiment does not limit this;

[0151] S23: manufacturing a second pixel definition layer 40, patterning the second pixel definition layer 40 to form a plurality of second openings 40K1, the second openings 40K1 at least partially overlapping the first openings 30K1 in the orthographic projection of the substrate 10; at least part of the second pixel definition layer 40 is filled in the third openings 30K2, as shown in Figure 21 and Figure 27 , Figure 27 is a structural schematic diagram of the first pixel definition layer after the patterning in the manufacturing method of Figure 25Figure 6 shows a schematic view of the structure after the second opening of the second pixel definition layer is completed in the method of manufacturing the display panel; in this process, the size of the first opening 30K1 can be slightly smaller than the size of the second opening 40K1, that is, the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 on the substrate 10 is located within the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 on the substrate 10, so that the first opening 30K1 and the second opening 40K1 overlap each other to form a containing space of at least part of the light-emitting layer 50, and the first opening 30K1 and the second opening 40K1 overlap each other to form the light-emitting area of the sub-pixel 00. The size of the first opening 30K1 can also be slightly larger than the size of the second opening 40K1, that is, the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 on the substrate 10 is located within the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 on the substrate 10, so that after the first pixel definition layer 20 is patterned, when the second pixel definition layer 40 is manufactured, the second pixel definition layer 40 can cover the first pixel definition layer 30 at the first opening 30K1, avoiding the possible foreign matter residue at the first opening 30K1 from affecting the evaporation of the light-emitting layer 50.

[0152] S24: manufacturing the partition port JK, the partition port JK is located between two adjacent sub-pixels 00, and in the direction Z perpendicular to the plane where the substrate 10 is located, the partition port JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least part of the first pixel definition layer 30, and the first sub-partition JK1 and the second sub-partition JK2 are communicated to form the partition port JK; in the partition port JK formed in this step, at the junction of the first sub-partition JK1 and the second sub-partition JK2, in the direction of one sub-pixel 00 pointing to another sub-pixel 00 adjacent thereto, such as the direction X of the first sub-pixel 00A pointing to the second sub-pixel 00B, the second sub-partition JK2 protrudes relative to the first sub-partition JK1 in the direction close to the first sub-pixel 00A;

[0153] S241: manufacturing the partition port JK includes providing a mask L1 (not filled in the figure), the opening L1K of the mask L1 is located between two adjacent sub-pixels 00; etching the second pixel definition layer 40 and the first pixel definition layer 30 at the same etching rate; wherein, in the direction Z perpendicular to the plane where the substrate 10 is located, one side of the opening L1K of the mask L1 is located within the third opening 30K2, and the other side of the opening L1K of the mask L1 is located outside the third opening 30K2;

[0154] The first sub-partition JK1 is formed between two adjacent sub-pixels 00 of the second pixel definition layer 40, and the second sub-partition JK2 is formed between two adjacent sub-pixels 00 of the first pixel definition layer 30, and in the direction Z perpendicular to the plane where the substrate 10 is located, the first sub-partition JK1 and the second sub-partition JK2 are communicated;

[0155] The second sub-portion JK2 exposes a first surface 40A of the second pixel definition layer 40, wherein the first surface 40A refers to a surface of the second pixel definition layer 40 facing the first pixel definition layer 30; as shown in Figure 28 and Figure 29 , the first surface 40A is exposed by the second sub-portion JK2. Figure 28 is a schematic diagram of a position of a mask in the manufacturing method of Figure 25 . Figure 29 is a schematic diagram of another position of a mask in the manufacturing method of Figure 25 .

[0156] S25: manufacturing the light-emitting layer 50, at least part of the light-emitting layer 50 is located in the first opening 30K1 on the side of the second pixel definition layer 40 away from the substrate 10; the light-emitting layer 50 includes a common layer, the common layer is interrupted at the interruption portion JK; as shown in Figure 3 , the common layer can be one or more of a hole injection layer 501, a hole transport layer 502, a hole blocking layer 504, an electron transport layer 505, and an electron injection layer 506; as shown in Figure 5 , the common layer can be one or more of a hole injection layer 5011, a hole transport layer 5012, a charge generation layer 5014, a hole blocking layer 5016, an electron transport layer 5017, and an electron injection layer 5018; as shown in Figure 23 and Figure 30 , the common layer is interrupted at the interruption portion JK. Figure 30 is a schematic diagram of a structure after the light-emitting layer is completed in the manufacturing method of Figure 25 .

[0157] S26: manufacturing the cathode layer 60, the cathode layer 60 is interrupted at the interruption portion JK; as shown in Figure 24 and Figure 31 , the cathode layer is interrupted at the interruption portion JK. Figure 31 is a schematic diagram of a structure after the cathode layer is completed in the manufacturing method of Figure 25 .

[0158] The present embodiment explains that when the first pixel definition layer 30 is patterned, a third opening 30K2 can be formed between two adjacent first openings 30K1, the third opening 30K2 can penetrate the thickness of the first pixel definition layer 30 (as shown in Figure 20 ), or can only penetrate part of the thickness of the first pixel definition layer 30 (as shown in Figure 26 ); the third opening 30K2 in the first pixel definition layer 30 can make the second pixel definition layer 40 after coating to fill in the third opening 30K2 to cover the first pixel definition layer 30 on one side (as shown in Figure 21 and Figure 27As shown, the second pixel definition layer 40 can fill the third opening 30K2 and cover one side of the first pixel definition layer 30. Therefore, after the first pixel definition layer 30 and the second pixel definition layer 40 are both fabricated, when fabricating the partition JK, the first pixel definition layer 30 on one side of the third opening 30K2 is protected, so that the one-sided undercut structure of the second sub-partition JK2 can only be formed on the side closest to the first sub-pixel 00A (as shown). Figure 28 and Figure 29 As shown, a mask L1 is used when fabricating the partition JK. The opening L1K of the mask L1 is located between two adjacent sub-pixels 00. The second pixel definition layer 40 and the first pixel definition layer 30 are etched at the same etching rate. In the direction Z perpendicular to the plane of the substrate 10, one side of the opening L1K of the mask L1 is located inside the third opening 30K2, and the other side of the opening L1K of the mask L1 is located outside the third opening 30K2. Since the materials used to fabricate the first pixel definition layer 30 and the second pixel definition layer 40 can be different, under the same etching conditions, the etching rate of the first pixel definition layer 30 is greater than the etching rate of the second pixel definition layer 40. The etching rate of the first pixel definition layer 30 with low light transmittance can be about three times that of the second pixel definition layer 40 with high light transmittance. If the first pixel definition layer 30 is a negative material and the second pixel definition layer 40 is a positive material, when the same mask L1 is used to fabricate the partition opening JK, the exposure position of the mask L1 opening L1K of the second pixel definition layer 40 with positive material will be removed, and the mask L1 blocking position will remain; the exposure position of the mask L1 opening L1K of the first pixel definition layer 30 with negative material will remain, and the mask L1 blocking position will be removed. This allows the partition opening JK to form a single-sided undercut structure on only one side of the second sub-partition JK2 at the junction of the first sub-partition JK1 and the second sub-partition JK2. The manufacturing process of the first pixel definition layer 30 and the partition JK in this embodiment makes it possible to achieve the shape of the partition JK required in this embodiment during the manufacturing process, ensuring that the common layer of the light-emitting layer 50 can be effectively isolated, the cathode layer 50 can also be effectively isolated, and there will be no cathode layer material residue, which effectively improves the color crosstalk between adjacent sub-pixels and improves touch performance.

[0159] It can be understood that, due to the different materials of the first pixel definition layer 30 and the second pixel definition layer 40 in the embodiment, the first pixel definition layer 30 can be a negative material, and the second pixel definition layer can be selected as a positive material, so that after the coating of the first pixel definition layer 30 is completed, the patterning process is performed to form the first opening 30K1 and the third opening 30K2 of the first pixel definition layer 30, and then the coating of the second pixel definition layer 40 is performed, and the opening of the second opening 40K1 is completed. Finally, a mask L1 is used to form the partition port JK including the first sub-partition JK1 and the second sub-partition JK2 between the adjacent sub-pixels 00.

[0160] In some optional embodiments, referring to Figure 32 , Figure 32 is a schematic diagram of a planar structure of a display device provided by the embodiment of the present disclosure. The display device 111 provided by the embodiment includes the display panel 000 provided by the above-mentioned embodiments of the present disclosure. Figure 32 The embodiment only takes a mobile phone as an example to describe the display device 111, and it can be understood that the display device 111 provided by the embodiment of the present disclosure can be a computer, a television, a vehicle-mounted display device, or other display devices 111 having a display function, and the present disclosure does not specifically limit this. The display device 111 provided by the embodiment of the present disclosure has the beneficial effects of the display panel 000 provided by the embodiment of the present disclosure, and specific descriptions can be referred to the specific descriptions of the display panel 000 in the above-mentioned embodiments. The embodiment will not be described here.

[0161] It should be noted that, in this document, relational terms such as“first” and“second”, and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms“comprises”,“comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the phrase“comprising a……” does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0162] The foregoing is merely illustrative of the various implementations of the present disclosure and the general principles thereof. Numerous modifications can be made to these illustrations, and equivalents can be substituted therefor, without departing from the scope of the present disclosure. The specific embodiments commensurate with the specific application are intended to be illustrative only and not limiting of the scope of the application as set forth in the following claims.

Claims

1. A display panel, characterized in that, The display panel includes a plurality of sub-pixels, and the sub-pixels include an anode; The display panel also includes: A substrate, wherein the anode is located on one side of the substrate; A first pixel definition layer is located on the side of the anode away from the substrate. The first pixel definition layer includes a plurality of first openings, the first openings exposing a portion of the anode. A second pixel definition layer is located on the side of the first pixel definition layer away from the substrate. The second pixel definition layer includes a plurality of second openings. The orthographic projection of the second openings on the substrate at least partially overlaps with the orthographic projection of the first openings on the substrate. The transmittance of the first pixel definition layer is less than that of the second pixel definition layer. A light-emitting layer, at least a portion of which is located within the first opening; A cathode layer, the cathode layer being located on the side of the light-emitting layer away from the substrate; Between two adjacent sub-pixels, the display panel includes at least one partition opening along a direction perpendicular to the plane of the substrate. The partition opening includes a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least a portion of the first pixel definition layer. The first sub-partition and the second sub-partition are connected. At the junction of the first sub-division and the second sub-division, along the direction from one of the sub-pixels to the adjacent sub-pixel, the second sub-division protrudes towards the sub-pixel relative to the first sub-division.

2. The display panel according to claim 1, characterized in that, The sub-pixel includes an adjacent first sub-pixel and a second sub-pixel, and the second sub-division includes a first end and a second end opposite to each other, with the first end located between the second end and the first sub-pixel; At the junction of the first sub-partition and the second sub-partition, the first end of the second sub-partition protrudes toward the first sub-pixel relative to the first sub-partition.

3. The display panel according to claim 2, characterized in that, The second pixel definition layer includes a first surface that contacts the first pixel definition layer; Along the direction from the first sub-pixel to the second sub-pixel, at the first end, the second sub-partition exposes a portion of the first surface; At the second end, the first surface of the second pixel definition layer is not exposed within the partition.

4. The display panel according to claim 1, characterized in that, Within the partition, the cathode layer comprises only one slit along the direction from one of the sub-pixels to its adjacent sub-pixel.

5. The display panel according to claim 4, characterized in that, The cathode layer, except for the slit, has a continuous structure.

6. The display panel according to claim 1, characterized in that, The display panel further includes a color filter layer, which is located on the side of the cathode layer away from the substrate; The color filter layer includes a black matrix and color resist disposed between the black matrix; In a direction perpendicular to the plane of the substrate, the color resist corresponds to the light-emitting layer.

7. The display panel according to claim 1, characterized in that, The first pixel definition layer includes black material.

8. The display panel according to claim 1, characterized in that, The display panel further includes a touch layer located on the side of the cathode layer away from the substrate; The touch layer includes touch electrodes, which are mesh structures surrounding the light-emitting layer. The orthographic projection of the touch electrodes onto the substrate is located between two adjacent sub-pixels.

9. The display panel according to claim 1, characterized in that, The orthographic projection of the first opening onto the substrate lies within the orthographic projection of the second opening onto the substrate.

10. The display panel according to claim 1, characterized in that, The second opening is projected onto the substrate in the same direction as the first opening in the same direction as the substrate. At the first opening, the second pixel definition layer covers the first pixel definition layer.

11. The display panel according to claim 1, characterized in that, In a direction perpendicular to the plane of the substrate, the second sub-partition penetrates a portion of the thickness of the first pixel definition layer, and the first sub-partition penetrates the thickness of the second pixel definition layer.

12. The display panel according to claim 1, characterized in that, In a direction perpendicular to the plane of the substrate, the second sub-partition extends through the thickness of the first pixel definition layer, and the first sub-partition extends through the thickness of the second pixel definition layer.

13. The display panel according to claim 1, characterized in that, The first pixel definition layer also includes a plurality of third openings, the third openings being located between two adjacent first openings and penetrating the first pixel definition layer; In a direction perpendicular to the plane of the substrate, the partition opening at least partially overlaps with the third opening, and at least a portion of the second pixel definition layer fills the third opening.

14. The display panel according to claim 13, characterized in that, In a direction perpendicular to the plane of the substrate, the third opening penetrates the thickness of the first pixel definition layer; The display panel further includes a photosensitive element, which at least partially overlaps with the third opening in a direction perpendicular to the plane of the substrate.

15. The display panel according to claim 1, characterized in that, The light-emitting layer includes a hole injection layer, a hole transport layer, an organic light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer stacked along a direction perpendicular to the plane of the substrate. The light-emitting layer includes a common layer; the common layer includes one or more of the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer.

16. The display panel according to claim 1, characterized in that, The light-emitting layer includes a hole injection layer, a hole transport layer, a first organic light-emitting layer, a charge generation layer, a second organic light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer, which are stacked along a direction perpendicular to the plane of the substrate. The light-emitting layer includes a common layer; The common layer includes one or more of the hole injection layer, the hole transport layer, the charge generation layer, the hole blocking layer, the electron transport layer, and the electron injection layer.

17. The display panel according to claim 1, characterized in that, Under the same etching conditions, the etching rate of the first pixel definition layer is greater than that of the second pixel definition layer.

18. The display panel according to claim 17, characterized in that, The first pixel definition layer is made of negative material, and the second pixel definition layer is made of positive material.

19. The display panel according to claim 1, characterized in that, The width of the gap ranges from 2 to 8 μm along the direction from one of the sub-pixels to another adjacent sub-pixel.

20. A method for manufacturing a display panel, characterized in that, include: Provide substrate; Multiple anodes are fabricated, each anode corresponding to a sub-pixel; A first pixel definition layer is created, the first pixel definition layer is patterned, and a plurality of first openings are formed, the first openings exposing a portion of the anode; A second pixel definition layer is fabricated, and the second pixel definition layer is patterned to form a plurality of second openings. The orthographic projection of the second openings on the substrate at least partially overlaps with the orthographic projection of the first openings on the substrate. The transmittance of the first pixel definition layer is less than that of the second pixel definition layer. A partition is fabricated, the partition being located between two adjacent sub-pixels, and in a direction perpendicular to the plane of the substrate, the partition includes a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least a portion of the first pixel definition layer, the first sub-partition and the second sub-partition communicating to form the partition. At the junction of the first sub-partition and the second sub-partition, along the direction from one of the sub-pixels to the other adjacent sub-pixel, the second sub-partition protrudes towards the sub-pixel relative to the first sub-partition; A light-emitting layer is fabricated, at least a portion of which is located within a first opening on the side of the second pixel definition layer away from the substrate; the light-emitting layer includes a common layer that is interrupted at the partition opening; A cathode layer is fabricated, wherein the cathode layer is isolated at the partition opening.

21. The method for manufacturing a display panel according to claim 20, characterized in that, Within the partition, the cathode layer comprises only one slit along the direction from one of the sub-pixels to its adjacent sub-pixel.

22. The method for manufacturing a display panel according to claim 20, characterized in that, The first pixel definition layer includes negative material, and the second pixel definition layer includes positive material; Under the same etching conditions, the etching rate of the first pixel definition layer is greater than that of the second pixel definition layer.

23. The method for manufacturing a display panel according to claim 22, characterized in that, Creating the first pixel definition layer, patterning the first pixel definition layer, also includes: A third opening is formed, which is located between two adjacent first openings, and the third opening at least partially penetrates the thickness of the first pixel definition layer.

24. The method for manufacturing a display panel according to claim 23, characterized in that, Creating a second pixel definition layer and patterning the second pixel definition layer further includes: at least a portion of the second pixel definition layer filling the third opening; The construction of the partition includes: A mask is provided, the opening of the mask being located between two adjacent sub-pixels; the second pixel definition layer and the first pixel definition layer are etched at the same etching rate; wherein, in a direction perpendicular to the plane of the substrate, one side of the opening of the mask is located inside the third opening, and the other side of the opening of the mask is located outside the third opening; A first sub-separation is formed between two adjacent sub-pixels of the second pixel definition layer, and a second sub-separation is formed between two adjacent sub-pixels of the first pixel definition layer. The first sub-separation and the second sub-separation are connected in a direction perpendicular to the plane of the substrate. The second sub-partition exposes a portion of the first surface of the second pixel definition layer, wherein the first surface refers to the surface of the second pixel definition layer facing the first pixel definition layer.

25. A display device, characterized in that, Includes the display panel as described in any one of claims 1-19.

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