Multi-logic-layer superconducting integrated circuit and preparation method thereof

Abstract

The invention provides a multi-logic-layer superconducting integrated circuit and a preparation method thereof, the circuit comprises a substrate, n logic layers and n current bias layers, each logic layer comprises a Josephson junction used for storage and / or logic operation, and the current bias layers with the same n value are electrically connected with the logic layers, and bias current is provided for the correspondingly arranged logic layer through the current bias layer. The multi-logic-layer superconducting integrated circuit is arranged in the vertical direction, vertical signal connection is carried out through the through holes, the higher integration level can be achieved, the signal path can be shortened, and delay can be reduced; furthermore, the arrangement of the grounding layer can effectively shield electromagnetic interference, and the performance and reliability of the circuit are improved. Therefore, the invention provides the multi-logic-layer superconducting integrated circuit which is efficient in integration and excellent in performance.

Description

Technical Field

[0001] The invention belongs to the technical field of superconducting electronics and relates to a multi-logic layer superconducting integrated circuit and a preparation method thereof. Background Art

[0002] Rapid Single Flux Quantum (RSFQ) technology is an emerging superconducting digital logic technology that uses the presence or absence of magnetic flux quanta in a superconducting circuit loop as a digital signal carrier. The basic device that constitutes the SFQ circuit is the Josephson Junction (JJ). The switching speed of the JJ can reach the picosecond level and the energy consumed by the switch is extremely low. The ultra-high frequency (~770GHz) and extremely low power consumption (~nW / gate) characteristics of the superconducting SFQ circuit are due to this. x The JJ integration scale of superconducting SFQ circuits with Nb / Nb Josephson junctions is limited to 10 6 JJs / cm 2 , which is 5 orders of magnitude different from the transistor integration scale of CMOS digital integrated circuits. In order to face the future large-scale high-performance superconducting circuit applications, especially in the fields of artificial intelligence and large-scale model computing, it is imperative to increase the scale of superconducting integrated circuits.

[0003] The main ideas for improving the integration scale of superconducting circuits are as follows:

[0004] 1. Reduce the feature size in the process preparation, such as the line width and line spacing of metal lines, and the opening size of the insulating layer. This is often limited by the process equipment and lithography accuracy, and it is difficult to make a big breakthrough.

[0005] 2. Increase the critical current of the Josephson junction to make it a self-shunted junction. The SIS (superconducting-insulating-superconducting) Josephson junction without external parallel resistance has hysteresis. Only a JJ without hysteresis can ensure the normal operation of the SFQ circuit. The hysteresis of the JJ can be determined by the damping coefficient β c =2π(I c R N ) 2 C s / Φ0J c Characterization, β c ≤1 means JJ is in an overdamped state without hysteresis, β c >1 indicates that JJ is in an underdamped state with hysteresis. From the damping coefficient formula, it can be seen that in order to make JJ reach an overdamped state without hysteresis, a resistor is often needed to suppress the damping coefficient, but it can also be achieved by increasing the critical current density (J c ) to suppress hysteresis. However, the preparation of high quality high Jc The Josephson junction requires extremely high process stability and controllability, and it is often difficult to meet such high requirements.

[0006] 3. Use high resistance and high inductance layers to reduce the unit size. The SFQ unit circuit is mainly composed of two parts: the overdamped Josephson junction of the parallel resistor and the superconducting inductor connected to the Josephson junction. Therefore, the resistor and inductor occupy a large area of ​​the unit circuit. Increasing the square resistance or square inductance value can reduce the unit size, but it will reduce the uniformity of small resistance or inductance.

[0007] 4. Increase the number of wiring layers. The conventional method is to add more passive transmission line (PTL) transmission layers.

[0008] In advanced superconducting integrated circuits, there are many active and passive components including millions of Josephson junctions, resistors and inductors. The number of Josephson junctions on each chip has exceeded 10 million and is expected to increase to more than 100 million in the next few years. Superconducting logic units are mainly composed of these components and must be connected through signal transmission units to form superconducting logic circuits. As the integration scale of superconducting SFQ circuits increases and the functions become more complex, the demand for efficient interconnection systems has increased dramatically. One solution is to arrange multi-layer wiring above the device. The multi-layer wiring scheme reduces the average length of the connection between devices, which significantly reduces the signal processing delay and improves the circuit performance. There are two main types of signal transmission units in superconducting circuits: Josephson transmission line (JTL) and passive transmission line (PTL). At present, the integrated process structure of superconducting SFQ circuits commonly used at home and abroad is based on single-layer logic and multi-layer PTL wiring. PTL is inherently more suitable for long-distance transmission. PTL cannot perform timing adjustment, but for large-scale superconducting circuits, complex timing adjustment is inevitable. At the same time, the conventional single-layer JTL wiring method can only be used for winding wiring in the two-dimensional plane where the logic unit is located, which occupies a large area, but its unique advantage is that it can adjust the timing of the logic circuit. In the heterogeneous wiring scheme currently being developed, the wiring unit uses a uniform size of unshunted Josephson junctions, and each wiring unit is equipped with at least one large inductor greater than 500pH to effectively suppress the redistribution of bias current. This design occupies a large amount of layout area; in addition, other key wiring units, such as splitters and drivers, need to use shunted Josephson junctions and bias resistors of different sizes, so these units can only be placed in the lower logic layer, which to a certain extent limits the integration scale of superconducting circuits; further, signal transmission depends on the transmission from the logic layer port to the wiring layer through the vertical through-hole. This process uses a large number of upper and lower layer connection through-holes, which increases the complexity and difficulty of process preparation.

[0009] Therefore, developing a new type of superconducting integrated circuit and its preparation method to improve the integration scale of superconducting integrated circuits is a difficult problem that researchers in this field urgently need to solve. Summary of the invention

[0010] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a multi-logic layer superconducting integrated circuit and a method for manufacturing the same, so as to solve the problem of the limitation of the integration degree of the superconducting integrated circuit in the prior art.

[0011] To achieve the above-mentioned object and other related objects, the present invention provides a multi-logic layer superconducting integrated circuit, the multi-logic layer superconducting integrated circuit comprising:

[0012] substrate;

[0013] A logic stack, the logic stack is located on the substrate and is composed of n logic layers stacked and electrically connected from bottom to top, each of the logic layers having a Josephson junction for storage and / or logic operation;

[0014] The current bias stack is composed of n stacked current bias layers from bottom to top, and the current bias layers with the same value of n are electrically connected to the logic layer to provide bias current for the corresponding logic layer through the current bias layer.

[0015] Optionally, n>1 and is an integer.

[0016] Optionally, the logic layer also includes a resistor, and the resistor includes a parallel resistor connected in parallel with the Josephson junction in the logic layer for storage and / or logic operation; or when the logic layer includes multiple Josephson junctions, the resistor includes a bias resistor for distributing current to multiple Josephson junctions.

[0017] Optionally, each of the logic layers further includes a Josephson transmission line.

[0018] Optionally, a ground layer is further included between adjacent logic layers.

[0019] Optionally, the Josephson junctions in each of the logic layers include Josephson junctions of different types or Josephson junctions with different critical currents.

[0020] The present invention also provides a method for preparing a multi-logic layer superconducting integrated circuit, comprising the following steps:

[0021] providing a substrate;

[0022] Forming a logic stack on the substrate, wherein the logic stack is composed of n logic layers stacked and electrically connected from bottom to top, and each of the logic layers has a Josephson junction for storage and / or logic operation;

[0023] A current bias stack is formed on the logic stack, and the current bias stack is composed of n stacked current bias layers from bottom to top, and the current bias layers with the same value of n are electrically connected to the logic layer to provide bias current for the corresponding logic layer through the current bias layer.

[0024] Optionally, the method further includes forming a resistor in the logic layer, and the resistor includes a parallel resistor connected in parallel with the Josephson junction in the logic layer for storage and / or logic operation; or when the logic layer includes a plurality of Josephson junctions, the resistor includes a bias resistor for distributing current to the plurality of Josephson junctions.

[0025] Optionally, the method further includes forming a ground layer between adjacent logic layers.

[0026] Optionally, each of the logic layers further includes a Josephson transmission line.

[0027] As described above, the multi-logic layer superconducting integrated circuit and its preparation method of the present invention include a substrate, n logic layers and n current bias layers, each logic layer includes a Josephson junction for storage and / or logical operation, and the current bias layers with the same value of n are electrically connected to the logic layer to provide bias current for the correspondingly set logic layer through the current bias layer.

[0028] The multi-logic layer superconducting integrated circuit of the present invention is arranged vertically, and vertical signal connection is performed through through holes, which can achieve higher integration, shorten the signal path, and reduce delay; further, the setting of the ground layer can also effectively shield electromagnetic interference and improve the performance and reliability of the circuit. Therefore, the present invention provides a multi-logic layer superconducting integrated circuit with efficient integration and superior performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 to Figure 14 Shown is a schematic diagram of the structure of each step in the preparation process of a multi-logic layer superconducting integrated circuit according to an embodiment of the present invention.

[0030] Fig.15 Shown is a schematic diagram of the circuit structure of a multi-logic layer superconducting integrated circuit in an embodiment of the present invention.

[0031] Description of Reference Numerals

[0032] 100 Substrate

[0033] 101 resistance material layer

[0034] 102 first insulating material layer

[0035] 103 First opening

[0036] 104 First superconducting material layer

[0037] 105 Barrier material layer

[0038] 106 Second superconducting material layer

[0039] 107 second insulating material layer

[0040] 108 Second opening

[0041] 109 Third opening

[0042] 110 Third superconducting material layer

[0043] 111 third insulating material layer

[0044] 112 Fourth opening

[0045] 113 Fourth superconducting material layer

[0046] 114 fourth insulating material layer

[0047] 115 Fifth opening

[0048] 116 Fifth superconducting material layer

[0049] 117 fifth insulating material layer DETAILED DESCRIPTION

[0050] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0052] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0053] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] This embodiment provides a method for preparing a multi-logic layer superconducting integrated circuit, wherein, referring to Figures 1 to 9 , which illustrates the specific preparation process of the logic 0 layer at the bottom layer, as follows:

[0055] like Figure 1 As shown, first, a substrate 100 is provided.

[0056] Specifically, the substrate 100 may include at least one of a silicon substrate, a silicon oxide substrate, a magnesium oxide substrate, a sapphire substrate and a silicon nitride substrate, but is not limited thereto. Any substrate suitable for preparing a superconducting circuit may be used.

[0057] Then, if Figure 2 As shown, a resistor is formed on the substrate 100 .

[0058] The resistor includes a parallel resistor connected in parallel with the Josephson junction in the logic layer for storage and / or logic operation; or when the logic layer includes multiple Josephson junctions, the resistor includes a bias resistor for distributing current to multiple Josephson junctions.

[0059] As an example, a specific method for forming the resistor may include: first forming a resistor material layer 101 on the substrate 100; then performing photolithography-etching and other process steps on the resistor material layer 101 to achieve patterning of the resistor material layer 101 to obtain the resistor.

[0060] Specifically, the resistance material layer 101 may be a single Mo layer or a MoN layer.x layer, where due to the same thickness of MoN x The layer has a higher square resistance than the Mo layer, so it can be used in circuits with higher process nodes. The thickness of the resistor material layer 101 can be set according to the needs of the size of the specific circuit, and may include 40nm to 100nm, such as 40nm, 60nm, 80nm, 100nm, etc. Of course, the resistor material layer 101 can also be selected as a stacked structure such as a Pd layer and a Ti layer, wherein the Ti layer can be used as an adhesion layer, and the Pd layer can be used as the main resistance layer, so that the substrate 100 can be well adhered to the Pd layer through the Ti layer, wherein the thickness of the Ti layer is relatively thin, preferably 6nm to 20nm, such as 6nm, 10nm, 15nm, 20nm, etc., and the thickness of the Pd layer can be set according to the needs of the specific circuit size, preferably 20nm to 100nm, such as 20nm, 30nm, 50nm, 100nm, etc. In this example, the resistor uses a Mo layer with a thickness of 40nm, but it is not limited to this. The shape and layout of the resistor can be designed according to actual needs.

[0061] Then, if Figure 3 As shown, a patterned first insulating material layer 102 having a first opening 103 is formed on the surface of the structure obtained above, and the first opening 103 exposes the resistor.

[0062] As a specific example method, the first insulating material layer 102 may be formed on the surface of the structure obtained above by using a PECVD process, and then the first insulating material layer 102 may be subjected to photolithography-etching and other process steps to form the first opening 103 to obtain a patterned first insulating material layer 102. The first insulating material layer may be a SiO2 layer, but is not limited thereto, and other materials with better insulating properties may also be used.

[0063] Then, if Figure 4 As shown, a three-layer film structure of a first superconducting material layer 104, a barrier material layer 105, and a second superconducting material layer 106 is sequentially formed on the surface of the structure obtained above; and the three-layer film structure is etched from top to bottom to form a Josephson junction.

[0064] As an example, a specific method of forming the Josephson junction may include:

[0065] The three-layer film structure of the first superconducting material layer 104, the barrier material layer 105 and the second superconducting material layer 106 is prepared in situ in sequence without breaking the vacuum condition by using multi-cavity magnetron sputtering;

[0066] The three-layer film structure is etched from top to bottom using masks with different patterns to form a Josephson junction.

[0067] Specifically, the second superconducting material layer 106 is first subjected to photolithography-etching and other process steps to form the top electrode of the Josephson junction; then the barrier material layer 105 is subjected to photolithography-etching and other process steps to obtain the barrier layer of the Josephson junction; finally, the first superconducting material layer 104 is subjected to photolithography-etching and other process steps to form the bottom electrode of the Josephson junction, and the bottom electrode of the Josephson junction is electrically connected to the resistor. The shapes and layouts of the top electrode of the Josephson junction, the barrier layer of the Josephson junction and the bottom electrode of the Josephson junction can be designed according to actual needs.

[0068] Specifically, the first superconducting material layer 104 may include at least one of a NbN layer and a Nb layer, that is, it may be one of them or a stacked structure consisting of two material layers; similarly, the second superconducting material layer 106 may include at least one of a NbN layer and a Nb layer, that is, it may be one of them or a stacked structure consisting of two material layers. The barrier material layer 105 may be an Al-containing material layer, and the Al-containing material layer may include, for example, an Al layer, AlO x Layer and AlN x At least one of the layers may be one of them, or a stacked structure consisting of two or more Al-containing material layers. In this embodiment, the first superconducting material layer 104 is a Nb layer; the second superconducting material layer 106 is a Nb layer; the barrier material layer 105 is Al-AlO x layer, but is not limited to it.

[0069] Then, if Figure 5-6 As shown, a second insulating material layer 107 having a second opening 108 and a third opening 109 is formed on the surface of the structure obtained above, wherein the second opening 108 exposes the top electrode of the Josephson junction, and the third opening 109 exposes the bottom electrode of the Josephson junction. A third superconducting material layer 110 is formed on the second insulating material layer 107, and the third superconducting material layer 110 is etched to form a wiring layer.

[0070] The specific steps are as follows: Figure 5 As shown, the second insulating material layer 107 is first formed on the surface of the structure obtained above by using a PECVD process; then the second insulating material layer 107 is subjected to a CMP planarization process. Since the thickness of the remaining second insulating material layer 107 on the top electrode of the Josephson junction and the bottom electrode of the Josephson junction after CMP is different, it is necessary to perform two photolithography-etching process steps to achieve the patterning of the second insulating material layer 107 and form the second opening 108 and the third opening 109. The second opening 108 exposes the top electrode of the Josephson junction, and the third opening 109 exposes the bottom electrode of the Josephson junction. Then as Figure 6 As shown, a third superconducting material layer 110 is deposited on the patterned second insulating material layer 107, and then the third superconducting material layer 110 is patterned by photolithography-etching and other process steps to form the wiring layer.

[0071] As an example, the material of the second insulating material layer 107 may be SiO 2 material, but it is not limited thereto, and other materials with better insulating properties may also be used.

[0072] As an example, the material of the third superconducting material layer 110 may be NbN or Nb. Since NbN has a larger square inductance than Nb at the same thickness, NbN can be used in circuits that require a large inductance layer, thereby further improving the integration of superconducting circuits. In this embodiment, the third superconducting material layer 110 uses Nb, but is not limited thereto.

[0073] like Figure 7-Figure 8 As shown, a patterned third insulating material layer 111 having a fourth opening 112 is first formed on the surface of the structure obtained above, the fourth opening 112 exposes the third superconducting material layer 110 (wiring layer), and a fourth superconducting material layer 113 is deposited on the third insulating material layer 111, and the fourth superconducting material layer 113 is etched to form a ground layer (GND).

[0074] The specific steps are as follows: Figure 7 As shown, the third insulating material layer 111 is first formed on the surface of the structure obtained above by using a PECVD process, and then the third insulating material layer 111 is subjected to a CMP planarization process, followed by a photolithography-etching process to pattern the third insulating material layer 111, and the fourth opening 112 is formed to expose the third superconducting material layer 110 (wiring layer); then, as Figure 8 As shown, a fourth superconducting material layer 113 is deposited on the patterned third insulating material layer 111, and then the fourth superconducting material layer 113 is patterned by photolithography-etching and other process steps to form the grounding layer, so as to shield the signal crosstalk between adjacent logic layers through the grounding layer.

[0075] In this embodiment, the ground layer is preferably provided between the logic layers stacked one above the other to shield the signal crosstalk between adjacent logic layers through the ground layer. However, the ground layer may not be provided as required, and no excessive restriction is made here.

[0076] As an example, the material of the third insulating material layer 111 may be SiO 2 material, but it is not limited thereto, and other materials with better insulating properties may also be used.

[0077] As an example, the material of the fourth superconducting material layer 113 may be NbN or Nb. However, since the fourth superconducting material layer 113 is used as the grounding layer, it is necessary to satisfy that the thickness t is greater than twice the London penetration depth of its material. The London penetration depth of NbN is generally greater than 200nm, while the London penetration depth of Nb is about 90nm. In this embodiment, the thickness of the grounding layer is preferably 200nm to 300nm, such as 200nm, 250nm, 300nm, etc. Therefore, in this embodiment, the fourth superconducting material layer 113 is made of Nb.

[0078] like Fig. 9 As shown, a fourth insulating material layer 114 is formed on the surface of the structure obtained above. After the fourth insulating material layer 114 is formed, it is first subjected to CMP planarization treatment to provide a flat surface for the subsequent preparation of the logic layer. The preparation of the logic 0 layer is now completed.

[0079] Then, the above steps are repeated to prepare the logic stack of n layers stacked from bottom to top, and the specific preparation is not described here. Fig.10 The structure of the logic stack when n is 2 is shown as follows: Fig.11 The structure of the logic stack having n logic layers is illustrated.

[0080] Next, see Figure 12 to Figure 14 After preparing n layers of the logic layer, n layers of current bias layers stacked from bottom to top are sequentially prepared on top of the logic stack to form a current bias stack, and the current bias layers with the same value of n are electrically connected to the logic layer to provide bias current for the corresponding logic layer through the current bias layer.

[0081] Among them, Fig.15 A schematic diagram of a circuit structure having n logic layers and n corresponding current bias layers is shown. The specific preparation process of the current bias stack may include:

[0082] like Figure 12-13 As shown, a fifth opening 115 corresponding to the logic 0 layer is formed on the surface of the insulating material layer of the logic stack, and the fifth opening 115 exposes the ground layer of the logic 1 layer below.

[0083] like Fig.13 As shown, a fifth superconducting material layer 116 is deposited on top of the patterned insulating material layer, and then the fifth superconducting material layer 116 is patterned by photolithography-etching and other process steps to form a current bias 0 layer for the logic 0 layer, and the current bias 0 layer provides a bias current for the logic 0 layer by opening holes multiple times in succession.

[0084] As an example, the material of the fifth superconducting material layer 116 may be NbN, Nb or other superconducting materials, and different material types may be selected according to different bias allocation requirements. In this example, Nb is used as the current bias layer material.

[0085] like Fig.13 As shown, a fifth insulating material layer 117 is then formed on the surface of the structure obtained above. After the fifth insulating material layer 117 is formed, it is first subjected to a CMP planarization process to provide a flat surface for the subsequent preparation of the current bias layer for other logic layers. At this point, the preparation of the current bias 0 layer is completed, and the current bias 0 layer with the same n value is electrically connected to the logic 0 layer, as shown by the dotted line with an arrow on the right side of the figure, thereby shortening the signal path, reducing delay, and improving integration.

[0086] like Fig.14 As shown, the above preparation of the current bias 0 layer is repeated to prepare the current bias 1 layer corresponding to the logic 1 layer, wherein the current bias 1 layer with the same value of n is electrically connected to the logic 1 layer, as shown by the dotted line with an arrow on the left side of the figure, thereby shortening the signal path, reducing the delay, and improving the integration. The preparation of the current bias 1 layer is not described in detail here.

[0087] It should be noted that the insulating material layers used in the method for preparing a multi-logic layer superconducting integrated circuit of this embodiment can all be kept consistent, so as to achieve homogeneous growth of insulating material layers, and there is no obvious interface during homogeneous growth, which has no effect on subsequent processes. In addition, except for the first insulating material layer 102 of the logic 0 layer, all other insulating material layers to be used in the logic layers are preferably processed by CMP planarization, so as to reduce the process feature size and overcome the problem of thicker films being stacked.

[0088] Fig.14 The multi-logic layer superconducting integrated circuit in the embodiment is a case where n is 2, that is, it has 2 logic layers and 2 current bias layers, but the value of n is not limited thereto. n can be any integer greater than 1 as required, such as 3, 4, 5, 10, etc. Fig.15 A circuit structure diagram of the multi-logic layer superconducting integrated circuit having n≥3 logic layers and n≥3 current bias layers is shown.

[0089] See also Figure 2 to Figure 15 This embodiment also provides a multi-logic layer superconducting integrated circuit, wherein the multi-logic layer superconducting integrated circuit can be prepared by the above-mentioned preparation method, but is not limited thereto. In this embodiment, the multi-logic layer superconducting integrated circuit is directly prepared by the above-mentioned preparation process, so the specific materials and structures of the multi-logic layer superconducting integrated circuit can refer to the above-mentioned preparation method. Specifically, the multi-logic layer superconducting integrated circuit includes:

[0090] Substrate 100;

[0091] A logic stack, the logic stack is located on the substrate 100 and is composed of n logic layers stacked and electrically connected from bottom to top, each of the logic layers having a Josephson junction for storage and / or logic operation;

[0092] The current bias stack is composed of n stacked current bias layers from bottom to top, and the current bias layers with the same value of n are electrically connected to the logic layer to provide bias current for the corresponding logic layer through the current bias layer.

[0093] As an example, n>1 and is an integer, such as n can be 2, 3, 5, 6, 10, etc.

[0094] As an example, the logic layer also includes a resistor, and the resistor includes a parallel resistor connected in parallel with the Josephson junction in the logic layer for storage and / or logic operation; or when the logic layer includes multiple Josephson junctions, the resistor includes a bias resistor for distributing current to multiple Josephson junctions.

[0095] Specifically, the logic layer is responsible for implementing the tasks of processing logic operations and signal transmission in superconducting integrated circuits. In digital circuit design, the logic layer is usually responsible for implementing logic functions, such as basic logic gate operations such as AND, XOR, OR, etc. These logic gates are basic elements for building more complex circuits (such as adders, multipliers, etc.). A parallel resistor for storage and / or logic operations connected in parallel with the Josephson junction in the logic layer may be set in the logic layer; or when the logic layer includes multiple Josephson junctions, the resistor includes a bias resistor for distributing current to multiple Josephson junctions.

[0096] As an example, each of the logic layers further includes a Josephson transmission line (not shown), that is, the logic layer may include the logic layer as a logic circuit layer, and may also be used as a wiring layer. If the logic layer is used as a wiring layer, it can be regarded as a Josephson transmission line (JTL). Of course, a passive transmission line (PTL) may also be provided in the logic layer.

[0097] As an example, a ground layer may be included between adjacent logic layers to effectively shield electromagnetic interference through the ground layer, thereby improving the performance and reliability of the circuit.

[0098] As an example, the Josephson junctions in each of the logic layers include different types of Josephson junctions or Josephson junctions with different critical currents, which can be selected according to needs.

[0099] In summary, the multi-logic layer superconducting integrated circuit and its preparation method of the present invention include a substrate, n logic layers and n current bias layers, each logic layer includes a Josephson junction for storage and / or logical operation, and the current bias layers with the same value of n are electrically connected to the logic layer to provide a bias current for the correspondingly set logic layer through the current bias layer.

[0100] The multi-logic layer superconducting integrated circuit of the present invention is arranged vertically, and vertical signal connection is performed through through holes, which can achieve higher integration, shorten the signal path, and reduce delay; further, the setting of the ground layer can also effectively shield electromagnetic interference and improve the performance and reliability of the circuit. Therefore, the present invention provides a multi-logic layer superconducting integrated circuit with efficient integration and superior performance.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A multi-logic layer superconducting integrated circuit, characterized in that: The multi-logic layer superconducting integrated circuit comprises: substrate; A logic stack, the logic stack is located on the substrate and is composed of n logic layers stacked and electrically connected from bottom to top, each of the logic layers having a Josephson junction for storage and / or logic operation; The current bias stack is composed of n stacked current bias layers from bottom to top, and the current bias layers with the same value of n are electrically connected to the logic layer to provide bias current for the corresponding logic layer through the current bias layer.

2. The multi-logic layer superconducting integrated circuit according to claim 1, characterized in that: n>1 and is an integer.

3. The multi-logic layer superconducting integrated circuit according to claim 1, characterized in that: The logic layer also includes a resistor, and the resistor includes a parallel resistor connected in parallel with the Josephson junction in the logic layer for storage and / or logic operation; or when the logic layer includes multiple Josephson junctions, the resistor includes a bias resistor for distributing current to multiple Josephson junctions.

4. The multi-logic layer superconducting integrated circuit according to claim 1, characterized in that: Each of the logic layers also includes a Josephson transmission line.

5. The multi-logic layer superconducting integrated circuit according to claim 1, characterized in that: A ground layer is also included between adjacent logic layers.

6. The multi-logic layer superconducting integrated circuit according to claim 1, characterized in that: The Josephson junctions in each of the logic layers include Josephson junctions of different types or Josephson junctions with different critical currents.

7. A method for preparing a multi-logic layer superconducting integrated circuit, characterized in that: The following steps are involved: providing a substrate; Forming a logic stack on the substrate, wherein the logic stack is composed of n logic layers stacked and electrically connected from bottom to top, and each of the logic layers has a Josephson junction for storage and / or logic operation; A current bias stack is formed on the logic stack, and the current bias stack is composed of n stacked current bias layers from bottom to top, and the current bias layers with the same value of n are electrically connected to the logic layer to provide bias current for the corresponding logic layer through the current bias layer.

8. The method for preparing a multi-logic layer superconducting integrated circuit according to claim 7, characterized in that: The method also includes forming a resistor in the logic layer, wherein the resistor includes a parallel resistor connected in parallel with the Josephson junction in the logic layer for storage and / or logic operation; or when the logic layer includes a plurality of Josephson junctions, the resistor includes a bias resistor for distributing current to the plurality of Josephson junctions.

9. The method for preparing a multi-logic layer superconducting integrated circuit according to claim 7, characterized in that: The method also includes the step of forming a ground layer between adjacent logic layers.

10. The method for preparing a multi-logic layer superconducting integrated circuit according to claim 7, characterized in that: Each of the logic layers also includes a Josephson transmission line.

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