Method for manufacturing capacitor structure and capacitor structure

Abstract

The present application discloses a method for manufacturing a capacitor structure and a capacitor structure, belonging to the field of semiconductor technology. The method for manufacturing the capacitor structure includes: providing a first plate layer, an initial dielectric layer, and a second plate layer stacked in sequence; forming a mask layer for defining a first plate on the side of the second plate layer away from the initial dielectric layer; etching the second plate layer to obtain a second plate, the orthographic projection of the second plate on the plane where the mask layer is located is located within the mask layer, and the cross-sectional area of ​​the second plate is smaller than the cross-sectional area of ​​the mask layer; etching the initial dielectric layer and the first plate layer through the mask layer to obtain a first dielectric layer and the first plate. The present application can simplify the manufacturing process and reduce process costs.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a method for manufacturing a capacitor structure and a capacitor structure. Background Art

[0002] The cross-sectional area of ​​the upper plate in a MIM (Metal-Insulator-Metal) capacitor is smaller than that of the lower plate, so the upper plate and the lower plate in the MIM capacitor must be etched separately. The related art first uses a first mask layer defining the upper plate area to etch out the upper plate and the dielectric layer of the MIM capacitor, and then uses a second mask layer defining the lower plate area to etch out the lower plate of the MIM capacitor. The manufacturing process is complex and the process cost is high. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for manufacturing a capacitor structure and a capacitor structure, which can simplify the manufacturing process and reduce the process cost.

[0004] In a first aspect, the present application provides a method for manufacturing a capacitor structure, comprising:

[0005] Providing a first electrode layer, an initial dielectric layer, and a second electrode layer stacked in sequence;

[0006] forming a mask layer for defining a first electrode plate on a side of the second electrode plate layer away from the initial dielectric layer;

[0007] Etching the second electrode layer to obtain a second electrode, wherein the orthographic projection of the second electrode on the plane where the mask layer is located is located within the mask layer, and the cross-sectional area of ​​the second electrode is smaller than the cross-sectional area of ​​the mask layer;

[0008] The initial dielectric layer and the first electrode layer are etched through the mask layer to obtain a first dielectric layer and the first electrode.

[0009] According to the manufacturing method of the capacitor structure of the present application, a mask layer for defining the first electrode plate is first formed on the second electrode plate layer, and then the second electrode plate layer is etched into the second electrode plate, and the orthographic projection of the second electrode plate on the plane where the mask layer is located is located in the mask layer, so that the first electrode plate layer can be etched through the mask layer, and the cross-sectional area of ​​the second electrode plate is smaller than the cross-sectional area of ​​the mask layer, so that the cross-sectional area of ​​the first electrode plate formed by etching the mask layer is larger than the cross-sectional area of ​​the second electrode plate, wherein the second electrode plate does not need to be formed by etching the mask layer, thereby saving masks, simplifying the manufacturing process, and reducing process costs.

[0010] According to one embodiment of the present application, etching the second electrode layer includes:

[0011] The second electrode layer is etched by a wet etching process.

[0012] According to one embodiment of the present application, the wet etching process satisfies at least one of the following characteristics:

[0013] The etching solution includes SCE solution, nitric acid, phosphoric acid or hydrochloric acid;

[0014] The concentration of the etching solution is 20%-80%;

[0015] The etching time is 10s-10min;

[0016] The etching temperature is 25°C-200°C.

[0017] According to an embodiment of the present application, etching the initial dielectric layer and the first electrode layer includes:

[0018] The initial dielectric layer and the first electrode layer are etched by dry etching process.

[0019] According to one embodiment of the present application, the orthographic projection of the second electrode plate on the plane where the mask layer is located is located at the center of the mask layer, the orthographic projection of the second electrode plate on the plane where the first electrode plate is located is located at the center of the first electrode plate, and the edges of the orthographic projection of the second electrode plate on the plane where the first electrode plate is located are at the same distance from the corresponding edges of the first electrode plate.

[0020] According to an embodiment of the present application, after etching the initial dielectric layer and the first electrode layer, the method further includes:

[0021] The mask layer is removed.

[0022] According to one embodiment of the present application, the method further includes:

[0023] forming a second dielectric layer covering the second electrode plate and the first dielectric layer;

[0024] A first contact structure and a second contact structure are formed, wherein the first contact structure penetrates the second dielectric layer and the first dielectric layer and is connected to the first electrode plate, and the second contact structure penetrates the second dielectric layer and is connected to the second electrode plate.

[0025] According to one embodiment of the present application, the first electrode plate and the second electrode plate respectively include at least one of aluminum and tantalum nitride.

[0026] In a second aspect, the present application provides a capacitor structure, comprising:

[0027] A first plate;

[0028] A first dielectric layer is located on one side of the first electrode plate, and an orthographic projection of the first dielectric layer on the plane where the first electrode plate is located coincides with the first electrode plate;

[0029] The second electrode plate is located on the side of the first dielectric layer away from the first electrode plate, the orthographic projection of the second electrode plate on the plane where the first electrode plate is located is located inside the first electrode plate, and the cross-sectional area of ​​the second electrode plate is smaller than the cross-sectional area of ​​the first electrode plate.

[0030] According to one embodiment of the present application, the orthographic projection of the second electrode plate on the plane where the first electrode plate is located is located at the center of the first electrode plate, and the distance between each edge of the orthographic projection of the second electrode plate on the plane where the first electrode plate is located and the corresponding edge of the first electrode plate is the same.

[0031] According to one embodiment of the present application, the capacitor structure further includes:

[0032] a second dielectric layer, covering the second electrode plate and the first dielectric layer;

[0033] a first contact structure, penetrating the second dielectric layer and the first dielectric layer and connected to the first electrode plate;

[0034] The second contact structure penetrates the second dielectric layer and is connected to the second electrode plate.

[0035] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0036] First, a mask layer for defining the first electrode plate is formed on the second electrode plate layer, and then the second electrode plate layer is etched into the second electrode plate, and the orthographic projection of the second electrode plate on the plane where the mask layer is located is located in the mask layer, so that the first electrode plate layer can be etched through the mask layer, and the cross-sectional area of ​​the second electrode plate is smaller than the cross-sectional area of ​​the mask layer, so that the cross-sectional area of ​​the first electrode plate formed by etching the mask layer is larger than the cross-sectional area of ​​the second electrode plate, wherein the second electrode plate does not need to be formed by etching the mask layer, thereby saving masks, simplifying the manufacturing process, and reducing the process cost.

[0037] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0039] Figure 1 is a schematic diagram of a process for manufacturing a capacitor structure provided in an embodiment of the present application;

[0040] Figure 2 It is one of the structural schematic diagrams of the method for manufacturing a capacitor structure provided in an embodiment of the present application;

[0041] Figure 3 This is the second structural schematic diagram of the method for manufacturing a capacitor structure provided in an embodiment of the present application;

[0042] Figure 4 This is the third structural schematic diagram of the method for manufacturing a capacitor structure provided in an embodiment of the present application;

[0043] Figure 5 This is the fourth structural schematic diagram of the method for manufacturing a capacitor structure provided in an embodiment of the present application;

[0044] Figure 6 This is the fifth structural diagram of the method for manufacturing a capacitor structure provided in an embodiment of the present application;

[0045] Figure 7 It is a structural schematic diagram of the capacitor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0047] The following describes the manufacturing method and capacitor structure of the capacitor structure provided by the embodiment of the present application with reference to the accompanying drawings. The capacitor structure may be a MIM capacitor structure or other parallel plate capacitor structure, which is not specifically limited here.

[0048] Figure 1 A schematic diagram of a process for manufacturing a capacitor structure provided in an embodiment of the present application.

[0049] like Figure 1 As shown, the method for manufacturing a semiconductor device provided in an embodiment of the present application includes steps 110 to 140.

[0050] Step 110 , providing a first electrode layer, an initial dielectric layer, and a second electrode layer stacked in sequence.

[0051] Combination Figure 2 As shown, a substrate 1 is first provided. In some embodiments, the substrate 1 may include a substrate and an insulating layer, and the insulating layer is located on one side of the thickness direction of the substrate. The substrate may be a silicon substrate or a semiconductor substrate including other elements. The insulating layer may include one or more combinations of silicon oxide and silicon nitride.

[0052] Then, a thin film deposition process is used to form a first electrode layer 2 on one side of the substrate 1 in the thickness direction. For example, the first electrode layer is located on the side of the insulating layer away from the substrate. The thin film deposition process may be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, etc. The first electrode layer 2 may include one or more combinations of tantalum nitride and aluminum.

[0053] Then, a thin film deposition process is used to form an initial dielectric layer 3 on the side of the first electrode layer 2 facing away from the substrate 1. The initial dielectric layer 3 may include silicon oxide or silicon nitride.

[0054] Then, a thin film deposition process is used to form a second electrode layer 4 on a side of the initial dielectric layer 3 away from the first electrode layer 2. The second electrode layer 4 may include one or more combinations of tantalum nitride and aluminum.

[0055] Step 120 , forming a mask layer for defining the first electrode plate on a side of the second electrode plate layer away from the initial dielectric layer.

[0056] Combination Figure 2 As shown, a mask layer 5 is formed on the side of the second electrode layer 4 away from the initial dielectric layer 3. The mask layer 5 is used to define the first electrode, that is, the size and shape of the transverse cross section of the mask layer 5 are the same as the size and shape of the transverse cross section of the first electrode to be formed. The transverse direction is perpendicular to the thickness direction.

[0057] In some embodiments, the mask layer 5 may include a photoresist, which is located on the side of the second electrode layer 4 away from the initial dielectric layer 3. The photoresist 52 is used to define the area of ​​the first electrode, that is, the size and shape of the transverse cross-section of the photoresist 52 are the same as the size and shape of the transverse cross-section of the first electrode to be formed, so that the mask layer 5 defines the area of ​​the first electrode.

[0058] In some embodiments, the mask layer 5 may include a hard mask layer 51 and a photoresist 52. The hard mask layer 51 is located on the side of the second electrode layer 4 away from the initial dielectric layer 3, and the photoresist 52 is located on the side of the hard mask layer 51 away from the second electrode layer 4. The photoresist 52 is used to define the area of ​​the first electrode, that is, the size and shape of the transverse cross section of the photoresist 52 are the same as the size and shape of the transverse cross section of the first electrode to be formed. The hard mask layer 51 is etched by the photoresist 52 so that the size and shape of the transverse cross section of the hard mask layer 51 are the same as the size and shape of the transverse cross section of the first electrode to be formed, so that the mask layer 5 defines the area of ​​the first electrode.

[0059] In some embodiments, the mask layer 5 is located at the center of the second electrode layer 4. The cross-sectional area of ​​the mask layer 5 is smaller than that of the second electrode layer 4, and the orthographic projection of the mask layer 5 on the plane where the second electrode layer 4 is located is located at the center of the second electrode layer 4.

[0060] Step 130 , etching the second electrode layer to obtain a second electrode, wherein the orthographic projection of the second electrode on the plane where the mask layer is located is located within the mask layer, and the cross-sectional area of ​​the second electrode is smaller than the cross-sectional area of ​​the mask layer.

[0061] Combination Figure 3 As shown, the second electrode layer 4 is directly etched without using a mask layer to obtain a second electrode 4'. The second electrode 4' may include one or more combinations of tantalum nitride and aluminum.

[0062] The orthographic projection of the second electrode plate 4' on the plane where the mask layer 5 is located is located within the mask layer 5, so as to ensure that the first electrode layer 2 can be subsequently etched through the mask layer 5 without affecting the second electrode plate 4'. The cross-sectional area of ​​the second electrode plate 4' is smaller than the cross-sectional area of ​​the mask layer 5, so as to ensure that the cross-sectional area of ​​the first electrode plate 2' obtained by etching the mask layer 5 is larger than the cross-sectional area of ​​the second electrode plate 4'.

[0063] In addition, since the cross-sectional area of ​​the mask layer 5 is larger than that of the second electrode plate 4 ′, the mask layer 5 needs to be formed on the second electrode plate layer 4 before etching the second electrode plate layer 4 , but the mask layer 5 is not used to etch the second electrode plate layer 4 .

[0064] In some embodiments, etching the second electrode layer in step 130 includes:

[0065] The second electrode layer is etched by a wet etching process.

[0066] The second electrode layer 4 is wet-etched without using a mask layer to obtain the second electrode 4'. The second electrode layer 4 is etched into a second electrode 2' of a desired size and shape by controlling the etching solution concentration, etching time and etching temperature in the wet etching process.

[0067] In some embodiments, the wet etching process satisfies at least one of the following characteristics:

[0068] The etching solution includes SCE solution, nitric acid, phosphoric acid or hydrochloric acid;

[0069] The concentration of the etching solution is 20%-80%;

[0070] The etching time is 10s-10min;

[0071] The etching temperature is 25°C-200°C.

[0072] By controlling the process parameters in the wet etching process, the second electrode layer 4 is wet-etched, and the cross-sectional area of ​​the obtained second electrode 4 ′ is smaller than the cross-sectional area of ​​the mask layer 5 .

[0073] In some embodiments, the orthographic projection of the second electrode plate 4 ′ on the plane where the mask layer 5 is located is located at the center of the mask layer 5 .

[0074] Wet etching has isotropic characteristics, and the second electrode layer 4 is uniformly etched in all directions by using a wet etching process. The mask layer 5 is located at the center of the second electrode layer 4, so that the second electrode 4' obtained by uniformly etching the second electrode layer 4 in all directions is located at the center of the mask layer 5, that is, the orthographic projection of the second electrode 4' on the plane where the mask layer 5 is located is located at the center of the mask layer 5, and the edges of the orthographic projection of the second electrode 4' on the plane where the mask layer 5 is located are at the same distance from the corresponding edges of the mask layer 5. For example, the second electrode 4' and the mask layer 5 are both rectangular, and the four edges of the orthographic projection (rectangular) of the second electrode 4' on the plane where the mask layer 5 is located are arranged in parallel with the four edges of the mask layer 5 in a one-to-one correspondence, and the four edges of the orthographic projection of the second electrode 4' on the plane where the mask layer 5 is located are at the same distance from the four corresponding edges of the mask layer 5.

[0075] Step 140 , etching the initial dielectric layer and the first electrode layer through the mask layer to obtain a first dielectric layer and a first electrode.

[0076] After the second electrode layer 4 is etched into the second electrode 4', the initial dielectric layer 3 is exposed. Moreover, the cross-sectional area of ​​the second electrode 4' is smaller than the cross-sectional area of ​​the mask layer 5. Figure 4 As shown, the initial dielectric layer 3 and the first electrode layer 2 can be etched through the mask layer 5 to etch the initial dielectric layer 3 into the first dielectric layer 3', and the first electrode layer 2 into the first electrode 2'. The first dielectric layer 3' can include silicon oxide or silicon nitride, etc., and the first electrode 2' can include one or more combinations of tantalum nitride and aluminum.

[0077] In some embodiments, etching the initial dielectric layer and the first electrode layer in step 140 includes:

[0078] The initial dielectric layer and the first electrode layer are etched by dry etching process.

[0079] The mask layer 5 is used and a dry etching process is used to etch the initial dielectric layer 3 into the first dielectric layer 3' and the first electrode layer 2 into the first electrode 2', thereby effectively improving the etching accuracy of the first electrode 2'.

[0080] The orthographic projection of the first electrode plate 2' on the plane where the mask layer 5 is located coincides with the mask layer 5, and the size and shape of the transverse cross section of the first electrode plate 2' are the same as the size and shape of the transverse cross section of the mask layer 5. The orthographic projection of the first dielectric layer 3' on the plane where the mask layer 5 is located coincides with the mask layer 5, and the size and shape of the transverse cross section of the first dielectric layer 3' are the same as the size and shape of the transverse cross section of the mask layer 5. The first electrode plate 2' coincides with the first dielectric layer 3', and the size and shape of the transverse cross section of the first electrode plate 2' may be the same as the size and shape of the transverse cross section of the first dielectric layer 3'.

[0081] The cross-sectional area of ​​the second electrode plate 4' is smaller than the cross-sectional area of ​​the first electrode plate 2', and the orthographic projection of the second electrode plate 4' on the plane where the first electrode plate 2' is located is located inside the first electrode plate 2'. The cross-sectional area of ​​the second electrode plate 4' is smaller than the cross-sectional area of ​​the first dielectric layer 3', and the orthographic projection of the second electrode plate 4' on the plane where the dielectric layer 3' is located is located inside the first dielectric layer 3'.

[0082] The first plate 2' can be used as the lower plate of the capacitor, the second plate 4' can be used as the upper plate of the capacitor, and the first plate 2', the second plate 4' and the first dielectric layer 3' therebetween constitute a capacitor.

[0083] In some embodiments, the orthographic projection of the second electrode plate 4' on the plane where the first electrode plate 2' is located is located at the center of the first electrode plate 2', and the spacing between the edges of the orthographic projection of the second electrode plate 4' on the plane where the first electrode plate 2' is located and the corresponding edges of the first electrode plate 2' are the same. For example, the second electrode plate 4' and the first electrode plate 2' are both rectangular, and the four edges of the orthographic projection (rectangular) of the second electrode plate 4' on the plane where the first electrode plate 2' is located are arranged in parallel with the four edges of the first electrode plate 2', and the spacing between the four edges of the orthographic projection of the second electrode plate 4' on the plane where the first electrode plate 2' is located and the four corresponding edges of the first electrode plate 2' are the same.

[0084] The orthographic projection of the second electrode plate 4' on the plane where the first dielectric layer 3' is located is located in the middle position of the first dielectric layer 3', and the spacing between the edges of the orthographic projection of the second electrode plate 4' on the plane where the first dielectric layer 3' is located and the corresponding edges of the first dielectric layer 3' are the same. For example, the second electrode plate 4' and the first dielectric layer 3' are both rectangular, and the four edges of the orthographic projection (rectangular) of the second electrode plate 4' on the plane where the first dielectric layer 3' is located are arranged in parallel with the four edges of the first dielectric layer 3' in a one-to-one correspondence, and the four edges of the orthographic projection of the second electrode plate 4' on the plane where the first dielectric layer 3' is located are the same as the spacing between the four edges of the corresponding four edges of the first dielectric layer 3'.

[0085] In this embodiment, the second electrode layer 4 is wet-etched without using a mask layer, which saves masks, simplifies the manufacturing process, and reduces the process cost.

[0086] In some embodiments, after etching the initial dielectric layer and the first electrode layer in step 140, the process further includes:

[0087] The mask layer is removed.

[0088] Combination Figure 5 As shown, after etching to form the first dielectric layer 3' and the first electrode plate 2', the mask layer 5 is removed to expose the second electrode plate 4'.

[0089] In some embodiments, the method for manufacturing the capacitor structure further includes:

[0090] forming a second dielectric layer covering the second electrode plate and the first dielectric layer;

[0091] forming a first contact structure and a second contact structure, wherein the first contact structure penetrates the second dielectric layer and the first dielectric layer and is connected to the first electrode plate, and the second contact structure penetrates the second dielectric layer and is connected to the second electrode plate;

[0092] A metal connection line is formed on a side of the second dielectric layer away from the second electrode plate, and the metal connection line is respectively connected to the first contact structure and the second contact structure.

[0093] Combination Figure 6 As shown, after etching to form the first electrode 2', a thin film deposition process can be used to form a second dielectric layer 6. The second dielectric layer 6 covers the upper surface of the substrate 1 not covered by the first electrode 2', the upper surface of the first dielectric layer 3' not covered by the second electrode 4', and the upper surface of the second electrode 4', and the upper surface of the second dielectric layer 6 is a plane. The second dielectric layer 6 includes one or more combinations of silicon oxide and silicon nitride.

[0094] Then, an etching process is used to form a first contact hole and a second contact hole. The first contact hole is located on the peripheral side of the second electrode plate 4' and above the first electrode plate 2', and penetrates the second dielectric layer 6 and the first dielectric layer 3', exposing a portion of the first electrode plate 2'. The second contact hole is located above the second electrode plate 4' and penetrates the second dielectric layer 6, exposing a portion of the second electrode plate 4'.

[0095] Then, a first contact structure 7 is formed in the first contact hole, the first contact structure 7 penetrates the second dielectric layer 6 and the first dielectric layer 3', and contacts the first electrode plate 2', so that the first contact structure 7 is connected to the first electrode plate 2'. A second contact structure 8 is formed in the second contact hole, the second contact structure 8 penetrates the second dielectric layer 6, and contacts the second electrode plate 4', so that the second contact structure 8 is connected to the second electrode plate 2'. The first contact structure 7 and the second contact structure 8 may respectively include metals such as copper, aluminum, and tungsten.

[0096] In some embodiments, the method for manufacturing the capacitor structure further includes:

[0097] A wiring layer is formed on a side of the second dielectric layer away from the second electrode plate, and the wiring layer is connected to the first contact structure and the second contact structure respectively.

[0098] Combination Figure 7 As shown, a thin film deposition process is used to form a wiring layer 9 on the side of the second dielectric layer 6 facing away from the substrate 1. The wiring layer 9 may include a first wiring and a second wiring, and the first wiring may be connected to the first contact structure 7, so that the first wiring is connected to the first electrode 2' through the first contact structure 7, that is, the first electrode 2' can be led out through the first contact structure 7 and the first wiring. The second wiring may be connected to the second contact structure 8, so that the second wiring is connected to the second electrode 4' through the second contact structure 8, that is, the second electrode 4' can be led out through the second contact structure 8 and the second wiring. Among them, the wiring layer 9 may include metals such as copper and aluminum.

[0099] It should be noted that the capacitor structure in this embodiment can be applied to electronic devices such as memory, filter and oscillator.

[0100] In summary, according to the manufacturing method of the capacitor structure provided in the embodiment of the present application, a mask layer 5 for defining the first electrode plate 2' is first formed on the second electrode layer 4, and then the second electrode layer 4 is etched into the second electrode plate 4', and the orthographic projection of the second electrode plate 4' on the plane where the mask layer 5 is located is located in the mask layer 5, so that the first electrode layer 2 is etched through the mask layer 5, and the cross-sectional area of ​​the second electrode plate 4' is smaller than the cross-sectional area of ​​the mask layer 5, so that the cross-sectional area of ​​the first electrode plate 2' formed by etching the mask layer 5 is larger than the cross-sectional area of ​​the second electrode plate 4', wherein the second electrode plate 4' does not need to be formed by etching the mask layer, saving masks, simplifying the manufacturing process, and reducing process costs.

[0101] Correspondingly, an embodiment of the present application further provides a capacitor structure that can be manufactured using the manufacturing method of the capacitor structure in the above embodiment.

[0102] like Figure 5 As shown, the capacitor structure provided in the embodiment of the present application includes a first electrode plate 2', a first dielectric layer 3' and a second electrode plate 4'.

[0103] The first electrode plate 2' may be a lower electrode plate of the capacitor. The first electrode plate 2' may include one or more combinations of tantalum nitride and aluminum.

[0104] The first dielectric layer 3' is located on one side of the first electrode plate 2', and the orthographic projection of the first dielectric layer 3' on the plane where the first electrode plate 2' is located coincides with the first electrode plate 2'. The size and shape of the transverse cross section of the first electrode plate 2' can be the same as the size and shape of the transverse cross section of the first dielectric layer 3'. The first dielectric layer 3' can include silicon oxide or silicon nitride.

[0105] The second electrode plate 4' is located on the side of the first dielectric layer 3' away from the first electrode plate 2', the orthographic projection of the second electrode plate 4' on the plane where the first electrode plate 2' is located is located inside the first electrode plate 2', and the cross-sectional area of ​​the second electrode plate 4' is smaller than the cross-sectional area of ​​the first electrode plate 2'. The cross-sectional area of ​​the second electrode plate 4' is smaller than the cross-sectional area of ​​the first dielectric layer 3', and the orthographic projection of the second electrode plate 4' on the plane where the dielectric layer 3' is located is located inside the first dielectric layer 3'. The second electrode plate 4' may include one or more combinations of tantalum nitride and aluminum.

[0106] The second electrode plate 4' can be used as an upper electrode plate of a capacitor, and the first electrode plate 2', the second electrode plate 4' and the first dielectric layer 3' therebetween constitute a capacitor.

[0107] In this embodiment, the second electrode 4 ′ does not need to be formed by etching the mask layer, which saves masks, simplifies the manufacturing process, and reduces the process cost.

[0108] In some embodiments, the orthographic projection of the second electrode plate 4' on the plane where the first electrode plate 2' is located is located at the center of the first electrode plate 2', and the spacing between the edges of the orthographic projection of the second electrode plate 4' on the plane where the first electrode plate 2' is located and the corresponding edges of the first electrode plate 2' are the same. For example, the second electrode plate 4' and the first electrode plate 2' are both rectangular, and the four edges of the orthographic projection (rectangular) of the second electrode plate 4' on the plane where the first electrode plate 2' is located are arranged in parallel with the four edges of the first electrode plate 2', and the spacing between the four edges of the orthographic projection of the second electrode plate 4' on the plane where the first electrode plate 2' is located and the four corresponding edges of the first electrode plate 2' are the same.

[0109] The orthographic projection of the second electrode plate 4' on the plane where the first dielectric layer 3' is located is located at the center of the first dielectric layer 3', and the spacing between the edges of the orthographic projection of the second electrode plate 4' on the plane where the first dielectric layer 3' is located and the corresponding edges of the first dielectric layer 3' are the same. For example, the second electrode plate 4' and the first dielectric layer 3' are both rectangular, and the four edges of the orthographic projection (rectangular) of the second electrode plate 4' on the plane where the first dielectric layer 3' is located are arranged in parallel with the four edges of the first dielectric layer 3' in a one-to-one correspondence, and the four edges of the orthographic projection of the second electrode plate 4' on the plane where the first dielectric layer 3' is located are the same as the spacing between the four edges of the corresponding four edges of the first dielectric layer 3'.

[0110] In some embodiments, the capacitor structure further comprises:

[0111] The substrate 1 is located on a side of the first electrode plate 2' that is away from the first dielectric layer 3'.

[0112] In some embodiments, the base 1 may include a substrate and an insulating layer, wherein the substrate is located on the side of the first plate 2' away from the first dielectric layer 3', and the insulating layer is located between the substrate and the first plate 2'. The substrate may be a silicon substrate or a semiconductor substrate including other elements. The insulating layer may include one or more combinations of silicon oxide and silicon nitride.

[0113] In some embodiments, Figure 6 As shown, the capacitor structure also includes:

[0114] A second dielectric layer 6, covering the second electrode plate 4' and the first dielectric layer 3';

[0115] A first contact structure 7, penetrating the second dielectric layer 6 and the first dielectric layer 3' and connected to the first electrode plate 2';

[0116] The second contact structure 8 penetrates the second dielectric layer 6 and is connected to the second electrode plate 4 ′.

[0117] The second dielectric layer 6 can cover the upper surface of the substrate 1 not covered by the first electrode 2', the upper surface of the first dielectric layer 3' not covered by the second electrode 4', and the upper surface of the second electrode 4', and the upper surface of the second dielectric layer 6 is a plane. The second dielectric layer 6 includes one or more combinations of silicon oxide and silicon nitride.

[0118] The first contact structure 7 is located around the second electrode plate 4' and above the first electrode plate 2', and penetrates the second dielectric layer 6 and the first dielectric layer 3', and contacts the first electrode plate 2', so that the first contact structure 7 is connected to the first electrode plate 2'. The first contact structure 7 may include metals such as copper, aluminum, and tungsten.

[0119] The second contact structure 8 is located above the second electrode plate 4' and penetrates the second dielectric layer 6 to contact the second electrode plate 4', so that the second contact structure 8 is connected to the second electrode plate 2'. The second contact structure 8 may include metals such as copper, aluminum, and tungsten.

[0120] In some embodiments, in combination Figure 7 As shown, the capacitor structure also includes:

[0121] The wiring layer 9 is located on the side of the second dielectric layer 6 away from the second electrode plate 4 ′ and is connected to the first contact structure 7 and the second contact structure 8 respectively.

[0122] The wiring layer 9 may include a first wiring and a second wiring. The first wiring may be connected to the first contact structure 7, so that the first wiring is connected to the first electrode 2' through the first contact structure 7, that is, the first electrode 2' may be led out through the first contact structure 7 and the first wiring. The second wiring may be connected to the second contact structure 8, so that the second wiring is connected to the second electrode 4' through the second contact structure 8, that is, the second electrode 4' may be led out through the second contact structure 8 and the second wiring. The wiring layer 9 may include metals such as copper and aluminum.

[0123] According to the capacitor structure provided in the embodiment of the present application, the first dielectric layer 3' and the first electrode 2' are formed by etching the mask layer, and the second electrode 4' is formed by wet etching, that is, the second electrode 4' does not need to be formed by etching the mask layer, which saves masks, simplifies the manufacturing process, and reduces the process cost.

[0124] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0125] In the description of the present application, “plurality” means two or more.

[0126] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0127] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for manufacturing a capacitor structure, characterized in that: include: Providing a first electrode layer, an initial dielectric layer, and a second electrode layer stacked in sequence; forming a mask layer for defining a first electrode plate on a side of the second electrode plate layer away from the initial dielectric layer; Etching the second electrode layer to obtain a second electrode, wherein the orthographic projection of the second electrode on the plane where the mask layer is located is located within the mask layer, and the cross-sectional area of ​​the second electrode is smaller than the cross-sectional area of ​​the mask layer; The initial dielectric layer and the first electrode layer are etched through the mask layer to obtain a first dielectric layer and the first electrode.

2. The method for manufacturing a capacitor structure according to claim 1, characterized in that: The etching of the second electrode layer comprises: The second electrode layer is etched by a wet etching process.

3. The method for manufacturing a capacitor structure according to claim 2, characterized in that: The wet etching process satisfies at least one of the following characteristics: The etching solution includes SCE solution, nitric acid, phosphoric acid or hydrochloric acid; The concentration of the etching solution is 20%-80%; The etching time is 10s-10min; The etching temperature is 25°C-200°C.

4. The method for manufacturing a capacitor structure according to claim 1, characterized in that: The etching of the initial dielectric layer and the first electrode layer comprises: The initial dielectric layer and the first electrode layer are etched by dry etching process.

5. The method for manufacturing a capacitor structure according to claim 1, characterized in that: The orthographic projection of the second electrode plate on the plane where the mask layer is located is located at the center of the mask layer, the orthographic projection of the second electrode plate on the plane where the first electrode plate is located is located at the center of the first electrode plate, and the distances between the edges of the orthographic projection of the second electrode plate on the plane where the first electrode plate is located and the corresponding edges of the first electrode plate are the same.

6. The method for manufacturing a capacitor structure according to claim 1, characterized in that: The method further comprises: removing the mask layer; forming a second dielectric layer covering the second electrode plate and the first dielectric layer; A first contact structure and a second contact structure are formed, wherein the first contact structure penetrates the second dielectric layer and the first dielectric layer and is connected to the first electrode plate, and the second contact structure penetrates the second dielectric layer and is connected to the second electrode plate.

7. The method for manufacturing a capacitor structure according to any one of claims 1 to 6, characterized in that: The first electrode plate and the second electrode plate respectively include at least one of aluminum and tantalum nitride.

8. A capacitor structure, characterized in that: include: A first plate; A first dielectric layer is located on one side of the first electrode plate, and an orthographic projection of the first dielectric layer on the plane where the first electrode plate is located coincides with the first electrode plate; The second electrode plate is located on the side of the first dielectric layer away from the first electrode plate, the orthographic projection of the second electrode plate on the plane where the first electrode plate is located is located inside the first electrode plate, and the cross-sectional area of ​​the second electrode plate is smaller than the cross-sectional area of ​​the first electrode plate.

9. The capacitor structure according to claim 8, characterized in that: The orthographic projection of the second electrode plate on the plane where the first electrode plate is located is located at the center of the first electrode plate, and the distances between the edges of the orthographic projection of the second electrode plate on the plane where the first electrode plate is located and the corresponding edges of the first electrode plate are the same.

10. The capacitor structure according to claim 8 or 9, characterized in that: The capacitor structure further includes: a second dielectric layer, covering the second electrode plate and the first dielectric layer; a first contact structure, penetrating the second dielectric layer and the first dielectric layer and connected to the first electrode plate; The second contact structure penetrates the second dielectric layer and is connected to the second electrode plate.

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