Capacitor preparation method

Abstract

The present application discloses a method for preparing a capacitor, which belongs to the field of semiconductor technology. The method comprises: providing a first plate layer, a dielectric layer, and a second plate layer stacked in sequence; forming a first mask layer on the side of the second plate layer away from the dielectric layer; thinning the first mask layer; and etching the second plate layer using the thinned first mask layer. The present application can improve the etching effect of the plate layer, improve the electrical performance and stability of the capacitor, and increase the yield.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a method for preparing a capacitor. Background Art

[0002] In the process of preparing capacitors, when a mask layer is used to etch the plate layer, the mask layer is relatively thick, and the etching byproducts of the plate layer will remain on the sidewalls of the mask layer. The remaining etching byproducts are horn-shaped and difficult to remove, which will affect the etching effect of the plate layer. In addition, the byproducts may fall on the surface of the device, affecting the electrical performance and stability of the capacitor and reducing the yield. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for preparing a capacitor, which can improve the etching effect of the plate layer, improve the electrical performance and stability of the capacitor, and increase the yield.

[0004] The present application provides a method for preparing a capacitor, comprising:

[0005] Providing a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence;

[0006] forming a first mask layer on a side of the second electrode layer away from the dielectric layer;

[0007] performing a thinning process on the first mask layer;

[0008] The second electrode layer is etched using the first mask layer after thinning.

[0009] According to an embodiment of the present application, the thinning process of the first mask layer includes: thinning the first mask layer by a descum process using oxygen and an inert gas.

[0010] According to an embodiment of the present application, after etching the second electrode layer, the method further includes:

[0011] removing the first mask layer;

[0012] forming a second mask layer on a side of the second electrode layer away from the dielectric layer;

[0013] performing a thinning process on the second mask layer;

[0014] Using the thinned second mask layer, etching the dielectric layer and the first electrode layer;

[0015] The second mask layer is removed.

[0016] According to an embodiment of the present application, the thinning process of the second mask layer includes: thinning the second mask layer by a descum process using oxygen and an inert gas.

[0017] According to one embodiment of the present application, the inert gas includes argon; and / or the ratio of the oxygen to the inert gas is 150:50.

[0018] According to an embodiment of the present application, the bias power in the descum process is 40-200W; and / or the source power in the descum process is 700-1300W.

[0019] According to an embodiment of the present application, the first mask layer and the second mask layer are thinned to a thickness of 1000-4000 angstroms respectively.

[0020] According to one embodiment of the present application, the width of the first mask layer is greater than the width of the second electrode layer after etching; and / or the width of the second mask layer is greater than the width of the first electrode layer after etching.

[0021] According to one embodiment of the present application, the first electrode layer includes a first tantalum nitride layer, a metal layer, and a second tantalum nitride layer; the first tantalum nitride layer is located on a side of the dielectric layer away from the second electrode layer, the metal layer is located on a side of the first tantalum nitride layer away from the dielectric layer, and the second tantalum nitride layer is located on a side of the metal layer away from the first tantalum nitride layer.

[0022] According to one embodiment of the present application, the second electrode layer includes a third tantalum nitride layer and an anti-reflection layer; the third tantalum nitride layer is located on the side of the dielectric layer away from the first electrode layer, and the anti-reflection layer is located on the side of the third tantalum nitride layer away from the dielectric layer.

[0023] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0024] By thinning the first mask layer and using the thinned first mask layer to etch the second electrode layer, the adhesion degree of etching byproducts of the second electrode layer to the side wall of the thinned first mask layer is reduced, the etching effect of the second electrode layer is improved, and the risk of etching byproducts falling on the surface of the device is reduced, thereby improving the electrical performance and stability of the capacitor and improving the yield.

[0025] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0027] Figure 1 It is a schematic diagram of a process for preparing a capacitor provided in an embodiment of the present application;

[0028] Figure 2 It is one of the structural schematic diagrams of the method for preparing a capacitor provided in an embodiment of the present application;

[0029] Figure 3 This is the second structural schematic diagram of the method for preparing a capacitor provided in an embodiment of the present application;

[0030] Figure 4 This is the third structural schematic diagram of the method for preparing a capacitor provided in an embodiment of the present application;

[0031] Figure 5 This is the fourth structural schematic diagram of the method for preparing a capacitor provided in an embodiment of the present application;

[0032] Figure 6 This is the fifth structural diagram of the method for preparing a capacitor provided in an embodiment of the present application;

[0033] Figure 7 This is the sixth structural schematic diagram of the method for preparing a capacitor provided in an embodiment of the present application;

[0034] Figure 8 This is one of the scanning electron microscope images of a capacitor in the related art;

[0035] Fig. 9 This is the second scanning electron microscope image of a capacitor in the related art;

[0036] Fig.10 is one of the scanning electron microscope images of the capacitor provided in the embodiment of the present application;

[0037] Fig.11 This is the second scanning electron microscope image of the capacitor provided in the embodiment of the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0039] The following describes a method for preparing a capacitor provided in an embodiment of the present application with reference to the accompanying drawings.

[0040] Figure 1A schematic diagram of a method for preparing a capacitor provided in an embodiment of the present application. The capacitor may include a MIM (Metal-Insulator-Metal) capacitor or other parallel plate capacitors, which are not specifically limited here.

[0041] like Figure 1 As shown, the method for preparing a capacitor provided in the embodiment of the present application includes steps 110 to 140.

[0042] Step 110 , providing a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence.

[0043] In some embodiments, Figure 2 As shown, an insulating layer 4 may be provided first. Then, a first electrode layer 1 is formed on the insulating layer 4 by a thin film deposition process. A dielectric layer 3 is formed on the side of the first electrode layer 1 away from the insulating layer 4 by a thin film deposition process. A second electrode layer 2 is formed on the side of the dielectric layer 3 away from the first electrode layer 1 by a thin film deposition process. The thin film deposition process may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

[0044] Among them, the dielectric layer 3 can isolate the first plate layer 1 from the second plate layer 2 to prevent current short circuit, and the dielectric layer 3 can also serve as an etching stop layer for the second plate layer 2. The insulating layer 4 can isolate the first plate layer 1 from some other film layer structures (for example, a substrate can also be provided below the insulating layer 4, and the insulating layer 4 can isolate the first plate layer 1 from the substrate), and the insulating layer 4 can also serve as an etching stop layer for the first plate layer 1. The first plate layer 1 and the second plate layer 2 can be a single-layer structure or a stacked structure, respectively. The first plate layer 1 and the second plate layer 2 can respectively include one or more combinations of materials such as aluminum and tantalum nitride. The material of the dielectric layer 3 can include silicon nitride, etc. The material of the insulating layer 4 can include silicon nitride, etc.

[0045] Step 120 , forming a first mask layer on a side of the second electrode layer facing away from the dielectric layer.

[0046] like Figure 2 As shown, a coating process is used to form a first mask layer 51 above the second electrode layer 2. Then, the first intermediate structure is placed in the etching cavity, and the first intermediate structure may include an insulating layer 4, a first electrode layer 1, a dielectric layer 3, a second electrode layer 2 and a first mask layer 51. The first mask layer 51 can be used to etch the second electrode layer 2 into a second electrode of a desired size. The material of the first mask layer 51 may include a photoresist, such as an I-line photoresist, etc. The thickness of the first mask layer 51 may be 9000 angstroms.

[0047] Step 130 , thinning the first mask layer.

[0048] In order to prepare the second electrode of the required size, the thickness of the first mask layer 51 is relatively large. However, in the subsequent process of etching the second electrode layer 2 into the second electrode of the required size through the first mask layer 51, etching byproducts will be produced. The etching byproducts adhere to the top of the side wall of the first mask layer 51, which will affect the subsequent etching effect of the second electrode layer 2. In addition, there is a high risk that the etching byproducts will fall on the surface of the device, which will affect the electrical performance, stability and yield of the capacitor. Therefore, if Figure 3 As shown, in this embodiment, the first mask layer 51 is thinned to reduce the adhesion degree of the subsequent etching by-products of the second electrode layer 2 on the side wall of the first mask layer 51, improve the subsequent etching effect of the second electrode layer 2, and reduce the risk of etching by-products falling on the surface of the device, thereby improving the electrical performance and stability of the capacitor and improving the yield.

[0049] In some embodiments, the first mask layer 51 is thinned by performing a descum process and using oxygen and an inert gas to thin the first mask layer 51 .

[0050] First, the descum process is adopted to introduce oxygen and inert gas into the etching chamber. Among them, oxygen is used as the main reaction gas to act on the first mask layer 51. Under the action of radio frequency or microwave, oxygen is ionized into oxygen atoms and chemically reacts with the part of the first mask layer 51 that needs to be removed to generate volatile reaction products (such as water and carbon dioxide, etc.). The inert gas is used as a protective gas to prevent the remaining part of the first mask layer 51 that does not need to be removed from chemically reacting, thereby improving the performance stability of the remaining part of the first mask layer 51. Then, the etching chamber is vacuumed to remove the chemical reaction products generated by the action of oxygen on the part of the first mask layer 51 that needs to be removed. Therefore, under the joint action of oxygen and inert gas in the descum process, part of the first mask layer 51 is removed, thereby achieving the thinning process of the first mask layer 51.

[0051] In some embodiments, the inert gas includes argon. The inert gas has stable chemical properties and can be used as a dilution gas and a protective gas in the descum process to improve the stability of the descum process and achieve precise thinning of the first mask layer 51. The inert gas can also be other inert gases (such as nitrogen, etc.). The selection of the inert gas can be determined according to the needs in the actual application and is not limited here.

[0052] In some embodiments, the ratio of oxygen to inert gas is 150:50. The ratio of oxygen to inert gas may also be other values, and the ratio of oxygen to inert gas may be determined according to factors such as actual process requirements (such as thinning rate, etc.) and the material selection of the first mask layer 51. For example, increasing the proportion of oxygen content can increase the rate of chemical reaction between oxygen and the portion of the first mask layer 51 that needs to be thinned, thereby accelerating the thinning rate of the first mask layer 51 in the descum process.

[0053] In some embodiments, the bias power in the descum process is 40-200W.

[0054] When oxygen and inert gas are introduced into the etching chamber by the descum process to thin the first mask layer 51, a bias power needs to be applied to the first intermediate structure to generate plasma. The bias power is used to control the charged ions in the plasma in the descum process. Increasing the bias power can enhance the bombardment energy of the charged ions on the first mask layer 51, increase the thinning rate of the first mask layer 51, and affect the directionality and selectivity of the thinning.

[0055] It should be noted that the bias power in this embodiment does not exceed 200 W to avoid aggravation of sputtering caused by excessive bias power and poor roughness of the sidewall of the first mask layer 51, thereby avoiding affecting the subsequent preparation of the second electrode plate 2'.

[0056] In some embodiments, the source power in the descum process is 700-1300W.

[0057] When the descum process is adopted and oxygen and inert gas are introduced into the etching chamber to thin the first mask layer 51, the source power needs to be set to excite and maintain the plasma. Increasing the source power can increase the density of the plasma and the rate of generation of charged ions. At the same time, the source power is set between 700-1300W, which can maintain the stability and uniformity of the descum process and improve the uniformity of the thinning process of the first mask layer 51.

[0058] In some embodiments, the first mask layer 51 is thinned to a thickness of 1000-4000 angstroms, that is, the difference in thickness between the first mask layer 51 before and after thinning is 1000-4000 angstroms. The thickness of the first mask layer 51 can be determined according to actual process requirements.

[0059] Step 140: Use the thinned first mask layer to etch the second electrode layer.

[0060] like Figure 3As shown, the second electrode layer 2 is etched by etching the first mask layer 51 after thinning obtained in step 130, and the etching stops at the dielectric layer 3 to obtain the second electrode 2'. The etching process may include dry etching, reactive ion etching, etc.

[0061] When etching the second electrode layer 2, etching byproducts will be generated (for example, when the second electrode layer 2 includes a tantalum nitride layer, etching the second electrode layer 2 will generate etching byproducts containing tantalum). If the thickness of the first mask layer 51 is large, the etching byproducts are likely to adhere to the top of the sidewall of the first mask layer 51. Figure 8 and Fig. 9 As shown ( Figure 8 is a top view, Fig. 9 As shown in the slice diagram, etching byproducts 53 remain on the top of the side wall of the first mask layer 51, and when the first mask layer 51 is ashed and debonded, the remaining etching byproducts 53 are in the shape of horns, and the etching byproducts 53 are not easy to remove, thereby affecting the etching effect of the second electrode layer 2.

[0062] In this embodiment, the first mask layer 51 is thinned to reduce the adhesion of the etching byproducts of the second electrode layer 2 to the sidewall of the first mask layer 51. Fig.10 and Fig.11 As shown ( Fig.10 is a top view, Fig.11 2 is a slice diagram), and no residual etching byproducts are found on the sidewalls of the first mask layer 51 after thinning. This embodiment improves the etching effect of the second electrode layer 2, reduces the risk of etching byproducts falling on the device surface, improves the electrical performance and stability of the second electrode 2', and improves the yield.

[0063] In some embodiments, Figure 2 As shown, the second electrode layer 2 includes a third tantalum nitride layer 21 and an anti-reflection layer 22. The third tantalum nitride layer 21 is located on the side of the dielectric layer 3 away from the first electrode layer 1, and the anti-reflection layer 22 is located on the side of the third tantalum nitride layer 21 away from the dielectric layer 3.

[0064] like Figure 3 As shown, the anti-reflection layer 22 is etched by the first mask layer 51 after the thinning process obtained in step 130, to obtain the anti-reflection pattern layer 22', and then the third tantalum nitride layer 21 is etched to obtain the third tantalum nitride pattern layer 21'. The anti-reflection pattern layer 22' and the third tantalum nitride pattern layer 21' together constitute the second electrode 2'. The material of the anti-reflection layer 22 may include one or more combinations of dielectric materials such as SiN (silicon nitride) and SiON (silicon oxynitride).

[0065] In the process of etching the third tantalum nitride layer 21 and the anti-reflection layer 22, the third tantalum nitride layer 21 generates etching byproducts containing tantalum. In this embodiment, by thinning the first mask layer 51, the adhesion degree of the etching byproducts containing tantalum on the side wall of the first mask layer 51 is reduced, the etching effect of the second electrode 2' is improved, and the risk of the etching byproducts falling on the surface of the device is reduced, thereby improving the electrical performance and stability of the capacitor and improving the yield.

[0066] In some embodiments, Figure 3 As shown, the width of the first mask layer 51 is greater than the width of the second electrode layer 2 after etching.

[0067] In the related art, the width of the mask layer is the same as the width of the electrode of the required size. In order to etch the electrode of the required size, the thickness of the mask layer needs to meet certain requirements. In this embodiment, the first mask layer 51 is thinned. In order to ensure that the second electrode layer 2 can still be etched into the second electrode 2' of the required size through the first mask layer 51 after the thinning process, the width of the first mask layer 51 is greater than the width of the second electrode layer 2 (i.e., the second electrode 2') after etching. The difference in width between the first mask layer 51 and the second electrode 2' can be determined according to the thinned thickness of the first mask layer 51.

[0068] In some embodiments, after etching the second electrode layer 2 in step 140 , the method for preparing the capacitor further includes steps 150 to 190 .

[0069] Step 150: remove the first mask layer.

[0070] like Figure 4 As shown, after etching the second electrode layer 2 to obtain the second electrode 2', a stripping process is used to remove the first mask layer 51 after thinning. The stripping process may include wet stripping or dry stripping, etc. The solvent of the wet stripping may include an organic solvent or an inorganic solvent, and the dry stripping may use plasma to remove the photoresist.

[0071] Step 160 , forming a second mask layer on a side of the second electrode layer away from the dielectric layer.

[0072] like Figure 5 As shown, a coating process is used to form a second mask layer 52 above the second electrode 2' and a portion of the dielectric layer 3. Then, the second intermediate structure is placed in the etching cavity, and the second intermediate structure may include an insulating layer 4, a first electrode layer 1, a dielectric layer 3, a second electrode 2' and a second mask layer 52. The second mask layer 52 can be used to etch the first electrode layer 1 into a first electrode of a desired size. The material of the second mask layer 52 may include photoresist, such as I-line photoresist, etc. The thickness of the second mask layer 52 may be 9000 angstroms.

[0073] Step 170 , thinning the second mask layer.

[0074] In order to prepare the first electrode of the required size, the thickness of the second mask layer 52 is relatively large. However, in the subsequent process of etching the first electrode layer 1 into the first electrode of the required size through the second mask layer 52, etching byproducts will be produced. The etching byproducts adhere to the top of the side wall of the second mask layer 52, which will affect the subsequent etching effect of the first electrode layer 1. In addition, there is a high risk that the etching byproducts will fall on the surface of the device, which will affect the electrical performance, stability and yield of the capacitor. Therefore, if Figure 6 As shown, in this embodiment, the second mask layer 52 is thinned to reduce the degree of adhesion of the subsequent etching by-products of the first electrode layer 1 on the side wall of the second mask layer 52, thereby improving the subsequent etching effect of the first electrode layer 1 and reducing the risk of the etching by-products falling on the surface of the device, thereby improving the electrical performance and stability of the capacitor and improving the yield.

[0075] In some embodiments, the second mask layer 52 is thinned by a descum process using oxygen and an inert gas.

[0076] First, the descum process is adopted to introduce oxygen and inert gas into the etching chamber. Among them, oxygen is used as the main reaction gas to act on the second mask layer 52. Under the action of radio frequency or microwave, oxygen is ionized into oxygen atoms and chemically reacts with the part of the second mask layer 52 that needs to be removed to generate volatile reaction products (such as water and carbon dioxide, etc.). The inert gas is used as a protective gas to prevent the remaining part of the second mask layer 52 that does not need to be removed from chemically reacting, thereby improving the performance stability of the remaining part of the second mask layer 52. Then, the etching chamber is vacuumed to remove the chemical reaction products generated by the oxygen acting on the part of the second mask layer 52 that needs to be removed. Therefore, under the joint action of oxygen and inert gas in the descum process, part of the second mask layer 52 is removed, thereby realizing the thinning process of the second mask layer 52.

[0077] In some embodiments, the inert gas includes argon. The inert gas has stable chemical properties and can be used as a dilution gas and a protective gas in the descum process to improve the stability of the descum process and achieve precise thinning of the second mask layer 52. The inert gas can also be other inert gases (such as nitrogen, etc.). The selection of the inert gas can be determined according to the needs in the actual application and is not limited here.

[0078] In some embodiments, the ratio of oxygen to inert gas is 150:50. The ratio of oxygen to inert gas may also be other values, and the ratio of oxygen to inert gas may be determined according to factors such as actual process requirements (such as thinning rate, etc.) and the material selection of the second mask layer 52. For example, increasing the proportion of oxygen content can increase the rate of chemical reaction between oxygen and the portion of the second mask layer 52 that needs to be thinned, thereby accelerating the thinning rate of the second mask layer 52 in the descum process.

[0079] In some embodiments, the bias power in the descum process is 40-200W.

[0080] When oxygen and inert gas are introduced into the etching chamber by the descum process to thin the second mask layer 52, a bias power needs to be applied to the second intermediate structure to generate plasma. The bias power is used to control the charged ions in the plasma in the descum process. Increasing the bias power can enhance the bombardment energy of the charged ions on the second mask layer 52, increase the thinning rate of the second mask layer 52, and affect the directionality and selectivity of the thinning.

[0081] It should be noted that the bias power in this embodiment does not exceed 200 W to avoid aggravation of the sputtering phenomenon caused by excessive bias power, to avoid poor roughness of the sidewall of the second mask layer 52, and thus to avoid affecting the subsequent preparation of the first electrode plate 1 ′.

[0082] In some embodiments, the source power in the descum process is 700-1300W.

[0083] When the descum process is adopted and oxygen and inert gas are introduced into the etching chamber to thin the second mask layer 52, the source power needs to be set to excite and maintain the plasma. Increasing the source power can increase the density of the plasma and the rate of generation of charged ions. At the same time, the source power is set between 700-1300W, which can maintain the stability and uniformity of the descum process and improve the uniformity of the thinning process of the second mask layer 52.

[0084] In some embodiments, the second mask layer 52 is thinned to a thickness of 1000-4000 angstroms, that is, the difference in thickness between the second mask layer 52 before and after thinning is 1000-4000 angstroms. The thickness of the second mask layer 52 can be determined according to actual process requirements.

[0085] Step 180: Use the thinned second mask layer to etch the dielectric layer and the first electrode layer.

[0086] like Figure 6As shown, the dielectric layer 3 and the first electrode layer 1 are etched by etching process through the thinned second mask layer 52 obtained in step 170, and the etching stops at the insulating layer 4 to obtain the dielectric pattern layer 3' and the first electrode 1'.

[0087] When etching the first electrode layer 1, etching by-products will be produced (for example, when the first electrode layer 1 includes a tantalum nitride layer, etching the first electrode layer 1 will produce etching by-products containing tantalum). If the thickness of the second mask layer 52 is large, the etching by-products are likely to adhere to the top of the side wall of the second mask layer 52. Moreover, when the second mask layer 52 is ashed and de-glued, the remaining etching by-products are in the shape of horns, and the etching by-products are not easy to remove, thereby affecting the etching effect of the first electrode layer 1.

[0088] In this embodiment, by thinning the second mask layer 52, the adhesion degree of the etching byproducts of the first electrode layer 1 on the side wall of the second mask layer 52 is reduced, the etching effect of the first electrode layer 1 is improved, and the risk of the etching byproducts falling on the surface of the device is reduced, thereby improving the electrical performance and stability of the first electrode 1' and improving the yield.

[0089] In some embodiments, Figures 2 to 5 As shown, the first electrode layer 1 includes a first tantalum nitride layer 11, a metal layer 13 and a second tantalum nitride layer 12. The first tantalum nitride layer 11 is located on the side of the dielectric layer 3 away from the second electrode layer 2, the metal layer 13 is located on the side of the first tantalum nitride layer 11 away from the dielectric layer 3, and the second tantalum nitride layer 12 is located on the side of the metal layer 13 away from the first tantalum nitride layer 11.

[0090] like Figure 6 As shown, the dielectric layer 3 is etched by the second mask layer 52 after the thinning process obtained in step 170 using an etching process to obtain a dielectric pattern layer 3'. Then, the first tantalum nitride layer 11 is etched to obtain a first tantalum nitride pattern layer 11'. The metal layer 13 is etched to obtain a metal pattern layer 13'. The second tantalum nitride layer 12 is etched to obtain a second tantalum nitride pattern layer 12'. The first tantalum nitride pattern layer 11', the metal pattern layer 13' and the second tantalum nitride pattern layer 12' together constitute the first electrode 1'. The material of the metal layer 13 may include metals such as aluminum.

[0091] In the process of etching the dielectric layer 3, the first tantalum nitride layer 11, the metal layer 13 and the second tantalum nitride layer 12, etching byproducts containing tantalum are generated in the first tantalum nitride layer 11 and the second tantalum nitride layer 12. In this embodiment, by thinning the second mask layer 52, the adhesion degree of the etching byproducts containing tantalum on the side wall of the second mask layer 52 is reduced, the etching effect of the first electrode 1' is improved, and the risk of etching byproducts falling on the surface of the device is reduced, thereby improving the electrical performance and stability of the capacitor and improving the yield.

[0092] In some embodiments, Figure 6 As shown, the width of the second mask layer 52 is greater than the width of the first electrode layer 1 after etching.

[0093] In the related art, the width of the mask layer is the same as the width of the electrode of the required size. In order to etch the electrode of the required size, the thickness of the mask layer needs to meet certain requirements. In this embodiment, the second mask layer 52 is thinned. In order to ensure that the first electrode layer 1 can still be etched into the first electrode 1' of the required size through the second mask layer 52 after the thinning process, the width of the second mask layer 52 is greater than the width of the first electrode layer 1 (i.e., the first electrode 1') after etching. The width difference between the second mask layer 52 and the first electrode 1' can be determined according to the thinned thickness of the second mask layer 52.

[0094] Step 190: remove the second mask layer.

[0095] like Figure 7 As shown, after the dielectric layer 3 and the first electrode layer 1 are etched to obtain the dielectric pattern layer 3 ′ and the first electrode 1 ′, a stripping process is used to remove the second mask layer 52 after the thinning process.

[0096] In summary, according to the preparation method of the capacitor provided in the embodiment of the present application, the first mask layer 51 is thinned by the descum process, and the third tantalum nitride layer 21 and the anti-reflection layer 22 are etched using the thinned first mask layer 51, thereby reducing the adhesion of the tantalum-containing etching byproducts to the side walls of the first mask layer 51, improving the etching effect of the second plate 2', and reducing the risk of the etching byproducts falling on the surface of the device, thereby improving the electrical performance and stability of the capacitor, and improving the yield. The second mask layer 52 is thinned by the descum process, and the dielectric layer 3, the second tantalum nitride layer 12, the metal layer 13 and the first tantalum nitride layer 11 are etched using the thinned second mask layer 52, thereby reducing the adhesion of the tantalum-containing etching byproducts to the side walls of the second mask layer 52, and the etching byproducts improve the etching effect of the first plate 1', and reduce the risk of the etching byproducts falling on the surface of the device, thereby improving the electrical performance and stability of the capacitor, and improving the yield.

[0097] Accordingly, an embodiment of the present application provides a capacitor, which is manufactured using the capacitor manufacturing method in the above embodiment.

[0098] like Figure 7As shown, the capacitor provided by the embodiment of the present application includes a first electrode 1', a dielectric pattern layer 3' and a second electrode 2' which are stacked in sequence. The dielectric pattern layer 3' is located between the first electrode 1' and the second electrode 2'. The cross-sectional area of ​​the second electrode 2' is smaller than the cross-sectional area of ​​the first electrode 1', and the orthographic projection of the second electrode 2' on the plane where the first electrode 1' is located is located in the first electrode 1'. The orthographic projection of the dielectric pattern layer 3' on the plane where the first electrode 1' is located coincides with the first electrode 1'. . The first electrode 1' and the second electrode 2' can be a single-layer structure or a laminated structure, respectively. The first electrode 1' and the second electrode 2' can respectively include one or more combinations of materials such as aluminum and tantalum nitride. The material of the dielectric pattern layer 3' can include silicon nitride, etc.

[0099] In some embodiments, the capacitor may further include an insulating layer 4. The insulating layer 4 is located on the side of the first electrode 1' away from the dielectric pattern layer 3'. The cross-sectional area of ​​the first electrode 1' may be smaller than the cross-sectional area of ​​the insulating layer 4, and the orthographic projection of the first electrode 1' on the plane where the insulating layer 4 is located is located in the insulating layer 4. The material of the insulating layer 4 may include silicon nitride, etc.

[0100] In some embodiments, the first electrode 1' includes a first tantalum nitride pattern layer 11', a metal pattern layer 13' and a second tantalum nitride pattern layer 12'. The first tantalum nitride pattern layer 11' is located on the side of the dielectric pattern layer 3' away from the second electrode 2', the metal pattern layer 13' is located on the side of the first tantalum nitride pattern layer 11' away from the dielectric pattern layer 3', and the second tantalum nitride pattern layer 12' is located on the side of the metal pattern layer 13' away from the first tantalum nitride pattern layer 11'. The material of the metal pattern layer 13' may include metals such as aluminum.

[0101] In some embodiments, the second electrode 2' includes a third tantalum nitride pattern layer 21' and an anti-reflection pattern layer 22'. The third tantalum nitride pattern layer 21' is located on the side of the dielectric pattern layer 3' away from the first electrode 1', and the anti-reflection pattern layer 22' is located on the side of the third tantalum nitride pattern layer 21' away from the dielectric pattern layer 3'. The material of the anti-reflection pattern layer 22' may include one or more combinations of dielectric materials such as SIN (silicon nitride) and SION (silicon oxynitride).

[0102] In summary, according to the capacitor provided by the embodiment of the present application, the second electrode plate 2' is prepared by thinning the first mask layer 51, the degree of adhesion of etching byproducts to the side walls of the first mask layer 51 is reduced, the etching effect of the second electrode plate 2' is improved, and the risk of etching byproducts falling on the surface of the device is reduced, the electrical performance and stability of the capacitor are improved, and the yield rate is improved. The first electrode plate 1' is prepared by thinning the second mask layer 52, the degree of adhesion of etching byproducts to the side walls of the second mask layer 52 is reduced, the etching effect of the first electrode plate 1' is improved, and the risk of etching byproducts falling on the surface of the device is reduced, the electrical performance and stability of the capacitor are improved, and the yield rate is improved.

[0103] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0104] In the description of the present application, “plurality” means two or more.

[0105] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0106] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a capacitor, characterized in that: include: Providing a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence; forming a first mask layer on a side of the second electrode layer away from the dielectric layer; performing a thinning process on the first mask layer; The second electrode layer is etched using the first mask layer after thinning.

2. The method for preparing a capacitor according to claim 1, characterized in that: The thinning process of the first mask layer includes: The first mask layer is thinned by a descum process using oxygen and an inert gas.

3. The method for preparing a capacitor according to claim 1, characterized in that: After etching the second electrode layer, the method further includes: removing the first mask layer; forming a second mask layer on a side of the second electrode layer away from the dielectric layer; performing a thinning process on the second mask layer; Using the thinned second mask layer, etching the dielectric layer and the first electrode layer; The second mask layer is removed.

4. The method for preparing a capacitor according to claim 3, characterized in that: The thinning process of the second mask layer includes: The second mask layer is thinned by a descum process using oxygen and an inert gas.

5. The method for preparing a capacitor according to claim 2 or 4, characterized in that: The inert gas comprises argon; and / or, The ratio of the oxygen to the inert gas is 150:

50.

6. The method for preparing a capacitor according to claim 2 or 4, characterized in that: The bias power in the descum process is 40-200W; and / or, The source power in the descum process is 700-1300W.

7. The method for preparing a capacitor according to claim 3, characterized in that: The first mask layer and the second mask layer are thinned to a thickness of 1000-4000 angstroms respectively.

8. The method for preparing a capacitor according to claim 3, characterized in that: The width of the first mask layer is greater than the width of the second electrode layer after etching; and / or, The width of the second mask layer is greater than the width of the first electrode layer after etching.

9. The method for preparing a capacitor according to any one of claims 1 to 4, characterized in that: The first electrode layer includes a first tantalum nitride layer, a metal layer, and a second tantalum nitride layer; The first tantalum nitride layer is located on a side of the dielectric layer away from the second electrode layer, the metal layer is located on a side of the first tantalum nitride layer away from the dielectric layer, and the second tantalum nitride layer is located on a side of the metal layer away from the first tantalum nitride layer.

10. The method for preparing a capacitor according to any one of claims 1 to 4, characterized in that: The second electrode layer includes a third tantalum nitride layer and an anti-reflection layer; The third tantalum nitride layer is located on a side of the dielectric layer away from the first electrode layer, and the anti-reflection layer is located on a side of the third tantalum nitride layer away from the dielectric layer.

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