Frequency monitoring circuit with voltage conversion

Abstract

An integrated circuit may include a frequency monitoring circuit. The frequency monitoring circuit may include: a voltage-based frequency monitoring circuit to monitor an input clock signal having an input clock frequency within a first set of frequencies; and a coarse frequency monitoring circuit to monitor an input clock signal having an input clock frequency within a second set of frequencies different from the first set of frequencies. The voltage-based frequency monitoring circuit may be configured to generate an output voltage having a first value when the input clock frequency is greater than a reference frequency and a second value when the input clock frequency is less than the reference frequency. The coarse frequency monitoring circuit may include a reference counter and an input clock counter that generates a count value for calculating the input clock frequency.

Description

[0001] This application claims priority to U.S. Patent Application No. 17 / 986,612 filed on November 14, 2022 and U.S. Provisional Patent Application No. 63 / 408,782 filed on September 21, 2022, which are hereby incorporated by reference in their entirety. Technical Field

[0002] Embodiments described herein relate generally to integrated circuits, and more particularly to integrated circuits having frequency monitoring circuits. Background Art

[0003] The integrated circuit may include a frequency monitoring circuit for monitoring the frequency of the input clock signal. Conventional frequency monitoring circuits typically include a high-precision low-frequency oscillator that generates a reference clock signal. The reference clock signal may control a reference clock counter, and the input clock signal may control an input clock counter. The frequency of the input clock signal may then be calculated based on the count values ​​of the reference clock counter and the input clock counter and the frequency of the reference clock signal.

[0004] Designing frequency monitoring circuits can be challenging. For example, the resolution of conventional frequency monitoring circuits can be increased by reducing the frequency of the reference clock signal or by increasing the bit width of the clock counter, both of which increase the overall delay. It is against this background that the embodiments of this article are generated. Summary of the invention

[0005] An electronic device may include an integrated circuit having a frequency monitoring circuit configured to monitor or measure the frequency of an input clock signal. The frequency monitoring circuit may include a voltage-based frequency monitoring circuit and a coarse frequency monitoring circuit coupled to digital output logic. The voltage-based frequency monitor may perform a fast frequency detection to determine whether the frequency of the input clock signal is greater than or less than a frequency threshold. The coarse frequency monitoring circuit may be used to perform frequency detection at a limit frequency.

[0006] The voltage-based frequency monitoring circuit may include: a comparator having a first comparator input and a second comparator input; a capacitor coupled to the first comparator input; a resistor selectively coupled to the second comparator input; and a current source configured to provide a reference current to the capacitor during a first time period and to provide the reference current to the resistor during a second time period different from the first time period. The voltage-based frequency monitoring circuit may optionally include: a first switch coupled between the current source and the capacitor; a second switch coupled between the current source and the resistor; a third switch coupled between the resistor and the second comparator input; a fourth switch configured to reset the capacitor; an additional capacitor coupled to the second comparator input; and / or a clock phase generator configured to receive an input clock signal having an input clock frequency and configured to output a signal for controlling the first switch, the second switch, the third switch, and the fourth switch. The comparator may output a first voltage in response to detecting that the input clock frequency is greater than a reference frequency, and may output a second voltage different from the first voltage in response to detecting that the input clock frequency is less than the reference frequency.

[0007] The voltage-based frequency monitoring circuit may optionally include a clock jitter circuit configured to jitter the input clock signal provided to the clock phase generator. If desired, the voltage-based frequency monitoring circuit may optionally include: a first auto-zero switch coupled across the second comparator input and the output of the comparator; a second auto-zero switch having a first terminal coupled to the first comparator input and having a second terminal coupled to the second comparator input; and an auto-zero capacitor coupled to the second comparator input. If desired, the voltage-based frequency monitoring circuit may optionally include: a trimming circuit configured to tune the capacitor using a calibration setting; a self-test circuit configured to selectively couple the second comparator input to a corresponding tap point along the resistor ladder; a reset pulse generator coupled to the comparator and configured to generate an output signal for discharging the capacitor; and / or a dynamic element matching circuit configured to selectively provide two different reference currents to the capacitor and the resistor.

[0008] The coarse frequency monitoring circuit may be configured to receive the input clock signal and output one or more count values. The output circuit may generate a digital output based on the output voltage from the voltage-based frequency monitoring circuit when the input clock frequency is within a first frequency set and based on the one or more count values ​​from the coarse frequency monitoring circuit when the input clock frequency is within a second frequency set different from the first frequency set. The coarse frequency monitoring circuit may include: a reference counter configured to receive a reference clock signal and output a completion signal; and an input clock counter configured to receive the input clock signal, receive the completion signal from the reference counter, and generate a count value for calculating the input clock frequency. The ring oscillator may be used to generate the reference clock signal.

[0009] Other features of the invention, its nature and various advantages will become more apparent from the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram of an illustrative integrated circuit including a frequency monitoring circuit, according to some embodiments.

[0011] Figure 2 is a block diagram of an illustrative frequency monitoring circuit having a voltage-based frequency monitoring circuit and a coarse frequency monitoring circuit according to some implementations.

[0012] Figure 3 is a circuit diagram of an exemplary voltage-based frequency monitoring circuit according to some embodiments.

[0013] Figure 4 According to some embodiments, in operation Figure 3 A timing diagram of illustrative waveforms involved in a voltage-based frequency monitoring circuit of the type shown.

[0014] Figure 5 is a circuit diagram of an illustrative voltage-based frequency monitoring circuit with an analog-to-digital converter (ADC) output stage, according to some implementations.

[0015] Figure 6 is a diagram of a temperature compensated resistive circuit according to some embodiments.

[0016] Figure 7 is a circuit diagram of an illustrative voltage-based frequency monitoring circuit with an auto-zero comparator, according to some embodiments.

[0017] Figure 8 is a diagram of an illustrative clock dithering circuit configured to generate a control signal for a voltage-based frequency monitoring circuit, according to some embodiments.

[0018] Fig. 9 is a circuit diagram of an illustrative voltage-based frequency monitoring circuit with a capacitance trimming circuit, according to some implementations.

[0019] Fig.10 is a circuit diagram of an illustrative voltage-based frequency monitoring circuit with a self-test subcircuit according to some embodiments.

[0020] Fig.11 is a circuit diagram of an illustrative voltage-based frequency monitoring circuit configured as a relaxation oscillator, according to some embodiments.

[0021] Fig. 12A is a diagram illustrating a suitable operating frequency range for a voltage-based frequency monitoring circuit according to some embodiments.

[0022] Fig. 12B is a diagram illustrating a suitable operating frequency range for a coarse high frequency monitoring circuit according to some embodiments.

[0023] Fig. 12C is a diagram illustrating a suitable operating frequency range for a coarse low frequency monitoring circuit according to some embodiments.

[0024] Fig.13 is a diagram of an exemplary coarse frequency monitoring circuit according to some embodiments. DETAILED DESCRIPTION

[0025] The present invention relates to an integrated circuit with a frequency monitoring circuit. The frequency monitoring circuit may include a voltage-based frequency monitoring circuit and a coarse frequency monitoring circuit. The voltage-based frequency monitoring circuit may convert a frequency into a voltage, which enables fast frequency monitoring. The coarse frequency monitoring circuit uses a digital counter to perform fast frequency monitoring at higher frequencies. The combination of voltage-based frequency monitoring and coarse frequency monitoring provides fast frequency monitoring across a wide frequency range.

[0026] The voltage-based frequency monitoring circuit may include a comparator having an input coupled to a capacitive component and a resistive component and an associated switch. The voltage-based frequency monitoring circuit may operate in a charging phase, a comparison phase, and a reset phase. The comparator may have an output coupled to a digital majority voting circuit or an analog-to-digital converter. The voltage-based frequency monitoring circuit may include a temperature compensation resistor comprising a combination of a polysilicon resistor and a metal resistor. The comparator may automatically zero to mitigate comparator offset drift and flicker noise. The clock signal controlling the switch in the voltage-based frequency monitoring circuit may be jittered to help suppress power supply noise. The capacitive component within the voltage-based frequency monitoring circuit may be trimmed to a known reference frequency. A self-test circuit may be used to check the value of the capacitive component and the resistive component. Alternatively, the voltage-based frequency monitoring circuit may be optionally configured as a relaxation oscillator to check the value of the capacitive component and the resistive component.

[0027] Figure 1 1 is a diagram of an exemplary integrated circuit device (such as integrated circuit 10) having a frequency monitoring system (such as frequency monitoring circuit 12). Figure 1 As shown, the frequency monitoring circuit 12 may have an input terminal configured to receive an input clock signal Clk_in and an output terminal at which a corresponding digital value Dout is generated. The input clock signal Clk_in may represent a clock signal to be monitored and may be an external clock signal (e.g., a clock signal received off-chip from another integrated circuit device, a clock signal generated from a phase-locked loop, a recovered clock signal, or other internal clock signals generated from a component within the device 10). The frequency monitoring circuit 12 may output a digital Dout value. For example, the frequency monitoring circuit 12 may assert Dout (e.g., drive Dout high or to logic "1") when it detects that the frequency of Clk_in is higher than a predefined threshold frequency, and may de-assert Dout (e.g., drive Dout low or to logic "0") when it detects that the frequency of Clk_in is lower than a predefined threshold frequency. Figure 1 The example in which device 10 includes one frequency monitoring circuit is merely illustrative. In general, integrated circuit device 10 may include a frequency monitoring system that may monitor any suitable number of clock signals.

[0028] Figure 2 is a block diagram of an exemplary frequency monitoring circuit 12. Figure 2As shown, the frequency monitoring circuit 12 may include a voltage-based frequency monitoring circuit (such as a voltage-based frequency monitoring circuit 14), an accompanying coarse frequency monitoring circuit (such as a coarse frequency monitoring circuit 18), and an output logic circuit (such as a digital output logic 16). The voltage-based frequency monitoring circuit 14 may have an input terminal configured to receive an input clock signal Clk_in and an output terminal coupled to the digital output logic 16. The voltage-based frequency monitoring circuit 14 may be configured to convert the input clock signal Clk_in into a corresponding output voltage Vout having a value proportional to the frequency of the signal Clk_in (i.e., dependent on or based on the frequency). Therefore, the frequency monitoring circuit 14 is sometimes referred to as having frequency-to-voltage conversion functionality. The use of frequency-to-voltage conversion or voltage-based frequency monitoring schemes can allow for faster accurate frequency measurements than conventional frequency monitoring methods, which rely solely on counting the number of cycles in the input clock against a precise low-frequency clock signal. The voltage-based frequency monitoring circuit 14 may sometimes be referred to and defined as a frequency-to-voltage converter (FVC).

[0029] The coarse frequency monitoring circuit 18 may have a first input configured to receive an input clock signal Clk_in, a second input configured to receive a reference clock signal from an oscillator circuit (such as a local oscillator 20), and an output coupled to the digital output logic 16. The coarse frequency monitoring circuit 18 may help cover a frequency range where the voltage-based frequency monitoring circuit 14 may not operate properly. For example, the coarse frequency monitoring circuit 18 may help measure input clock signals Clk_in having very low frequencies (e.g., close to 0 Hz) and very high frequencies (e.g., close to a maximum operating frequency fmax). At these extreme frequencies, the voltage-based frequency monitoring circuit 16 may be unreliable or may take too long. Therefore, the digital output logic 16 may select between the output of the monitoring circuit 14 and the monitoring circuit 18 based on the frequency range of the input clock signal Clk_in. At extreme frequencies, the result from the coarse frequency monitor 18 may be selected for output (while bypassing or ignoring the result from the voltage-based monitor 14). Otherwise, the result from the voltage-based frequency monitor 18 may be selected for output (while bypassing or ignoring the result from the coarse monitor 18).

[0030] Figure 3 is a circuit diagram of an exemplary voltage-based frequency monitoring circuit 14 (eg, a frequency-to-voltage converter). Figure 3As shown, the voltage-based frequency monitoring circuit 14 may include a comparator circuit such as a comparator 32, passive components such as a resistor R and capacitors C1 and C2, and associated switches 22, 24, 26, and 28. The comparator 32 has a first (positive) input terminal coupled to the node X, a second (negative) input terminal selectively coupled to the node Y via the switch 26, and an output terminal at which an output voltage Vout may be generated. The first input terminal and the second input terminal of the comparator 32 may be referred to as a first comparator input terminal and a second comparator input terminal. The voltage Vc may be provided to the first (+) input terminal of the comparator 32 at the node X. The reference voltage Vref may be provided to the second (-) input terminal of the comparator 32. The switch 26 may be selectively activated by the control signal φc (e.g., the signal φc may be asserted to turn on the switch 26 and may be deasserted to turn off the switch 26). The comparator 32 itself may be controlled by the control signal φb. When signal φb is asserted, comparator 32 may perform a comparison operation, driving Vout high when Vc exceeds Vref, and driving Vout low when Vc drops below Vref. When signal φb is deasserted, comparator 32 may be in an idle state.

[0031] Node X may selectively receive a reference current Iref via switch 22. The reference current Iref may be provided from a reference current source. Switch 22 may be selectively activated by a control signal φa (e.g., signal φa may be asserted to turn switch 22 on and may be deasserted to turn switch 22 off). Capacitor C1 has a first terminal coupled to node X and a second terminal coupled to a ground power line 30 (e.g., a ground line on which a ground voltage is provided). When switch 22 is turned on, current Iref will charge capacitor C1, and as switch 22 is turned on, the voltage stored on capacitor C1 will increase linearly. The charging of capacitor C1 effectively converts φa (as a function of input clock signal Clk_in) into a voltage signal Vc. Switch 28 may be coupled in parallel with capacitor C1. Switch 28 may be selectively activated by a control signal φc (e.g., signal φc may be asserted to turn switch 28 on and may be deasserted to turn switch 28 off). Activating switch 28 may reset the charge stored on capacitor C1 to zero volts. Therefore, switch 28 is sometimes referred to as a reset or discharge switch.

[0032] Node Y may selectively receive a reference current Iref via switch 24. Switch 24 may be selectively activated by a control signal φa' (e.g., signal φa' may be asserted to turn on switch 24 and may be deasserted to turn off switch 24). Signal φa' may be an inverted version of signal φa. Thus, at any given point in time, only one of switches 22 and 24 may be turned on (e.g., when switch 22 is enabled, switch 24 will be disabled, and vice versa). Resistor R has a first terminal coupled to node Y and a second terminal coupled to ground line 30. When switch 24 is turned on, current Iref will flow through resistor R and generate a reference voltage Vref on node Y. Only when switch 26 is turned on (e.g., when signal φc is asserted) is the reference voltage on node Y provided to the second (-) input terminal of comparator 32. Capacitor C2 may have a first terminal coupled to the second input of comparator 32 and a second terminal coupled to ground line 30. Connected in this manner, capacitor C2 may help maintain the reference voltage Vref at the second input of comparator 32 .

[0033] The control signals φa, φb and φc may be generated using a clock phase generator 19 based on the input clock signal Clk_in being monitored. Figure 4 The operation of the voltage-based frequency monitoring circuit 14 may be best understood by referring to the example of a timing diagram of FIG. Figure 4 In the example of , the input clock signal Clk_in may be a square wave clock signal. This is merely exemplary. If desired, the signal Clk_in may be a sine waveform or other periodic waveform. If desired, the signal Clk_in may have a 50% duty cycle (as shown), a duty cycle greater than 50%, a duty cycle less than 50%, or any suitable duty cycle. Sometimes in this document, a device configuration in which the input clock signal Clk_in is a square wave with a 50% duty cycle is described as an example.

[0034] like Figure 4 As shown, the control signal φa can be a periodic signal having a frequency of half that of the input clock signal Clk_in. As an example, the signal φa can be generated from the clock signal Clk_in using a simple frequency divider or other circuit that can generate a control signal having a frequency of half or other fraction of the signal Clk_in. The control signal φb can be a pulse signal triggered from the falling (negative) edge of the signal φa, as indicated by arrow 34. The control signal φc can be a pulse signal triggered from the falling (negative) edge of the signal φb, as indicated by arrow 36. The control signals φa, φb, and φc can be generated using the clock phase generator 19 (see Figure 3 ) is generated from the clock signal Clk_in.

[0035] At time t1, the input clock signal Clk_in rises, which triggers the rising clock edge of the control signal φa. The signal φa may be high until time t2, which is the subsequent rising edge of the clock signal Clk_in. During the time period from time t1 to t2 when the signal φa is high, the reference current Iref will flow through the switch 22 to charge the capacitor C1 at a predetermined charging rate, so the voltage Vc at the node X will rise linearly from time t1 to t2. Therefore, the signal φa is sometimes referred to as a charging control signal, and the time period from t1 to t2 can be referred to and defined as a charging phase. At time t2, the signal φa is driven low, so the switch 22 is turned off and the voltage Vc stored on the capacitor C1 will remain at a constant level.

[0036] At time t3, control signal φb may be pulsed high. When signal φb is asserted (eg, pulsed high), comparator 32 is enabled and will generate Vout depending on whether Vc is greater than or less than a reference voltage level Vref. Figure 4 In the example of , Vout is driven from a low voltage to a high voltage at time t3, which indicates that Vc exceeds the Vref level (see the horizontal threshold line in the Vc waveform). However, this is merely illustrative. If the input clock signal Clk_in has a higher frequency, the resulting clock period will be shortened, which will effectively shorten the duration of the charging phase. If the frequency is high enough, the charging phase may be so short that Vc will not charge to a voltage level exceeding Vref. In such a scenario, the voltage Vout will remain de-asserted at the output of the comparator 32. Therefore, the signal φb is sometimes referred to as a comparison or comparator control signal, and the time period when φb is high may be referred to and defined as a comparison phase or a conversion phase.

[0037] At time t4, control signal φc may be pulsed high. When signal φc is asserted (e.g., pulsed high), switch 28 may be turned on to discharge capacitor C1. As a result, voltage Vc will be pulled back to a low voltage level (e.g., driven back to ground voltage). During this time, switch 26 may also be turned on, which recharges capacitor C2 to Vref in the event that any leakage has been present at the second input of comparator 32 (e.g., the capacitor resamples and holds Vref for the next clock cycle). Therefore, signal φc is sometimes referred to as a reset control signal, and the period of time that φc is high may be referred to and defined as a reset phase. At time t5, a subsequent comparison cycle may be repeated.

[0038] Operating in this manner, a fast and highly accurate frequency detection scheme is provided in which a voltage comparison is performed at each clock cycle. Thus, this voltage-based architecture enables single-cycle frequency monitoring to determine whether the frequency of the current input clock signal Clk_in is greater than or less than a reference frequency of the voltage-based frequency monitoring circuit 14. The reference frequency is sometimes referred to as the threshold frequency or detection frequency of the frequency monitoring circuit 14. However, in practice, multiple comparison cycles may be required to reliably monitor the input frequency in the presence of circuit noise and input clock jitter. As an example, the digital output logic 16 (see Figure 2 ) may include a digital majority voting circuit that is configured to average out transient errors that may occur due to random circuit noise, power supply noise, and clock jitter. Thus, the time required to detect the input clock frequency may only take a few input clock cycles.

[0039] Figure 3 The example uses the same reference current Iref to charge capacitor C1 at node X and generate a reference voltage at node Y. By sharing the same input current Iref, the frequency monitoring circuit 14 eliminates the need for a high-precision current / voltage reference for the comparator. The detection threshold can depend only on the first-order values ​​of resistor R and capacitor C1. This frequency-to-voltage conversion architecture can also help eliminate any low-frequency noise or flicker associated with the reference current and voltage.

[0040] Figure 3 The example in which the voltage-based frequency monitoring circuit 14 includes the comparator 32 is merely illustrative and is not intended to limit the scope of the embodiments of the present invention. In other embodiments, the comparator may be provided by, for example, an analog-to-digital converter (ADC) 33 (see, for example, Figure 5 ) data converter instead. Figure 5 As shown, the analog-to-digital converter 33 may have a first input terminal configured to receive a voltage Vc from a node X, a second input terminal configured to receive a reference voltage Vref, and a clock input terminal configured to receive a control signal φb. The first input terminal and the second input terminal of the analog-to-digital converter 33 are sometimes referred to as a first ADC input terminal and a second ADC input terminal. Configured in this manner, the analog-to-digital converter 33 may generate a corresponding digital signal Dout that is equal to the ratio of Vc to Vref (e.g., Dout may be equal to Vc / Vref). The converter 33 may be part of the digital output logic 16 (see Figure 2 ).

[0041] The voltage-based frequency monitoring circuit 14 is configured to compare the frequency of the input clock signal Clk_in with a reference frequency. The assertion of Vout may indicate that the current Clk_in has a measured frequency less than the reference frequency, while the de-assertion of Vout may indicate that the current Clk_in has a measured frequency greater than the reference frequency. The reference frequency (sometimes referred to as the threshold frequency) may be selected or designed by tuning the resistance of the resistor R and the capacitance of the capacitor C1. However, the value of the resistor R may vary as a function of temperature. For example, a polysilicon resistor (such as a resistor formed using polysilicon or other silicon-based materials) may exhibit a negative temperature coefficient (i.e., an increase in temperature may result in a decrease in resistance, and vice versa). Since the accuracy of frequency monitoring depends on the values ​​of R and C1, any temperature drift at the resistor R may be a major source of error for the frequency monitoring circuit 14.

[0042] According to some embodiments, the resistor R in the voltage-based frequency monitoring circuit 14 may use a temperature-compensated resistive circuit (such as Figure 6 The temperature compensation resistor R) shown in the figure is used to achieve this. Figure 6 In an example of , the resistor R may include a polysilicon resistor Rpoly coupled in series with a metal resistor Rmetal. The polysilicon resistor Rpoly may exhibit a negative temperature coefficient, while the metal resistor Rmetal may exhibit a positive temperature coefficient. By combining two different resistors with opposite temperature coefficients, the entire resistor R may exhibit a stable resistance even if there is a temperature drift. Figure 6 The example of the temperature compensation resistor of is only illustrative. If necessary, the resistor R can be implemented using other types of temperature-dependent resistive components.

[0043] The voltage-based frequency monitoring circuit 14 may be subject to comparator offset (and drift in the comparator offset) and flicker noise. Figure 7 Another suitable embodiment of a voltage-based frequency monitoring circuit 14 is shown provided with an auto-zero (AZ) component that can help compensate for any drift in the comparator offset while also mitigating flicker noise. Figure 7 As shown, an additional feedback switch such as switch 44 may be coupled across the output terminal and the second (-) input terminal of comparator 32, an additional capacitor such as auto-zero capacitor Caz may be coupled in series at the second input terminal of comparator 32, switch 40 may be coupled between node X and the first (+) input terminal of comparator 32, and switch 42 may be coupled between the two input terminals of comparator 32. Specifically, switch 42 may have a first terminal coupled to the first input terminal of comparator 32 and a second terminal coupled to capacitor C2.

[0044] Switches 40, 42, and 44 may be collectively referred to as auto-zero (AZ) or auto-zero switches. Switches 42 and 44 may be controlled by a signal φa (e.g., a charge control signal), while switch 40 may be controlled by a signal φb (e.g., a comparison control signal). As a result, switches 42 and 44 may be turned on during the charge phase to place the comparator in a unity gain feedback arrangement such that the comparator offset is stored across capacitor Caz. Switch 40 may then be activated during the comparison phase (also sometimes referred to as the conversion phase) such that capacitor Caz is connected in series with a reference voltage Vref to cancel any comparator offset and low frequency flicker noise. The use of such an auto-zero circuit is merely optional. Figure 7 The remaining structure and function of the frequency monitoring circuit 14 are the same as those already combined Figure 3 The description is similar and need not be repeated in detail to avoid obscuring the present embodiment.

[0045] Another potential source of error is power supply noise. The main path of power supply noise may be through the reference current source Iref. One way to reduce or mitigate the effects of this power supply noise is to jitter the clock edge of the switch control signal. Figure 8 is a diagram of an exemplary clock jittering circuit, such as clock jittering circuit 50 , that may be used to jitter the clock edges of input clock Clk_in so that corresponding switch control signals φa, φb, and φc output from clock phase generator 19 have rising / falling edges that are also jittered.

[0046] like Figure 8 As shown, the clock jitter circuit 50 may include a chain formed by a delay circuit 52 (e.g., a buffer, an inverter, or other delay component), a multiplexing circuit (such as a multiplexer 54), the multiplexing circuit having inputs connected to different tapping points along the delay chain and having a control input configured to receive a signal from a linear feedback shift register (LFSR) 56. The linear feedback shift register 56 may have a clock input configured to receive an input clock signal Clk_in and an output at which a pseudo-random number sequence is generated. By feeding the pseudo-random number sequence generated by the LSFR 56 to the control input of the multiplexer 54, the delay of Clk_in can be disrupted at each clock cycle. This effectively changes the period of the control signal φa at each clock cycle.

[0047] The power supply rejection ratio of the voltage-based frequency monitoring circuit 14 can be improved by varying the duration of the charging phase of each clock cycle and passing the output of the comparator 32 through a digital majority voting circuit or through a digital averaging filter that may be included in the digital output logic 16. If desired, the number of delay cells 52 and delay taps in the delay chain can be specifically designed to produce notches at any frequency of interest. The circuit 50 may include two or more delay cells 52, 2 to 10 delay cells 52, 10 to 20 delay cells 52, 20 to 50 delay cells 52, or any desired number of delay cells with corresponding delay taps. For example, if it is known that the environment in which the circuit 14 will operate contains an interferer at a particular frequency fx, the delay chain within the clock jitter circuit 50 can be designed to produce a notch (e.g., frequency rejection) at the interferer frequency fx. Figure 8 The example of (wherein the clock jitter circuit 50 uses a linear feedback shift register to control the multiplexer 54) is merely illustrative. In general, the clock jitter circuit 50 can be implemented using other types of pseudo-random number generators or other random number generators.

[0048] As described above, the reference (threshold) frequency of the voltage-based frequency monitoring circuit 14 may be a function of the resistance of the resistor R and the capacitance of the capacitor C1. Since the RC value may vary due to process variations, a (factory) calibration operation may be performed to trim (adjust) the value of the capacitor C1 so that the combined RC value is tuned to the desired reference frequency. Fig. 9 An embodiment of a voltage-based frequency monitoring circuit 14 is shown that includes a trimming circuit such as a trimming circuit 60. The trimming circuit 60 may monitor the voltage Vout from the output of the comparator 32 and adjust the capacitance of the capacitor C1 based on a setting 62. The capacitor C1 may be a capacitor bank or array that is selectively activated.

[0049] For example, the trimming circuit 60 may be a finite state machine configured to perform a series of calibration operations. The calibration operations may include first providing an input clock signal having a known input frequency (e.g., a known input frequency equal to a desired reference / threshold / detection frequency). By proportionally adjusting the resistance of R, the desired threshold frequency may be accurately programmed to the required level. The trimming circuit 60 may first set the capacitance of C1 to an intermediate code level for setting 62. If the comparator output Vout is low, the combined RC value is greater than the clock period of the input clock signal. Conversely, if the comparator output Vout is high, the combined RC value is less than the clock period of the input clock signal. The trimming circuit 60 may perform a binary search or other iterative search algorithm to continuously determine the next code for setting 62 so that the combined RC value is equal to the desired time period corresponding to the target reference / threshold frequency. Therefore, the trimming circuit 60 is sometimes referred to as a calibration circuit, and the setting 62 may be referred to as a calibrated (factory) capacitor setting. The use of the trimming / calibration circuit 60 is optional.

[0050] In certain embodiments, self-test techniques may also be provided to check or verify the combined RC value. Fig.10 One way to perform the self-test method is shown. Fig.10 As shown, the voltage-based frequency monitoring circuit 14 may be provided with a self-test circuit 66 having an input terminal configured to receive Vout from the output terminal of the comparator 32 and an output terminal for adjusting the pull-down resistance at the node Y. Fig.10 As shown, a resistance ladder including a plurality of unit resistors Ru can be coupled in series between node Y and ground line 30. By activating one of switches 64, the second (-) input terminal of comparator 32 can be selectively coupled to one of the tapping points along the resistance ladder. Switch 64 can be controlled by a signal φ_test, which is output by self-test circuit 66.

[0051] Configured in this manner, the self-test circuit 66 can sequentially select different tap points along the resistor ladder (e.g., by connecting the second input of the comparator to different nodes along the ladder) to proportionally shift the threshold frequency while the frequency of the input clock signal remains constant. From a system level perspective, this has the same effect as keeping the threshold frequency fixed and shifting the input clock frequency. Before shipping the device 10, the self-test operation can be performed one or more times in the factory to ensure that the combined RC value is tuned to the reference frequency. Fig.10 The remaining structure and function of the frequency monitoring circuit 14 are the same as those already combined Figure 3 The description is similar and need not be repeated in detail to avoid obscuring the present embodiment.

[0052] Fig.11 Another way to perform the self-checking method is shown. Fig.11As shown, the voltage-based frequency monitoring circuit 14 may be provided with a pulse generator, such as a reset pulse generator 72 connected in a feedback loop. The reset pulse generator 72 may have an input configured to receive the voltage Vout from the output of the comparator 32 and an output on which a reset pulse signal may be provided to the reset switch 28. The reset pulse generator 72 may be configured to generate a short pulse (e.g., a pulse signal having a duration of less than 1ns, less than 5ns, less than 10ns, 10ns to 50ns, etc.) at its output, which enables the switch 28 to periodically discharge the capacitor C1 whenever Vout switches or in response to detecting a rising edge and / or a falling edge of Vout. The switches 22, 24, and 26 may all be activated (turned on) at the same time. In addition, two different reference currents, such as Iref and Iref / 4, may be selectively provided to nodes X and Y via the dynamic element matching circuit 70. The dynamic element matching circuit 70 may rotate or alternate the currents provided to nodes X and Y.

[0053] Arranged in this way, the frequency monitoring circuit 14 is configured to operate as a relaxation oscillator. The current Iref / 4 can be used to keep the oscillation frequency low. Fig.11 The proportional factor 1 / 4 in the example of (where one of the reference current branches is divided by four) is merely illustrative. If desired, the proportional factor of one of the reference current branches may be 1 / 2, 1 / 3, 1 / 5, 2 / 3, 3 / 4, other fractional values, or even 1 (as an example). A smaller proportional factor typically reduces the oscillation frequency of the relaxation oscillator, which can reduce errors or increase the accuracy of the relaxation oscillator. The resulting oscillation frequency of this relaxation oscillator will be a function of the combined RC value of components R and C1. The output of the comparator 32 can be connected to a frequency counter, oscilloscope, or other frequency measurement circuit to measure the frequency of the relaxation circuit. This measured frequency can then be used to calculate the R and / or C1 values. If desired, other ways of configuring the voltage-based frequency monitoring circuit 14 as an oscillation circuit or a relaxation oscillator can also be used.

[0054] Figures 3 to 11 The embodiments are not mutually exclusive and may be implemented in any desired combination. As an example, the voltage-based frequency monitoring circuit 14 may have Fig. 9 The trimming circuit 60 and Fig.10 As another example, the voltage-based frequency monitoring circuit 14 may include Fig.10 The self-test circuit 66 and Fig.11 The circuit shown is for operating the circuit 14 in the relaxation oscillator mode to perform a self-test. As yet another example, the voltage-based frequency monitoring circuit 14 may include Figure 6 Temperature compensation resistors, Figure 7 Automatic zeroing circuit, Figure 8 Clock jitter circuit, Fig. 9 The trimming circuit and / or Fig.10 and Fig.11 Self-test circuit.

[0055] Combination Figures 2 to 11 Voltage-based frequency monitoring circuits 14 of the type described may be unreliable at extreme operating frequencies. For example, if the input clock frequency is too high, the comparator may not be able to complete the comparison, or if the input clock frequency is too low, leakage currents at the input terminals and / or other internal nodes of the comparator may affect the accuracy of the frequency monitoring.

[0056] Various switches (such as Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.10 and Fig.11 The switches 22, 24, 26, 28, 40, 42, 44, and 64 shown in the embodiments of the present invention may be implemented using any type of transistor technology. For example, the switches may be implemented as one or more metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), gate-all-around field effect transistors (GAAFETs), multi-channel bridge-connected field effect transistors (MBCFETs), junction-gate field effect transistors (JFETs), bipolar junction transistors (BJTs), some combination of these transistors, and / or other types of transistor-based switching devices.

[0057] Fig. 12A is a diagram showing an exemplary operating frequency range of the voltage-based frequency monitoring circuit 14. Fig. 12A As shown, the voltage-based frequency monitoring circuit 14 may have difficulty reliably generating accurate / consistent outputs at very low frequencies (see frequency range 80 from 0 Hz to f1), very high frequencies (see frequency range 84 close to the maximum operating frequency fmax), and close to the threshold / detection frequency (see frequency range 82 around the detection frequency). In the frequency ranges 80, 82, and 84, the comparator output Vout may be unreliable and may sometimes result in false positive or false negative identifications. When the input clock frequency is between the ranges 80 and 82, the voltage-based frequency monitoring circuit 14 can reliably generate a comparator output Vout of "0", and when the input clock frequency is between the ranges 82 and 84, the voltage-based frequency monitoring circuit can reliably generate a comparator output Vout of "1".

[0058] Coarse frequency monitoring circuit 18 (see Figure 2 ) can be used to overcome the limitations of the voltage-based frequency monitoring circuit 14. The coarse frequency monitoring circuit 18 can be configured to have Fig. 12BThe coarse high frequency monitor circuit may be unreliable only in the frequency range 86 (e.g., close to the threshold / detection frequency f_thres' of the coarse high frequency monitor), but may reliably generate a comparator output Vout of "0" when the input clock frequency is between 0 Hz and the range 86, and may reliably generate a comparator output Vout of "1" when the input clock frequency is between the range 86 and fmax.

[0059] The coarse frequency monitoring circuit 18 may also be configured to have Fig. 12C A coarse low frequency monitor for an exemplary operating frequency range is shown. The coarse low frequency monitoring circuit may be unreliable only in the frequency range 88 (e.g., close to the threshold / detection frequency f_thres" of the coarse low frequency monitor), but can reliably generate a comparator output Vout of "0" when the input clock frequency is between 0 Hz and the range 88, and can reliably generate a comparator output Vout of "1" when the input clock frequency is between the range 88 and fmax.

[0060] The detection frequency f_thres" of the coarse low frequency monitor is substantially less than the detection frequency f_thres' of the high frequency monitor. The coarse frequency monitoring circuit 18 may include a coarse high frequency monitoring subcircuit and / or a coarse low frequency monitoring subcircuit. Using a voltage-based frequency monitoring circuit 14 in combination with such a coarse frequency monitoring circuit 18 allows the frequency monitoring circuit 12 to provide fast frequency monitoring capabilities across the entire frequency range from 0 Hz to fmax without compromising speed or accuracy.

[0061] Fig.13 is a diagram of an exemplary coarse frequency monitoring circuit 18 according to some embodiments. Fig.13 The circuit can represent a rough high-frequency monitoring circuit or a rough low-frequency monitoring circuit. Fig.13 As shown, the coarse frequency monitoring circuit may include a reference counter circuit such as a reference counter 90 and an input clock counter circuit such as an input clock counter 92. The reference counter 90 may have: a clock input terminal configured to receive a reference clock signal Clk_ref from a reference oscillator 94; an enable input terminal configured to receive an enable signal; and an output terminal, at which a first count value Count1 may be generated. The input clock counter 92 may have: a clock input terminal configured to receive an input clock signal Clk_in; an enable input terminal configured to receive an enable signal; and an output terminal, at which a second count value Count2 may be generated. The count outputs Count1 and / or Count2 may be provided to the digital output logic 16 for further calculation.

[0062] When the enable signal is asserted, the operation of the coarse frequency monitoring circuit 18 begins. Once the enable signal goes high, both the reference counter 90 and the input clock counter will begin counting the rising edges (or falling edges) of their respective clock input signals. Once the reference counter 90 reaches its maximum value (e.g., when Count1 reaches 2^N-1, where the counter 90 has a bit width of N), the reference counter 90 will assert the "done" signal. The assertion of this done signal can stop the count at the input clock counter 92 and freeze the current Count2 value. The frequency of the input clock signal Clk_in can then be calculated using the following equation:

[0063]

[0064] Where fin represents the frequency of the input clock signal Clk_in, where fref represents the frequency of the reference clock signal Clk_ref, where Count2 is the frozen output of the input clock counter 92 when the completion signal is asserted from the counter 90, and where N is equal to the resolution of the counter 90. The frequency fref may be much lower than fin (e.g., fref may be less than 10% of fin, less than 1% of fin, less than 0.1% of fin, less than 0.01% of fin, etc.). The calculation of fin using equation 1 may be performed at the digital output logic 16 (see Figure 1 ).

[0065] Since the coarse frequency monitoring circuit 18 only needs to operate at very high and very low frequencies, the circuit 18 does not need to be very accurate. Due to this relaxed accuracy requirement, the switching speed of the coarse frequency monitoring circuit 18 can be very high. In addition, the relaxed accuracy requirement also makes the design of the reference oscillator 94 relatively simple and has low area and power. For example, the reference oscillator 94 can be a ring oscillator.

[0066] According to one embodiment, a frequency monitoring circuit is provided, which includes: a comparator having a first comparator input and a second comparator input; a capacitor coupled to the first comparator input; a resistor selectively coupled to the second comparator input; and a current source configured to provide a reference current to the capacitor during a first time period and to provide the reference current to the resistor during a second time period different from the first time period.

[0067] According to another embodiment, the frequency monitoring circuit provides: a first switch coupled between the current source and the capacitor; and a second switch coupled between the current source and the resistor.

[0068] According to another embodiment, the first switch is controlled by a control signal and the second switch is controlled by an inverted version of the control signal.

[0069] According to another embodiment, the frequency monitoring circuit includes a third switch coupled between the resistor and the second comparator input.

[0070] According to another embodiment, the frequency monitoring circuit includes a fourth switch configured to reset the capacitor.

[0071] According to another embodiment, the frequency monitoring circuit includes an additional capacitor coupled to the second comparator input.

[0072] According to another embodiment, the frequency monitoring circuit includes a clock phase generator configured to receive an input clock signal having an input clock frequency and configured to output a signal for controlling the first switch, the second switch, the third switch, and the fourth switch.

[0073] According to another embodiment, the comparator is configured to output a first voltage in response to detecting that the input clock frequency is greater than a reference frequency, and to output a second voltage different from the first voltage in response to detecting that the input clock frequency is less than the reference frequency.

[0074] According to another embodiment, the frequency monitoring circuit includes a clock dithering circuit configured to dither the input clock signal provided to the clock phase generator.

[0075] According to another embodiment, the resistor includes a polysilicon resistor and a metal resistor.

[0076] According to another embodiment, the frequency monitoring circuit includes: a first auto-zero switch, which is coupled across the second comparator input and the output of the comparator; a second auto-zero switch, which has a first terminal coupled to the first comparator input and a second terminal coupled to the second comparator input; and an auto-zero capacitor, which is coupled to the second comparator input.

[0077] According to another embodiment, the frequency monitoring circuit includes a trimming circuit configured to tune the capacitor using a calibration setting.

[0078] According to another embodiment, the frequency monitoring circuit includes a self-test circuit configured to selectively couple the second comparator input to a corresponding tap point along the resistor ladder.

[0079] According to another embodiment, the frequency monitoring circuit includes: a reset pulse generator, which is coupled to the comparator and configured to generate an output signal for discharging the capacitor; and a dynamic element matching circuit, which is configured to selectively provide two different reference currents to the capacitor and the resistor.

[0080] According to one embodiment, a circuit is provided, comprising: a voltage-based frequency monitoring circuit configured to receive an input clock signal having an input clock frequency and to generate a corresponding output voltage having a first value when the input clock frequency is greater than a reference frequency and to generate a corresponding output voltage having a second value when the input clock frequency is less than the reference frequency; a coarse frequency monitoring circuit configured to receive the input clock signal and to output one or more count values; and an output circuit configured to generate a digital output based on the output voltage from the voltage-based frequency monitoring circuit when the input clock frequency is within a first frequency set and based on the one or more count values ​​from the coarse frequency monitoring circuit when the input clock frequency is within a second frequency set different from the first frequency set.

[0081] According to another embodiment, the voltage-based frequency monitoring circuit includes: a comparator; a capacitor coupled to a first input terminal of the comparator; a resistor selectively coupled to a second input terminal of the comparator; and a first switch configured to selectively deliver a reference current to the capacitor; and a second switch configured to selectively deliver the reference current to the resistor.

[0082] According to another embodiment, the voltage-based frequency monitoring circuit includes: an analog-to-digital converter; a capacitor coupled to a first input terminal of the analog-to-digital converter; a resistor selectively coupled to a second input terminal of the analog-to-digital converter; and a first switch configured to selectively deliver a reference current to the capacitor; and a second switch configured to selectively deliver the reference current to the resistor.

[0083] According to another embodiment, the coarse frequency monitoring circuit includes: a reference counter, which is configured to receive a reference clock signal and output a completion signal; and an input clock counter, which is configured to receive the input clock signal, receive the completion signal from the reference counter, and generate a count value for calculating the input clock frequency.

[0084] According to another embodiment, the circuit includes a ring oscillator configured to generate the reference clock signal.

[0085] According to one embodiment, a frequency monitoring circuit is provided, which includes: an analog-to-digital converter (ADC) having a first ADC input terminal and a second ADC input terminal; a first capacitor, which is coupled to the first ADC input terminal; a resistor, which is selectively coupled to the second ADC input terminal; a second capacitor, which is coupled to the second ADC input terminal; a first switch, which is configured to pass a reference current to the first capacitor; a second switch, which is configured to pass the reference current to the resistor; and a third switch, which is configured to discharge the first capacitor.

[0086] The foregoing is merely illustrative and various modifications may be made to the embodiments described. The foregoing embodiments may be implemented individually or in any combination.

Claims

1. A frequency monitoring circuit, the frequency monitoring circuit comprising: a comparator having a first comparator input and a second comparator input; a capacitor coupled to the first comparator input terminal; a resistor selectively coupled to the second comparator input; and A current source is configured to provide a reference current to the capacitor during a first time period and to provide the reference current to the resistor during a second time period different from the first time period.

2. The frequency monitoring circuit according to claim 1, further comprising: a first switch coupled between the current source and the capacitor; and A second switch is coupled between the current source and the resistor.

3. The frequency monitoring circuit of claim 2, wherein the first switch is controlled by a control signal, and wherein the second switch is controlled by an inverted version of the control signal.

4. The frequency monitoring circuit according to claim 2, further comprising: A third switch is coupled between the resistor and the second comparator input terminal.

5. The frequency monitoring circuit according to claim 4, further comprising: A fourth switch is configured to reset the capacitor.

6. The frequency monitoring circuit according to claim 5, further comprising: An additional capacitor is coupled to the second comparator input.

7. The frequency monitoring circuit according to claim 5, further comprising: A clock phase generator is configured to receive an input clock signal having an input clock frequency and is configured to output a signal for controlling the first switch, the second switch, the third switch, and the fourth switch.

8. The frequency monitoring circuit of claim 7, wherein the comparator is configured to output a first voltage in response to detecting that the input clock frequency is greater than a reference frequency, and to output a second voltage different from the first voltage in response to detecting that the input clock frequency is less than the reference frequency.

9. The frequency monitoring circuit according to claim 7, further comprising: A clock dithering circuit is configured to dither the input clock signal provided to the clock phase generator.

10. The frequency monitoring circuit of claim 1, wherein the resistor comprises a polysilicon resistor and a metal resistor.

11. The frequency monitoring circuit according to claim 1, further comprising: a first auto-zero switch coupled across the second comparator input and an output of the comparator; a second auto-zero switch having a first terminal coupled to the first comparator input and having a second terminal coupled to the second comparator input; and An auto-zero capacitor is coupled to the second comparator input.

12. The frequency monitoring circuit according to claim 1, further comprising: A trimming circuit is configured to tune the capacitor using a calibration setting.

13. The frequency monitoring circuit according to claim 1, further comprising: A self-test circuit is configured to selectively couple the second comparator input to a corresponding tap point along the resistor ladder.

14. The frequency monitoring circuit according to claim 1, further comprising: a reset pulse generator coupled to the comparator and configured to generate an output signal for discharging the capacitor; and A dynamic element matching circuit is configured to selectively provide two different reference currents to the capacitor and the resistor.

15. A circuit, comprising: a voltage-based frequency monitoring circuit configured to receive an input clock signal having an input clock frequency and to generate a corresponding output voltage having a first value when the input clock frequency is greater than a reference frequency and a second value when the input clock frequency is less than the reference frequency; a coarse frequency monitoring circuit configured to receive the input clock signal and output one or more count values; and an output circuit configured to generate a digital output based on the output voltage from the voltage-based frequency monitoring circuit when the input clock frequency is within a first frequency set and based on the one or more count values ​​from the coarse frequency monitoring circuit when the input clock frequency is within a second frequency set different from the first frequency set.

16. The circuit of claim 15, wherein the voltage-based frequency monitoring circuit comprises: Comparator; a capacitor coupled to a first input terminal of the comparator; a resistor selectively coupled to a second input terminal of the comparator; and a first switch configured to selectively deliver a reference current to the capacitor; and A second switch is configured to selectively deliver the reference current to the resistor.

17. The circuit of claim 15, wherein the voltage-based frequency monitoring circuit comprises: Analog-to-digital converters; a capacitor coupled to a first input terminal of the analog-to-digital converter; a resistor selectively coupled to a second input terminal of the analog-to-digital converter; and a first switch configured to selectively deliver a reference current to the capacitor; and A second switch is configured to selectively deliver the reference current to the resistor.

18. The circuit of claim 15, wherein the coarse frequency monitoring circuit comprises: a reference counter configured to receive a reference clock signal and output a completion signal; and An input clock counter is configured to receive the input clock signal, receive the completion signal from the reference counter, and generate a count value for calculating the input clock frequency.

19. The circuit of claim 18, further comprising: A ring oscillator is configured to generate the reference clock signal.

20. A frequency monitoring circuit, the frequency monitoring circuit comprising: an analog-to-digital converter (ADC) having a first ADC input and a second ADC input; a first capacitor coupled to the first ADC input terminal; a resistor selectively coupled to the second ADC input terminal; a second capacitor coupled to the second ADC input terminal; a first switch configured to pass a reference current to the first capacitor; a second switch configured to pass the reference current to the resistor; and A third switch is configured to discharge the first capacitor.

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