Scalable power transfer system

Abstract

A power delivery system included in a computer system uses multiple power converter circuits to generate respective voltage levels on multiple power supply nodes. The power delivery system includes a buck power converter circuit that generates a voltage level for use by a host power converter circuit and follower power converter circuits. The host power converter circuit generates an external demand current that is shared by the multiple follower power converter circuits to regulate the voltage levels on the multiple power supply nodes. By adjusting the number of follower power converter circuits, the power delivery system can be scaled to different platforms of the computer system.

Description

BACKGROUND TECHNICAL FIELD

[0002] The present disclosure relates to power management in computer systems, and more specifically to regulator circuit operation.

[0003] RELATED ART

[0004] Modern computer systems can include multiple circuit blocks designed to perform various functions. For example, such circuit blocks can include processors, or processor cores, configured to execute software or program instructions. Additionally, circuit blocks can include memory circuits, mixed-signal or analog circuits, etc.

[0005] In some computer systems, circuit blocks can be designed to operate using different power supply voltage levels. For example, in some computer systems, a power management integrated circuit (also referred to as a “power management unit”) can generate and monitor various power supply signals.

[0006] Power management circuits typically include one or more power converter circuits configured to generate a regulator voltage level on a respective power supply signal line using a voltage level of an input power supply signal. Such converter circuits can employ multiple reactive circuit elements, such as inductors, capacitors, etc. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A block diagram illustrating an embodiment of a power delivery system for a computer system is shown.

[0008] Figure 2 A block diagram illustrating another embodiment of a power delivery system is shown.

[0009] Figure 3 A block diagram illustrating different embodiments of a power delivery system is shown.

[0010] Figure 4 A block diagram illustrating an embodiment of a host power converter circuit is shown.

[0011] Figure 5 A block diagram illustrating an embodiment of a follower power converter circuit is shown.

[0012] Figure 6 A block diagram illustrating an embodiment of a phase circuit included in a power converter circuit is shown.

[0013] Figure 7 A block diagram illustrating a control circuit for a phase circuit included in a power converter circuit is shown.

[0014] Figure 8 A block diagram illustrating an embodiment of a power delivery system for driving multiple regulated power supply nodes is shown.

[0015] Figure 9 FIG. illustrates a diagram of a possible power delivery system configuration utilizing a power converter circuit capable of driving multiple regulated power supply nodes.

[0016] Figure 10 FIG. illustrates a flowchart depicting an embodiment of a method for operating a power converter system having an initial power converter stage.

[0017] Figure 11 FIG. illustrates a flowchart depicting an embodiment of a method for operating a power converter system without an initial power converter stage.

[0018] Figure 12 FIG. illustrates a block diagram of a computer system including a system on a chip and multiple power converter circuits.

[0019] Figure 13 is a block diagram of a system on a chip.

[0020] Figure 14 is a block diagram of an embodiment of a computer system.

[0021] Figure 15 FIG. illustrates an example of a non-transitory computer-readable storage medium storing circuit design information.

[0022] While embodiments described in this disclosure can be susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the claims. DETAILED DESCRIPTION

[0023] A computer system can include multiple circuit blocks configured to perform specific functions. Such circuit blocks can be fabricated on a common substrate and can employ different power supply voltage levels. A power management unit, often referred to as a “PMU,” can include multiple power converter circuits or regulator circuits configured to generate regulated voltage levels for various power supply signals. Such regulator circuits can employ both passive circuit elements (e.g., inductors, capacitors, etc.) and active circuit elements (e.g., transistors, diodes, etc.).

[0024] Based on power requirements of the load circuit, available circuit area, etc., different types of regulator circuits can be employed. One commonly used type of regulator circuit is a buck converter circuit. Such converter circuits include a plurality of switches (also referred to as “power switches”) and a switching node that is coupled to a regulated supply node via an inductor. One switch is coupled between an input supply node and the switching node and is referred to as a “high-side switch.” Another switch is coupled between the switching node and a ground supply node and is referred to as a “low-side switch.”

[0025] When the high-side switch is closed (referred to as “on-time”), energy is applied to the inductor, causing an increase in current through the inductor. During this time, the inductor stores energy in the form of a magnetic field. When the high-side switch is opened and the low-side switch is closed (referred to as “off-time”), energy is no longer applied to the inductor, and the voltage across the inductor reverses, causing the inductor to act as a current source, with the energy stored in the magnetic field of the inductor supporting current flow into the load. The process of closing and opening the high-side and low-side switches is performed periodically to maintain a desired voltage level on the supply node.

[0026] Power converter circuits can employ different regulation modes to determine the periodicity and duration of on-time and off-time. As used herein, a regulation mode refers to a particular method of detecting operating conditions to determine the frequency and duration of on-time and off-time employed by a power converter circuit. For example, a power converter can detect a maximum current flowing through its inductor to determine the end of an on-time period. This type of regulation mode is referred to as “peak current regulation mode.” Alternatively, a power converter circuit can detect a minimum current flowing through its inductor to determine the end of an off-time period. This type of regulation mode is referred to as “valley current regulation mode.”

[0027] As the level of integration increases, power converter circuits are required to supply increasing amounts of current to load circuits. For example, in some cases, power converter circuits are required to be capable of supplying 100 A or more to a load circuit. In some cases, to allow for the increase in load current, higher voltage input supplies (e.g., batteries) can be employed, further complicating the design of the power converter circuit to allow for higher input voltages.

[0028] Existing power converter circuit solutions are limited by thermal budgets, packaging requirements, and input voltage. As a result, the scalability of current power converter circuit designs is limited and inefficient for large current applications. Furthermore, the efficiency of the power converter circuit must be maintained at lower loads, and the design of the power converter circuit must be flexible to allow for changes in current requirements at later stages of the design process, as well as to support different numbers of regulated supply nodes on different platforms, such as tablets, laptops, etc.

[0029] The techniques described in this disclosure allow for power delivery systems that employ a host power converter circuit that generates a shared demand current used by multiple follower power converter circuits. As computer system designs evolve, the shared demand current makes it easy to add or subtract follower power converter circuits to accommodate changes in load current. Using such host power converter circuits and follower power converter circuits will allow a single set of power converter circuits to be used to support multiple power delivery platforms. Additionally, an initial buck power converter circuit can be employed to accommodate higher input voltage sources in certain power delivery platforms.

[0030] Turning to Figure 1 , a block diagram of a power converter system is depicted. As shown, the power delivery system 100 includes a power converter circuit 101, a host power converter circuit 102, a follower power converter circuit 103, and inductors 104-106. Note that the power converter circuit 101, the host power converter circuit 102, and the follower power converter circuit 103 can be located on a common integrated circuit. In some cases, the inductors 104-106 can also be located on the common integrated circuit. Alternatively, the inductors 104-106 can be located on different integrated circuits or mounted on a circuit board or other substrate on which the common integrated circuit is located. In some embodiments, one or more of the inductors 104-106 can be mounted on the common integrated circuit, e.g., as a chiplet.

[0031] The power converter circuit 101 is coupled to a converter power supply node 111 via an inductor 106 and is configured to generate a particular voltage level on the converter power supply node 111 using a voltage level of an input power supply node 107. In various embodiments, the particular voltage level is less than the voltage level of the input power supply node 107. The power converter circuit 101 can be referred to as a “buck power converter” because it generates a lower voltage for other power converter circuits, such as the host power converter circuit 102 and the follower power converter circuit 103, that are unable to employ the higher voltage level of the input power supply node 107.

[0032] In various embodiments, the power converter circuit 101 can be implemented as a buck converter circuit that employs peak current regulation or valley current regulation. While the power converter circuit 101 is depicted as being coupled to the converter power supply node 111 via a single inductor, in other embodiments, the power converter circuit 101 can include multiple phase circuits that are each coupled to the converter power supply node 111 via a corresponding inductor.

[0033] The host power converter circuit 102 is coupled to the regulated power supply node 108 via the inductor 104. In various embodiments, the host power converter circuit 102 is configured to generate the internal demand current 117 and the external demand current 115 using (e.g., based on) the voltage level of the regulated power supply node 108 and the reference voltage 118. In some embodiments, the host power converter circuit 102 is also configured to generate the enable signal 116 using the voltage level of the regulated power supply node 108 and the reference voltage 118. The host power converter circuit 102 is also configured to source the current 112 to the regulated power supply node 108 using the voltage level of the converter power supply node 111 based on the internal demand current 117.

[0034] The follower power converter circuit 103 is coupled to the regulated power supply node 108 via the inductor 105. In various embodiments, the follower power converter circuit 103 is configured to source the current 113 to the regulated power supply node 108 using the voltage level of the converter power supply node 111 based on the external demand current 115. As described below, the follower power converter circuit 103 is also configured to source the current 113 to the regulated power supply node 108 based on the enable signal 116, which can be used to activate or deactivate the follower power converter circuit 103 or individual phase circuits included within the follower power converter circuit 103.

[0035] While only a single follower power converter circuit is depicted in Figure 1 In other embodiments, multiple follower power converter circuits can be employed. In such cases, each of the multiple follower power converter circuits share the external demand current 115, which provides a desired amount of output current per phase for the multiple follower power converter circuits. Sharing the external demand current 115 in this manner allows for easy scaling of the power delivery system by adding or subtracting follower power converter circuits to be able to source a desired amount of current to a particular regulated power supply node. In some embodiments, a follower power converter circuit (e.g., the follower power converter circuit 103) is characterized as a follower power converter circuit because it is configured to receive one or more enable signals (e.g., the enable signal 116) and / or receive an external demand current (e.g., the external demand current 115) from a host power converter circuit (e.g., the host power converter circuit 102).

[0036] In some cases, follower power converter circuits capable of using higher input voltages can be included in the power delivery system. Figure 2A block diagram depicting another embodiment of a power delivery system is shown. As shown, the power delivery system 200 includes a power converter circuit 201, a host power converter circuit 202, follower power converter circuits 203 and 204, and inductors 205-208.

[0037] The power converter circuit 201 is coupled to the converter power supply node 216 via the inductor 208, and is configured to generate a particular voltage level on the converter power supply node 216 using a voltage level of the input power supply node 107. In various embodiments, the particular voltage level is less than the voltage level of the input power supply node 107. In some embodiments, the power converter circuit 201 can correspond to the power converter circuit 101 as depicted in the embodiment of Figure 1

[0038] The host power converter circuit 202 is coupled to the regulated power supply node 108 via the inductor 205. In various embodiments, the host power converter circuit 202 is configured to generate an internal demand current (such as the internal demand current 117 described above with respect to Figure 1 Figure 1 In some embodiments, the host power converter circuit 202 is also configured to generate the enable signal 116 using the voltage level of the regulated power supply node 108 and the reference voltage. The host power converter circuit 202 is also configured to source a current 212 to the regulated power supply node 108 using a voltage level of the converter power supply node 216 based on the internal demand current. In various embodiments, the host power converter circuit 202 can correspond to the host power converter circuit 102 as depicted in the embodiment of Figure 1

[0039] The follower power converter circuit 203 is coupled to the regulated power supply node 108 via the inductor 206. In various embodiments, the follower power converter circuit 203 is configured to source a current 213 to the regulated power supply node 108 using a voltage level of the converter power supply node 216 based at least in part on the external demand current 115. In some embodiments, the follower power converter circuit 203 can correspond to the follower power converter circuit 103 as depicted in the embodiment of Figure 1

[0040] ​​​​The follower power converter circuit 204 is coupled to the regulated power supply node 108 via the inductor 207. In various embodiments, the follower power converter circuit 204 is configured to use the voltage level of the input power supply node 107 to supply a current 214 to the regulated power supply node 108 based on the external demand current 115. In some embodiments, the follower power converter circuit 204 is further configured to supply the current 214 to the regulated power supply node 108 based on the enable signal 116, which can be used to activate or deactivate the follower power converter circuit 204 or individual phase circuits included within the follower power converter circuit 204.

[0041] Although only two follower power converter circuits are depicted in Figure 2 , in other embodiments, more than 2 follower power converter circuits can be employed. The additional power converter circuits can use the voltage level of the input power supply node 107 or the converter power supply node 216 to supply a respective current to the regulated power supply node 108.

[0042] In some cases, in a computer system, the host power converter circuit and the follower power converter circuits can have an input power supply with a suitable voltage. In such cases, a step-down power converter circuit is not needed to generate a lower voltage level for the host power converter circuit and the follower power converter circuits. Turning to Figure 3 , a block diagram of an embodiment of a power delivery system without a step-down power converter circuit is depicted. As shown, the power delivery system 300 includes a host power converter circuit 301, follower power converter circuits 302 and 303, and inductors 304-306.

[0043] The host power converter circuit 301 is coupled to the regulated power supply node 108 via the inductor 304. In various embodiments, the host power converter circuit 301 is configured to use the voltage level of the regulated power supply node 108 and the reference voltage 118 to generate the internal demand current 117 and the external demand current 115. In some embodiments, the host power converter circuit 301 is further configured to use the voltage level of the regulated power supply node 108 and the reference voltage 118 to generate the enable signal 116. The host power converter circuit 301 is further configured to use the voltage level of the input power supply node 313 to supply a current 310 to the regulated power supply node 108 based on the internal demand current 117. Note that in various embodiments, the voltage level of the input power supply node 313 is less than the voltage level of the input power supply node 107 as shown in Figure 1 and Figure 2 .

[0044] Follower power converter circuit 302 is coupled to regulated power node 108 via inductor 305. In various embodiments, follower power converter circuit 302 is configured to supply current 311 to regulated power node 108 using the voltage level of input power node 313 based on external demand current 115. As described below, follower power converter circuit 302 is also configured to supply current 311 to regulated power node 108 based on an enable signal 116, which can be used to activate or deactivate follower power converter circuit 302 or various phase circuits included within follower power converter circuit 302.

[0045] Follower power converter circuit 303 is coupled to regulated power node 108 via inductor 306. In various embodiments, follower power converter circuit 303 is configured to supply current 312 to regulated power node 108 using the voltage level of input power node 313 based on external demand current 115. As described below, follower power converter circuit 303 is also configured to supply current 312 to regulated power node 108 based on an enable signal 116, which can be used to activate or deactivate follower power converter circuit 303 or various phase circuits included within follower power converter circuit 303.

[0046] Although Figure 2 The proposed implementation depicts only two follower power converter circuits, but in other implementations, any suitable number of follower power converter circuits may be used. In some cases, the number of follower power converter circuits may be based on the maximum load current to be drawn from the regulated power supply node 108.

[0047] Go to Figure 4 A block diagram of a host power converter circuit is depicted. As shown, the host power converter circuit 400 includes a control circuit 401, phase circuits 402A and 402B, a feedback circuit 403, and a multiplexing circuit 408. Note that in various embodiments, the host power converter circuit 400 may correspond to host power converter circuit 102, host power converter circuit 202, or host power converter circuit 301.

[0048] Both phase circuits 402A and 402B are coupled to a power supply node 405. In various embodiments, the power supply node 405 can correspond to the input power supply node 107, the converter power supply node 111, the converter power supply node 216, or the input power supply node 313. As described below, the phase circuits 402A and 402B can include switching devices configured to couple the switching nodes 404A and 404B to the power supply node 405 to source the currents 406A and 406B, respectively. Note that in various embodiments, the switching nodes 404A and 404B can correspond to any of the switching nodes 109, 110, 209-211, or 307-309. While only two phase circuits are depicted in the embodiment of FIG. 4, in other embodiments, any suitable number of phase circuits can be employed. Figure 4

[0049] The phase circuit 402A is configured to source the current 406A to the switching node 404A based on the selected demand current 411 and a particular enable signal of the enable signals 116 received, for example, from the control circuit 401. In a similar manner, the phase circuit 402B is configured to source the current 406B to the switching node 404B based on the selected demand current 411 and a different enable signal of the enable signals 116. In various embodiments, the phase circuits 402A and 402B are active when their corresponding enable signals 116 are active. In the event that one or both of the corresponding enable signals 116 are inactive, the phase circuits 402A and 402B remain inactive or in a standby state.

[0050] The control circuit 401 is configured to generate the internal demand current 117 and the external demand current 115 based on the voltage level of the regulated power supply node 108. In various embodiments, to generate the internal demand current 117 and the external demand current 115, the control circuit 401 is further configured to perform a comparison of the feedback signal 407 and the reference voltage 118; and use the result of the comparison to generate the internal demand current 117 and the external demand current 115. In other embodiments, the control circuit 401 is further configured to use the result of the comparison to generate the enable signals 116. As described below, the control circuit 401 can be implemented using a combination of analog and digital circuits.

[0051] ​The feedback circuit 403 is configured to generate a feedback signal 407 based on the voltage level of the regulated supply node 108. In various embodiments, the voltage level of the feedback signal 407 can be less than the voltage level of the regulated supply node 108. By scaling the voltage level of the regulated supply node 108 before comparing it to the reference voltage 118, the regulated supply node 108 can be regulated to a voltage level that is higher than the reference voltage 118. In various embodiments, the feedback circuit 403 can be implemented using a resistive voltage divider circuit or any other suitable circuit configured to scale an input voltage level to generate an output voltage level.

[0052] The multiplexing circuit 408 is configured to generate a selected demand current 411 by selecting one of the alternative demand current 409 or the internal demand current 117. In various embodiments, the multiplexing circuit 408 is further configured to select one of the alternative demand current 409 or the internal demand current 117 based on the value of the control signal 410. By providing an alternative to the internal demand current 117, the host power converter circuit 400 can be used as a follower power converter circuit by varying the value of the control signal 410. In some embodiments, the multiplexing circuit 408 can be implemented using a plurality of pass-gate circuits coupled together in a wired-OR fashion and controlled by the control signal 410.

[0053] Turning to Figure 5 , a block diagram of a follower power converter circuit is depicted. As shown, the follower power converter circuit 500 includes a phase circuit 501 and a phase circuit 502. In various embodiments, the follower power converter circuit 500 can correspond to any of the follower power converter circuits 103, 203, 204, 302, and 303.

[0054] Both the phase circuit 501 and the phase circuit 502 are coupled to a supply node 503. In some embodiments, as described above, the supply node 503 can correspond to an output node of a power converter circuit or a buck converter (e.g., the converter supply node 216 of the power converter circuit 201) or an input supply node of a system such as described above with respect to the host power converter circuit 100. Figure 3The depicted input supply node 313). As described below, phase circuits 501 and 502 can include switching devices configured to couple switching nodes 504 and 505 to supply node 503 to source currents 509 and 510. Phase circuit 501 is configured to source current 509 to switching node 504 based on external demand current 506 and enable signal 507. In a similar manner, phase circuit 502 is configured to source current 510 to switching node 505 based on external demand current 506 and enable signal 508. In various embodiments, phase circuits 501 and 502 function when enable signals 507 and 508 are active. In the event that one or both of enable signals 507 and 508 are inactive, the corresponding one of phase circuits 501 and 502 remains inactive or in a standby state.

[0055] In various embodiments, phase circuits 501 and 502 can operate in a peak current regulation mode or a valley current regulation mode. In the peak current regulation mode, phase circuits 501 and 502 stop sourcing currents 509 and 510 when the values of these currents match the value of external demand current 506. Alternatively, in the valley current regulation mode, phase circuits 501 and 502 can stop their respective off times based on a comparison of external demand current 506 to currents 509 and 510. For example, in some embodiments, phase circuits 501 and 402 can stop their respective off times in response to determining that currents 509 and 510 are less than external demand current 506.

[0056] Note that while two phase circuits are depicted in the embodiments of Figure 5 , in other embodiments, any suitable number of phase circuits can be employed. In some cases, two of the phase circuits can be coupled to a common regulated supply node via a set of inductors that share a common core, referred to as “coupling inductors.”

[0057] Turning to Figure 6 , a block diagram of an embodiment of a phase circuit is depicted. As shown, phase circuit 600 includes drive circuit 601, device 608, device 609, latch circuit 602, comparator circuit 606, slope compensation circuit 605, and current sensor circuit 603. In various embodiments, phase circuit 600 can correspond to any of phase circuits 402A-B, 501, or 502.

[0058] Device 608 is coupled between input supply node 610 and switch node 607 and is controlled by control signal 620. In a similar manner, device 609 is coupled between switch node 607 and ground supply node 611 and is controlled by control signal 621. In various embodiments, switch node 607 can be further coupled to an inductor, which in turn is coupled to regulated supply node.

[0059] In response to activation of control signal 620, device 608 is configured to couple input supply node 610 to switch node 607, thereby allowing current to flow through into the inductor, thereby magnetizing the inductor. In response to activation of control signal 621, device 609 is configured to couple switch node 607 to ground supply node 611. With switch node 607 coupled to ground supply node 611, energy is no longer supplied to the inductor, thereby causing the magnetic field of the inductor to collapse. When the magnetic field collapses, the inductor acts as a current source, thereby providing current to the regulated supply node.

[0060] In various embodiments, device 608 can be implemented as a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAAFET), or any other suitable transconductance device. In some embodiments, device 609 can be implemented as an n-channel MOSFET, a FinFET, a GAAFET, or any other suitable transconductance device.

[0061] Drive circuit 601 is configured to generate control signal 620 and control signal 621 using control signal 617. In various embodiments, drive circuit 601 can be configured to activate control signal 620 and deactivate control signal 621 in response to activation of control signal 617. Drive circuit 601 can be further configured to deactivate control signal 620 and activate control signal 621 in response to deactivation of control signal 617. In some embodiments, drive circuit 601 can include any suitable combination of logic gates, sequential logic circuit elements, MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices.

[0062] The latch circuit 602 is configured to disable the control signal 617 using the reset signal 612, the set signal 618, and the enable signal 622. In some embodiments, the latch circuit 602 is configured to activate the control signal 617 in response to activation of the set signal 618 while the enable signal 622 is active, and to disable the control signal 617 in response to activation of the reset signal 612 while the enable signal 622 is active. In various embodiments, the reset signal 612 can be a clock signal or other suitable timing reference signal. The latch circuit 602 is configured to disable the control signal 617 in response to determining that the enable signal 622 is inactive. In various embodiments, the latch circuit 602 can be implemented as a set-reset (SR) latch circuit comprising any suitable combination of logic gates.

[0063] The current sensor circuit 603 is configured to generate the inductor current 616. In various embodiments, the current sensor circuit 603 can measure a voltage drop across the device 609, and use the measured voltage drop to generate the inductor current 616. The current sensor circuit 603 can comprise any suitable combination of reference circuits and amplifier circuits.

[0064] The slope compensation circuit 605 is configured to modify the inductor current 616. In various embodiments, the slope compensation circuit 605 can be configured to combine a periodic current ramp with the inductor current 616 in a process referred to as “slope compensation.” Note that slope compensation is used to improve stability of the phase circuit 600 by increasing a frequency at which the voltage regulator feedback loop is operable, thereby reducing a time for the phase circuit 600 to recover from transients.

[0065] The comparator circuit 606 is configured to generate the set signal 618 using the demand current 614 and the inductor current 616. Note that the demand current 614 can correspond to the internal demand current 117, the external demand current 115, or any other suitable demand current. In some embodiments, the comparator circuit 606 can be configured to compare the demand current 614 to the inductor current 616, and to activate the set signal 618 in response to determining that the demand current 614 is less than the inductor current 616. In various embodiments, the comparator circuit 606 can be implemented using a differential amplifier circuit, a Schmitt trigger circuit, or any other suitable comparator circuit.

[0066] Turning to Figure 7 , a block diagram of an embodiment of the control circuit 401 is depicted. As shown, the control circuit 401 includes an error amplifier 701, a management circuit 702, a current comparison circuit 703, and a logic circuit 711.

[0067] The error amplifier 701 is configured to generate a demand current 705 using the reference voltage 704 and the feedback signal 407. In various embodiments, the value of the feedback signal 407 can be based on the voltage level of the regulated power supply node 108. In various embodiments, the error amplifier 701 can be configured to generate the demand current 705 such that the value of the demand current 705 is proportional to the difference between the reference voltage 704 and the feedback signal 407. In some embodiments, the error amplifier 701 can be implemented using a differential amplifier circuit or any other suitable comparator circuit.

[0068] The management circuit 702 is configured to generate the external demand current 115 and the internal demand current 117 using the demand current 705. While a single external demand current and a single internal demand current are depicted in the embodiment of FIG. 7, in other embodiments, the management circuit 702 can be configured to generate any suitable number of internal demand currents and external demand currents. In some embodiments, the management circuit 702 can be configured to scale the demand current 705 in order to generate the external demand current 115 and the internal demand current 117. In various embodiments, the management circuit 702 can include any suitable combination of current mirror circuits, amplifier circuits, and biasing circuits. Figure 7

[0069] The current comparison circuit 703 is configured to generate the comparison signal 709 using the sensed currents 708 and the current thresholds 707. Note that the sensed currents 708 can correspond to the currents flowing in the inductors 104 and 105. In various embodiments, the current comparison circuit 703 can be configured to compare a given sensed current in the sensed currents 708 to a corresponding current threshold in the current thresholds 707 to generate a particular comparison signal in the comparison signal 709.

[0070] In various embodiments, the current comparison circuit 703 can be implemented using multiple differential amplifier circuits or other comparator circuits with resistors coupled to their respective inputs in order to convert the current thresholds 707 and the sensed currents 708 to voltages for comparison. In some embodiments, additional circuitry (e.g., a Schmitt trigger circuit) can be used to convert the outputs of the differential amplifier circuits to digital values for the comparison signal 709.

[0071] ​The logic circuit 711 is configured to use the comparison signals 709 to generate the enable signals 116. In various embodiments, the logic circuit 711 can be configured to activate a given one of the enable signals in response to determining that the number of comparison signals 709 has exceeded a threshold. For example, if two of the enable signals are in an active state, and the comparison signals of the two phase circuits coupled to the active enable signals are in an active state, the current limit of the two phase circuits has been reached, and the logic circuit 711 can activate a third enable signal to activate a third phase circuit. By generating the enable signals 116 in this way, an increase or decrease in the load current drawn from the regulated supply node 108 causes a corresponding increase or decrease in the number of active phase circuits. Adjusting the number of active phase circuits can ensure that a sufficient number of phase circuits are in an active state to supply the required current and prevent an undesirable drop in the voltage level of the regulated supply node 108.

[0072] In various embodiments, the logic circuit 711 can be implemented using any suitable combination of combinational logic circuits and sequential logic circuits. In some cases, the logic circuit 711 can be implemented as a microcontroller or general purpose processor circuit configured to execute software or program instructions.

[0073] In some cases, a power converter circuit can be used to regulate voltage levels on multiple supply nodes. To implement this, the power converter circuit can use the respective voltage levels of the multiple supply nodes to generate a plurality of internal demand currents. By using a multiplexing circuit, a single power converter circuit can be used in various environments, each having a different number of regulated supply nodes.

[0074] Figure 8 A block diagram of an embodiment of a power delivery system capable of supporting multiple regulated supply nodes is depicted in FIG. 8. As shown, the power delivery system 800 includes phase circuits 801A-801B, phase circuits 802A-802B, feedback circuits 803 and 804, comparator circuits 805 and 806, a memory circuit 807, and a multiplexing circuit 808. Note that in some embodiments, the functionality associated with selecting a particular demand current from a plurality of demand currents can be employed in a host power converter circuit or a follower power converter circuit as described above.

[0075] Phase circuits 801A and 801B are coupled to regulated supply node 811 via inductors 809A and 809B, respectively. In a similar manner, phase circuits 802A and 802B are coupled to regulated supply node 812 via inductors 810A and 810B, respectively. Phase circuits 801A and 801B are configured to source respective currents to regulated supply node 811 based on selected current 819 and using a voltage level of supply node 813. Phase circuits 802A and 802B are configured to source respective currents to regulated supply node 812 based on demand current 818 and using a voltage level of supply node 813. In various embodiments, phase circuits 801A, 801B, 802A, and 802B can correspond to phase circuits 600 as depicted in FIG. 6. Figure 6

[0076] In the illustrated embodiment, since phase circuits 801A and 801B are coupled to different regulated supply nodes than phase circuits 802A and 802B, control bit 820 is selected so that multiplexing circuit 808 selects demand current 817 as selected current 819. In other embodiments, if phase circuits 801A and 801B are coupled to the same regulated supply nodes as phase circuits 802A and 802B, control bit 820 is selected so that multiplexing circuit 808 selects demand current 818 as selected current 819.

[0077] Feedback circuit 803 is configured to generate feedback signal 815 using a voltage level of regulated supply node 811. In a similar manner, feedback circuit 804 is configured to generate feedback signal 816 using a voltage level of regulated supply node 812. In various embodiments, a voltage level of feedback signal 815 can be less than a voltage level of regulated supply node 811, and a voltage level of feedback signal 816 can be less than a voltage level of regulated supply node 812. In various embodiments, feedback circuit 803 and feedback circuit 804 can be implemented using resistive divider circuits or other suitable circuits.

[0078] Comparator circuit 805 is configured to generate demand current 817 using feedback signal 815 and reference voltage 823. In some embodiments, to generate demand current 817, comparator circuit 805 is further configured to perform a comparison of feedback signal 815 and reference voltage 823, and to use a result of the comparison to generate demand current 817.

[0079] Comparator circuit 806 is configured to generate demand current 818 using feedback signal 816 and reference voltage 814. In some embodiments, to generate demand current 818, comparator circuit 806 is further configured to perform a comparison of feedback signal 816 and reference voltage 814, and to use a result of the comparison to generate demand current 818.​

[0080] In various implementations, comparator circuit 805 and comparator circuit 806 can be implemented as operational transconductance amplifier (OTA) circuits or any other suitable comparator circuit. Although two comparator circuits are depicted in the implementation of FIG. 8, in other implementations, any suitable number of comparator circuits can be employed. In some cases, the number of comparator circuits included in power delivery system 800 can be based on the number of regulated power supply nodes that the power delivery system is designed to support. Figure 8

[0081] Multiplexing circuit 808 is configured to generate a selected current 819 by selecting one of demand current 817 or demand current 818 based on control bit 820. In various implementations, multiplexing circuit 808 can be implemented using multiple pass gate circuits coupled together in a wired-OR fashion and controlled by control bit 820. Although only a single multiplexing circuit is depicted in the implementation of FIG. 8, in other implementations, any suitable number of multiplexing circuits can be employed. In some cases, the number of multiplexing circuits included in power delivery system 800 can correspond to the number of regulated power supply nodes that power delivery system 800 is capable of supporting. Figure 8

[0082] Memory circuit 807 is configured to store control bit 820. In various implementations, memory circuit 807 can be implemented as a one-time programmable memory circuit, a read-only memory (ROM) circuit, or any other suitable type of non-volatile memory circuit.

[0083] As described above, a power delivery system can be designed to support multiple regulated power supply nodes. By setting control bits (e.g., control bit 820) to route demand currents for individual regulated power supply nodes when necessary, such a power delivery system can be deployed on different power delivery platforms, each having a different number of regulated power supply nodes.

[0084] Turning to Figure 9 , the chart depicts how a power delivery system having a total of N phase circuits (where N is a positive integer) can be used to implement different power delivery platforms having different numbers of regulated power supply nodes.

[0085] Platform 904 utilizes only regulated power supply node 901. In this case, all N phase circuits included in the power delivery system are coupled to regulated power supply node 901 via corresponding inductors. As described above, control bit 820 is selected to route demand currents generated using the voltage level of regulated power supply node 901 to all phase circuits.

[0086] ​​The platform 905 utilizes regulated power supply nodes 901 and 902. As shown, A number of phase circuits are coupled to the regulated power supply node 901 and B number of phase circuits are coupled to the regulated power supply node 902. The A number of phase circuits use a demand current generated using a voltage level of the regulated power supply node 901, while the B number of phase circuits use a different demand current generated using a voltage level of the regulated power supply node 902. Note that in some embodiments, a total of N number of phase circuits can be evenly distributed among the A number of phase circuits and the B number of phase circuits. Alternatively, if a load current for the regulated power supply node 901 is greater than a load current for the regulated power supply node 902, more phase circuits can be included in the A number of phase circuits than in the B number of phase circuits. In some cases, based on the load currents of the regulated power supply nodes 901 and 902, some of the total of N number of phase circuits can remain unassigned to either of the regulated power supply nodes 901 and 902.

[0087] The platform 906 utilizes regulated power supply nodes 901-903. D number of phase circuits are coupled to the regulated power supply node 901, E number of phase circuits are coupled to the regulated power supply node 902, and F number of phase circuits are coupled to the regulated power supply node 903. The D number of phase circuits, the E number of phase circuits, and the F number of phase circuits use corresponding demand currents generated using respective voltage levels of the regulated power supply nodes 901-903. The number of phase circuits included in each of the D number of phase circuits, the E number of phase circuits, and the F number of phase circuits can be based on load currents of the regulated power supply nodes 901-903, respectively.

[0088] Note that, Figure 9 The different power delivery platforms depicted in the charts of FIGS. 9-11 are merely examples. In other cases, different numbers of regulated power supply nodes and different numbers of phase circuits assigned to different active regulated power supply nodes are possible and contemplated.

[0089] In summary, various embodiments of a power delivery system for a computer system are disclosed. Generally, an apparatus is contemplated in which a first power converter circuit can be configured to generate a particular voltage level on a converter power supply using a voltage level of an input power supply node. In various embodiments, the particular voltage level is less than the voltage level of the input power supply node.

[0090] A host power converter circuit coupled to a regulated power supply node via a first inductor can be configured to generate an internal demand current and an external demand current using a voltage level of the regulated power supply node and a reference voltage. The host power converter circuit can also be configured to supply a first current to the regulated power supply node using a voltage level of a converter power supply node based on the internal demand current.

[0091] The first follower power converter circuit coupled to the regulated power supply node via the second inductor can be configured to supply a second current to the regulated power supply node using the voltage level of the converter power supply node based on the external demand current. In other embodiments, the second follower power converter circuit coupled to the regulated power supply node via the third inductor can be configured to supply a third current to the regulated power supply node using the voltage level of the input power supply node based on the external demand current.

[0092] Turning to Figure 10 , a flow diagram depicting an embodiment of a method for operating a power delivery system having an initial power converter stage is illustrated. The method begins in block 1001 and can be applied to a variety of power delivery systems, including the power delivery system 100 as shown in Figure 1

[0093] The method includes generating, by the buck power converter circuit, a particular voltage level on the converter power supply node using the voltage level of the input power supply node (block 1002). In various embodiments, the particular voltage level is less than the voltage level of the input power supply node.

[0094] The method also includes generating, by the host power converter circuit, an internal demand current and an external demand current using the voltage level of the regulated power supply node and a reference voltage, where the host power converter circuit is coupled to the regulated power supply node via the first inductor (block 1003). In some embodiments, the method also includes generating, by the host power converter circuit, a plurality of enable signals using the voltage level of the regulated power supply node and the reference voltage.

[0095] In some embodiments, generating the external demand current and the internal demand current can include generating, by the host power converter circuit, a feedback signal using the voltage level of the regulated power supply node and performing, by the host power converter circuit, a comparison of the feedback signal to the reference voltage. The method can also include generating, by the host power converter circuit, the external demand current and the internal demand current using a result of the comparison.

[0096] The method also includes supplying, by the host power converter circuit and based on the internal demand current, a first current to the regulated power supply node using the voltage level of the converter power supply node (block 1004).

[0097] The method also includes supplying, by the first follower power converter circuit and based on the external demand current, a second current to the regulated power supply node using the voltage level of the converter power supply node, where the first follower power converter circuit is coupled to the regulated power supply node via the second inductor (block 1005).

[0098] ​In some embodiments, the first follower power converter circuit includes a first phase circuit coupled to the regulated power supply node via a third inductor and a second phase circuit coupled to the regulated power supply node via a fourth inductor. In this case, the method can further include supplying, by the first phase circuit, the first portion of the second current to the regulated power supply node in response to determining that a first enable signal of the plurality of enable signals has been activated. The method can further include supplying, by the second phase circuit, a second portion of the second current to the regulated power supply node in response to determining that a second enable signal of the plurality of enable signals has been activated.

[0099] In other embodiments, supplying the first portion of the second current to the regulated power supply node can include performing a comparison of the external demand current and a sensed third inductor current, and activating a driver control signal using a result of the comparison. The method can further include coupling the first terminal of the third inductor to the converter power supply node in response to activation of the driver control signal, where the second terminal of the third inductor is coupled to the regulated power supply node. The method can further include deactivating the driver control signal in response to activation of the clock signal, and coupling the first terminal of the third inductor to the ground power supply node in response to deactivation of the driver control signal.

[0100] In various embodiments, the method can further include supplying, by a second follower power converter circuit and based on the external demand current, a third current to the regulated power supply node using a voltage level of the input power supply node, where the second follower power converter circuit is coupled to the regulated power supply node via a third inductor. The method ends at block 1006.

[0101] Turning to Figure 11 , a flow diagram depicting an embodiment of a method for operating a power delivery system that does not include a step-down power converter is illustrated. The method begins in block 1101 and can be applied to various power delivery systems, including the power delivery system 300 as shown in Figure 3

[0102] The method includes generating, by the host power converter circuit, an external demand current and an internal demand current using a voltage level of the regulated power supply node and a reference voltage (block 1102). In various embodiments, the host power converter circuit is coupled to the regulated power supply node via a first inductor.

[0103] In some embodiments, generating the external demand current and the internal demand current can include generating, by the host power converter circuit, a feedback signal using the voltage level of the regulated power supply node, and performing, by the host power converter circuit, a comparison of the feedback signal and the reference voltage. The method can further include generating, by the host power converter circuit, the external demand current and the internal demand current using a result of the comparison.​

[0104] The method also includes supplying, by the host power converter circuit and based on the internal demand current, a first current to the regulated power supply node using a voltage level of the input power supply node (block 1103).

[0105] The method also includes supplying, by the follower power converter circuit and based on the external demand current, a second current to the regulated power supply node using a voltage level of the input power supply node (block 1104). In various embodiments, the follower power converter circuit is coupled to the regulated power supply node via a second inductor. The method ends in block 1105.

[0106] Turning to Figure 12 , a block diagram of a computer system including a system on a chip and multiple power converter circuits is depicted. As shown, the computer system 1200 includes a system on a chip 1201 (denoted as “SoC 1201”), power converter circuits 1202, 1203A-B, and 1204A-C, and inductors 1205, 1206A-B, and 1207A-C.

[0107] The power converter circuit 1202 is coupled to the converter power supply node 1209 via the inductor 1205 and is configured to supply a current to the converter power supply node 1209 using a voltage level of the input power supply node 1208. In various embodiments, the power converter circuit 1202 can correspond to the power converter circuit 101 as depicted in the embodiment of Figure 1

[0108] The power converter circuits 1203A and 1203B are coupled to the regulated power supply node 1210 via inductors 1206A and 1206B, respectively. In various embodiments, the power converter circuit 1203A is configured to supply a particular current to the regulated power supply node 1210 via the inductor 1206A, and the power converter circuit 1203B is configured to supply a different current to the regulated power supply node 1210 via the inductor 1206B. In some embodiments, the power converter circuit 1203A can correspond to the host power converter circuit 102, while the power converter circuit 1203B can correspond to the follower power converter circuit 103. Note that while two power converter circuits are depicted as supplying current to the regulated power supply node 1210, in other embodiments, additional power converter circuits can be employed to supply current to the regulated power supply node 1210.

[0109] ​The power converter circuits 1204A-1204C are coupled to the regulated power supply node 1211 via inductors 1207A-1207C, respectively. In various embodiments, the power converter circuit 1204A is configured to use the voltage level of the input power supply node 1208 to source a particular current to the regulated power supply node 1211. Additionally, the power converter circuits 1204B and 1204C are configured to use the voltage level of the input power supply node 1208 to source respective currents to the regulated power supply node 1211. In some embodiments, the power converter circuit 1204A can correspond to the host power converter circuit 101, while the power converter circuits 1204B and 1204C can correspond to the follower power converter circuits 103. Note that while three power converter circuits are depicted as being capable of sourcing current to the regulated power supply node 1211, in other embodiments any suitable number of power converter circuits can be employed to source current to the regulated power supply node 1211.

[0110] Although the SoC 1201 is depicted as having only two regulated power supply nodes, in other embodiments the SoC 1201 can include any suitable number of regulated power supply nodes. In such cases, additional power converter circuits can be employed to regulate the voltage levels on the regulated power supply nodes.

[0111] Figure 13 A block diagram of a system-on-a-chip (SoC) is illustrated in FIG. 13. In the illustrated embodiment, the SoC 1300 includes processor circuitry 1301, memory circuitry 1302, analog / mixed-signal circuitry 1303, and input / output circuitry 1304. The processor circuitry 1301 and the memory circuitry 1302 are coupled to a power supply node 1305, while the analog / mixed-signal circuitry 103 and the input / output circuitry 1304 are coupled to a power supply node 1306. The voltage levels on the power supply nodes 1305 and 1306 can be generated by different arrangements of power converter circuits, such as the arrangements described above. In various embodiments, the SoC 1300 can be configured for use in a desktop computer, a server, or in a mobile computing application such as, for example, a tablet computer, a laptop computer, or a wearable computing device.

[0112] In various embodiments, the processor circuitry 1301 can represent a general-purpose processor that performs computational operations. For example, the processor circuitry 1301 can be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).

[0113] In various embodiments, memory circuitry 1302 can include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Note that while a single memory circuit is exemplified in Figure 13

[0114] Analog / mixed-signal circuitry 1303 can include crystal oscillator circuitry, phase-locked loop (PLL) circuitry, analog-to-digital converter (ADC) circuitry, and digital-to-analog converter (DAC) circuitry (none shown). In other embodiments, analog / mixed-signal circuitry 1303 can be configured to perform power management tasks by including on-chip power sources and voltage regulators.

[0115] Input / output circuitry 1304 can be configured to coordinate data transfers between SoC 1300 and one or more peripheral devices. Such peripheral devices can include, without limitation, storage devices (e.g., storage devices based on magnetic or optical media, including hard disk drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, input / output circuitry 1304 can be configured to implement versions of the Universal Serial Bus (USB) protocol or IEEE 1394

[0116] Input / output circuitry 1304 can also be configured to coordinate data transfers between SoC 1300 and one or more devices coupled to SoC 1300 via a network (e.g., other computing systems or integrated circuits). In one embodiment, input / output circuitry 1304 can be configured to perform data processing required to implement the Ethernet (IEEE 802.3) networking standard, such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, although it is contemplated that any suitable networking standard could be implemented. In some embodiments, input / output circuitry 1304 can be configured to implement multiple discrete network interface ports.

[0117] Turning now to Figure 14 , various types of systems that can include any of the above-discussed circuits, devices, or systems are exemplified. Systems or devices 1400, which can incorporate or otherwise utilize one or more of the techniques described herein, can be used in a wide range of fields. For example, systems or devices 1400 can be used as part of the hardware of a system such as a desktop computer 1410, a laptop computer 1420, a tablet computer 1430, a cellular or mobile telephone 1440, or a television 1450 (or a set-top box coupled to a television). ​​

[0118] Similarly, the disclosed elements can be used in a wearable device 1460, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions— e.g., access to email, cellular service, a calendar, health monitoring, etc. A wearable device can also be designed to perform only health monitoring functions, such as monitoring a user’s vital signs, performing epidemiological functions such as contact tracing, providing communication to emergency medical services, etc. Other types of devices are also contemplated, including devices worn on the neck, devices implantable in the human body, glasses or headsets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0119] The system or device 1400 can also be used in a variety of other contexts. For example, the system or device 1400 can be used in the context of a server computer system, such as a dedicated server, or on shared hardware that implements a cloud-based service 1470. Still further, the system or device 1400 can be implemented in a wide range of specialized everyday devices, including devices commonly found in the home 1480, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). The elements can also be implemented in various modes of transportation. For example, the system or device 1400 can be used in control systems, guidance systems, entertainment systems, etc. of various types of vehicles 1490.

[0120] Figure 14 The applications exemplified in FIG. 15 are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0121] Figure 15 is a block diagram exemplifying an example of a non-transitory computer- readable storage medium storing circuit design information, in accordance with some embodiments. In the exemplified embodiment, a semiconductor manufacturing system 1520 is configured to process design information 1515 stored on a non-transitory computer- readable storage medium 1510 and manufacture an integrated circuit 1530 based on the design information 1515.

[0122] The non-transitory computer-readable storage medium 1510 can include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer- readable storage medium 1510 can be an installation medium, such as a CD-ROM, floppy disks, or tape device; computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory such as a magnetic hard drive or optical storage; registers; or other like memory elements. The non-transitory computer-readable storage medium 1510 can include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1510 can include two or more memory mediums that reside in different locations, e.g., on different computer systems that are connected over a network.

[0123] The design information 1515 can be specified using any of a variety of suitable computer languages, including hardware description languages such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1515 can be usable by the semiconductor fabrication system 1520 to fabricate at least a portion of the integrated circuit 1530. The format of the design information 1515 can be recognized by at least one semiconductor fabrication system, such as, for example, the semiconductor fabrication system 1520. In some embodiments, the design information 1515 can include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in the integrated circuit 1530 can also be included in the design information 1515. Such cell libraries can include information indicative of device or transistor level netlists, mask design data, and characterization data of cells included in the cell library, etc.

[0124] In various embodiments, the integrated circuit 1530 can include one or more custom macro cells, e.g., memory, analog or mixed-signal circuits, etc. In such cases, the design information 1515 can include information related to the included macro cells. Such information can include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data can be formatted according to Graphic Data System (GDSII) or any other suitable format.

[0125] The semiconductor fabrication system 1520 can include any of a variety of appropriate elements configured to fabricate integrated circuits. This can include, for example, elements for depositing semiconductor materials, removing materials, changing the shape of deposited materials, modifying materials (e.g., by doping materials or using ultraviolet treatment to modify the dielectric constant), etc. (e.g., on a wafer that can include a mask). The semiconductor fabrication system 1520 can also be configured to perform various tests of the fabricated circuits for correct operation.

[0126] In various embodiments, the integrated circuit 1530 is configured to operate according to a circuit design specified by the design information 1515, which can include performing any of the functions described herein. For example, the integrated circuit 1530 can include any of the various elements shown or described herein. In addition, the integrated circuit 1530 can be configured to perform the various functions described herein in connection with other components. In addition, the functionality described herein can be performed by multiple connected integrated circuits.

[0127] As used herein, the phrase “design information specifying a design of a circuit configured to…” does not imply that the referenced circuit must be fabricated in order to satisfy that element. Rather, the phrase indicates that the design information describes a circuit that, when fabricated, will be configured to perform the indicated action or will include the specified components

[0128] ***

[0129] The disclosure includes reference to “embodiments,” which are non-limiting specific implementations of the disclosed concepts. Reference to “embodiment,” “one embodiment,” “certain embodiments,” “some embodiments,” “various embodiments,” etc., are not necessarily to the same embodiment, and the inclusion of such expressions is not to be construed as a limitation on the scope of the disclosure or on the scope of the claims. Numerous possible embodiments are contemplated, including embodiments that fall within the scope of the instant disclosure and equivalents or alternatives of those embodiments. Not all of these possible embodiments can necessarily exhibit any or all of the potential advantages described herein.

[0130] Unless otherwise stated, the embodiments are not intended to be limited based on the disclosure of the form of the disclosure on which the claims are drafted, even if only a single example is described for a particular feature. Accordingly, the disclosed embodiments are intended to be illustrative, but not limiting, without any statement to the contrary. This patent application is intended to cover such alternatives, modifications and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.

[0131] Particular features, structures, or characteristics can be combined in any suitable way. Therefore, the present disclosure intends to embrace any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof. Thus, new claims can be formed during prosecution of the present application (or an application claiming priority to it) based on any such combination of features. Specifically, with respect to the claims appended to this application, features of dependent claims can be combined with features of the independent claims and features from different independent claims can be combined, in any suitable manner, and can be combined by any suitable means, not just the specific combinations listed in the appended claims.

[0132] For example, although the appended claims are drafted in the form of a single independent claim, dependent claims may

[0133] ***

[0134] Because the present disclosure is a legal document, various terms and phrases can be subject to interpretation and judicial discretion. It is hereby expressly provided that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how to interpret claims drafted based on the present disclosure.

[0135] Unless the context clearly indicates otherwise, references to the singular form “a,” “an,” and “the” are intended to refer to the plural form as well. Thus, reference to “items” in a claim is not exclusionary of additional instances of the item.

[0136] The word “may” is used herein in the permissive sense (i.e., having the potential to), and not in the mandatory sense (i.e., must). The words “include,” “including,” and “includes” are open-ended, and do not exclude additional, unrecited elements, or method steps.

[0137] The terms “comprise,” “comprising,” “include,” “including,” and “includes” are open-ended, and do not exclude additional, unrecited elements or method steps.

[0138] When the term “or” is used in the present disclosure in reference to a list of options, it will be understood, unless the context clearly indicates otherwise, that the term is used in the inclusive sense. Thus, the expression “x or y” is equivalent to “x or y, or both,” covering x but not y, y but not x, and both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in the exclusive sense.

[0139] The expressions "w, x, y, or z, or any combination thereof" or "at least one of w, x, y, and z" are intended to cover all possibilities involving up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase "at least one of w, x, y, and z" refers to at least one element of the set [w, x, y, z], thereby covering all possible combinations in the list of options. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0140] In this disclosure, various "labels" can precede nouns. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Unless otherwise noted, the labels "first," "second," and "third" when applied to a particular feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0141] Within this disclosure, different entities (which can be variously referred to as "units," "circuits," other components, etc.) can be described or claimed as "configured" to perform one or more tasks or operations. This structure— configured to [perform one or more tasks]— is used herein to refer to a structure (i.e., something physical) that is made to be arranged to perform the task(s). More specifically, this expression is used to indicate that a structure has been created or made to have one or more physical components arranged to perform the task(s). A structure can be considered "configured to" perform some task even when the structure is not currently being operated or is not currently performing that task. Thus, an entity described or recited as "configured to" perform some task refers to something physical that is made to be arranged to perform the task. It will be appreciated that the phrase "configured to" can include structures that are not currently being operated or are not currently performing that task, but are capable of being configured to perform the task. The phrase "configured to" can also include structures that are currently being operated or are currently performing that task, but are capable of being configured to perform another task.

[0142] The term "configured to" is not intended to mean "can be configured to." For example, an unprogrammed FPGA would not be considered to be "configured to" perform some specific function until it is programmed to do so. However, the unprogrammed FPGA can be "capable of being configured to" perform that function.

[0143] The recitation of "configured to" in the appended claims is expressly intended to not invoke 35 U.S.C. § 112(f) for that claim element. If the applicant wishes the claim element to invoke 112(f), it will be recited using the "means for" structure.

[0144] The phrase "based on" is used to describe one or more factors to which a determination is based. This term is not exclusive, meaning that additional factors can also influence the determination. That is, a determination can be based on only the specified factors or on the specified factors and other unspecified factors. Consider the phrase "determine A based on B." This phrase specifies that B is a factor in determining A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A can also be based on some other factors, such as C. This phrase is also intended to cover implementations in which A is determined based on B alone. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0145] The phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors can influence or otherwise trigger the effect. That is, an effect can be triggered in response to only these factors, or it can be triggered in response to the specified factors and other unspecified factors. Consider the phrase "perform A in response to B." This phrase specifies that B is a factor that triggers the performance of A. This phrase does not exclude the possibility that A can also be performed in response to some other factors, such as C. This phrase is also intended to cover implementations in which A is performed in response to B alone.

Claims

1. An apparatus comprising: a first power converter circuit configured to generate a particular voltage level on a converter power supply node based on a voltage level of an input power supply node; a host power converter circuit coupled to a regulated power supply node via a first inductor, wherein the host power converter circuit is configured to: generate an internal demand current and an external demand current using a voltage level of the regulated power supply node and a reference voltage; and supply a first current to the regulated power supply node using a voltage level of the converter power supply node; and a first follower power converter circuit coupled to the regulated power supply node via a second inductor, wherein the first follower power converter circuit is configured to supply a second current to the regulated power supply node using the voltage level of the converter power supply node.

2. The apparatus of claim 1, further comprising a second follower power converter circuit coupled to the regulated power supply node via a third inductor, wherein the second follower power converter circuit is configured to supply a third current to the regulated power supply node using the voltage level of the input power supply node.

3. The apparatus of claim 1, wherein the host power converter circuit is further configured to generate one or more enable signals using the voltage level of the regulated power supply node and the reference voltage.

4. The apparatus of claim 3, wherein the first follower power converter circuit is further configured to supply the second current to the regulated power supply node based on the one or more enable signals.

5. The apparatus of claim 3, wherein the first follower power converter circuit comprises a plurality of phase circuits coupled to the regulated power supply node via a corresponding plurality of inductors, wherein a given phase circuit of the plurality of phase circuits is configured to supply a portion of the second current to the regulated power supply node based on the external demand current and at least one of the one or more enable signals.

6. The apparatus of claim 1, wherein the host power converter circuit is further configured to: generate a feedback signal using the voltage level of the regulated power supply node; perform a comparison of the feedback signal and the reference voltage; and generate the external demand current and the internal demand current using a result of the comparison.

7. A method comprising: generating, by a host power converter circuit, an internal demand current and an external demand current using a voltage level of a regulated power supply node and a reference voltage, wherein the host power converter circuit is coupled to the regulated power supply node via a first inductor; supplying, by the host power converter circuit and based on the internal demand current, a first current to the regulated power supply node using a voltage level of an input power supply node; and ​ using the voltage level of the input supply node to supply a second current to the regulated supply node through a first follower power converter circuit coupled to the regulated supply node via a second inductor, and based on the external demand current.

8. The method of claim 7, further comprising using a voltage level of a converter supply node to supply a third current to the regulated supply node through a second follower power converter circuit coupled to the regulated supply node via a third inductor, and based on the external demand current, wherein the voltage level of the converter supply node is less than the voltage level of the input supply node.

9. The method of claim 8, further comprising generating a plurality of enable signals using the voltage level of the regulated supply node and the reference voltage by the host power converter circuit.

10. The method of claim 9, wherein the first follower power converter circuit comprises a first phase circuit coupled to the regulated supply node via a third inductor and a second phase circuit coupled to the regulated supply node via a fourth inductor, and further comprising: in response to determining that a first enable signal of the plurality of enable signals has been activated, supplying a first portion of the second current to the regulated supply node through the first phase circuit; and in response to determining that a second enable signal of the plurality of enable signals has been activated, supplying a second portion of the second current to the regulated supply node through the second phase circuit.

11. The method of claim 10, wherein supplying the first portion of the second current to the regulated supply node comprises: performing a comparison of the external demand current and a sensed third inductor current; using a result of the comparison to activate a driver control signal; and in response to activation of the driver control signal, coupling a first terminal of the third inductor to the converter supply node, wherein a second terminal of the third inductor is coupled to the regulated supply node.

12. The method of claim 11, further comprising: in response to activation of a clock signal, deactivating the driver control signal; and in response to deactivation of the driver control signal, coupling the first terminal of the third inductor to a ground supply node.

13. The method of claim 7, wherein generating the external demand current and the internal demand current comprises: generating a feedback signal using the voltage level of the regulated supply node by the host power converter circuit; performing a comparison of the feedback signal and the reference voltage by the host power converter circuit; and generating the external demand current and the internal demand current using a result of the comparison by the host power converter circuit.

14. An apparatus, comprising: a first power converter circuit coupled to a first regulated power supply node and a second regulated power supply node, wherein the first power converter circuit comprises: one or more first phase circuits coupled to the first regulated power supply node through a corresponding inductor of one or more first inductors; a plurality of second phase circuits coupled to the second regulated power supply node through a corresponding inductor of a second plurality of inductors; a first error amplifier circuit configured to generate a first demand current using a first voltage level of the first regulated power supply node and a first reference voltage; a second error amplifier circuit configured to generate a second demand current using a second voltage level of the second regulated power supply node and a second reference voltage; and a multiplexing circuit configured to select the first demand current or the second demand current using one or more control bits to generate a selected demand current; wherein the one or more first phase circuits are configured to source a corresponding current of one or more first currents to the first regulated power supply node based on the first demand current and a voltage level of a converter power supply node; and wherein the plurality of second phase circuits are configured to source a corresponding current of a plurality of second currents to the second regulated power supply node based on the selected demand current and the voltage level of the converter power supply node.

15. The apparatus of claim 14, further comprising a buck power converter circuit configured to generate a particular voltage level on the converter power supply node using a voltage level of an input power supply node, wherein the particular voltage level is less than the voltage level of the input power supply node.

16. The apparatus of claim 14, wherein the one or more first inductors comprise at least one pair of coupled inductors, wherein a particular phase circuit of the one or more first phase circuits is coupled to the first regulated power supply node via a first inductor of the at least one pair of coupled inductors, and wherein a different phase circuit of the one or more first phase circuits is coupled to the first regulated power supply node via a second inductor of the at least one pair of coupled inductors.

17. The apparatus of claim 16, further comprising: a first feedback circuit configured to generate a first feedback signal using the first voltage level of the first regulated power supply node; and a second feedback circuit configured to generate a second feedback signal using the second voltage level of the second regulated power supply node; wherein to generate the first demand current, the first error amplifier circuit is further configured to compare the first feedback signal to the first reference voltage; and wherein to generate the second demand current, the second error amplifier circuit is further configured to compare the second feedback signal to the second reference voltage.

18. The apparatus of claim 14, wherein a particular phase circuit of the one or more first phase circuits is coupled to a particular inductor of the one or more first inductors, wherein the particular phase circuit is configured to: perform a comparison of the first demand current and a sensed current in the particular inductor; use a result of the comparison to activate a driver control signal; and in response to activation of the driver control signal, couple a first terminal of the particular inductor to the converter power node, wherein a second terminal of the particular inductor is coupled to the first regulated power supply node.

19. The apparatus of claim 18, wherein the particular phase circuit is further configured to: in response to activation of a clock signal, deactivate the driver control signal; and in response to deactivation of the driver control signal, couple the first terminal of the particular inductor to a ground power supply node.

20. The apparatus of claim 14, further comprising a memory circuit configured to store the one or more control bits.

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