Error correction coding device and error correction coding method

Abstract

An error correction encoding device is configured to comprise: an exclusive OR calculation unit (3) that acquires a plurality of information bit strings, which are tags for each of a plurality of multi-valued modulation symbols, from a frame in which a plurality of information bit strings, which are tags for each of the plurality of multi-valued modulation symbols, are arranged, and calculates an exclusive OR for a plurality of information bits, which are tags for each of the multi-valued modulation symbols; and a soft-decision error correction encoding unit (4) that generates soft-decision error correction redundant bits by performing soft-decision error correction encoding on the results of the plurality of exclusive-or operations by the exclusive-or operation unit (3).

Description

Technical Field

[0001] The present disclosure relates to an error correction coding device and an error correction coding method. Background Art

[0002] There is a transmission device having an error correction coding device that generates soft-decision error correction redundant bits by performing soft-decision error correction coding on multi-value modulation symbols (for example, refer to Non-Patent Document 1).

[0003] The bit sequence representing the multi-value modulation symbol includes the most significant bit of dimension, the middle bit of dimension×K (K is an integer greater than or equal to 1), and the least significant bit of dimension. The middle bit is a bit between the most significant bit and the least significant bit.

[0004] The error correction coding device obtains each multi-value modulation symbol from a frame in which a plurality of multi-value modulation symbols are arranged. The error correction coding device uses the information bit assigned to the least significant bit of each multi-value modulation symbol and the information bit assigned to the middle bit of each multi-value modulation symbol to perform soft decision error correction coding on each multi-value modulation symbol, thereby generating soft decision error correction redundant bits.

[0005] Prior art literature

[0006] Non-patent literature

[0007] Non-patent literature 1: K. Sugitani et al., “Partial multilevel coding with probabilistic shaping for low-power optical transmission”, Proc. OECC / PSC 2019, Paper TuB1-5. Summary of the invention

[0008] Problems to be solved by the invention

[0009] The error correction coding device disclosed in Non-Patent Document 1 has the following problem: the amount of calculation required for soft decision error correction coding increases as the number of median bits in a multi-value modulation symbol increases and the number of multi-value modulation symbols increases.

[0010] The present disclosure is completed to solve the above-mentioned problems, and its purpose is to obtain an error correction coding device that can reduce the amount of computational complexity of soft decision error correction coding processing compared to the error correction coding device disclosed in non-patent document 1 when the number of median bits of a multi-value modulation symbol and the number of multi-value modulation symbols are increased respectively.

[0011] Means for solving problems

[0012] The error correction coding device disclosed in the present invention comprises: an exclusive-OR operation unit, which obtains multiple information bit strings as labels of each multi-value modulation symbol from a frame in which multiple information bit strings as labels of each multi-value modulation symbol are arranged, and calculates the exclusive-OR of the multiple information bits as labels of each multi-value modulation symbol; and a soft-decision error correction coding unit, which generates soft-decision error correction redundant bits by performing soft-decision error correction coding on the multiple exclusive-OR operation results of the exclusive-OR operation unit.

[0013] Effects of the Invention

[0014] According to the present disclosure, when the number of median bits of a multi-value modulation symbol and the number of multi-value modulation symbols are increased, the amount of calculation of the soft decision error correction coding process can be reduced compared to the error correction coding device disclosed in Non-Patent Document 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] [ Figure 1 ] is a structural diagram of the error correction coding device of embodiment 1.

[0016] [ Figure 2 ] is a hardware structure diagram showing the hardware of the error correction coding device of embodiment 1.

[0017] [ Figure 3 ] is a hardware structure diagram of a computer when the error correction coding device is implemented by software or firmware.

[0018] [ Figure 4 ] is a flowchart of an error correction coding method representing the processing procedure of an error correction coding device.

[0019] [ Figure 5 ] Figure 5 A is an explanatory diagram showing an example of a first bit string provided to the probability shaping coding unit 1, Figure 5 B is an explanatory diagram showing a frame generated by the probability shaping encoding unit 1.

[0020] [ Figure 6 ] Figure 6 A is an explanatory diagram showing a frame output from the probability shaping coding unit 1 to the hard decision error correction coding unit 2. Figure 6 A is an explanatory diagram showing a frame output from the probability shaping coding unit 1 to the hard decision error correction coding unit 2.

[0021] [ Figure 7 ] Figure 7 A is an explanatory diagram showing a frame output from the hard decision error correction coding unit 2 to the exclusive OR operation unit 3. Figure 7 B is an explanatory diagram showing the set division bits output from the exclusive OR operation unit 3.

[0022] [ Figure 8] is an explanatory diagram showing the XOR operation processing of the XOR operation unit 3.

[0023] [ Fig. 9 ] is an explanatory diagram showing a set of segmented bits that are the objects of soft decision error correction coding by the soft decision error correction coding unit 4.

[0024] [ Fig.10 ] Fig.10 A is an explanatory diagram showing a frame in which hard decision error correction redundant bits and soft decision error correction redundant bits are stored respectively. Fig.10 B is an explanatory diagram showing a frame storing a pulse amplitude modulation symbol sequence including X[1][1:N3] and X[2][1:N3].

[0025] [ Fig.11 ] Fig.11 A is an explanatory diagram showing the correspondence between the signal point position and the bit string as its label when two 8-value pulse amplitude modulation symbols are arranged in the real part and the imaginary part. Fig.11 B means as Fig.11 An illustration of the XOR operation results of the bit strings of the labels corresponding to each signal point of A. DETAILED DESCRIPTION

[0026] Hereinafter, in order to explain the present disclosure in more detail, a mode for implementing the present disclosure will be described with reference to the drawings.

[0027] Implementation Method 1

[0028] Figure 1 This is a diagram showing the structure of the error correction coding device according to the first embodiment.

[0029] Figure 2 This is a hardware configuration diagram showing the hardware of the error correction coding device according to the first embodiment.

[0030] Figure 1 The error correction coding device shown is installed in, for example, a transmitting device not shown in the figure. Figure 1 The error correction coding device shown includes a probability shaping coding unit 1 , a hard decision error correction coding unit 2 , an exclusive OR operation unit 3 , a soft decision error correction coding unit 4 , and a symbol generation unit 5 .

[0031] The transmitting device (not shown) has Figure 1 The error correction coding device shown in the figure enables a receiving device (not shown) to correct, for example, a bit error that occurs in a communication path.

[0032] The probability shaping coding unit 1 is composed of, for example, Figure 2 The probability shaping encoding circuit 11 shown is implemented.

[0033] The probabilistic shaping coding unit 1 is supplied with a first bit string as a communication target from the outside.

[0034] The probability shaping coding unit 1 performs probability shaping coding on the first bit string. When the first bit string is converted into a multi-value modulation symbol by subsequent processing, the probability of occurrence of a signal point is biased, thereby improving communication quality.

[0035] The probability shaping coding unit 1 uses the second bit string which is the first bit string after the probability shaping coding as an information bit string, and outputs a frame in which a plurality of information bit strings are arranged to the hard decision error correction coding unit 2 .

[0036] The hard decision error correction coding unit 2 is composed of, for example, Figure 2 The hard decision error correction coding circuit 12 is shown to be implemented.

[0037] The hard decision error correction coding unit 2 obtains the frame from the probability shaping coding unit 1 .

[0038] The hard decision error correction coding unit 2 obtains multiple information bit strings from the frame. The second bit string as a label of the multi-value modulation symbol includes the most significant bit of dimension D (hereinafter referred to as "MSB"), the middle bit of dimension D×K (hereinafter referred to as "SSB"), and the least significant bit of dimension D (hereinafter referred to as "LSB"). SSB is a bit between MSB and LSB. If the hard decision error correction redundant bits and the soft decision error correction redundant bits are not aligned, they will not be a complete label. In this case, the second bit string is part of the label of the multi-value modulation symbol. D represents the dimension of each of the multiple bits contained in the multi-value modulation symbol. D is an integer greater than 1. K is an integer greater than 0. When K=0, M=2, in which case the second bit string includes MSB and LSB, but does not include SSB.

[0039] The hard decision error correction coding unit 2 generates hard decision error correction redundant bits by performing hard decision error correction coding on the acquired plurality of information bits.

[0040] The hard decision error correction coding unit 2 stores the hard decision error correction redundant bits in a hard decision error correction redundant bit storage area within the frame.

[0041] The hard decision error correction coding unit 2 outputs the frame in which the hard decision error correction redundant bits are stored to the exclusive OR operation unit 3 and the symbol generation unit 5, respectively.

[0042] The XOR operation unit 3 is composed of, for example, Figure 2 The XOR operation circuit 13 shown is implemented.

[0043] The exclusive OR operation unit 3 obtains the frame from the hard decision error correction coding unit 2 .

[0044] The exclusive-OR calculation unit 3 obtains a plurality of information bit sequences as labels of respective multi-value modulation symbols from the frame, and calculates exclusive-ORs of the plurality of information bits.

[0045] The exclusive-OR operation unit 3 outputs the set division bits representing the respective exclusive-OR operation results to the soft-decision error correction coding unit 4 .

[0046] The soft decision error correction coding unit 4 is composed of, for example, Figure 2 The soft decision error correction coding circuit 14 shown is implemented.

[0047] The soft decision error correction coding unit 4 obtains a plurality of set division bits from the exclusive OR operation unit 3 .

[0048] The soft decision error correction coding unit 4 generates soft decision error correction redundant bits by performing soft decision error correction coding on the exclusive OR operation results indicated by the plurality of set division bits.

[0049] The soft decision error correction coding unit 4 outputs the soft decision error correction redundant bits to the symbol generating unit 5 .

[0050] The symbol generation unit 5 is composed of, for example, Figure 2 The symbol generation circuit 15 shown is implemented.

[0051] The symbol generation unit 5 obtains the frame from the hard decision error correction coding unit 2 and obtains the soft decision error correction redundant bits from the soft decision error correction coding unit 4 .

[0052] The symbol generator 5 obtains the second bit string from the frame, and generates a plurality of pulse amplitude modulation symbols based on the second bit string, hard decision error correction redundant bits, and soft decision error correction redundant bits. The second bit string is a part of the label of each multi-value modulation symbol, or the entirety of the label of each multi-value modulation symbol.

[0053] The symbol generating unit 5 outputs a communication symbol sequence in which a plurality of pulse amplitude modulation symbols are arranged to a receiving device (not shown) via a communication path (not shown).

[0054] exist Figure 1 In the embodiment, it is assumed that the probability shaping coding unit 1, the hard decision error correction coding unit 2, the XOR operation unit 3, the soft decision error correction coding unit 4 and the symbol generation unit 5, which are components of the error correction coding device, are respectively Figure 2 That is, it is assumed that the error correction coding device is implemented by the probability shaping coding circuit 11, the hard decision error correction coding circuit 12, the exclusive OR operation circuit 13, the soft decision error correction coding circuit 14 and the symbol generation circuit 15.

[0055] The probability shaping coding circuit 11, the hard decision error correction coding circuit 12, the XOR operation circuit 13, the soft decision error correction coding circuit 14 and the symbol generation circuit 15 are respectively equivalent to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or a circuit composed of a combination thereof.

[0056] The constituent elements of the error correction coding device are not limited to being implemented by dedicated hardware, and the error correction coding device may be implemented by software, firmware, or a combination of software and firmware.

[0057] Software or firmware is stored as a program in the computer's memory. A computer refers to hardware that executes programs, such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, a processor, or a DSP (Digital Signal Processor).

[0058] Figure 3 This is a hardware configuration diagram of a computer when the error correction coding device is implemented by software, firmware, etc.

[0059] When the error correction coding device is implemented by software or firmware, a program for causing a computer to execute each process in the probability shaping coding unit 1, the hard decision error correction coding unit 2, the exclusive OR operation unit 3, the soft decision error correction coding unit 4, and the symbol generation unit 5 is stored in the memory 21. Then, the processor 22 of the computer executes the program stored in the memory 21.

[0060] In addition, Figure 2 In FIG. 1 , an example is shown in which the constituent elements of the error correction coding device are each implemented by dedicated hardware. Figure 3 In the embodiment, an example is shown in which the error correction coding device is implemented by software or firmware. However, this is only an example, and some components of the error correction coding device may be implemented by dedicated hardware, and the remaining components may be implemented by software or firmware.

[0061] Next, explain Figure 1 The operation of the error correction coding device shown.

[0062] Figure 4 It is a flowchart showing an error correction coding method as a processing procedure of an error correction coding apparatus.

[0063] The probability shaping coding unit 1 obtains from the outside Figure 5 A shows the first bit string to be communicated.

[0064] Figure 5 A is an explanatory diagram showing an example of the first bit string provided to the probability shaping coding unit 1.

[0065] The first bit string is composed of a plurality of frames arranged in a row, and each frame is divided into the MSB and the rest of the MSB.

[0066] A[1][1:2N1] allocated to the MSB and A[2][1:N0] allocated to the parts other than the MSB are information bits. N1 and N0 are integers greater than or equal to 1.

[0067] [1:2N1] is a notation indicating from the 1st column to the 2×N1th column. [1:N0] is a notation indicating from the 1st column to the N0th column.

[0068] The HD-FEC reserved area allocated to the MSB is a hard decision error correction redundant bit storage area, and stores the first dummy bit.

[0069] The SD-FEC reserved area allocated to the MSB is a soft decision error correction redundant bit storage area, and stores the second dummy bit.

[0070] The PCS (Probabilistic Constellation Shaping) reserved area allocated to other than the MSB is an area for storing bits increased by probabilistic constellation shaping coding, and stores the third dummy bit.

[0071] The probabilistic shaping coding unit 1 performs probabilistic shaping coding on a first bit string to be communicated.

[0072] That is, the probability shaping coding unit 1 generates a frame ( Figure 4 Step ST1).

[0073] The probability shaping coding unit 1 outputs a frame in which a plurality of probability shaping-coded first bit sequences, namely, second bit sequences, are arranged to the hard decision error correction coding unit 2 .

[0074] Figure 5 B is an explanatory diagram showing a frame generated by the probability shaping encoding unit 1.

[0075] The frame generated by the probability shaping coding unit 1 includes group "1" (g=1) and group "2" (g=2). Group "1" is the first group, and group "2" is the second group.

[0076] Group "1" includes a multivalue modulation symbol in which neither the first virtual bit nor the second virtual bit is included in the MSB or a label of the multivalue modulation symbol, and a multivalue modulation symbol in which the first virtual bit is included in the MSB or a label of the multivalue modulation symbol.

[0077] The group "2" is a group including the SD-FEC reserved area allocated to the MSB. That is, the group "2" includes a multi-value modulation symbol in which the second dummy bit is included in the MSB or a label of the multi-value modulation symbol.

[0078] exist Figure 5 In the example, D = 2. j is a dimension index indicating a dimension, j = 1 indicates the first dimension, and j = 2 indicates the second dimension.

[0079] The number of bits of a D-dimensional multi-value modulation symbol is D×M. M is an integer greater than 2. Figure 5 In the example, M=3, the number of bits of the D-dimensional multi-value modulation symbol is 6 (=2×3). i is the bit sequence index. Figure 5 In the example, M=3, therefore, i=1, 2, 3.

[0080] Assume that the bits of the multi-value modulation symbol are represented as B[i][j][g][c]. g is a group index, and c is a column index. c=[1:N1] means from the 1st column to the N1th column.

[0081] Probability shaping coding unit 1 Figure 5 As shown in B, Figure 5 A[1][1:2N1] assigned to the MSB in A is assigned to B[1][1][1][1:N1] of the first dimension and B[1][2][1][1:N1] of the second dimension.

[0082] Specifically, the probability shaping coding unit 1 assigns A[1][1] as B[1][1][1][1] to the first dimension (i, j) = (1, 1) in the first column of MSB, and assigns A[1][2] as B[1][2][1][1] to the second dimension (i, j) = (1, 2) in the first column of MSB.

[0083] In addition, the probability shaping coding unit 1, for example, assigns A[1][3] as B[1][1][1][2] to the first dimension (i, j) = (1, 1) in the second column of MSB, and assigns A[1][4] as B[1][2][1][2] to the second dimension (i, j) = (1, 2) in the second column of MSB.

[0084] The probability shaping coding unit 1 will be Figure 5 A[2][1:N0] other than the MSB in B is converted into 4×N3 bits after probability shaping. N3 is an integer greater than or equal to 1.

[0085] The probability shaping coding unit 1, for example, assigns B[2][1][1][1:N2] to the first dimension (i, j) = (2, 1) of the SSB in group "1", and assigns B[2][1][2][N2+1:N3] to the first dimension (i, j) = (2, 1) of the SSB in group "2".

[0086] The probability shaping coding unit 1, for example, assigns B[2][2][1][1:N2] to the second dimension (i, j) = (2, 2) of the SSB in group "1", and assigns B[2][1][2][N2+1:N3] to the second dimension (i, j) = (2, 2) of the SSB in group "2".

[0087] The probability shaping coding unit 1, for example, assigns B[3][1][1][1:N2] to the first dimension (i, j) = (3, 1) of the LSB in group "1", and assigns B[3][1][2][N2+1:N3] to the first dimension (i, j) = (3, 1) of the LSB in group "2".

[0088] The probability shaping coding unit 1, for example, assigns B[3][2][1][1:N2] to the second dimension (i, j) = (3, 2) of the LSB in group "1", and assigns B[3][2][2][N2+1:N3] to the second dimension (i, j) = (3, 2) of the LSB in group "2".

[0089] The first dummy bit is stored in the HD-FEC reserved area allocated to the MSB, and the second dummy bit is stored in the SD-FEC reserved area allocated to the MSB.

[0090] The hard decision error correction coding unit 2 obtains the Figure 6 The frame shown in A.

[0091] Figure 6 A is an explanatory diagram showing a frame output from the probability shaping coding unit 1 to the hard decision error correction coding unit 2.

[0092] The hard decision error correction coding unit 2 obtains a plurality of information bits that are part of labels of a plurality of multi-value modulation symbols from the frame.

[0093] Specifically, the hard decision error correction coding unit 2 obtains B[1][1][1][c], B[1][2][1][c], B[2][1][1][c], B[2][2][1][c], B[3][1][1][c], and B[3][2][1][c] as D×M information bits included in the multi-value modulation symbol arranged in the c-th column (c=1, ..., N2). However, the hard decision error correction coding unit 2 does not obtain the first dummy bit stored in the HD-FEC reserved area.

[0094] In addition, the hard decision error correction coding unit 2 obtains B[2][1][2][c], B[2][2][2][c], B[3][1][2][c] and B[3][2][2][c] respectively as D×(M-1) information bits contained in the multi-value modulation symbols configured in the cth column (c=N2+1,…,N3).

[0095] After obtaining D×M information bits and the like contained in the multi-value modulation symbol arranged in the c-th column (c=1, ..., N2), the hard decision error correction coding unit 2 performs the following operation: Figure 6 As shown in FIG. B, information bits included in the portion surrounded by a dotted line are set as HD-FEC information bits. HD-FEC information bits are bits to be hard-decision error correction coded.

[0096] The information bits included in the parts surrounded by dotted lines are B[2:3][1:2][2][N2+1:N3], B[1][1:2][1][1:N1], and B[2:3][1:2][1][1:N2].

[0097] The hard decision error correction coding unit 2 generates hard decision error correction redundant bits ( Figure 4 The hard decision error correction coding process itself is a well-known technique, so a detailed description thereof is omitted.

[0098] As the hard decision error correction code used in the hard decision error correction coding process, for example, a well-known code such as BCH code, Staircase code or Zipper code can be used. BCH code is disclosed in "R. Bose and D. Ray-Chaudhuri, "On a class of error correcting binary group codes," Information and Control, vol. 3, no. 1, pp. 68-79, March 1960".

[0099] Staircase codes are disclosed in, for example, “BP Smith et al., “Staircase codes: FEC for 100 Gb / s OTN,” J. Lightw. Technol., vol. 30, no. 1, pp. 110-117, Jan. 2012, doi: 10.1109 / JLT.2011.2175479”.

[0100] Zipper codes are disclosed, for example, in “AYSukmadji et al., “Zipper codes: Spatially-coupled product-like codes with iterative algebraic decoding,” Canadian Workshop on Information Theory (CWIT), Hamilton, ON, Canada, June 2019, pp. 1-6, doi: 10.1109 / CWIT.2019.8929906”.

[0101] like Figure 6 As shown in FIG. 1B, the hard decision error correction coding unit 2 stores the generated hard decision error correction redundant bits as B[1][1:2][1][N1+1:N2] in the HD-FEC reserved area allocated to the MSB. That is, the hard decision error correction coding unit 2 replaces the first dummy data stored in the HD-FEC reserved area and stores the hard decision error correction redundant bits in the HD-FEC reserved area.

[0102] Figure 6 B is an explanatory diagram showing a frame in which hard decision error correction redundant bits are stored in the HD-FEC reserved area.

[0103] The hard decision error correction coding unit 2 outputs the frame in which the hard decision error correction redundant bits are stored to the exclusive OR operation unit 3 and the symbol generation unit 5, respectively.

[0104] The hard decision error correction coding unit 2 may rearrange the bit positions after performing hard decision error correction coding on the HD-FEC information bits. By rearranging the bit positions, the influence of continuous bit errors generated in the communication path can be reduced before decoding.

[0105] like Figure 7 As shown in A, the exclusive OR operation unit 3 obtains the frame in which the hard decision error correction redundant bits are stored from the hard decision error correction coding unit 2.

[0106] Figure 7 A is an explanatory diagram showing a frame output from the hard decision error correction coding unit 2 to the exclusive OR operation unit 3. Figure 7The frame shown in A is Figure 6 The frame shown in B is the same frame.

[0107] Figure 8 It is an explanatory diagram showing the exclusive OR operation processing of the exclusive OR operation unit 3.

[0108] The exclusive OR operation unit 3 obtains a plurality of information bits that are part of the label of each multi-value modulation symbol from the frame.

[0109] Specifically, if Figure 8 As shown, the XOR operation unit 3 obtains B[1][1][1][c], B[1][2][1][c], B[2][1][1][c], B[2][2][1][c], B[3][1][1][c] and B[3][2][1][c] from the frame of group "1" as D×M information bits, and the D×M information bits are labels of the multi-value modulation symbols configured in the cth column (c=1, ..., N2).

[0110] Figure 8 The "123456" marked in represents the order of bits from (i, j) = (1, 1) to (i, j) = (3, 2), and does not represent the values ​​stored in B[1][1][1][c], etc. The values ​​stored in B[1][1][1][c], etc. are "0" or "1".

[0111] The exclusive OR operation unit 3 obtains D×(M-1) information bits as labels of multi-value modulation symbols from the frame of group "2". T is an integer greater than or equal to 1 and set so that D×(M-1)×T is an integer.

[0112] In the case of T = 2, if Figure 8 As shown, the XOR operation unit 3 obtains B[2][1][2][c], B[2][2][2][c:c], B[3][1][2][c] and B[3][2][2][c] from the frame of group "2" as D×(M-1) information bits arranged in the cth column (c=N2+1, ..., N3).

[0113] In addition, the XOR operation unit 3 obtains B[2][1][2][c+1], B[2][2][2][c+1], B[3][1][2][c+1] and B[3][2][2][c+1] as D×(M-1) information bits arranged in the c+1th column (c=N2+1,…,N3).

[0114] Figure 8The "12345678" marked in represents the order of bits from the first dimension (i, j) = (2, 1) to the second dimension (i, j) = (3, 2), and does not represent the values ​​stored in B[2][1][2][c+1], etc. The values ​​stored in B[2][1][2][c+1], etc. are "0" or "1".

[0115] like Figure 8 As shown, when the exclusive-OR operation unit 3 obtains the bit strings of D×M information bits from the frame of group "1" as N2 bit strings, it calculates the exclusive-OR ( Figure 4 Step ST3). However, the hard decision error correction redundant bits included in the HD-FEC reserved area are not included in the XOR operation object.

[0116] In addition, if Figure 8 As shown, when the exclusive-OR operation unit 3 obtains the bit strings of D×(M-1)×T information bits from the frame of group "2" as (N3-N2) / T bit strings, it calculates the exclusive-OR ( Figure 4 Step ST3).

[0117] like Figure 7 As shown in B, the XOR operation unit 3 outputs the set division bits indicating the XOR operation results for each of the D×M information bits obtained from the frame of group “1” to the soft decision error correction coding unit 4 as SPB[1:N2].

[0118] like Figure 7 As shown in B, the XOR operation unit 3 outputs the set of partitioned bits representing the XOR operation results for each D×(M-1)×T information bit obtained from the frame of group "2" as SPB[N2+1:N4] to the soft decision error correction coding unit 4. N4 is an integer greater than 1, and N4≤N3.

[0119] Figure 7 B is an explanatory diagram showing the set division bits output from the exclusive OR operation unit 3.

[0120] The amount of XOR calculation performed by the XOR calculation unit 3 is negligibly small compared to the amount of calculation performed by the soft decision error correction coding unit 4 .

[0121] Soft decision error correction coding unit 4 Fig. 9 As shown, SPB[1:N4] including SPB[1:N2] and SPB[N2+1:N4] is obtained from the XOR operation unit 3.

[0122] The soft decision error correction coding unit 4 generates soft decision error correction redundant bits ( Figure 4 Step ST4). The soft decision error correction coding process itself is a well-known technology, so the detailed description is omitted.

[0123] like Fig. 9 As shown, the soft decision error correction coding unit 4 sets the soft decision error correction redundant bits to B[1][1:2][2][N2+1:N3] and stores them in the SD-FEC reserved area allocated to the MSB. That is, the soft decision error correction coding unit 4 stores the soft decision error correction redundant bits in the SD-FEC reserved area instead of the second dummy data stored in the SD-FEC reserved area.

[0124] The soft decision error correction coding unit 4 outputs the soft decision error correction redundant bits to the symbol generating unit 5 .

[0125] Fig. 9 1 is an explanatory diagram showing the set of division bits that are the target of soft decision error correction coding by the soft decision error correction coding unit 4.

[0126] One of the objects of the soft decision error correction coding process of the error correction coding device disclosed in Non-Patent Document 1 is all the information bits assigned to the LSB of the multi-value modulation symbol and the information bits assigned to the SSB of the multi-value modulation symbol of Group 2. Fig. 9 In the example, the soft decision error correction coding processing object is N3 symbols for the 2 information bits of LSB, and is N3-N2 symbols for the 2 information bits of SSB.

[0127] Therefore, in Fig. 9 In the example, the error correction coding device disclosed in non-patent document 1 performs soft decision error correction coding on 2×N3+2×(N3-N2) bits.

[0128] Figure 1 The number of soft decision error correction coding processing objects of the error correction coding device shown is one. Fig. 9 In the example of , the objects of soft decision error correction coding processing are N4 bits. N4≤N3.

[0129] therefore, Figure 1 The amount of computation for soft decision error correction coding processing in the error correction coding apparatus shown is less than that of soft decision error correction coding processing in the error correction coding apparatus disclosed in non-patent document 1 by (2×N3+2×(N3-N2)-N4) bits. For the D-dimensional 2^M-valued pulse amplitude modulation symbol, the object of soft decision coding processing is D×N3+D×(M-2)×(N3-N2) in the case of the error correction coding apparatus disclosed in non-patent document 1. Figure 1 In the case of the error correction coding device shown, it is N4. Therefore, Figure 1The error correction coding device shown has a computational complexity less than 1 / D compared to the error correction coding device disclosed in Patent Document 1, and the effect becomes better as D, M, and T are each larger.

[0130] The symbol generation unit 5 obtains the frame from the hard decision error correction coding unit 2 and obtains the soft decision error correction redundant bits from the soft decision error correction coding unit 4 .

[0131] The symbol generating unit 5 may obtain a frame in which soft decision error correction redundant bits are stored from the soft decision error correction encoding unit 4 instead of obtaining the frame from the hard decision error correction encoding unit 2 .

[0132] Fig.10 A is an explanatory diagram showing a frame in which hard-decision error correction redundant bits and soft-decision error correction redundant bits are respectively stored.

[0133] exist Fig.10 In the frame shown in A, hard-decision error correction redundant bits are stored in the HD-FEC reserved area, and soft-decision error correction redundant bits are stored in the SD-FEC reserved area.

[0134] However, in Fig.10 In A, the HD-FEC reserved area and the SD-FEC reserved area are not clearly described separately.

[0135] In addition, Fig.10 In A, the groups are not divided into group "1" and group "2".

[0136] For example, when D=2, the symbol generation unit 5 obtains B[1][1][c], B[2][1][c], and B[3][1][c] from the above frame as M information bits, and the M information bits are labels of multi-value modulation symbols arranged in the c-th column (c=1, ..., N3) of the first dimension. Since grouping is not performed, the group index g of the above information bits is omitted.

[0137] Furthermore, the symbol generating unit 5 obtains B[1][2][c], B[2][2][c], and B[3][2][c] from the above-mentioned frame as M information bits arranged in the c-th column (c=1, ..., N3) of the second dimension.

[0138] In the case of D = 2, Fig.10 As shown in FIG. 1B , the symbol generation unit 5 generates a pulse amplitude modulation symbol X based on B[1][1][c], B[2][1][c], and B[3][1][c], which are the M information bits of the first dimension. j (j=1, ..., D), and the pulse amplitude modulation symbol X j Stored in the area X[1][1:N3] ( Figure 4 Step ST5).

[0139] In addition, if Fig.10 As shown in FIG. 1B , the symbol generation unit 5 generates a pulse modulation symbol X based on B[1][2][c], B[2][2][c], and B[3][2][c], which are the M information bits of the second dimension. j , and the pulse modulation symbol X j Stored in the area X[2][1:N3] ( Figure 4 Step ST5).

[0140] Fig.10 B is an explanatory diagram showing a frame storing a pulse modulation symbol sequence including X[1][1:N3] and X[2][1:N3].

[0141] The symbol generation unit 5 arranges D pulse modulation symbols X including X[1][1:N3] and X[2][1:N3] j The communication symbol sequence is output to a receiving device (not shown) via a communication path (not shown).

[0142] Here, when generating pulse modulation symbols in which each dimension takes a value of 2 to the power of M or less, the symbol generating unit 5 can generate the pulse modulation symbol X by performing reflected binary Gray coding on D×M bits so that the bit difference between adjacent symbols is only 1 bit. j (j=1,…,D).

[0143] When generating a pulse modulation symbol, for example, when M=3 and the Euclidean distance between signal points is set to 2, Fig.11 As shown in A, the symbol generation unit 5 can assign bit "000" to the symbol "1", bit "001" to the symbol "3", bit "011" to the symbol "5", and bit "010" to the symbol "7". In addition, the symbol generation unit 5 can assign bit "100" to the symbol "-1", bit "101" to the symbol "-3", bit "111" to the symbol "-5", and bit "110" to the symbol "-7".

[0144] In addition, if Fig.11 As shown in B, the symbol generating unit 5 can assign "0" or "1" to symbol "-7", symbol "-5", symbol "-3", symbol "-1", symbol "1", symbol "3", symbol "5" or symbol "7" by performing XOR on the bits.

[0145] Fig.11 A is an explanatory diagram showing the correspondence between signal point positions and bit strings serving as their labels when two 8-value pulse modulation symbols are arranged in the real part and the imaginary part.

[0146] Fig.11 B means as Fig.11 The diagram is an illustration of the XOR operation result of the bit string of the label corresponding to each signal point of A. For each signal point, the set partition bit is taken Fig.11 The value shown in B can be divided into two sets, one on the "0" side and the other on the "1" side.

[0147] In the above-mentioned Embodiment 1, the error correction coding apparatus is configured to include: an exclusive OR operation unit 3, which obtains a plurality of information bit strings as labels of each multi-value modulation symbol from a frame in which a plurality of information bit strings as labels of each multi-value modulation symbol are arranged, and calculates an exclusive OR of a plurality of information bits as labels of each multi-value modulation symbol; and a soft decision error correction coding unit 4, which generates soft decision error correction redundant bits by performing soft decision error correction coding on a plurality of exclusive OR operation results of the exclusive OR operation unit 3. Therefore, the error correction coding apparatus can reduce the amount of calculation of the soft decision error correction coding process compared with the error correction coding apparatus disclosed in Non-Patent Document 1 when the number of median bits of the multi-value modulation symbol and the number of multi-value modulation symbols are increased.

[0148] In the first embodiment, the error correction coding device is configured to include: a hard decision error correction coding unit 2 that obtains a plurality of information bits as labels of each multi-value modulation symbol from a frame, generates hard decision error correction redundant bits by performing hard decision error correction coding on the plurality of information bits; and a symbol generating unit 5 that generates a plurality of pulse modulation symbols based on a part of the label of each multi-value modulation symbol or all of the label of each multi-value modulation symbol, the hard decision error correction redundant bits, and the soft decision error correction redundant bits. Therefore, the error correction coding device can generate a plurality of pulse modulation symbols while suppressing an increase in the amount of calculation of the soft decision error correction coding process.

[0149] Furthermore, the present disclosure can modify any constituent elements of the embodiments or omit any constituent elements of the embodiments.

[0150] Industrial Applicability

[0151] The present disclosure is applicable to an error correction coding device and an error correction coding method.

[0152] Description of symbols

[0153] 1: Probability shaping coding unit; 2: Hard decision error correction coding unit; 3: XOR operation unit; 4: Soft decision error correction coding unit; 5: Symbol generation unit; 11: Probability shaping coding circuit; 12: Hard decision error correction coding circuit; 13: XOR operation circuit; 14: Soft decision error correction coding circuit; 15: Symbol generation circuit; 21: Memory; 22: Processor.

Claims

1. An error correction coding device, characterized in that: The error correction coding device comprises: an exclusive-OR operation unit that obtains a plurality of information bit sequences as labels of each of the plurality of multi-value modulation symbols from a frame in which a plurality of information bit sequences as labels of each of the plurality of multi-value modulation symbols are arranged, and operates an exclusive-OR operation on the plurality of information bits as labels of each of the multi-value modulation symbols; as well as The soft decision error correction coding unit generates soft decision error correction redundant bits by performing soft decision error correction coding on a plurality of XOR operation results of the XOR operation unit.

2. The error correction coding device according to claim 1, characterized in that The error correction coding device comprises: a hard decision error correction coding unit that obtains a plurality of information bit strings as labels of respective multi-value modulation symbols from the frame, performs hard decision error correction coding on the plurality of information bits to generate hard decision error correction redundant bits; as well as A symbol generation unit generates a plurality of pulse amplitude modulation symbols based on a part of the label of each multi-value modulation symbol or the entirety of the label of each multi-value modulation symbol, the hard decision error correction redundant bits, and the soft decision error correction redundant bits.

3. The error correction coding device according to claim 2, characterized in that The most significant bit of the information bit string as a tag of a part of the plurality of multi-value modulation symbols includes the first dummy bit or the second dummy bit, The hard decision error correction coding unit includes the hard decision error correction redundant bit in place of the first dummy bit into the most significant bit including the first dummy bit, The soft decision error correction coding unit includes the soft decision error correction redundant bit in place of the second dummy bit in the most significant bit including the second dummy bit.

4. The error correction coding device according to claim 3, characterized in that The frame has: A first group, comprising: a multi-value modulation symbol or a label of the multi-value modulation symbol that does not include any one of the first virtual bit and the second virtual bit in the most significant bit, and a multi-value modulation symbol or a label of the multi-value modulation symbol that includes the first virtual bit in the most significant bit; as well as A second group, comprising: a multi-value modulation symbol including the second virtual bit in the most significant bit or a label of the multi-value modulation symbol, The XOR operation unit calculates an XOR of a plurality of information bits as labels of the multi-value modulation symbols included in the first group. The XOR operation unit calculates an XOR of a plurality of information bits that are labels of each of T multi-value modulation symbols included in the second group, where T is an integer greater than or equal to 1.

5. The error correction coding device according to claim 3, characterized in that: When the dimension of each of the multiple bits serving as a label of each multi-value modulation symbol is D, and the number of bits possessed by each multi-value modulation symbol is D×M, the symbol generation unit generates each pulse amplitude modulation symbol by performing reflected binary Gray coding on the D×M bits possessed by each multi-value modulation symbol, where D is an integer greater than 1 and M is an integer greater than 2.

6. The error correction coding device according to claim 2, characterized in that The error correction coding device has a probability shaping coding unit, which performs probability shaping coding on the first bit string as the communication object, uses the first bit string after probability shaping coding, that is, the second bit string, as an information bit string, and outputs a frame in which a plurality of the information bit strings are arranged to the hard decision error correction coding unit.

7. An error correction coding method, characterized in that: The exclusive-OR operation unit obtains a plurality of information bit sequences as labels of each of the multi-value modulation symbols from a frame in which a plurality of information bit sequences as labels of each of the multi-value modulation symbols are arranged, and calculates an exclusive-OR of the plurality of information bits as labels of each of the multi-value modulation symbols. The soft decision error correction coding unit generates soft decision error correction redundant bits by performing soft decision error correction coding on a plurality of XOR operation results of the XOR operation unit.

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