High-precision weak signal acquisition system and method based on ARM processor

Abstract

The invention provides a high-precision weak signal acquisition system and method based on an ARM processor, and belongs to the technical field of signal processing, and the system comprises a fully differential amplification circuit, an emitter follower circuit, an anti-aliasing filter circuit, an analog-to-digital conversion module and a main control module. The fully differential amplification circuit is used for receiving and amplifying a detected weak signal; the emitter follower circuit receives the amplified detected weak signal and is used for matching impedance and transmitting the signal to the anti-aliasing filter circuit for filtering; the analog-to-digital conversion module converts the filtered analog signal into a digital signal; and the main control module is used for controlling and realizing high-precision weak signal acquisition. According to the invention, high-precision conversion of the ADC can be maintained under a microvolt-level signal, and good anti-interference performance is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of signal processing, and in particular relates to a high-precision weak signal acquisition system and method based on an ARM processor. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] With the vigorous development of electronic information technology in aerospace, radar measurement and control, mobile communications and other fields, the complexity and mass of signals are increasing day by day. For example, 5G technology requires GBPS-level signal throughput and transient weak signals prevalent in frequency-hopping radio stations. The need for high-speed transmission and capturing weak signals poses a higher challenge to the difficulty of data acquisition and testing. Therefore, it is particularly important to conduct research on improving data acquisition performance.

[0004] At present, in the field of electronic testing, the leaders of data acquisition systems are National Instruments and Keysight (formerly Agilent). NI has launched three types of data acquisition products: CompactRIO chassis, CompactDAQ system and PXI system. Among them, the CompactDAQ system has a flexible modular design and is suitable for data acquisition. It is mainly used in laboratories and industrial tests. For example, the NI9239 data acquisition card uses a Delta-Sigma ADC, which can achieve a sampling accuracy of 24-bit resolution and a maximum sampling rate of 50kS / s for a single channel. The NI 9239 has high-precision measurement and high-frequency sampling capabilities, thereby ensuring that the accuracy of signal acquisition reaches a very high level. It is an extremely efficient data acquisition device. An FPGA-based data acquisition module solution in the high-end NI data acquisition card realizes multi-channel data input and output through optocoupler control switches and multiplexers; FPGA, as a high-speed main control unit, is responsible for control signal acquisition, data storage, and sending data to the host computer; the analog-to-digital conversion module uses ADI's AD9288 chip with dual-core ADC, with a signal-to-noise ratio of 47dB and a high conversion rate. The final data is realized through the CY7C68013 controller to interact with the host computer software LabVIEW, and has excellent dynamic performance in the entire working range.

[0005] Keysight Technologies has been providing data acquisition systems and switch solutions for nearly 30 years. Among its USB modular instruments, the U2300A series of multi-function data acquisition devices use a high-speed USB interface to transmit data, have a resolution of 12 to 16 bits, and can achieve 24-bit programmable digital input / output. When configured with multiple channels, the sampling rate can reach 1MSa / s. The U2300A series of data acquisition modules have high acquisition accuracy and can be used as independent or modular units. They are ideal tools for design verification and manufacturing engineers to record, measure or monitor data in various industries. A data acquisition module solution based on the Cortex core of Keysight Technologies in the United States supports up to 24-bit resolution. The STM32F103RET6 microcontroller is used as the MCU to control the data acquisition, processing and communication of the acquisition card. The AD9279 is used to achieve analog-to-digital conversion. The AD chip is a 24-bit high-speed, low-power analog-to-digital converter that supports dual-channel analog-to-digital conversion, but the chip needs to be calibrated to ensure its correct operation. This feature directly increases the complexity of the system design and testing process, and the main control chip does not have a built-in floating-point unit, making it unsuitable for applications that require high-precision calculations.

[0006] In East Asia, KEYENCE is a representative company in data acquisition systems. Compared with American companies, considering the compatibility with computers and software and the efficiency of data analysis, KEYENCE data acquisition instruments focus on the development of host computers, data synchronization, and the overall design can be ultra-small and ultra-lightweight. For example, the input frequency bandwidth of the NR-HA08 series acquisition instrument can reach 250kHz, the AD resolution is 14 bits, and the input signal range is between -10V and +10V. The AD conversion method of the NR-HA08 acquisition card is the successive comparison method. The main disadvantage of this method is the low conversion speed, which will inevitably restrict the acquisition rate of the product. Therefore, although it has a wide measurement range and small size, its bandwidth and resolution may not meet the needs of high-speed data acquisition in all application scenarios.

[0007] Although the NI9239 data acquisition card has a maximum sampling accuracy of 24 bits, its sampling rate is limited to 50kS / s, which cannot meet the sampling requirements of higher frequencies. In addition, the NI9239 acquisition card can greatly improve the sampling speed by using FPGA as the main control, but at the cost of wasting the main control performance, high power consumption, complex timing design, and low economic return rate in general. The U2300A series multi-function data acquisition equipment provided by Keysight Technologies has a sampling rate advantage of mega-level, but only has a 16-bit resolution, sacrificing sampling accuracy, and the system design and testing process is complex, making it difficult to match the high-speed acquisition environment. The NR-HA08 acquisition card of Keyence is subject to the AD conversion method, and its data acquisition rate is low. Its modular design needs to be used in conjunction with a matching host, which reduces the convenience of the acquisition card. In addition, the above-mentioned analog acquisition systems are not only expensive, but may also face Western blockades at any time.

[0008] In summary, there have always been two problems with high-precision and high-resolution data acquisition systems: First, due to the constraints of device performance, the high precision and high resolution of the acquisition card cannot be improved in the same direction, and ultimately only one-sided performance advantages are pursued, which makes it difficult to meet today's demand for the acquisition of high-frequency, complex, and weak signals; second, due to the relatively weak competition of existing technologies in the field of high-performance data acquisition, the problems of data acquisition equipment such as high price, low integration, and complex control system cannot be improved, and it does not have a good driving effect and application value. Summary of the invention

[0009] In order to overcome the shortcomings of the above-mentioned prior art, the present invention proposes a high-precision weak signal acquisition system and method based on an ARM processor, and designs a high-precision, high-speed analog signal acquisition system, which requires sufficiently high sampling accuracy, supports weak signal acquisition, high resistance to signal aliasing, sufficiently high sampling rate, multi-signal adaptability, and has the characteristics of low cost.

[0010] To achieve the above objectives, one or more embodiments of the present invention provide the following technical solutions: In the first aspect, a high-precision weak signal acquisition system based on an ARM processor is disclosed, comprising: a fully differential amplifier circuit, an emitter follower circuit, an anti-aliasing filter circuit, an analog-to-digital conversion module and a main control module; The fully differential amplifier circuit is used to receive and amplify the weak signal to be measured; The emitter follower circuit receives the amplified weak signal to be measured for impedance matching, and transmits it to the anti-aliasing filter circuit for filtering; The analog-to-digital conversion module converts the filtered analog signal into a digital signal; The main control module is used to control the acquisition of high-precision weak signals.

[0011] In the second aspect, a high-precision weak signal acquisition method based on an ARM processor is disclosed, comprising: A fully differential amplifier circuit is used to receive and amplify the weak signal to be measured; An emitter follower circuit is used to receive the amplified weak signal to be measured, which is used for impedance matching and transmitted to the anti-aliasing filter circuit for filtering; An analog-to-digital conversion module is used to convert the filtered analog signal into a digital signal; The main control module is used to realize the acquisition of high-precision weak signals.

[0012] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a high-precision weak signal acquisition system based on an ARM processor, which has a wider input signal range, can maintain high-precision conversion of ADC under microvolt-level signals, and has good anti-interference performance.

[0013] The system proposed in the present invention is based on ARM master control, which ensures the advantages of the system in terms of cost-effectiveness and power consumption, and is convenient for software maintenance and updating. The high-performance and low-cost ARM master control STM32F407VGT6 is adopted, and the CPU burden can be effectively reduced by reasonably calling the DMA function of the ARM master control and directly exchanging data between the peripheral and the memory. The method is low-cost and has lower power consumption.

[0014] The present invention proposes a single-ended to differential amplifier module designed by jointly using AD8132ARZ differential amplifier and THS4001 follower, which completes fixed gain amplification of the signal without changing the input signal type, thereby ensuring the accuracy and strong anti-interference of the analog-to-digital conversion result.

[0015] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0017] Figure 1 This is a schematic diagram of the high-precision weak signal acquisition system based on an ARM processor described in Example 1 of the present invention.

[0018] Figure 2 Schematic diagram of the structure of the fully differential amplifier circuit described in Embodiment 1 of the present invention.

[0019] Figure 3Schematic diagram of the structure of the emitter follower circuit described in the first embodiment of the present invention.

[0020] Figure 4 Schematic diagram of the structure of the anti-aliasing filter circuit described in Embodiment 1 of the present invention.

[0021] Figure 5 The figure is a schematic diagram of the structure of the ADC voltage reference source circuit described in the first embodiment of the present invention.

[0022] Figure 6 Schematic diagram of the structure of the external clock circuit described in the first embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of the structure of the minimum system of the ARM main control module described in the first embodiment of the present invention.

[0024] Figure 8 The figure is a schematic diagram of the structure of the ADC reset circuit of the ARM main control module described in the first embodiment of the present invention.

[0025] Fig. 9 This is a schematic diagram of the structure of the USB communication module described in Embodiment 1 of the present invention.

[0026] Fig.10 This is a schematic diagram of a power supply design for a digital-to-analog conversion module according to Embodiment 1 of the present invention.

[0027] Fig.11 This is a schematic diagram of the power supply design solution for the main control module described in Embodiment 1 of the present invention.

[0028] Fig.12 This is a schematic diagram of the operational amplifier power supply design scheme described in Embodiment 1 of the present invention.

[0029] Fig.13 This is a schematic diagram of the FPGA-based data acquisition module solution described in Embodiment 1 of the present invention.

[0030] Fig.14 This is a schematic diagram of the data acquisition module solution based on Atmega128A described in Example 1 of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0032] It should be noted that the terms used herein are for describing specific embodiments only and are not intended to be limiting of exemplary embodiments according to the present invention.

[0033] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0034] Embodiment 1 In one or more embodiments, a high-precision weak signal acquisition system based on an ARM processor is disclosed, such as Figure 1 As shown, it includes: a fully differential amplifier circuit, an emitter follower circuit, an anti-aliasing filter circuit, an analog-to-digital conversion module, an ARM main control module, a power module, a USB communication module and a host computer; The present invention can realize the acquisition of signals as low as microvolt level. In order to reduce the interference of noise on the weak signal to be measured, a fully differential amplifier circuit is used to suppress temperature drift and common mode interference, and amplify the weak signal to be measured to make it reach a convenient and controllable volt value range; the fully differential amplifier circuit is used to amplify the weak signal to be measured to a signal that can be recognized by the subsequent circuit; the output impedance of the differential circuit is high and the input impedance of the filter circuit is low, and an emitter follower circuit is required to achieve impedance matching with the subsequent circuit, improve the circuit's load capacity, and ensure smooth transmission of the signal in the circuit; the filter circuit is designed as a first-order anti-aliasing filter, which limits the bandwidth of the input signal to the bandwidth that can be processed by the analog-to-digital conversion module, suppresses the interference of high-frequency signals, and minimizes the noise. The performance of the post-stage analog-to-digital conversion module is maximized; the 24-bit AD7760 analog-to-digital conversion module with ultra-high precision and ultra-low power consumption is used to convert the analog signal conditioned by the previous stage into a digital signal; at the same time, the overall circuit system is based on the Cortex-M series STM32F4 microprocessor to realize data acquisition control, transmission and interaction with the host computer; in order to increase the data transmission rate with the host computer, the USB3.0 communication interface circuit is designed to realize USART-TTL serial port to USB communication, so that the transmission rate reaches 2MByte / s; in addition, the circuit system design has independent power supply and clock modules, and the function is easy to expand to facilitate the needs of other secondary development.

[0035] Specific: Since the amplitude of the measured weak signal is as low as μV level, it is very susceptible to interference from common-mode signals such as temperature drift. At the same time, the subsequent analog-to-digital conversion chip is a true differential input, so it is necessary to cooperate with a fully differential op amp structure. The fully differential op amp has a differential signal input and a differential signal output. By adjusting the op amp gain and outputting the voltage difference of the amplified signal, the interference of the common-mode signal is suppressed. In this embodiment, the single-ended signal of the first snap-fit ​​connector (Bayonet Neill-Concelman, BNC) is converted into a differential signal through the first operational amplifier AD8132ARZ.

[0036] Fully differential amplifier circuit, such as Figure 2As shown, it includes a first snap-fit ​​connector, a first resistor R34, a second resistor R35, a third resistor R36, a fourth resistor R38, a fifth resistor R40, a sixth resistor R41, a seventh resistor R43, a first capacitor C20, a second capacitor C22, a third capacitor C24 and a first operational amplifier; the first pin of the first snap-fit ​​connector is respectively connected to the first end of the fifth resistor R40 and the first end of the seventh resistor R43, the second end of the seventh resistor R43 is grounded, the second pin of the first snap-fit ​​connector is respectively grounded and connected to the first end of the second capacitor C22, the second end of the second capacitor C22 is connected to the second pin of the first operational amplifier, the second end of the fifth resistor R40 is respectively connected to the first pin of the first operational amplifier and the first end of the sixth resistor R41, the first end of the first resistor R34 is grounded, and the first resistor The second end of R34 is connected to the first end of the third resistor R36, the second end of the third resistor R36 is respectively connected to the 8th pin of the first operational amplifier and the first end of the second resistor R35, the second end of the second resistor R35 is respectively connected to the 5th pin of the first operational amplifier and the first end of the fourth resistor R38 to the negative output terminal of the first operational amplifier, the second end of the sixth resistor R41 is respectively connected to the 4th pin of the first operational amplifier and the second end of the fourth resistor R38 to the positive output terminal of the first operational amplifier, the 6th pin of the first operational amplifier is respectively connected to the first end of the third capacitor C24 and the negative power supply terminal of the first operational amplifier, the second end of the third capacitor C24 is grounded, the 3rd pin of the first operational amplifier is respectively connected to the first end of the first capacitor C20 and the positive power supply terminal of the first operational amplifier, and the second end of the first capacitor C20 is grounded.

[0037] In the fully differential amplifier circuit, when the positive and negative terminals meet the gain resistor R G1 =R G2 , feedback resistor R F1 =R F2 When , the input and output formula is:

[0038] in, is the positive output voltage value of the first operational amplifier; is the negative output voltage value of the first operational amplifier; is the gain, and G=RF / RG; is the single-ended input voltage value. After calculation and debugging, the fixed gain resistor R G =499Ω, adjust the gain G to 10, that is, R F =5kΩ, the signal in the input range of 1uV~1mV can be amplified normally and accurately adapted to the input range of the subsequent analog-to-digital conversion module.

[0039] In order to match the impedance with the internal resistance of the signal source of 50Ω, a 49.9Ω precision resistor R43 to ground is configured at the negative phase input end. At the same time, in order to compensate for the imbalance of the gain resistor, according to the Thevenin theorem, a 24.9Ω correction resistor R34 is added and connected in series with the positive phase input gain resistor. In addition, in order to prevent the load from reacting with the pins and bonding wire inductance of the AD8132ARZ, which causes high-frequency ringing in the pulse response, a 200Ω transimpedance resistor R38 is connected in series at the output of the amplifier to improve the symmetry of the differential signal.

[0040] Since the output current capacity of the fully differential amplifier circuit is limited, if it is directly connected to the subsequent digital-to-analog conversion circuit (ADC circuit), there will be an impedance mismatch problem. In order to improve the load driving capability of the amplifier circuit, it is necessary to add follower circuits at both ends of the output of the fully differential amplifier circuit to maintain the output capacity. This embodiment uses two THS4001 operational amplifiers to complete the design of the follower circuit. The THS4001 internal emitter amplifier circuit is composed of transistors, which is cheap and easy to use.

[0041] Emitter follower circuit Figure 3 As shown, it includes: a second snap-fit ​​connector, an eighth resistor R32, a ninth resistor R33, a tenth resistor R37, an eleventh resistor R39, a twelfth resistor R42, a thirteenth resistor R44, a second operational amplifier and a third operational amplifier; the second pin of the second snap-fit ​​connector is connected to the first end of the eighth resistor R32, the second end of the eighth resistor R32 is connected to the third pin of the second operational amplifier, the second pin of the second operational amplifier is connected to the first end of the tenth resistor R37, the second end of the tenth resistor R37 is respectively connected to the 6th pin of the second operational amplifier and the first end of the ninth resistor R33, and the second end of the ninth resistor R33 is connected to the 6th pin of the second operational amplifier and the first end of the ninth resistor R33. The first pin of the second snap-fit ​​connector is connected to the first end of the twelfth resistor R42, the second end of the twelfth resistor R42 is connected to the third pin of the third operational amplifier, the second end of the eleventh resistor R39 is connected to the first end of the eleventh resistor R39, the second end of the eleventh resistor R39 is respectively connected to the sixth pin of the third operational amplifier and the first end of the thirteenth resistor R44, the second end of the thirteenth resistor R44 is connected to the output end of the third operational amplifier, and the seventh pin of the third operational amplifier is connected to the 12V voltage supply end.

[0042] This embodiment adopts a single-ended to differential amplifier module designed by combining AD8132ARZ differential amplifier and THS4001 follower. This design is also applicable to differential input signal amplification, and can stably and effectively amplify weak signals into differential signals with load capacity. In general, fixed gain amplification of the signal is completed without changing the input signal type, ensuring the accuracy and strong anti-interference of the analog-to-digital conversion result.

[0043] In this embodiment, the anti-aliasing filter circuit uses the Nyquist sampling theorem, and the sampling rate is f s , any value greater than f s / 2 The frequency signal will be mirrored to 0 to f s / 2 In this embodiment, the high-precision ADC7760 chip selected by the analog-to-digital conversion module in the anti-aliasing filter circuit has a built-in digital filter, but it can only filter out the cutoff frequency to f s / 2 Noise within the interval, outside the interval f s There is still interference, so it is necessary to add an external analog anti-aliasing filter circuit. The AD7760 has an on-chip differential amplifier, which can be used to configure a first-order anti-aliasing filter, significantly reducing the anti-aliasing requirements. Therefore, based on the on-chip differential amplifier, a feedback resistor is added. R f and feedback capacitor C f When the input signal is 1kHz, the cutoff frequency is set to 1.59kHz through the input resistor Rin and the bypass capacitor Cs to filter out the aliasing signal returned by the high-frequency noise. The feedback resistor Rfb and the feedback capacitor Cfb are used to control the gain frequency response of the amplifier to ensure the stability of the amplifier, improve the signal-to-noise ratio of the system, and achieve the purpose of anti-aliasing filtering.

[0044] Anti-aliasing filter circuit such as Figure 4As shown, the embodiment includes: a fourteenth resistor Rin1, a fifteenth resistor Rin2, a sixteenth resistor Rfb1, a seventeenth resistor Rfb2, an eighteenth resistor Rm1, a nineteenth resistor Rm2, a fourth capacitor Cs, a fifth capacitor Cfb1 and a sixth capacitor Cfb2; a first end of the fourteenth resistor Rin1 is connected to the output end of the second operational amplifier, a second end of the fourteenth resistor Rin1 is respectively connected to the first end of the fourth capacitor Cs, the first end of the fifth capacitor Cfb1 and the first end of the sixteenth resistor Rfb1, a second end of the fifth capacitor Cfb1 and a second end of the sixteenth resistor Rfb1 are connected to The first end of the eighteenth resistor Rm1 and the second end of the eighteenth resistor Rm1 are connected to the negative input terminal of the signal of the subsequent AD7760 chip, the first end of the fifteenth resistor Rin2 is connected to the output terminal of the third operational amplifier, the second end of the fifteenth resistor Rin2 is respectively connected to the second end of the fourth capacitor Cs, the first end of the sixth capacitor Cfb2 and the first end of the seventeenth resistor Rfb2, the second end of the sixth capacitor Cfb2 and the second end of the seventeenth resistor Rfb2 are connected to the first end of the nineteenth resistor Rm2, and the second end of the nineteenth resistor Rm2 is connected to the positive input terminal of the signal of the subsequent AD7760 chip.

[0045] In this embodiment, the analog-to-digital conversion module is a Sigma-Delta analog-to-digital conversion module, specifically including: an analog-to-digital conversion chip, a voltage reference source circuit and an external clock circuit; wherein, the analog-to-digital conversion chip adopts a 24-bit resolution, Sigma-Delta type AD7760 chip, combining the advantages of wide input bandwidth, high-speed characteristics and Sigma-Delta conversion technology. The chip can achieve a signal-to-noise ratio of up to 100dB at a sampling rate of 2.5MSPS, which is very suitable for data acquisition applications; to ensure the smooth operation of the analog-to-digital conversion, the ADC peripheral voltage reference source circuit and the external clock circuit are designed. In order to make the AD7760 achieve an accurate 24-bit resolution, a 4.096V voltage is required as the reference source. Following the performance requirements of ultra-low noise and extremely low temperature drift, the module selects ADR434ARMZ as the ADC voltage reference chip to provide a 4.096V accurate voltage. The ADC voltage reference source circuit scheme is as follows, adding a passive RC low-pass filter, and the low-pass filter circuit includes the twentieth resistor R47 and the ninth capacitor C29 to enhance the stability of the output voltage.

[0046] The structure of the voltage reference source circuit is as follows: Figure 5As shown, it includes: a voltage reference chip, a seventh capacitor C27, an eighth capacitor C28, a ninth capacitor C29, a twentieth resistor R47 and a twenty-first resistor R48; the second pin of the voltage reference chip is respectively connected to the first end of the seventh capacitor C27, the first end of the eighth capacitor C28 and the 5V power supply end, the fourth pin of the voltage reference chip is respectively connected to the second end of the seventh capacitor C27 and the second end of the eighth capacitor C28 and grounded, the sixth pin of the voltage reference chip is connected to the first end of the twentieth resistor R47, the second end of the twentieth resistor R47 is respectively connected to the first end of the ninth capacitor C29 and the first end of the twenty-first resistor R48, the second end of the ninth capacitor C29 is grounded, and the second end of the twenty-first resistor R48 is connected to the reference voltage input end.

[0047] Furthermore, in order to improve the sampling and conversion rate of the analog-to-digital conversion module, the upper limit of the main frequency of the analog-to-digital conversion module ADC is taken as 40MHz, which is used as the external clock of the ADC. The external clock circuit is designed as follows: Since the high-frequency noise of the power supply has a very serious impact on the crystal oscillator frequency, according to the electromagnetic compatibility (EMC) requirements of the active crystal oscillator, an LC filtering circuit is added to the crystal oscillator power supply to improve the purity of the signal; the NC7SZ08M5X buffer chip is used to divide the output into two paths, and different clock levels are provided at the same time: one path is provided to the analog-to-digital conversion module ADC as a sampling clock reference, and the other path is provided to the main control module MCU as an external trigger source to control the sampling timing.

[0048] External clock circuit such as Figure 6As shown, it includes: a first buffer chip, a second buffer chip, a first inductor L1, a twenty-second resistor R46, a twenty-third resistor R49, a twenty-fourth resistor R51, a tenth capacitor C26 and an active crystal oscillator chip; wherein the active crystal oscillator chip is specifically a 40M active crystal oscillator chip, a first end of the first inductor L1 is connected to a 5V voltage supply terminal, a second end of the first inductor L1 is respectively connected to a first end of the tenth capacitor C26, a first pin and an eighth pin of the active crystal oscillator chip, a second end of the tenth capacitor C26 is connected to a fourth pin of the active crystal oscillator chip and is grounded, a fifth pin of the active crystal oscillator chip is connected to a first end of the twenty-third resistor R49, and a The second end is respectively connected to the first pin and the second pin of the first buffer chip, and the first pin and the second pin of the second buffer chip, the third pin of the first buffer chip is grounded, the third pin of the second buffer chip is grounded, the fifth pin of the first buffer chip is connected to the 5V voltage power supply end, the fifth pin of the second buffer chip is connected to the 5V voltage power supply end, the fourth pin of the first buffer chip is connected to the first end of the twenty-second resistor R46, the second end of the twenty-second resistor R46 is connected to the clock input end of the analog-to-digital conversion module, the fourth pin of the second buffer chip is connected to the first end of the twenty-fourth resistor R51, and the second end of the twenty-fourth resistor R51 is connected to the clock input end of the main control module.

[0049] The ARM main control module consists of the STM32F407VGT6 minimum system and ADC reset circuit. Figure 7 As shown in the figure, the minimum system provides the basic hardware environment for the microcontroller to operate normally, is responsible for data transmission and timing synchronization control with the ADC, and finally sends the collected data to the user via USB. Compared with traditional FPGA chips, this solution achieves a significant reduction in cost and maximizes the performance utilization efficiency of the main control chip.

[0050] like Figure 8 As shown, the ADC reset circuit is responsible for initializing the ADC to a known initial state when the system starts up, ensuring that the ADC can start working reliably when it starts up or resets. It can be intervened and controlled manually by the main control module. The circuit scheme is as follows: through the coordinated application of the microprocessor monitoring chip ADM6711 and the logic gate circuit, the ADC power-on reset, manual reset and software reset are realized.

[0051] The present invention adopts the STM32F407VGT6 high-performance, low-cost ARM master control to replace the traditional FPGA to drive the high-speed ADC chip and communicate with the host computer. Although the general ARM master control runs relatively slowly, the DMA+timer trigger transmission technology is used to allow the peripherals and the memory to directly exchange data, which can effectively reduce the burden of the CPU, ensure the sampling speed, and improve the performance utilization of the master chip year-on-year; and compared with the data acquisition system of NI company using FPGA master control, this method has low cost, low power consumption, and higher cost performance.

[0052] like Fig. 9 As shown in the figure, the USB communication module is divided into two USB ports, and the circuit design is as follows: one end is connected to the UART pin of the microcontroller through the USB to serial port adapter chip CP2102, which serves as the information printing serial port for software debugging; the other end is directly connected to the USB pin of the microcontroller through a 22Ω resistor, which serves as the main interface for data communication with the host computer and is responsible for transmitting the data collected by the ADC to the host computer at a rate of up to 2MByte / s.

[0053] Since each circuit module has different power consumption requirements, the power supply part adopts a separate power supply design to reduce power supply noise and interference transmission, improve the flexibility and expandability of the power supply module, and ensure the stable operation of each module. The power supply design of this system is divided into three parts: the digital-to-analog conversion module AD7760, the main control module and other circuits, each of which is powered independently.

[0054] The AD7760 part of the digital-to-analog conversion module requires multiple independent analog power supplies (AVDDx) and a separate digital power supply for power supply. The power supply design scheme of the digital-to-analog conversion module is as follows: Fig.10 As shown in the figure, the total power supply is 7.5V through the AD terminal input, and the input port is connected in series with an SS24 anti-reverse diode and a feedthrough filter capacitor to increase the safety and stability of the system. Then the upper end is regulated by the ADP7104 power chip to generate a 2.5V voltage, which is used to power VDRIVE, AVDD1, and DVDD respectively; the lower end is also converted to a 5V voltage by the ADP7104 power chip, which is used to power AVDD2, AVDD3, and AVDD4 respectively. In order to prevent high-frequency interference caused by power supply noise on ADC sampling, each output is equipped with a 1nF feedthrough capacitor filter to ensure the accuracy and stability of ADC data acquisition.

[0055] The main control module requires digital power supply, and two ADP7104 low-noise power chips are used to generate 5V and 2.5V outputs respectively. The 5V output generates 3.3V voltage through low-power LDO to power the MCU and its peripheral circuits to ensure the normal operation of the system; and the 2.5V voltage is used to power the voltage monitoring and reset circuits to ensure that the system can be correctly reset during startup and operation. Fig.11 shown.

[0056] The remaining power supply is mainly used to power the differential amplifier circuit and the follower circuit. The op amp power supply design is designed. Since this part of the power supply is used to power the analog circuit, and to avoid interference with the AD7760 circuit, it is designed separately to reduce electromagnetic interference and radio frequency interference and improve the stability of the entire system. Fig.12 shown.

[0057] For Fig.13 The FPGA-based data acquisition module solution shown in the figure has problems such as high power consumption and complex timing design. Fig.14 The data acquisition module solution based on Atmega128A shown has the problems of low sampling accuracy, complex system design and testing process, and difficulty in matching high-speed acquisition environment. The present invention designs a high-precision, high-speed analog signal acquisition system with sufficiently high sampling accuracy and a resolution of not less than 24 bits; supports weak signal acquisition, and the minimum resolution signal for weak signal acquisition is 10uV; has high resistance to signal aliasing and a signal-to-noise ratio of not less than 100dB; has a sufficiently high sampling rate and a sampling rate of not less than 1MSPS; has multi-signal adaptability, flexible coupling forms, a wide frequency domain range, and a large amplitude range span; and has the characteristics of low cost.

[0058] Embodiment 2 In one or more embodiments, a high-precision weak signal acquisition method based on an ARM processor is disclosed, comprising: A fully differential amplifier circuit is used to receive and amplify the weak signal to be measured; An emitter follower circuit is used to receive the amplified weak signal to be measured, which is used for impedance matching and transmitted to the anti-aliasing filter circuit for filtering; An analog-to-digital conversion module is used to convert the filtered analog signal into a digital signal; The main control module is used to realize the acquisition of high-precision weak signals.

[0059] In this embodiment, the analog-to-digital conversion module, the main control module, the full differential amplifier circuit and the emitter follower circuit are powered by three independent parts.

[0060] The description of each embodiment in the above embodiments has different emphases. For parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0061] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A high-precision weak signal acquisition system based on ARM processor, characterized in that: include: Fully differential amplifier circuit, emitter follower circuit, anti-aliasing filter circuit, analog-to-digital conversion module and main control module; The fully differential amplifier circuit is used to receive and amplify the weak signal to be measured; The emitter follower circuit receives the amplified weak signal to be measured for impedance matching, and transmits it to the anti-aliasing filter circuit for filtering; The analog-to-digital conversion module converts the filtered analog signal into a digital signal; The main control module is used to control the acquisition of high-precision weak signals.

2. A high-precision weak signal acquisition system based on an ARM processor as claimed in claim 1, characterized in that: The fully differential amplifier circuit has a differential signal input and a differential signal output, and outputs a voltage value of the amplified signal by adjusting the operational amplifier gain.

3. A high-precision weak signal acquisition system based on an ARM processor as claimed in claim 2, characterized in that: In the fully differential amplifier circuit, when the positive and negative terminals meet the gain resistance R G1 =R G2 , feedback resistor R F1 =R F2 When , the input and output formula is: in, is the positive output voltage value of the first operational amplifier; is the negative output voltage value of the first operational amplifier; is the gain, and G=RF / RG; is the single-ended input voltage value.

4. A high-precision weak signal acquisition system based on an ARM processor as claimed in claim 1, characterized in that: Adding emitter follower circuits at both ends of the output of the fully differential amplifier circuit respectively; The emitter follower circuit achieves fixed gain amplification of the signal without changing the input signal type through a single-ended to differential amplification module combined with a fully differential amplification circuit, and amplifies the weak signal into a differential signal with load capacity.

5. The high-precision weak signal acquisition system based on an ARM processor as claimed in claim 1, characterized in that: The anti-aliasing filter circuit is a first-order anti-aliasing filter, which controls the gain frequency response of the amplifier by adding a feedback resistor and a feedback capacitor.

6. A high-precision weak signal acquisition system based on an ARM processor as claimed in claim 1, characterized in that: The analog-to-digital conversion module includes an analog-to-digital conversion chip, a voltage reference source circuit and an external clock circuit; The voltage reference source circuit includes a voltage reference chip, and a low-pass filter circuit is added to the voltage reference chip to stabilize the output voltage; The external clock circuit includes a first buffer chip and a second buffer chip; the output of the clock signal is divided into two paths through the first buffer chip and the second buffer chip, one path is used as the sampling clock reference of the analog-to-digital conversion module, and the other path is used as the external trigger source of the main control module to control the sampling timing.

7. A high-precision weak signal acquisition system based on an ARM processor as claimed in claim 1, characterized in that: include: The main control module is used to perform data transmission and timing synchronization control with the analog-to-digital conversion module.

8. The high-precision weak signal acquisition system based on an ARM processor as claimed in claim 1, characterized in that: It also includes a power module, a communication module and a host computer; The power supply module includes a first power supply unit, a second power supply unit and a third power supply unit, each of which supplies power independently; the first power supply unit is used to power the digital-to-analog conversion module, the second power supply unit is used to power the main control module; the third power supply unit is used to power the differential amplifier circuit and the emitter follower circuit.

9. A high-precision weak signal acquisition method based on an ARM processor, characterized in that: include: A fully differential amplifier circuit is used to receive and amplify the weak signal to be measured; An emitter follower circuit is used to receive the amplified weak signal to be measured, which is used for impedance matching and transmitted to the anti-aliasing filter circuit for filtering; An analog-to-digital conversion module is used to convert the filtered analog signal into a digital signal; The main control module is used to realize the acquisition of high-precision weak signals.

10. A high-precision weak signal acquisition method based on an ARM processor as claimed in claim 9, characterized in that: Also includes: The analog-to-digital conversion module, the main control module, the full differential amplifier circuit and the emitter follower circuit are powered by three independent parts.

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