Quick-assembly pipeline performance testing device and testing method

Abstract

The invention discloses a device and a method for testing the performance of a fast-assembly pipeline. The device comprises a host and a slave, the host comprises a host power supply management module, a boost circuit, an insulation current sampling module, a first single-chip microcomputer, a host communication module, a high-low voltage power supply switching module and a host line switching module. The slave machine comprises a slave machine power supply management module, a second single chip microcomputer, a slave machine line switching module and a slave machine communication module; the host line switching module is used for switching the host to different lines to be connected with the slave, and the slave line switching module is used for switching the slave to different lines to be connected with the host, so that the insulation resistance, the conductivity and the line sequence of the fast-assembly pipeline are tested.

Description

Technical Field

[0001] The invention belongs to the field of electrical technology, and in particular relates to a quick-install pipeline performance testing device and a testing method. Background Art

[0002] The construction market is an important pillar industry in my country, and wires and cables are an important carrier in building electrical construction. In the design and construction of building electrical appliances, the terminal electrical pipelines entering the house are currently mostly wired in protective pipes. The construction procedures are: cutting grooves, burying pipes, threading, wiring, etc. In order to facilitate threading in the pipe, it is necessary to reserve threading wires in the pipe when laying the wire pipe, and polish the end of the protective pipe to prevent the wires from being scratched during threading. In order to make threading smooth, the pipe mouth should be pre-treated, and threading boxes and junction boxes should be set up at turns and branches according to construction specifications. Special tools are required to connect the bends and pipes during on-site construction, and wiring must be carried out in accordance with electrical specifications.

[0003] The quick-install pipeline technology can realize factory prefabrication of wire pipes, quick connection on site, and the elimination of junction boxes and on-site bending of pipes, which greatly simplifies the wire threading and wiring links in construction. It has the advantages of high product quality, simple and fast and efficient on-site construction, low technical requirements for construction personnel, and easy control of construction quality. It is an upgraded replacement method for traditional electrical terminal pipeline construction.

[0004] After the quick-install pipeline is installed, relevant tests need to be carried out to ensure the reliability of the product. However, since the quick-install pipeline is different from the electrical pipeline in the traditional construction industry, the previous test scheme cannot be used for quick-install pipelines, and there is currently no relevant equipment for quick-install pipeline performance testing. Summary of the invention

[0005] An object of the present invention is to provide a quick-install pipeline performance testing device and a testing method, which can solve the technical problem that the quick-install pipeline cannot be tested for performance in the prior art.

[0006] According to a first aspect of the present invention, there is provided a fast-assembly pipeline performance testing device, comprising a host and a slave;

[0007] The host includes a host power management module, a boost circuit, an insulation current sampling module, a first single-chip microcomputer, a host communication module, a high-low voltage power switching module, and a host line switching module;

[0008] The host power management module is used to output a 3.3V voltage to the first single-chip microcomputer, output a 5V voltage to the high-low voltage power switching module, and provide a battery voltage to the boost circuit;

[0009] The boost circuit is used to increase the battery voltage output by the host power management module to 500V, and output 500V voltage to the insulation current sampling module;

[0010] The high and low voltage power supply switching module is used to switch the test voltage during the test to 500V or 5V. The 500V test voltage is used in the insulation resistance test process, and the 5V test voltage is used in the continuity test process and the line sequence test process.

[0011] The first single chip microcomputer is used to communicate with the slave through the host communication module, control the insulation current sampling module to perform sampling, and control the host line switching module to perform line switching;

[0012] The slave includes a slave power management module, a second single-chip microcomputer, a slave line switching module, and a slave communication module;

[0013] The slave power management module is used to supply power to the second single-chip microcomputer;

[0014] The second single chip microcomputer is used to communicate with the host through the slave communication module and control the slave line switching module to perform line switching;

[0015] The host line switching module is used to switch the host to different lines to connect with the slave, and the slave line switching module is used to switch the slave to different lines to connect with the host, so as to test the insulation resistance, conductivity and line sequence of the quick-install pipeline.

[0016] Optionally, the host line switching module includes a first switching module, a second switching module, and a third switching module, the first switching module and the second switching module are located at a later stage of the third switching module, the first switching module and the second switching module are used to switch the host output direction, and the third switching module is used to switch between high and low voltage;

[0017] The first switching module includes a first relay, a first diode, a first resistor, a second resistor, and a first MOS tube;

[0018] The first end of the first resistor is connected to the K1_COM port, the K1_COM port is connected to the first single-chip computer, the second end of the first resistor is respectively connected to the first end of the second resistor and the gate of the first MOS tube, the second end of the second resistor and the source of the first MOS tube are grounded, the drain of the first MOS tube is respectively connected to the anode of the first diode and the first end of the first relay, the cathode of the first diode is respectively connected to the eighth end of the first relay and VCC_FORLDO, the second end of the first relay is connected to L_TEST, the third end of the first relay is connected to the OUT_Power port, the fourth end of the first relay is connected to the SW_K2A port, the fifth end of the first relay is connected to the SW_K2B port, the SW_K2A port and the SW_K2B port are connected to the second switching module, the sixth end of the first relay is connected to the OUT_Ground port, the seventh end of the first relay is connected to the N_TEST port, the third end of the first relay is connected to the second end of the first relay or the third end of the first relay is connected to the fourth end of the first relay, the sixth end of the first relay is connected to the seventh end of the first relay or the sixth end of the first relay is connected to the fifth end of the first relay.

[0019] Optionally, the second switching module includes a second relay, a second diode, a third resistor, a fourth resistor, and a second MOS tube;

[0020] A first end of the third resistor is connected to the K2_COM port, which is connected to the first single-chip computer; a second end of the third resistor is respectively connected to the first end of the fourth resistor and the gate of the second MOS tube; a second end of the fourth resistor and the source of the second MOS tube are grounded; a drain of the second MOS tube is respectively connected to the anode of the second diode and the first end of the second relay; a cathode of the second diode is respectively connected to the eighth end of the second relay and the VCC_FORLDO port; a second end of the second relay is connected to the G_TEST port; a third end of the second relay is connected to the SW_K2A port; a fourth end of the second relay is connected to the N_TEST port; a fifth end of the second relay is connected to the G_TEST port; a sixth end of the second relay is connected to the SW_K2B port; a seventh end of the second relay is connected to the L_TEST port; a third end of the second relay is connected to the second end of the second relay or a third end of the second relay is connected to the fourth end of the second relay; a sixth end of the second relay is connected to the seventh end of the second relay or a sixth end of the second relay is connected to the fifth end of the second relay.

[0021] Optionally, the third switching module includes a third relay, a sixth diode, a nineteenth resistor, a twentieth resistor, and a seventh MOS tube;

[0022] The first end of the nineteenth resistor is connected to the K3_COM port, and the K3_COM port is connected to the first single-chip computer. The second end of the nineteenth resistor is respectively connected to the first end of the twentieth resistor and the gate of the seventh MOS tube. The second end of the twentieth resistor and the source of the seventh MOS tube are grounded. The drain of the seventh MOS tube is respectively connected to the anode of the sixth diode and the first end of the third relay. The cathode of the sixth diode is respectively connected to the eighth end of the third relay and the VCC_FORLDO port. The second end of the third relay is connected to the VCC_FORLDO port via the thirtieth resistor. The third end of the third relay is connected to the anode of the seventh diode, and the cathode of the seventh diode is connected to the OUT_Power port. The fourth end of the third relay is connected to 500V. The fifth end of the third relay is connected to the AGND_BEFORE port. The sixth end of the third relay is connected to the OUT_Ground port. The seventh end of the third relay is connected to the GND port. The third end of the third relay is connected to the second end of the third relay or the third end of the third relay is connected to the fourth end of the third relay. The sixth end of the third relay is connected to the seventh end of the third relay or the sixth end of the third relay is connected to the fifth end of the third relay.

[0023] Optionally, the insulation current sampling module includes a fourteenth resistor and a transient voltage suppression diode;

[0024] The two ends of the transient voltage suppression diode are respectively connected to the two ends of the fourteenth resistor, the two ends of the fourteenth resistor are respectively connected to the positive input pin of the amplifier chip and the negative input pin of the amplifier chip, the positive input pin of the amplifier chip is connected to the AGND_BEFORE port, the negative input pin of the amplifier chip is connected to 500V_GND, the output pin of the amplifier chip is respectively connected to the ADC sampling interface ADC2 of the first microcontroller and the first end of the thirtieth capacitor, the second end of the thirtieth capacitor is grounded, the power pin of the amplifier chip is respectively connected to the VCC_FORLDO port and the first end of the fifteenth capacitor, and the second end of the fifteenth capacitor is grounded.

[0025] Optionally, the host further includes a high-voltage overcurrent protection module, which includes a first connector, a fuse, and a twenty-third resistor;

[0026] The first end of the fuse is connected to pin 1 of the first connector, the second end of the fuse is connected to the first end of the twenty-third resistor, the second end of the twenty-third resistor is connected to the 500V port, and the pin 3 of the first connector is connected to the 500V_GND port.

[0027] Optionally, the slave line switching module includes a fourth switching module and a fifth switching module;

[0028] The LOW_OUT_L port of the fourth switching module is respectively connected to the first end of the eighth resistor and the first end of the twelfth resistor, the LOW_OUT_N port of the fourth switching module is respectively connected to the first end of the eleventh resistor and the first end of the tenth resistor, and the LOW_OUT_G port of the fifth switching module is respectively connected to the first end of the ninth resistor and the first end of the thirteenth resistor;

[0029] The second end of the eighth resistor and the second end of the eleventh resistor are connected to the ADC sampling interface TEST_LN of the second single-chip microcomputer, the second end of the ninth resistor and the second end of the twelfth resistor are connected to the ADC sampling interface TEST_GL of the second single-chip microcomputer, and the second end of the tenth resistor and the second end of the thirteenth resistor are connected to the ADC sampling interface TEST_NG of the second single-chip microcomputer.

[0030] Optionally, the fourth switching module includes a fourth relay, a fourth diode, a fifteenth resistor, a sixteenth resistor, a third MOS tube, a fifth resistor, and a sixth resistor;

[0031] The first end of the fourth relay is respectively connected to the VOUT port and the cathode of the fourth diode, the eighth end of the fourth relay is respectively connected to the anode of the fourth diode and the drain of the third MOS tube, the source of the third MOS tube is connected to the GND port, the gate of the third MOS tube is respectively connected to the first end of the fifteenth resistor and the first end of the sixteenth resistor, the second end of the fifteenth resistor is connected to the K1&K2_COM port, the K1&K2_COM port is connected to the second single-chip computer, the second end of the sixteenth resistor is connected to GND, the second end of the fourth relay is connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the L_TEST port, the seventh end of the fourth relay is connected to the first end of the sixth resistor, the second end of the sixth resistor is connected to the G_TEST port, the third end of the fourth relay is connected to the N_TEST port of the second connector, the sixth end of the fourth relay is connected to the L_TEST port of the second connector, the fourth end of the fourth relay is connected to the LOW_OUT_N port, and the fifth end of the fourth relay is connected to the LOW_OUT_L port;

[0032] The third end of the fourth relay is connected to the second end of the fourth relay or the third end of the fourth relay is connected to the fourth end of the fourth relay, the sixth end of the fourth relay is connected to the seventh end of the fourth relay or the sixth end of the fourth relay is connected to the fifth end of the fourth relay;

[0033] The VOUT port is connected to the cathode of the third diode, and the anode of the third diode is connected to the slave battery.

[0034] Optionally, the fifth switching module includes a fifth relay, a fifth diode, a seventeenth resistor, an eighteenth resistor, a fourth MOS tube, and a seventh resistor;

[0035] The first end of the fifth relay is respectively connected to the VOUT port and the cathode of the fifth diode, the eighth end of the fifth relay is respectively connected to the anode of the fifth diode and the drain of the fourth MOS tube, the source of the fourth MOS tube is connected to the GND port, the gate of the fourth MOS tube is respectively connected to the first end of the seventeenth resistor and the first end of the eighteenth resistor, the second end of the eighteenth resistor is connected to GND, the second end of the seventeenth resistor is connected to the K1&K2_COM port, the K1&K2_COM port is connected to the second single-chip computer, the second end of the fifth relay is connected to the first end of the seventh resistor, the second end of the seventh resistor is connected to the N_TEST port, the third end of the fifth relay is connected to the G_TEST port of the second connector, and the fourth end of the fifth relay is connected to the LOW_OUT_G port.

[0036] Optionally, the host is provided with a storage compartment for storing the slave, a third connector including five pins is provided in the storage compartment of the host, a fourth connector corresponding to the third connector is provided on the slave, and when the slave is in the storage compartment, each pin of the fourth connector is correspondingly connected to each pin of the third connector;

[0037] Pin 5 of the third connector is connected to pin 1 of the fourth connector to enable output when charging the slave device;

[0038] Pin 4 of the third connector and pin 2 of the fourth connector are connected to the GND port;

[0039] Pin 3 of the third connector is connected to the TX pin of the UART interface of the first single-chip microcomputer and pin 3 of the fourth connector, and pin 3 of the fourth connector is connected to the RX pin of the UART interface of the second single-chip microcomputer;

[0040] Pin 2 of the third connector is connected to pin 4 of the fourth connector, and pin 2 of the third connector is used to obtain the slave battery voltage through pin 4 of the fourth connector;

[0041] Pin 1 of the third connector is connected to pin 5 of the fourth connector. Pin 1 of the third connector is used to control whether the slave is powered on in the storage bin. It outputs a high level when the slave needs to be powered on in the storage bin, and outputs a low level in other cases.

[0042] According to a second aspect of the present invention, there is provided a testing method for the fast-assembly pipeline performance testing device according to the first aspect of the present invention, comprising:

[0043] Before starting the test, pair the slave with the master in the storage compartment;

[0044] After pairing is completed, remove the slave from the storage compartment, the slave will automatically power on, and the host and slave will establish wireless communication;

[0045] Install the master and slave at both ends of the pipeline respectively;

[0046] Press the test button, the host switches to 5V low voltage mode, and performs low voltage test in 5V low voltage mode. The low voltage test includes continuity test and line sequence test.

[0047] If the low-voltage test result is abnormal, perform troubleshooting based on the low-voltage test result;

[0048] If the result of the low-voltage test is normal, the host switches to the 500V high-voltage mode and performs the insulation resistance test in the 500V high-voltage mode;

[0049] If the insulation resistance test result is abnormal, perform troubleshooting based on the insulation resistance test result;

[0050] If the insulation resistance test result is normal, determine whether there are other output ports that need to be tested;

[0051] If it exists, remove the slave and install it at other output ports that need to be tested, and then retest.

[0052] Optionally, during the low voltage test, the slave determines the output direction of the host line by wirelessly communicating with the host;

[0053] When the output direction is L positive and N negative, the voltages of the three points TEST_LN, TEST_GL, and TEST_NG are collected, and the first result bit is determined according to the voltages of the three points;

[0054] When the output direction is G positive and L negative, the voltages of the three points TEST_LN, TEST_GL, and TEST_NG are collected, and the second result bit is determined according to the voltages of the three points;

[0055] When the output direction is N positive and G negative, the voltages of the three points TEST_LN, TEST_GL, and TEST_NG are collected, and the third result bit is determined according to the voltages of the three points;

[0056] The slave sends the first result bit, the second result bit, and the third result bit to the host via wireless communication;

[0057] The host searches the error dictionary according to the received first result bit, second result bit, and third result bit to determine the fault type.

[0058] Optionally, the process of determining the first result bit includes:

[0059] If the voltages at the three points are floating values, the first result bit is determined to be 4;

[0060] If the voltages at the three points are not floating values ​​and the first condition and the second condition are met, the first result bit is determined to be 1;

[0061] If the voltages of the three points are not floating values ​​and the first and third conditions are met, the first result bit is determined to be 2;

[0062] If the voltages of the three points are not floating values, and the first condition, the second condition, and the third condition are not satisfied, the first result bit is determined to be 3;

[0063] Among them, the first condition is TEST_GL>TEST_LN+0.3V;

[0064] The second condition is TEST_LN>TEST_NG+0.3V;

[0065] The third condition is TEST_GL>TEST_NG+0.3V.

[0066] Optionally, the process of determining the second result bit includes:

[0067] If the voltages at the three points are floating, the second result bit is determined to be 4;

[0068] If the voltages of the three points are not floating values ​​and the fourth condition and the first condition are met, the second result bit is determined to be 1;

[0069] If the voltages of the three points are not floating values ​​and the fourth and fifth conditions are met, the second result bit is determined to be 2;

[0070] If the voltages at the three points are not floating values, and the fourth condition, the fifth condition and the first condition are not satisfied, the second result bit is determined to be 3;

[0071] Among them, the fourth condition is TEST_NG>TEST_GL+0.3V;

[0072] The fifth condition is TEST_NG>TEST_LN+0.3V;

[0073] Optionally, the process of determining the third result bit includes:

[0074] If the voltages at the three points are floating values, the third result bit is determined to be 4;

[0075] If the voltages at the three points are not floating values ​​and the fourth and sixth conditions are met, the third result bit is determined to be 1;

[0076] If the voltages at the three points are not floating values ​​and the sixth and seventh conditions are met, the third result bit is determined to be 2;

[0077] If the voltages at the three points are not floating values, and the fourth condition, the sixth condition, and the seventh condition are not satisfied, the third result bit is determined to be 3;

[0078] Among them, the sixth condition is TEST_LN>TEST_NG+0.3V;

[0079] The seventh condition is TEST_LN>TEST_GL+0.3V.

[0080] Optionally, if the value of the target result bit is outside the normal range, the target result bit is set to 5, indicating that the slave has a fault.

[0081] Optionally, the pairing process of the master and the slave includes:

[0082] After receiving the pairing command, the host controls the slave to turn on in the storage compartment through pin 1 of the third connector;

[0083] After the slave is powered on, the host transmits the UID to the slave via wired communication for pairing.

[0084] The beneficial effect of the present invention is that the present invention can connect the host and the slave through different lines through the mutual cooperation of the host and the slave, so as to realize the test of the live wire, the neutral wire and the ground wire. It is only necessary to install the host and the slave at both ends of the pipeline respectively, so as to automatically complete the test of the insulation resistance, conductivity and line sequence of the pipeline. The equipment can measure all three types of parameters through a test process, and display whether the insulation resistance is good, display the conduction result, and display whether the line sequence is connected correctly. If the fault type is a single fault, it can be measured and prompted. For non-single faults, prompts can be given. In a single fault, when the line sequence is reversed, the two wires that are specifically connected in reverse are displayed, when the conduction is short-circuited, the two wires that are specifically short-circuited are displayed, and when the conduction is disconnected, a single wire that is specifically disconnected is displayed; in a non-single fault, it is informed that there is a fault and it is not a single fault. Compared with traditional shaking meters and multimeter testing methods, the present invention has high integration, more convenient testing, and can accurately display the fault situation, helping staff to quickly complete fault troubleshooting and improve work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Figure 1 It is a schematic diagram of a quick-install pipeline performance testing device of the present invention.

[0086] Figure 2 It is a schematic diagram of the quick-install pipeline performance test process in an embodiment of the present invention.

[0087] Figure 3 is a schematic diagram of a first switching module in an embodiment of the present invention.

[0088] Figure 4 is a schematic diagram of a second switching module in an embodiment of the present invention.

[0089] Figure 5 is a schematic diagram of a third switching module in an embodiment of the present invention.

[0090] Figure 6Schematic diagram of an insulation current sampling module in an embodiment of the present invention.

[0091] Figure 7 Schematic diagram of a high-voltage overcurrent protection module in an embodiment of the present invention.

[0092] Figure 8 Schematic diagram of slave sampling in an embodiment of the present invention.

[0093] Fig. 9 is a schematic diagram of a fourth switching module and a fifth switching module in an embodiment of the present invention.

[0094] Fig.10 Schematic diagram of the connection of the VOUT port in an embodiment of the present invention. DETAILED DESCRIPTION

[0095] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0096] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0097] The techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0098] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0099] In the specification and claims of the present invention, if the term "first" or "second" is involved, it may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the related objects are in an "or" relationship.

[0100] like Figure 1 As shown, this embodiment introduces a fast-assembly pipeline performance testing device, including a host and a slave.

[0101] The host includes a host power management module, a boost circuit, an insulation current sampling module, a first single-chip microcomputer, a host communication module, a high-low voltage power switching module, and a host line switching module.

[0102] The host power management module is used to output 3.3V voltage to the first single-chip microcomputer, output 5V voltage to the high and low voltage power switching module, and provide battery voltage to the boost circuit; the boost circuit is used to increase the battery voltage output by the host power management module to 500V voltage, and output 500V voltage to the insulation current sampling module; the high and low voltage power switching module is used to switch the test voltage during the test process to 500V or 5V, the 500V test voltage is used for the insulation resistance test process, and the 5V test voltage is used for the conductivity test process and the line sequence test process; the first single-chip microcomputer is used to communicate with the slave through the host communication module, control the insulation current sampling module to perform sampling, and control the host line switching module to perform line switching.

[0103] The slave includes a slave power management module, a second single-chip microcomputer, a slave line switching module, and a slave communication module.

[0104] The slave power management module is used to supply power to the second single-chip microcomputer; the second single-chip microcomputer is used to communicate with the host through the slave communication module, and to control the slave line switching module to switch the line; the host line switching module is used to switch the host to different lines to connect with the slave, and the slave line switching module is used to switch the slave to different lines to connect with the host, so as to realize the insulation resistance, conductivity and line sequence testing of the quick-install pipeline.

[0105] The host power management module includes the host battery and corresponding circuits to power other low-voltage parts of the host, and provide a 500V test voltage for the test process through a boost circuit.

[0106] The host part needs to test the insulation resistance, so it needs to be equipped with a voltage reference chip. However, the accuracy requirement of the slave test part is not high, so no voltage reference chip is needed.

[0107] The performance test of the quick-install pipeline includes insulation resistance test, continuity test and line sequence test. The continuity test results include short circuit, open circuit and normal conduction of the neutral wire, live wire and ground wire. The line sequence test results include reverse connection of the neutral wire and live wire, reverse connection of the neutral wire and ground wire, reverse connection of the live wire and ground wire, disordered sequence of the three wires and normal line sequence.

[0108] Before starting the test, the host and slave need to be paired. The purpose of pairing is to ensure normal data transmission between the host and the slave. Both the host and the slave are equipped with a communication module, which is used to realize data transmission between the host and the slave. The communication method adopts 433M low-frequency communication to ensure long-distance transmission as much as possible. The 433 communication module is a broadcast mode. In order to avoid mistransmission of information, interference from multiple devices and external interference, the proposed data packet format is shown in Table 1.

[0109] Table 1 Data packet format

[0110]

[0111] The address part is the basis for ensuring data mistransmission, multi-device interference and external interference. To ensure the recognition and difference of the address, part of the UID code of the first microcontroller of the host is used as the address. At the same time, the automatic pairing function can be realized in this way.

[0112] After pairing is completed, install the host and slave at both ends of the quick-install pipeline respectively, and test the quick-install pipeline between the host and slave. The host line switching module can switch the host to different lines, and the slave line switching module can switch the slave to different lines. Through the cooperation of the host line switching module and the slave line switching module, the host and slave are connected through different lines, thereby completing the test process. The specific test process is as follows Figure 2 shown.

[0113] In this embodiment, the host line switching module includes a first switching module, a second switching module, and a third switching module. The first switching module and the second switching module are located at the rear stage of the third switching module. The first switching module and the second switching module are used to switch the host output direction, and the third switching module is used to switch between high and low voltage.

[0114] like Figure 3 As shown, the first switching module includes a first relay K1, a first diode D1, a first resistor R1, a second resistor R2, and a first MOS tube Q1.

[0115] The first end of the first resistor R1 is connected to the K1_COM port, and the K1_COM port is connected to the first single-chip computer. The second end of the first resistor R1 is respectively connected to the first end of the second resistor R2 and the gate of the first MOS tube Q1. The second end of the second resistor R2 and the source of the first MOS tube Q1 are grounded. The drain of the first MOS tube Q1 is respectively connected to the anode of the first diode D1 and the first end of the first relay K1. The cathode of the first diode D1 is respectively connected to the eighth end of the first relay K1 and VCC_FORLDO. The second end of the first relay K1 is connected to L_TEST. The third end of the first relay K1 is connected to the OUT_Power port. The fourth terminal of the electrical appliance K1 is connected to the SW_K2A port, the fifth terminal of the first relay K1 is connected to the SW_K2B port, the SW_K2A port and the SW_K2B port are connected to the second switching module, the sixth terminal of the first relay K1 is connected to the OUT_Ground port, the seventh terminal of the first relay K1 is connected to the N_TEST port, the third terminal of the first relay K1 is connected to the second terminal of the first relay K1 or the third terminal of the first relay K1 is connected to the fourth terminal of the first relay K1, the sixth terminal of the first relay K1 is connected to the seventh terminal of the first relay K1 or the sixth terminal of the first relay K1 is connected to the fifth terminal of the first relay K1.

[0116] In this embodiment, Figure 4 As shown, the second switching module includes a second relay K2, a second diode D2, a third resistor R3, a fourth resistor R4, and a second MOS tube Q2.

[0117] The first end of the third resistor R3 is connected to the K2_COM port, and the K2_COM port is connected to the first single-chip computer. The second end of the third resistor R3 is respectively connected to the first end of the fourth resistor R4 and the gate of the second MOS tube Q2. The second end of the fourth resistor R4 is connected to the source of the second MOS tube Q2. The drain of the second MOS tube Q2 is respectively connected to the anode of the second diode D2 and the first end of the second relay K2. The cathode of the second diode D2 is respectively connected to the eighth end of the second relay K2 and the VCC_FORLDO port. The second end of the second relay K2 is connected to the G_TEST port. The third terminal is connected to the SW_K2A port, the fourth terminal of the second relay K2 is connected to the N_TEST port, the fifth terminal of the second relay K2 is connected to the G_TEST port, the sixth terminal of the second relay K2 is connected to the SW_K2B port, the seventh terminal of the second relay K2 is connected to the L_TEST port, the third terminal of the second relay K2 is connected to the second terminal of the second relay K2 or the third terminal of the second relay K2 is connected to the fourth terminal of the second relay K2, the sixth terminal of the second relay K2 is connected to the seventh terminal of the second relay K2 or the sixth terminal of the second relay K2 is connected to the fifth terminal of the second relay K2. The VCC_FORLDO port is a voltage-stabilized power supply terminal.

[0118] like Figure 3 As shown, the K1_COM port is connected to the first single-chip microcomputer, and the first single-chip microcomputer can output a high level or a low level to the K1_COM port. Since the K1_COM port is connected to the gate of the first MOS tube Q1 through the resistor R1, the conduction state of the first MOS tube Q1 can be controlled, and the state of the internal switch of the first relay K1 can be further controlled, so that the outputs OUT_Ground and OUT_Power of the first relay K1 are output to different positions respectively.

[0119] like Figure 4 As shown, the K2_COM port and the K2_COM port are connected to the first single-chip microcomputer, and the first single-chip microcomputer can output a high level or a low level to the K2_COM port. Since the K2_COM port is connected to the gate of the second MOS tube Q2 through the resistor R3, the conduction state of the second MOS tube Q2 can be controlled, and the state of the internal switch of the second relay K2 can be further controlled, which cooperates with the different conduction states of the internal switch of the first relay K1 to realize the three-wire output of OUT_Ground and OUT_Power.

[0120] When pin 6 and pin 7 of the first relay K1 are connected, the output position of OUT_Ground is N_TEST. When pin 3 and pin 2 of the first relay K1 are connected, the output position of OUT_Power is L_TEST.

[0121] In the case where the pin 6 and the pin 5 of the first relay K1 are conductive, if the pin 6 and the pin 7 of the second relay K2 are conductive, the output position of OUT_Ground is L_TEST.

[0122] In the case where the pin 6 and the pin 5 of the first relay K1 are conductive, if the pin 6 and the pin 5 of the second relay K2 are conductive, the output position of OUT_Ground is G_TEST.

[0123] In the case where the pin 3 and the pin 4 of the first relay K1 are conducting, if the pin 3 and the pin 2 of the second relay K2 are conducting, the output position of OUT_Power is G_TEST.

[0124] In the case where the pin 3 and the pin 4 of the first relay K1 are conductive, if the pin 3 and the pin 4 of the second relay K2 are conductive, the output position of OUT_Power is N_TEST.

[0125] The relationship between the high and low levels of the K1_COM port and the high and low levels of the K2_COM port and the output position of OUT_Power and the output position of OUT_Ground is shown in Table 2.

[0126] Table 2 Relay output position table

[0127]

[0128] When the K1_COM level is low, pin 6 of the first relay K1 is connected to pin 7, and pin 3 of the first relay K1 is connected to pin 2. When the K1_COM level is high, pin 6 of the first relay K1 is connected to pin 5, and pin 3 of the first relay K1 is connected to pin 4.

[0129] When the K2_COM level is low, pin 6 of the second relay K2 is connected to pin 7, and pin 3 of the second relay K2 is connected to pin 2. When the K2_COM level is high, pin 6 of the second relay K2 is connected to pin 5, and pin 3 of the second relay K2 is connected to pin 4.

[0130] In case 1, the OUT_Ground output position is N_TEST, and the OUT_Power output position is L_TEST. At this time, the L line and the N line can be tested. The L line represents the live line, the N line represents the neutral line, and the G line represents the ground line. The conductivity of the L line and the N line and the line sequence test results are determined according to the high and low levels of N_TEST and L_TEST. The details are shown in Table 3.

[0131] Table 3 Case 1 - Output status identification table at 5V

[0132] Level Case 1 Level Case 2 Level Case 3 Level 4 N_TEST Low Low high high L_TEST high Low high Low G_TEST / / / / / / / / determination normal L line is disconnected LN short circuit LN is connected reversely

[0133] In case 2, the OUT_Ground output position is L_TEST, and the OUT_Power output position is G_TEST. At this time, the L line and the G line can be tested. The conductivity of the L line and the G line and the line sequence test results are determined according to the high and low levels of L_TEST and G_TEST. The details are shown in Table 4.

[0134] Table 4 Case 2 - Output status identification table at 5V

[0135] Level Case 1 Level Case 2 Level Case 3 Level 4 N_TEST / / / / / / / / L_TEST Low Low high high G_TEST high Low high Low determination normal G line is disconnected LG short circuit LG reverse connection

[0136] In case 3, the OUT_Ground output position is G_TEST, and the OUT_Power output position is N_TEST. At this time, the N line and the G line can be tested. The conductivity of the N line and the G line and the line sequence test results are determined according to the high and low levels of N_TEST and G_TEST. The details are shown in Table 5.

[0137] Table 5 Case 3 - Output status identification table at 5V

[0138]

[0139]

[0140] In this embodiment, Figure 5 As shown, the third switching module includes a third relay K3, a sixth diode D6, a nineteenth resistor R19, a twentieth resistor R20, and a seventh MOS tube Q7.

[0141] The first end of the nineteenth resistor R19 is connected to the K3_COM port, and the K3_COM port is connected to the first single-chip computer. The second end of the nineteenth resistor R19 is respectively connected to the first end of the twentieth resistor R20 and the gate of the seventh MOS tube Q7. The second end of the twentieth resistor R20 and the source of the seventh MOS tube Q7 are grounded. The drain of the seventh MOS tube Q7 is respectively connected to the anode of the sixth diode D6 and the first end of the third relay K3. The cathode of the sixth diode D6 is respectively connected to the eighth end of the third relay K3 and the VCC_FORLDO port. The second end of the third relay K3 is connected to the VCC_FORLDO port via the thirtieth resistor R30. The third end of the third relay K3 is connected to the VCC_FORLDO port via the thirtieth resistor R30. The anode of the seventh diode D7 is connected to the OUT_Power port, the cathode of the seventh diode D7 is connected to the OUT_Power port, the fourth terminal of the third relay K3 is connected to 500V, the fifth terminal of the third relay K3 is connected to the AGND_BEFORE port, the sixth terminal of the third relay K3 is connected to the OUT_Ground port, the seventh terminal of the third relay K3 is connected to the GND port, the third terminal of the third relay K3 is connected to the second terminal of the third relay K3 or the third terminal of the third relay K3 is connected to the fourth terminal of the third relay K3, the sixth terminal of the third relay K3 is connected to the seventh terminal of the third relay K3 or the sixth terminal of the third relay K3 is connected to the fifth terminal of the third relay K3.

[0142] like Figure 6 As shown, the insulation current sampling module includes a fourteenth resistor R14 and a transient voltage suppression diode D8.

[0143] The two ends of the transient voltage suppression diode D8 are respectively connected to the two ends of the fourteenth resistor R14, the two ends of the fourteenth resistor R14 are respectively connected to the positive input pin IN+ of the amplifier chip U5 and the negative input pin IN- of the amplifier chip U5, the positive input pin IN+ of the amplifier chip U5 is connected to the AGND_BEFORE port, the negative input pin IN- of the amplifier chip U5 is connected to 500V_GND, the output pin OUT of the amplifier chip U5 is respectively connected to the ADC sampling interface ADC2 of the first microcontroller and the first end of the thirtieth capacitor C30, the second end of the thirtieth capacitor C30 is grounded, the power pin of the amplifier chip U5 is respectively connected to the VCC_FORLDO port and the first end of the fifteenth capacitor C15, and the second end of the fifteenth capacitor C15 is grounded.

[0144] like Figure 7As shown, the host further includes a high-voltage over-current protection module, which includes a first connector H1, a fuse F1, and a twenty-third resistor R23.

[0145] A first end of the fuse F1 is connected to pin 1 of the first connector H1 , a second end of the fuse F1 is connected to a first end of the twenty-third resistor R23 , a second end of the twenty-third resistor R23 is connected to the 500V port, and a pin 3 of the first connector H1 is connected to the 500V_GND port.

[0146] The boost circuit provides 500V voltage to the 500V port. The high voltage part is 500V, which is mainly used to provide test voltage during insulation resistance testing. This part of the current is very small, but if a short circuit or breakdown occurs, it will have an irreversible impact on the device, so a separate protection circuit is required. In order to prevent the voltage increase and the increase in current from affecting the sampling circuit and the ADC interface of the microcontroller, a fuse F1 is added to the 500V positive end.

[0147] The fourteenth resistor R14 is a sampling resistor, which is set at the negative end. The test result is obtained by collecting the voltage between the front end of the sampling resistor and GND. The amplifier circuit is clamped at both ends of the sampling resistor, and the first single-chip microcomputer ADC interface ADC2 is connected to the back end of the amplifier circuit. Therefore, a TVS (transient voltage suppression diode, Transient Voltage Suppressor) is added to the front end of the sampling circuit to limit the input voltage. Under normal circumstances, both ends of this TVS are close to GND. In the case of a 500V short circuit or breakdown, the front end voltage will rise sharply, the self-recovery fuse will suppress a part of it, and the remaining part will be eliminated by the TVS.

[0148] In this embodiment, the slave line switching module includes a fourth switching module and a fifth switching module.

[0149] like Figure 8 As shown, the LOW_OUT_L port of the fourth switching module is respectively connected to the first end of the eighth resistor R8 and the first end of the twelfth resistor R12, the LOW_OUT_N port of the fourth switching module is respectively connected to the first end of the eleventh resistor R11 and the first end of the tenth resistor R10, and the LOW_OUT_G port of the fifth switching module is respectively connected to the first end of the ninth resistor R9 and the first end of the thirteenth resistor R13.

[0150] The second end of the eighth resistor R8 and the second end of the eleventh resistor R11 are connected to the ADC sampling interface TEST_LN of the second single-chip microcomputer, the second end of the ninth resistor R9 and the second end of the twelfth resistor R12 are connected to the ADC sampling interface TEST_GL of the second single-chip microcomputer, and the second end of the tenth resistor R10 and the second end of the thirteenth resistor R13 are connected to the ADC sampling interface TEST_NG of the second single-chip microcomputer.

[0151] The slave determines the current output direction of the host line through wireless signals.

[0152] If the output direction is L positive and N negative, the voltages of TEST_LN, TEST_GL, and TEST_NG are collected. If the voltages of the three points are floating values, the first result bit is determined to be 4. If the voltages of the three points are not floating values, further judgment is performed: if TEST_GL>TEST_LN+0.3V and TEST_LN>TEST_NG+0.3V, the first result bit is determined to be 1; if TEST_GL>TEST_LN+0.3V and TEST_GL>TEST_NG+0.3V, the first result bit is determined to be 2; if none of the above conditions are met, the first result bit is determined to be 3.

[0153] If the output direction is G positive and L negative: collect the voltages of TEST_LN, TEST_GL, and TEST_NG. If the voltages of the three points are floating values, the second result bit is determined to be 4. If the voltages of the three points are not floating values, further judgment is made: if TEST_NG>TEST_GL+0.3V and TEST_GL>TEST_LN+0.3V, the second result bit is determined to be 1; if TEST_NG>TEST_GL+0.3V and TEST_NG>TEST_LN+0.3V, the second result bit is determined to be 2; if none of the above conditions are met, the second result bit is determined to be 3.

[0154] If the output direction is N positive and G negative: collect the voltages of TEST_LN, TEST_GL, and TEST_NG. If the voltages of the three points are floating values, the third result bit is determined to be 4. If the voltages of the three points are not floating values, further judgment is performed: if TEST_LN>TEST_NG+0.3V and TEST_NG>TEST_GL+0.3V, the third result bit is determined to be 1; if TEST_LN>TEST_NG+0.3V and TEST_LN>TEST_GL+0.3V, the third result bit is determined to be 2; if none of the above conditions are met, the third result bit is determined to be 3.

[0155] After the slave executes all three steps, it sends the three result bits to the host. If a step in the middle causes a result bit to not get a normal value, the result bit value sent to the host is 5.

[0156] After the host receives the result bit of the slave, it searches the error dictionary based on the result bit. For example, 111 indicates normal, 144 indicates an open ground line, and 414 indicates an open neutral line. There is a corresponding code in the error dictionary for each fault. If the result bit contains 5, it means the slave has a fault.

[0157] like Fig. 9As shown, the fourth switching module includes a fourth relay K4, a fourth diode D4, a fifteenth resistor R15, a sixteenth resistor R16, a third MOS tube Q3, a fifth resistor R5, and a sixth resistor R6.

[0158] The first end of the fourth relay K4 is respectively connected to the VOUT port and the cathode of the fourth diode D4, the eighth end of the fourth relay K4 is respectively connected to the anode of the fourth diode D4 and the drain of the third MOS tube Q3, the source of the third MOS tube Q3 is connected to the GND port, the gate of the third MOS tube Q3 is respectively connected to the first end of the fifteenth resistor R15 and the first end of the sixteenth resistor R16, the second end of the fifteenth resistor R15 is connected to the K1&K2_COM port, the K1&K2_COM port is connected to the second single-chip computer, the second end of the sixteenth resistor R16 is connected to GND, and the The second end of the fourth relay K4 is connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the L_TEST port, the seventh end of the fourth relay K4 is connected to the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected to the G_TEST port, the third end of the fourth relay K4 is connected to the N_TEST port of the second connector J1, the sixth end of the fourth relay K4 is connected to the L_TEST port of the second connector J1, the fourth end of the fourth relay K4 is connected to the LOW_OUT_N port, and the fifth end of the fourth relay K4 is connected to the LOW_OUT_L port.

[0159] The third end of the fourth relay K4 is connected to the second end of the fourth relay K4 or the third end of the fourth relay K4 is connected to the fourth end of the fourth relay K4, the sixth end of the fourth relay K4 is connected to the seventh end of the fourth relay K4 or the sixth end of the fourth relay K4 is connected to the fifth end of the fourth relay K4.

[0160] like Fig.10 As shown, the VOUT port is connected to the cathode of the third diode D3, and the anode of the third diode D3 is connected to the slave battery B.

[0161] like Fig. 9 As shown, the fifth switching module includes a fifth relay K5, a fifth diode D5, a seventeenth resistor R17, an eighteenth resistor R18, a fourth MOS tube Q4, and a seventh resistor R7.

[0162] A first end of the fifth relay K5 is respectively connected to the VOUT port and the cathode of the fifth diode D5, an eighth end of the fifth relay K5 is respectively connected to the anode of the fifth diode D5 and the drain of the fourth MOS tube Q4, a source of the fourth MOS tube Q4 is connected to the GND port, a gate of the fourth MOS tube Q4 is respectively connected to a first end of the seventeenth resistor R17 and a first end of the eighteenth resistor R18, a second end of the eighteenth resistor R18 is connected to GND, a second end of the seventeenth resistor R17 is connected to the K1&K2_COM port, the K1&K2_COM port is connected to the second single-chip computer, a second end of the fifth relay K5 is connected to a first end of the seventh resistor R7, a second end of the seventh resistor R7 is connected to the N_TEST port, a third end of the fifth relay K5 is connected to the G_TEST port of the second connector J1, and a fourth end of the fifth relay K5 is connected to the LOW_OUT_G port.

[0163] The second MCU can also output high and low levels to the K1&K2_COM port to switch the slave to different lines and cooperate with the host to test the L line, N line, and G line.

[0164] In this embodiment, the host is provided with a storage bin for accommodating the slave, and a third connector including five pins is provided in the storage bin of the host, and a fourth connector corresponding to the third connector is provided on the slave. When the slave is in the storage bin, the pins of the fourth connector are correspondingly connected to the pins of the third connector.

[0165] Pin 5 of the third connector is connected to pin 1 of the fourth connector, and is used to turn on the output when charging the slave. Pin 4 of the third connector and pin 2 of the fourth connector are connected to the GND port. Pin 3 of the third connector is connected to the TX pin of the UART interface of the first microcontroller and pin 3 of the fourth connector, and pin 3 of the fourth connector is connected to the RX pin of the UART interface of the second microcontroller. Pin 2 of the third connector is connected to pin 4 of the fourth connector, and pin 2 of the third connector is used to obtain the slave battery voltage through pin 4 of the fourth connector. Pin 1 of the third connector is connected to pin 5 of the fourth connector, and pin 1 of the third connector is used to control whether the slave is turned on in the storage compartment. When the slave needs to be turned on in the storage compartment, a high level is output, and a low level is output in other cases.

[0166] When the slave is in the storage compartment of the host, the host can obtain the battery voltage of the slave to determine whether the slave needs to be charged. When the slave needs to be charged, pin 5 of the third connector turns on the output. In addition, the pairing between the host and the slave can be completed through pin 3 of the third connector and pin 3 of the fourth connector.

[0167] This embodiment introduces a testing method for the quick-install pipeline performance testing device described in any embodiment of the present invention, including:

[0168] Before starting the test, pair the slave with the master in the storage compartment;

[0169] After pairing is completed, remove the slave from the storage compartment, the slave will automatically power on, and the host and slave will establish wireless communication;

[0170] Install the master and slave at both ends of the pipeline respectively;

[0171] Press the test button, the host switches to 5V low voltage mode, and performs low voltage test in 5V low voltage mode. The low voltage test includes continuity test and line sequence test.

[0172] If the low-voltage test result is abnormal, perform troubleshooting based on the low-voltage test result;

[0173] If the result of the low-voltage test is normal, the host switches to the 500V high-voltage mode and performs the insulation resistance test in the 500V high-voltage mode;

[0174] If the insulation resistance test result is abnormal, perform troubleshooting based on the insulation resistance test result;

[0175] If the insulation resistance test result is normal, determine whether there are other output ports that need to be tested;

[0176] If it exists, remove the slave and install it at other output ports that need to be tested, and then retest.

[0177] In this embodiment, during the low voltage test, the slave determines the output direction of the host line by wirelessly communicating with the host;

[0178] When the output direction is L positive and N negative, the voltages of the three points TEST_LN, TEST_GL, and TEST_NG are collected, and the first result bit is determined according to the voltages of the three points;

[0179] When the output direction is G positive and L negative, the voltages of the three points TEST_LN, TEST_GL, and TEST_NG are collected, and the second result bit is determined according to the voltages of the three points;

[0180] When the output direction is N positive and G negative, the voltages of the three points TEST_LN, TEST_GL, and TEST_NG are collected, and the third result bit is determined according to the voltages of the three points;

[0181] The slave sends the first result bit, the second result bit, and the third result bit to the host via wireless communication;

[0182] The host searches the error dictionary according to the received first result bit, second result bit, and third result bit to determine the fault type.

[0183] In this embodiment, the process of determining the first result bit includes:

[0184] If the voltages at the three points are floating values, the first result bit is determined to be 4;

[0185] If the voltages at the three points are not floating values ​​and the first condition and the second condition are met, the first result bit is determined to be 1;

[0186] If the voltages of the three points are not floating values ​​and the first and third conditions are met, the first result bit is determined to be 2;

[0187] If the voltages of the three points are not floating values, and the first condition, the second condition, and the third condition are not satisfied, the first result bit is determined to be 3;

[0188] Among them, the first condition is TEST_GL>TEST_LN+0.3V;

[0189] The second condition is TEST_LN>TEST_NG+0.3V;

[0190] The third condition is TEST_GL>TEST_NG+0.3V.

[0191] In this embodiment, the process of determining the second result bit includes:

[0192] If the voltages at the three points are floating, the second result bit is determined to be 4;

[0193] If the voltages of the three points are not floating values ​​and the fourth condition and the first condition are met, the second result bit is determined to be 1;

[0194] If the voltages of the three points are not floating values ​​and the fourth and fifth conditions are met, the second result bit is determined to be 2;

[0195] If the voltages at the three points are not floating values, and the fourth condition, the fifth condition and the first condition are not satisfied, the second result bit is determined to be 3;

[0196] Among them, the fourth condition is TEST_NG>TEST_GL+0.3V;

[0197] The fifth condition is TEST_NG>TEST_LN+0.3V;

[0198] In this embodiment, the process of determining the third result bit includes:

[0199] If the voltages at the three points are floating values, the third result bit is determined to be 4;

[0200] If the voltages at the three points are not floating values ​​and the fourth and sixth conditions are met, the third result bit is determined to be 1;

[0201] If the voltages at the three points are not floating values ​​and the sixth and seventh conditions are met, the third result bit is determined to be 2;

[0202] If the voltages at the three points are not floating values, and the fourth condition, the sixth condition, and the seventh condition are not satisfied, the third result bit is determined to be 3;

[0203] Among them, the sixth condition is TEST_LN>TEST_NG+0.3V;

[0204] The seventh condition is TEST_LN>TEST_GL+0.3V.

[0205] In this embodiment, if the value of the target result bit exceeds the normal range, the target result bit is set to 5, indicating that there is a fault in the slave.

[0206] In this embodiment, the pairing process of the host and the slave includes:

[0207] After receiving the pairing command, the host controls the slave to turn on in the storage compartment through pin 1 of the third connector;

[0208] After the slave is powered on, the host transmits the UID to the slave via wired communication for pairing.

[0209] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A quick-install pipeline performance testing device, characterized in that: Including master and slave; The host includes a host power management module, a boost circuit, an insulation current sampling module, a first single-chip microcomputer, a host communication module, a high-low voltage power switching module, and a host line switching module; The host power management module is used to output a 3.3V voltage to the first single-chip microcomputer, output a 5V voltage to the high-low voltage power switching module, and provide a battery voltage to the boost circuit; The boost circuit is used to increase the battery voltage output by the host power management module to 500V, and output 500V voltage to the insulation current sampling module; The high and low voltage power supply switching module is used to switch the test voltage during the test to 500V or 5V. The 500V test voltage is used in the insulation resistance test process, and the 5V test voltage is used in the continuity test process and the line sequence test process. The first single chip microcomputer is used to communicate with the slave through the host communication module, control the insulation current sampling module to perform sampling, and control the host line switching module to perform line switching; The slave includes a slave power management module, a second single-chip microcomputer, a slave line switching module, and a slave communication module; The slave power management module is used to supply power to the second single-chip microcomputer; The second single chip microcomputer is used to communicate with the host through the slave communication module and control the slave line switching module to perform line switching; The host line switching module is used to switch the host to different lines to connect with the slave, and the slave line switching module is used to switch the slave to different lines to connect with the host, so as to test the insulation resistance, conductivity and line sequence of the quick-install pipeline.

2. The device according to claim 1, characterized in that The host line switching module includes a first switching module, a second switching module, and a third switching module. The first switching module and the second switching module are located at the rear stage of the third switching module. The first switching module and the second switching module are used to switch the host output direction, and the third switching module is used to switch between high and low voltages. The first switching module includes a first relay, a first diode, a first resistor, a second resistor, and a first MOS tube; A first end of the first resistor is connected to the K1 COM port, which is connected to the first single-chip computer. A second end of the first resistor is respectively connected to the first end of the second resistor and the gate of the first MOS tube. The second end of the second resistor and the source of the first MOS tube are grounded. The drain of the first MOS tube is respectively connected to the anode of the first diode and the first end of the first relay. The cathode of the first diode is respectively connected to the eighth end of the first relay and VCC FORLDO. A second end of the first relay is connected to L TEST. A third end of the first relay is connected to the OUT Power port. A fourth end of the first relay is connected to the SW K2A port. A fifth end of the first relay is connected to the SW K2B port. The SW K2A port and the SW K2B port are connected to the second switching module. A sixth end of the first relay is connected to the OUTGround port. A seventh end of the first relay is connected to the N TEST port. The third end of the first relay is connected to the second end of the first relay or the third end of the first relay is connected to the fourth end of the first relay. The sixth end of the first relay is connected to the seventh end of the first relay or the sixth end of the first relay is connected to the fifth end of the first relay.

3. The device according to claim 2, characterized in that The second switching module includes a second relay, a second diode, a third resistor, a fourth resistor, and a second MOS tube; A first end of the third resistor is connected to the K2 COM port, which is connected to the first single-chip computer; a second end of the third resistor is respectively connected to the first end of the fourth resistor and the gate of the second MOS tube; a second end of the fourth resistor and the source of the second MOS tube are grounded; a drain of the second MOS tube is respectively connected to the anode of the second diode and the first end of the second relay; a cathode of the second diode is respectively connected to the eighth end of the second relay and the VCC FORLDO port; a second end of the second relay is connected to the G TEST port; a third end of the second relay is connected to the SW K2A port; a fourth end of the second relay is connected to the N TEST port; a fifth end of the second relay is connected to the G TEST port; a sixth end of the second relay is connected to the SW K2B port; a seventh end of the second relay is connected to the L TEST port; a third end of the second relay is conducted with the second end of the second relay or a third end of the second relay is conducted with the fourth end of the second relay; a sixth end of the second relay is conducted with the seventh end of the second relay or a sixth end of the second relay is conducted with the fifth end of the second relay.

4. The device according to claim 3, characterized in that The third switching module includes a third relay, a sixth diode, a nineteenth resistor, a twentieth resistor, and a seventh MOS tube; A first end of the nineteenth resistor is connected to the K3 COM port, which is connected to the first single-chip computer; a second end of the nineteenth resistor is respectively connected to the first end of the twentieth resistor and the gate of the seventh MOS tube; a second end of the twentieth resistor and the source of the seventh MOS tube are grounded; a drain of the seventh MOS tube is respectively connected to the anode of the sixth diode and the first end of the third relay; a cathode of the sixth diode is respectively connected to the eighth end of the third relay and the VCC FORLDO port; a second end of the third relay is connected to the VCC FORLDO port via the thirtieth resistor; a third end of the third relay is connected to the anode of the seventh diode; a cathode of the seventh diode is connected to the OUTPower port; a fourth end of the third relay is connected to 500V; a fifth end of the third relay is connected to the AGND BEFORE port; a sixth end of the third relay is connected to the OUT Ground port; a seventh end of the third relay is connected to the GND port; a third end of the third relay is conducted with the second end of the third relay or a third end of the third relay is conducted with the fourth end of the third relay; a sixth end of the third relay is conducted with the seventh end of the third relay or a sixth end of the third relay is conducted with the fifth end of the third relay.

5. The device according to claim 1, characterized in that The insulation current sampling module includes a fourteenth resistor and a transient voltage suppression diode; The two ends of the transient voltage suppression diode are respectively connected to the two ends of the fourteenth resistor, the two ends of the fourteenth resistor are respectively connected to the positive input pin of the amplifier chip and the negative input pin of the amplifier chip, the positive input pin of the amplifier chip is connected to the AGND BEFORE port, the negative input pin of the amplifier chip is connected to 500V GND, the output pin of the amplifier chip is respectively connected to the ADC sampling interface ADC2 of the first microcontroller and the first end of the thirtieth capacitor, the second end of the thirtieth capacitor is grounded, the power pin of the amplifier chip is respectively connected to the VCCFORLDO port and the first end of the fifteenth capacitor, and the second end of the fifteenth capacitor is grounded.

6. The device according to claim 5, characterized in that The host also includes a high-voltage over-current protection module, which includes a first connector, a fuse, and a twenty-third resistor; The first end of the fuse is connected to pin 1 of the first connector, the second end of the fuse is connected to the first end of the twenty-third resistor, the second end of the twenty-third resistor is connected to the 500V port, and the pin 3 of the first connector is connected to the 500V GND port.

7. The device according to claim 1, characterized in that The slave line switching module includes a fourth switching module and a fifth switching module; The LOW OUT L port of the fourth switching module is respectively connected to the first end of the eighth resistor and the first end of the twelfth resistor, the LOW OUT N port of the fourth switching module is respectively connected to the first end of the eleventh resistor and the first end of the tenth resistor, and the LOW OUT G port of the fifth switching module is respectively connected to the first end of the ninth resistor and the first end of the thirteenth resistor; The second end of the eighth resistor and the second end of the eleventh resistor are connected to the ADC sampling interface TEST LN of the second single-chip microcomputer, the second end of the ninth resistor and the second end of the twelfth resistor are connected to the ADC sampling interface TEST GL of the second single-chip microcomputer, and the second end of the tenth resistor and the second end of the thirteenth resistor are connected to the ADC sampling interface TEST NG of the second single-chip microcomputer.

8. The device according to claim 7, characterized in that The fourth switching module includes a fourth relay, a fourth diode, a fifteenth resistor, a sixteenth resistor, a third MOS tube, a fifth resistor, and a sixth resistor; A first end of the fourth relay is respectively connected to the VOUT port and the cathode of the fourth diode, an eighth end of the fourth relay is respectively connected to the anode of the fourth diode and the drain of the third MOS tube, a source of the third MOS tube is connected to the GND port, a gate of the third MOS tube is respectively connected to the first end of the fifteenth resistor and the first end of the sixteenth resistor, a second end of the fifteenth resistor is connected to the K1&K2 COM port, the K1&K2 COM port is connected to the second single-chip computer, a second end of the sixteenth resistor is connected to GND, a second end of the fourth relay is connected to the first end of the fifth resistor, a second end of the fifth resistor is connected to the L TEST port, a seventh end of the fourth relay is connected to the first end of the sixth resistor, a second end of the sixth resistor is connected to the G TEST port, a third end of the fourth relay is connected to the N TEST port of the second connector, a sixth end of the fourth relay is connected to the L TEST port of the second connector, a fourth end of the fourth relay is connected to the LOW OUT N port, and a fifth end of the fourth relay is connected to the LOW OUT L port; The third end of the fourth relay is connected to the second end of the fourth relay or the third end of the fourth relay is connected to the fourth end of the fourth relay, the sixth end of the fourth relay is connected to the seventh end of the fourth relay or the sixth end of the fourth relay is connected to the fifth end of the fourth relay; The VOUT port is connected to the cathode of the third diode, and the anode of the third diode is connected to the slave battery.

9. The device according to claim 8, characterized in that The fifth switching module includes a fifth relay, a fifth diode, a seventeenth resistor, an eighteenth resistor, a fourth MOS tube, and a seventh resistor; The first end of the fifth relay is respectively connected to the VOUT port and the cathode of the fifth diode, the eighth end of the fifth relay is respectively connected to the anode of the fifth diode and the drain of the fourth MOS tube, the source of the fourth MOS tube is connected to the GND port, the gate of the fourth MOS tube is respectively connected to the first end of the seventeenth resistor and the first end of the eighteenth resistor, the second end of the eighteenth resistor is connected to GND, the second end of the seventeenth resistor is connected to the K1&K2 COM port, the K1&K2 COM port is connected to the second single-chip computer, the second end of the fifth relay is connected to the first end of the seventh resistor, the second end of the seventh resistor is connected to the N TEST port, the third end of the fifth relay is connected to the G TEST port of the second connector, and the fourth end of the fifth relay is connected to the LOW OUT G port.

10. The device according to claim 1, characterized in that The host is provided with a storage compartment for storing the slave, a third connector including five pins is provided in the storage compartment of the host, a fourth connector corresponding to the third connector is provided on the slave, and when the slave is in the storage compartment, each pin of the fourth connector is connected to each pin of the third connector correspondingly; Pin 5 of the third connector is connected to pin 1 of the fourth connector to enable output when charging the slave device; Pin 4 of the third connector and pin 2 of the fourth connector are connected to the GND port; Pin 3 of the third connector is connected to the TX pin of the UART interface of the first single-chip microcomputer and pin 3 of the fourth connector, and pin 3 of the fourth connector is connected to the RX pin of the UART interface of the second single-chip microcomputer; Pin 2 of the third connector is connected to pin 4 of the fourth connector, and pin 2 of the third connector is used to obtain the slave battery voltage through pin 4 of the fourth connector; Pin 1 of the third connector is connected to pin 5 of the fourth connector. Pin 1 of the third connector is used to control whether the slave is powered on in the storage bin. It outputs a high level when the slave needs to be powered on in the storage bin, and outputs a low level in other cases.

11. A testing method for the quick-install pipeline performance testing device according to any one of claims 1 to 10, characterized in that: include: Before starting the test, pair the slave with the master in the storage compartment; After pairing is completed, remove the slave from the storage compartment, the slave will automatically power on, and the host and slave will establish wireless communication; Install the master and slave at both ends of the pipeline respectively; Press the test button, the host switches to 5V low voltage mode, and performs low voltage test in 5V low voltage mode. The low voltage test includes continuity test and line sequence test. If the low-voltage test result is abnormal, perform troubleshooting based on the low-voltage test result; If the result of the low-voltage test is normal, the host switches to the 500V high-voltage mode and performs the insulation resistance test in the 500V high-voltage mode; If the insulation resistance test result is abnormal, perform troubleshooting based on the insulation resistance test result; If the insulation resistance test result is normal, determine whether there are other output ports that need to be tested; If it exists, remove the slave and install it at other output ports that need to be tested, and then retest.

12. The method according to claim 11, characterized in that During the low voltage test, the slave determines the output direction of the host line by wirelessly communicating with the host; When the output direction is L positive and N negative, the voltages of the three points TEST LN, TEST GL, and TEST NG are collected, and the first result bit is determined according to the voltages of the three points; When the output direction is G positive and L negative, the voltages of the three points TEST LN, TEST GL, and TEST NG are collected, and the second result bit is determined according to the voltages of the three points; When the output direction is N positive and G negative, the voltages of the three points TEST LN, TEST GL, and TEST NG are collected, and the third result bit is determined according to the voltages of the three points; The slave sends the first result bit, the second result bit, and the third result bit to the host via wireless communication; The host searches the error dictionary according to the received first result bit, second result bit, and third result bit to determine the fault type.

13. The method according to claim 12, characterized in that The process of determining the first result bit includes: If the voltages at the three points are floating values, the first result bit is determined to be 4; If the voltages at the three points are not floating values ​​and the first condition and the second condition are met, the first result bit is determined to be 1; If the voltages of the three points are not floating values ​​and the first and third conditions are met, the first result bit is determined to be 2; If the voltages of the three points are not floating values, and the first condition, the second condition, and the third condition are not satisfied, the first result bit is determined to be 3; Among them, the first condition is TEST GL>TEST LN+0.3V; The second condition is TEST LN>TEST NG+0.3V; The third condition is TEST GL>TEST NG+0.3V.

14. The method according to claim 13, characterized in that The process of determining the second result bit includes: If the voltages at the three points are floating, the second result bit is determined to be 4; If the voltages of the three points are not floating values ​​and the fourth condition and the first condition are met, the second result bit is determined to be 1; If the voltages of the three points are not floating values ​​and the fourth and fifth conditions are met, the second result bit is determined to be 2; If the voltages at the three points are not floating values, and the fourth condition, the fifth condition and the first condition are not satisfied, the second result bit is determined to be 3; Among them, the fourth condition is TEST NG>TEST GL+0.3V; The fifth condition is TEST NG>TEST LN+0.3V.

15. The method according to claim 14, characterized in that The process of determining the third result digit includes: If the voltages at the three points are floating values, the third result bit is determined to be 4; If the voltages at the three points are not floating values ​​and the fourth and sixth conditions are met, the third result bit is determined to be 1; If the voltages at the three points are not floating values ​​and the sixth and seventh conditions are met, the third result bit is determined to be 2; If the voltages at the three points are not floating values, and the fourth condition, the sixth condition, and the seventh condition are not satisfied, the third result bit is determined to be 3; Among them, the sixth condition is TEST LN>TEST NG+0.3V; The seventh condition is TEST LN>TEST GL+0.3V.

16. The method according to claim 15, characterized in that If the value of the target result bit is outside the normal range, the target result bit is set to 5, indicating that the slave has a fault.

17. The method according to claim 10, characterized in that The pairing process between the master and slave includes: After receiving the pairing command, the host controls the slave to turn on in the storage compartment through pin 1 of the third connector; After the slave is powered on, the host transmits the UID to the slave via wired communication for pairing.

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