Image sensing device

Abstract

Disclosed is an image sensing apparatus capable of detecting a distance to a target object according to a time of flight (TOF) method. The image sensing apparatus includes: a plurality of light receiving elements each configured to generate a sensing voltage corresponding to a current pulse based on photons reflected from a target object; a plurality of quenching circuits corresponding to the respective light receiving elements and each configured to output a pixel signal by controlling a sensing voltage from a corresponding light receiving element among the light receiving elements; and a readout circuit shared by the plurality of quenching circuits and configured to generate a readout signal by controlling a delay time of the pixel signal.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to an image sensing device capable of detecting a distance of a target object according to a time-of-flight (TOF) method. Background Art

[0002] Recently, the time-of-flight (TOF) technology that has received attention transmits pulse-shaped light from a light source located in or near a sensor to a target object, receives light reflected from the target object, calculates the round-trip time using the emitted light and the reflected light, and uses the calculated round-trip time to measure the distance to the target object based on the constant speed of light principle. In order to accurately measure TOF, the TOF technology requires a photoelectric conversion element with very high sensitivity because a reaction must occur once the light reaches the light receiving element. To this end, research on single-photon avalanche diodes (SPADs) that can be manufactured by CMOS manufacturing technology has been actively conducted.

[0003] However, with the development of high-resolution TOF technology, the size of single-photon avalanche diode (SPAD) elements has gradually become smaller, and there may be a limit on the area of ​​the quenching circuit that processes the output of the SPAD element. In addition, as the number of SPAD elements increases, the number of output circuits and the number of interconnects (or wiring) increase, resulting in an increase in chip area. Summary of the invention

[0004] According to an embodiment of the present disclosure, an image sensing device may include: a plurality of light receiving elements, each of which is configured to generate a sensing voltage corresponding to a current pulse based on photons reflected from a target object; a plurality of quenching circuits, which correspond to the corresponding light receiving elements and are each configured to output a pixel signal by controlling the sensing voltage from a corresponding light receiving element among the light receiving elements; and a readout circuit, which is shared by the plurality of quenching circuits and is configured to generate a readout signal by controlling a delay time of the pixel signal.

[0005] According to another embodiment of the present disclosure, an image sensing device may include a circuit chip and a sensor chip stacked on an upper portion of the circuit chip. The sensor chip may include a plurality of light receiving elements, each of which is configured to generate a current pulse by detecting a single photon reflected from a target object. The circuit chip may include: a plurality of quenching circuits corresponding to the plurality of light receiving elements and configured to output a plurality of pixel signals by respectively controlling a sensing voltage corresponding to the current pulse; and a readout circuit shared by the plurality of quenching circuits and configured to generate a readout signal by reading out the plurality of pixel signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0007] Figure 1 is a schematic diagram illustrating an imaging device according to some embodiments of the present disclosure.

[0008] Figure 2 Some embodiments of the present disclosure are illustrated. Figure 1 A detailed circuit diagram of a pixel array of an image sensing device is shown.

[0009] Figure 3 Some embodiments of the present disclosure are illustrated. Figure 2 A diagram showing the structure of a pixel array.

[0010] Figure 4 Some embodiments of the present disclosure are illustrated. Figure 2 A timing diagram of the operation of the quenching circuit is shown.

[0011] Figure 5 Some embodiments of the present disclosure are illustrated. Figure 1 Detailed circuit diagram of the readout circuit of the image sensing device shown.

[0012] Figure 6 Some embodiments of the present disclosure are illustrated. Figure 5 A timing diagram of the operation of the readout circuit is shown.

[0013] Figure 7 Some embodiments of the present disclosure are illustrated. Figure 1 A diagram of the stacked structure of an image sensing device is shown.

[0014] Figure 8 Some embodiments of the present disclosure are illustrated in Figure 7 Diagram of the logic array in the circuit chip shown.

[0015] Fig. 9 is an example Figure 7 and Figure 8 Schematic diagram of the layout structure of the macro array and readout circuit within the circuit chip shown.

[0016] Fig.10 Some embodiments of the present disclosure are illustrated. Figure 7 The single photon avalanche diode (SPAD) device shown and Fig. 9 Diagram of the routing structure of the macrocell shown. DETAILED DESCRIPTION

[0017] Various embodiments of the present disclosure provide an image sensing device capable of detecting the distance of a target object according to a time-of-flight (TOF) method, which can be used in a configuration to substantially solve one or more technical or engineering problems and alleviate limitations or shortcomings encountered in some image sensing devices in the art. Some embodiments of the present disclosure relate to an image sensing device including a readout circuit shared by a plurality of quenching circuits configured to quench SPAD elements and forming the quenching circuits to be stacked with the SPAD elements, resulting in a reduced chip area. Recognizing the above problems, image sensing devices based on some embodiments of the present disclosure can be configured to have a short dead time in a small area.

[0018] Reference will now be made in detail to some embodiments of the present disclosure illustrated in the accompanying drawings. As much as possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Although the embodiments of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof are shown in the accompanying drawings by way of example. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0019] In the following, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized.

[0020] Various embodiments of the present disclosure are directed to an image sensing device including a readout circuit shared by a plurality of quenching circuits configured to quench a SPAD element and forming the quenching circuits to be stacked with the SPAD element, resulting in a reduced chip area.

[0021] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and descriptive and are intended to provide further description of the claimed embodiments.

[0022] Figure 1 is a schematic diagram illustrating an imaging device 1 according to some embodiments of the present disclosure.

[0023] Reference Figure 1 , the imaging device 1 may refer to a device such as a digital still camera for capturing still images or a digital video camera for capturing moving images. For example, the imaging device 1 may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, or a smart phone, etc. The imaging device 1 may include a device having both a lens and an image pickup element, so that the device can capture (or photograph) a target object and can thereby create an image of the target object.

[0024] The imaging device 1 may include an image sensing device 10 and an image signal processor (ISP).

[0025] The image sensing device 10 can measure the distance to the target object using the time of flight (TOF) principle. The image sensing device 10 may include a light source (LS), a lens module (LM), a pixel array 100, a pixel driver 200, a readout circuit 210, a timing controller 220, and a light source driver 230.

[0026] The light source (LS) may emit light to a target object (TO) upon receiving a clock signal (MLS) from the light source driver 230. The light source (LS) may be a laser diode (LD) or a light emitting diode (LED) for emitting light having a specific wavelength band (e.g., infrared (IR) light or visible light), or may be one of a near-infrared laser (NIR), a point light source, a monochromatic light source or a monochromator combined with white light, and a combination of other laser sources. For example, the light source (LS) may emit infrared (IR) light having a wavelength of 800 nm to 1000 nm. The light emitted from the light source (LS) may be modulated light modulated at a predetermined frequency. Although for the sake of convenience of description, Figure 1 Only one light source (LS) is shown, but the scope or spirit of the disclosed technology is not limited thereto, and a plurality of light sources (LS) may also be arranged near the lens module (LM).

[0027] The lens module (LM) may collect light reflected from the target object (TO) and may allow the collected light to be focused on the pixels of the pixel array 100. For example, the lens module (LM) may include a focusing lens having a surface formed of glass or plastic or another cylindrical optical element having a surface formed of glass or plastic. The lens module (LM) may include a single lens group of one or more lenses.

[0028] The pixel array 100 may include a plurality of pixels 110 arranged continuously in a two-dimensional (2D) matrix structure, wherein the pixels 110 are arranged continuously in a column direction and a row direction perpendicular to the column direction. Each pixel 110 may convert incident light received by a lens module (LM) into an electrical signal corresponding to the amount of incident light, and may thus output a pixel signal using the electrical signal. In this case, the pixel signal may not indicate the color of the target object (TO), and may be a signal indicating the distance to the target object (TO).

[0029] The pixel array 100 in which a plurality of pixels 110 are arranged can detect the distance of a target object (TO) using a direct TOF method. The direct TOF method can directly measure the round trip time from the first time when a pulse light is emitted to the target object (TO) to the second time when the pulse light reflected from the target object (TO) is incident, and can therefore calculate the distance to the target object (TO) by calculating the round trip time and the speed of light.

[0030] Each of the plurality of pixels 110 may include a light receiving element according to an embodiment (ie, a single photon avalanche diode SPAD).

[0031] The principle of operating the pixel 110 including the SPAD is as follows. When the electric field is increased by applying a reverse bias voltage to the SPAD, impact ionization in which electrons and hole pairs (hereinafter referred to as electron-hole pairs) are generated when electrons generated by photons move due to the strong electric field can occur. Specifically, in a SPAD operated in a Geiger mode in which a reverse bias voltage higher than the breakdown voltage is applied, countless carriers can be generated when electrons and holes generated by impact ionization caused by collisions with carriers (ie, electrons or holes) generated by incident light collide with each other. As a result, even if a single photon is incident on the SPAD, the single photon can trigger avalanche breakdown, enabling the generation of a measurable current pulse.

[0032] Each of the plurality of pixels 110 may include a quenching circuit corresponding to a SPAD element (i.e., a quenching circuit 112 to be described later). The pixel 110 according to some embodiments of the present disclosure may include an array of quenching circuits corresponding to the SPAD elements, respectively. In addition, the array of quenching circuits may be connected to a readout circuit 210 by being connected to a common node (i.e., a common node CN to be described later). Here, the quenching circuit may process the output of the corresponding SPAD element to output a pixel signal. This will be described later. Figures 2 to 4 A more detailed structure and operation of pixel 110 will be described.

[0033] On the other hand, although the embodiments of the present disclosure have disclosed a single photon avalanche diode (SPAD) element used as a light receiving element (i.e., light detecting element) of a pixel for the sake of convenience of description, the scope or spirit of the disclosed technology is not limited to the SPAD element. That is, not only the SPAD element, but also various elements operating in the Geiger mode such as an avalanche photodiode (APD) or a silicon photomultiplier (SiPM) can be used as a light receiving element of a pixel.

[0034] The pixel driver 200 may drive the pixel array 100 under the control of the timing controller 220. For example, the pixel driver 200 may generate a quenching control signal to control a quenching operation of reducing a reverse bias voltage applied to a SPAD element of the pixel 110 to a breakdown voltage or less. In addition, the pixel driver 200 may generate a recharge signal for controlling a recharge operation of injecting charges into a sensing node connected to the SPAD element of the pixel 110.

[0035] The readout circuit 210 may be disposed on one side of the pixel array 100, may calculate the time delay between the pulse signal output from each pixel 110 and the reference pulse, and may generate digital data corresponding to the time delay. Here, the reference pulse may be a pulse of a clock signal (MLS). The readout circuit 210 may include: a digital logic circuit configured to generate digital data by calculating the time delay between the pulse signal of each pixel 110 and the reference pulse; and an output buffer configured to store the generated digital data. The digital logic circuit and the output buffer may be collectively referred to as a time digital circuit (TDC) hereinafter. The readout circuit 210 may send the stored digital data to an image signal processor (ISP) under the control of the timing controller 220.

[0036] In addition, according to an embodiment of the present disclosure, one readout circuit 210 may be shared by a plurality of pixels 110 (i.e., a plurality of quenching circuits 112). The readout circuit 210 may drive pixel signals received from a plurality of pixels 110, may send the pixel signals to a common node (to be described later), and may control the delay time of each signal received through the common node to generate a readout signal (i.e., a pulse signal). The readout signal generated by the readout circuit 210 may be output to the above-mentioned TDC circuit. This will be described later. Figure 5 and Figure 6 A more detailed structure and operation of the readout circuit 210 will be described.

[0037] The timing controller 220 may control the overall operation of the image sensing device 10. That is, the timing controller 220 may generate a clock signal and a timing signal to control the operations of the pixel driver 200 and the light source driver 230. In addition, the timing controller 220 may control the activation or deactivation of the readout circuit 210, and may control the digital data stored in the readout circuit 210 to be simultaneously or sequentially transmitted to the image signal processor ISP.

[0038] The light source driver 230 may generate a clock signal (MLS) capable of driving the light source (LS) under the control of the timing controller 220 .

[0039] The image signal processor (ISP) may process the digital data received from the image sensing device 10 and may generate a depth image indicating the distance to the target object (TO). In more detail, the image signal processor (ISP) may calculate the distance to the target object (TO) for each pixel 110 based on the time delay represented by the digital data received from the readout circuit 210.

[0040] The image signal processor (ISP) may control the operation of the image sensing device 10. Specifically, the image signal processor (ISP) may analyze digital data received from the image sensing device 10, may decide a mode of the image sensing device 10 based on a result of the analysis, and may control the image sensing device 10 to operate in the determined mode.

[0041] The image signal processor (ISP) may perform image signal processing of the depth image, so that the image signal processor (ISP) can perform noise removal and image quality improvement of the depth image. The depth image generated from the image signal processor (ISP) may be stored in an internal memory of an imaging device or a device including the imaging device or in an external memory in response to a user request or in an automatic manner, so that the stored depth image can be displayed through a display. Alternatively, the depth image generated from the image signal processor (ISP) may be used to control the operation of the imaging device or a device including the imaging device.

[0042] Figure 2 Some embodiments of the present disclosure are illustrated. Figure 1 A detailed circuit diagram of a pixel array of an image sensing device is shown.

[0043] Reference Figure 2 , the pixel array 100 may include a plurality of pixels 110 . Each of the pixels 110 may include a SPAD element 111 (eg, SPAD_A) and a quenching circuit 112 .

[0044] Here, the SPAD element 111 can detect a single photon reflected by a target object (TO) and can generate a current pulse corresponding to the detected single photon. The SPAD element 111 can operate as a photodiode including a photosensitive PN junction. Since avalanche breakdown is triggered by a single photon incident in a Geiger mode in which a reverse bias voltage caused by a cathode-anode voltage higher than the breakdown voltage occurs, the SPAD element 111 can generate a current pulse. In this way, the process of triggering avalanche breakdown by a single photon and generating a current pulse will be defined as an avalanche process hereinafter.

[0045] One terminal of the SPAD element 111 may receive a first bias voltage (V ) for applying a reverse bias voltage (hereinafter referred to as an “operating voltage”) higher than a breakdown voltage to the SPAD element 111. ov For example, the first bias voltage (V ov ) may be a positive voltage having an absolute value lower than the absolute value of the breakdown voltage. The other terminal of the SPAD element 111 may be connected to the sensing node N1. The SPAD element 111 may output a current pulse generated by detecting a single photon to the sensing node N1. The current pulse generated by the SPAD element 111 may be output to the NOR gate (NOR1) at a sensing voltage (V_SPAD).

[0046] The quenching circuit 112 may process the output of the SPAD element 111 and may output a pixel signal (PX_OUT). For example, the quenching circuit 112 may control the reverse bias voltage applied to the SPAD element 111, may convert the current pulse applied to the sensing node N1 into a digital type pulse signal, and may thus output a pixel signal (PX_OUT).

[0047] The quenching circuit 112 may include a plurality of NMOS transistors ( NM1 to NM6 ), a PMOS transistor ( PM1 ), a plurality of NOR gates ( NOR1 , NOR2 ), a NAND gate ( ND1 ), and a plurality of inverters ( IV1 , IV2 ).

[0048] Here, the NMOS transistor NM1 (also referred to as an “enable transistor”) may be connected between the sensing node N1 and the NMOS transistor (NM2), and may receive a quenching enable signal (QCH_EN) through its gate terminal. The NMOS transistor NM2 (also referred to as a “bias transistor”) may be connected between the NMOS transistor (NM1) and a ground voltage (VSSQCH) input terminal, and may receive a quenching bias voltage (V_QCH) through its gate terminal.

[0049] In addition, an NMOS transistor NM3 (also referred to as a "clamping transistor") may be connected between the sensing node N1 and the ground voltage (VSSQCH) input terminal, and may receive the ground voltage (VSSQCH) through its gate terminal. The NMOS transistor (NM3) may function as a diode because its gate terminal and source terminal are commonly connected to the ground voltage (VSSQCH) input terminal. When an overvoltage exceeding a clamping voltage (e.g., a preset voltage) occurs in the SPAD element 111, the NMOS transistor NM3 may clamp the overvoltage to a constant voltage (e.g., a forward voltage).

[0050] An NMOS transistor (NM4) (also referred to as a "recharge transistor") may be connected between the sensing node (N1) and a ground voltage (VSSQCH) input terminal, and may receive a recharge signal (RCH_EN) through its gate terminal. When the recharge signal (RCH_EN) is activated, the NMOS transistor (NM4) is turned on and the sensing node (N1) can be recharged to a ground voltage (VSSQCH) level. After the avalanche process is quenched, the NMOS transistor NM4 may inject charge into the sensing node so that the SPAD element 111 can re-enter the Geiger mode to induce avalanche breakdown. Here, the recharge signal (RCH_EN) may be a signal input by feedback of the quenching signal SPAD_OUTB (or the quenching signal SPAD_OUTBB). The recharge signal (RCH_EN) may be a signal having the same logic level as the quenching signal SPAD_OUTB (or the quenching signal SPAD_OUTBB). Since the NMOS transistor NM4 is operated by the recharging signal (RCH_EN) of the feedback signal indicating the quenching signal SPAD_OUTB (or the quenching signal SPAD_OUTBB), the recharging operation can be quickly performed after the quenching operation is completed.

[0051] The PMOS transistor PM1 (also referred to as a “pre-charge transistor”) may be connected between the first power supply voltage (VDDAQCH) and the sensing node ( N1 ), and may receive a quenching enable signal (QCH_EN) through a gate terminal thereof.

[0052] The NMOS transistor (NM1) and the PMOS transistor (PM1) may operate complementary to each other. Therefore, when the quenching enable signal (QCH_EN) is activated, the NMOS transistor (NM1) may be turned on and the PMOS transistor (PM1) may be turned off. On the other hand, when the quenching enable signal (QCH_EN) is deactivated, the NMOS transistor (NM1) may be turned off and the PMOS transistor (PM1) may be turned on. As a result, the sensing voltage (V_SPAD) can be precharged to the voltage level of the first power supply voltage (VDDAQCH).

[0053] The NOR gate (NOR1) (also referred to as a "first logic operation circuit") may perform a NOR operation on the sensing voltage (V_SPAD) received from the sensing node (N1) and the quenching enable disable signal (QCH_ENB), and may thus output a quenching signal (SPAD_OUTBB). In this case, the quenching enable disable signal (QCH_ENB) may be an inverted signal of the quenching enable signal (QCH_EN).

[0054] Inverter IV1 (also referred to as an "inverting circuit") can invert the quenching signal (SPAD_OUTBB) to output the quenching signal (SPAD_OUTB). Here, the quenching signal (SPAD_OUTB) can be an inverted signal of the quenching signal (SPAD_OUTBB). In addition, inverter IV2 can invert the quenching signal (SPAD_OUTB) to output the quenching signal (SPAD_OUT). The quenching signal (SPAD_OUT) can be an inverted signal of the quenching signal (SPAD_OUTB). Figure 2 In the embodiment of the present invention, the circuit for generating the quenching signal (SPAD_OUT) is shown as an inverter (IV2) only, but it is not limited to this. Alternatively, a MOS transistor can be connected to the inverter (IV2) to adjust the dynamic current of the inverter (IV2) and the time delay of the quenching signal (SPAD_OUTB), so that a circuit capable of generating the quenching signal (SPAD_OUT) can be realized. Therefore, the configuration of the inverter (IV2) can also be referred to as an "inverting circuit" or a "delay circuit".

[0055] In addition, the source terminal and the drain terminal of the NMOS transistor NM5 (also referred to as a "pull-down transistor") can be commonly connected between the ground voltage (VSSQCH) input terminal. In addition, the NMOS transistor (NM5) can receive the quenching signal (SPAD_OUT) through its gate terminal. The NMOS transistor NM5 can operate as a capacitor and thus the NMOS transistor (NM5) can control the slope of the quenching signal (SPAD_OUT).

[0056] The NAND gate (ND1) (also referred to as a "second logic operation circuit") can output a single-shot pulse signal (OSP) by performing a NAND operation on a quenching signal (SPAD_OUTB) and another quenching signal (SPAD_OUT). The NAND gate (ND1) can generate a single-shot pulse signal (OSP) having one pulse by performing a NAND operation on a quenching signal (SPAD_OUT) whose slope is adjusted by an NMOS transistor (NM5) and the quenching signal (SPAD_OUTB). In this case, the structure including the NMOS transistor (NM5) and the NAND gate (ND1) will be collectively referred to as a "pulse generation circuit" hereinafter.

[0057] The NOR gate (NOR2) (also referred to as a “third logic operation circuit”) may generate an output signal (OUT) by performing a NOR operation on the one-shot pulse signal (OSP) and the output enable signal (OUT_ENB).

[0058] The NMOS transistor NM6 (also referred to as a "driving element") can be connected between the output terminal of the pixel signal (PX_OUT) and the ground voltage (VSSQCH) input terminal, and can receive the output signal (OUT) through its gate terminal. The pixel signal (PX_OUT) having a pulse shape can be output through the NMOS transistor (NM6). In this case, the structure including the NOR gate (NOR2) and the NMOS transistor (NM6) will be collectively referred to as the "output circuit" hereinafter.

[0059] In the quenching circuit 112 having the above-mentioned constituent elements, the PMOS transistor (PM1) and the NOR gate (NOR1) can receive the first power supply voltage (VDDAQCH) as a source power supply. In the quenching circuit 112, a plurality of inverters (IV1, IV2), a NAND gate (ND1), and a NOR gate (NOR2) can receive the second power supply voltage (VDDQCH) as a source power supply. In this case, the second power supply voltage (VDDQCH) can be lower than the first power supply voltage (VDDAQCH). For example, the first power supply voltage (VDDAQCH) can be a voltage generated by level-shifting the second power supply voltage (VDDQCH).

[0060] In addition, you can Figure 1 The illustrated pixel driver 200 provides the quench enable signal (QCH_EN), quench bias voltage (V_QCH), and output enable signal (OUT_ENB) described above.

[0061] in addition, Figure 2 The pixel array 100 shown may include a plurality of SPAD elements 111 and a plurality of quenching circuits 112. The plurality of SPAD elements 111 and the plurality of quenching circuits 112 may be connected to a common node (CN1). For example, when the number of SPAD elements 111 is 144 and the number of quenching circuits 112 is 144, 144 NMOS transistors (NM6) (each NMOS transistor (NM6) is located at the output end of each quenching circuit 112) can be connected to a common node (CN1). The common node (CN1) may be shared by the 144 NMOS transistors (NM6). The common node (CN1) may be an input node of the readout circuit 210, which will be referred to later. Figure 5 Describe it in detail.

[0062] Figure 3 Some embodiments of the present disclosure are illustrated. Figure 2 The structural diagram of the pixel array 100 is shown.

[0063] Reference Figure 3, the pixel array 100 may include a plurality of SPAD elements (111, 111_1, 111_2, 111_3) and a plurality of quenching circuits (112, 112_1, 112_2, 112_3). Since the detailed configuration of the quenching circuits (112_1, 112_2, 112_3) is different from Figure 2 The quenching circuit 112 is the same as shown, so for the sake of brevity, the description will be omitted herein. Figure 3 Redundant circuit diagram and detailed description of the quenching circuit (112_1, 112_2, 112_3).

[0064] In this case, the SPAD element 111 may be referred to as a SPAD_A element hereinafter, the SPAD element 111_1 may be referred to as a SPAD_B element hereinafter, the SPAD element 111_2 may be referred to as a SPAD_C element hereinafter, and the SPAD element 111_3 may be referred to as a SPAD_D element hereinafter.

[0065] Although for the convenience of description, Figure 2 It is only illustrated that a plurality of SPAD elements 111 and a plurality of quenching circuits 112 are connected to one common node (CN1), but the scope or spirit of the disclosed technology is not limited thereto. Figure 3 It can be seen that multiple SPAD elements (111_1 to 111_3) and multiple quenching circuits (112_1 to 112_3) can be implemented to be connected to multiple common nodes (CN2 to CN4) respectively. In more detail, SPAD element 111_1 and quenching circuit 112_1 can be connected to a common node (CN2), SPAD element 111_2 and quenching circuit 112_2 can be connected to a common node (CN3), and SPAD element 111_3 and quenching circuit 112_3 can be connected to a common node (CN4).

[0066] For example, when there are 144 SPAD elements 111_1 and 144 quenching circuits 112_1, 144 NMOS transistors (NM6) as output circuits of the quenching circuits 112_1 can be connected to one common node (CN2). The common node (CN2) can be shared by multiple SPAD elements 111_1 and multiple quenching circuits 112_1. The common node (CN2) can be connected to one readout circuit 210.

[0067] When there are 144 SPAD elements 111_2 and 144 quenching circuits 112_2, 144 NMOS transistors (NM6) as output circuits of the quenching circuits 112_2 can be connected to a common node (CN3). The common node (CN3) can be shared by multiple SPAD elements 111_2 and multiple quenching circuits 112_2. The common node (CN3) can be connected to a readout circuit 210.

[0068] When there are 144 SPAD elements 111_3 and 144 quenching circuits 112_3, 144 NMOS transistors (NM6) as output circuits of the quenching circuits 112_3 can be connected to a common node (CN4). The common node (CN4) can be shared by multiple SPAD elements 111_3 and multiple quenching circuits 112_3. The common node (CN4) can be connected to a readout circuit 210.

[0069] Figure 4 Some embodiments of the present disclosure are illustrated. Figure 2 A timing diagram of the operation of the quenching circuit is shown.

[0070] Reference Figure 4 , when the NMOS transistor (NM2) is turned on by the quenching bias voltage (V_QCH) and the quenching enable signal (QCH_EN) is activated, the NMOS transistor (NM1) may be turned on. As a result, a sense voltage (V_SPAD) of a logic low level may be applied to the NOR gate (NOR1) through the sense node N1. When a sense voltage (V_SPAD) of a logic low level and a quenching enable disable signal (QCH_ENB) of a logic low level are input to the NOR gate (NOR1), the quenching signal (SPAD_OUTBB) may become a logic high level and the quenching signal (SPAD_OUTB) may become a logic low level.

[0071] The time point T1 may be a section where avalanche breakdown is triggered by a single photon and a current pulse is generated. When the quenching enable disable signal (QCH_ENB) is at a logic low level and the sensing voltage (V_SPAD) transitions to a logic high level due to the operation of the SPAD element 111, the quenching signal (SPAD_OUTBB) as the output of the NOR gate (NOR1) may transition to a logic low level.

[0072] Thereafter, the quenching signal (SPAD_OUTB) as the output of the inverter (IV1) may transition from a logic low level to a logic high level at time point T2. As described above, the inverter (IV1) is driven by the second power supply voltage (VDDQCH) and the NOR gate (NOR1) is driven by the first power supply voltage (VDDAQCH), the second power supply voltage (VDDQCH) is lower than the first power supply voltage (VDDAQCH), and thus the quenching signal (SPAD_OUTB) may have a lower voltage level than the quenching signal (SPAD_OUTBB).

[0073] Subsequently, the quenching signal (SPAD_OUT), which is the output signal of the inverter (IV2), may be synchronously transitioned to a logic low level (at time point T3) with the rising edge of the quenching signal (SPAD_OUTB). Then, when the sensing voltage (V_SPAD) transitions to a logic low level, the quenching signal (SPAD_OUTBB) may be transitioned to a logic high level again at time point T4. Thereafter, the quenching signal (SPAD_OUT) may be synchronously transitioned to a logic high level (at time point T5) with the falling edge of the quenching signal (SPAD_OUTB).

[0074] The NAND gate (ND1) can perform a NAND operation on the quenching signal (SPAD_OUT) whose slope is adjusted by the NMOS transistor (NM5) and the quenching signal (SPAD_OUTB), and can generate a single-shot pulse signal (OSP) having a logic level of 0 or 1. The NAND gate (ND1) can reduce or increase the pulse width of the single-shot pulse signal (OSP) by adjusting the time delay between the quenching signal (SPAD_OUTB) and the quenching signal (SPAD_OUT). As an example, a single-shot pulse signal (OSP) can be generated that transitions to a logic high level at time point T3, which is a time point of a rising edge of the quenching signal (SPAD_OUTB), and then transitions to a logic low level at time point T5, which is a time point of a falling edge of the quenching signal (SPAD_OUTB).

[0075] Thereafter, in a state where an output enable signal (OUT_ENB) of a logic low level is applied to the NOR gate (NOR2), the output signal (OUT) can be controlled based on the logic level of the single-shot pulse signal (OSP). For example, when a single-shot pulse signal (OSP) of a logic high level is applied to the NOR gate (NOR2), the output signal (OUT) becomes a logic low level and the NMOS transistor (NM6) can be turned off. On the other hand, when a single-shot pulse signal (OSP) of a logic low level is applied to the NOR gate (NOR2), the output signal (OUT) becomes a logic high level and the NMOS transistor (NM6) can be turned on. As a result, a pixel signal (PX_OUT) having a logic low level can be output to the common node (CN1).

[0076] Figure 5 Some embodiments of the present disclosure are illustrated. Figure 1 FIG. 2 is a detailed circuit diagram of a readout circuit 210 of an image sensing device. Figure 5 In the embodiment of Figure 2 The readout circuit 210 shared by multiple quenching circuits 112 is shown as an example.

[0077] Reference Figure 5 The readout circuit 210 can control the pixel signal (PX_OUT) received from the common node (CN1) and can generate a readout signal (ROUT). The readout circuit 210 may include a drive circuit 213, a plurality of inverters (IV4, IV5, IV6) (also referred to as “inverting elements”) and a delay control circuit 214.

[0078] In this case, the driving circuit 213 may selectively provide the second power supply voltage (VDDQCH) to the node N5 based on the bias signal (BIAS) and the delay signal (DLYB). The driving circuit 213 may include a plurality of PMOS transistors (PM2, PM3) (also referred to as "driving transistors").

[0079] The PMOS transistor (PM2) may be connected between the input terminal of the second power supply voltage (VDDQCH) and the node N5, and the PMOS transistor (PM2) may receive a bias signal (BIAS) through its gate terminal. In this case, the bias signal (BIAS) may be a signal generated by the timing controller 220. In addition, the PMOS transistor (PM3) may be connected between the input terminal of the second power supply voltage (VDDQCH) and the node N5, and the PMOS transistor (PM3) may receive a delay signal (DLYB) through its gate terminal.

[0080] The inverter (IV4) can invert the output signal of the node N5. The inverter (IV5) can invert the output signal of the inverter (IV4). The inverter (IV6) can invert the output signal of the inverter (IV4) and output a readout signal (ROUT).

[0081] The delay control circuit 214 may control the delay time of the output signal of the inverter ( IV5 ), and may output a delay signal (DLYB).

[0082] The delay control circuit 214 may include a plurality of inverters (IV7, IV8) (so-called "delay elements") configured to perform non-inverting delay on the output signal of the inverter (IV5). Although the embodiment has disclosed that the delay control circuit 214 is shown as including two inverters (IV7, IV8), the scope or spirit of the disclosed technology is not limited thereto, and it should be noted that the number of inverters can be sufficiently changed depending on the delay time.

[0083] As described above, a common node (CN1) can be shared by multiple NMOS transistors (NM6). Since the node (N4) connected to the common node (CN1) is connected to multiple NMOS transistors (NM6), there may be parasitic resistance such as a resistor R and parasitic capacitance such as a capacitor C. Therefore, the drive circuit 213 can precharge the node (N5) with the second power supply voltage (VDDQCH) based on the bias signal (BIAS) and the delay signal (DLYB). In addition, the readout circuit 210 can use the delay control circuit 214 to control the delay time of the voltage level of the node (N5), and can therefore compensate for the delay time caused by the parasitic resistance and parasitic capacitance.

[0084] Figure 6 Some embodiments of the present disclosure are illustrated. Figure 5 A timing diagram of the operation of the readout circuit is shown.

[0085] Reference Figure 6 , when the bias signal (BIAS) of the driving circuit 213 transitions to a logic low level and the pixel signal (PX_OUT) is at a logic high level, the PMOS transistor (PM2) can be turned on. Then, the node (N5) can be precharged to the level of the second power supply voltage (VDDQCH). When the node (N5) is at a logic high level, the delay signal (DLYB) and the readout signal (ROUT) can also be maintained at a logic high level.

[0086] Thereafter, when the output signal (OUT) of the quenching circuit 112 transitions to a logic high level and the NMOS transistor NM6 is turned on, the pixel signal (PX_OUT) may transition to a logic low level. Then, the node (N5) connected to the common node (CN1) may be pulled down to a ground voltage (VSSQCH) level (at time point T11).

[0087] When the voltage level of the node ( N5 ) decreases, the read signal (ROUT) may also transition to a logic low level (at a time point T12 ) after a delay time corresponding to the inverters ( IV4 , IV6 ) has elapsed.

[0088] Thereafter, when the output signal (OUT) of the quenching circuit 112 returns to a logic low level and the NMOS transistor (NM6) is turned off, the pixel signal (PX_OUT) can be transformed to a logic high level (at time point T13). When the voltage level of the node (N5) becomes a logic low level, the delay signal (DLYB) can be transformed to a logic low level (at time point T14) after the delay time corresponding to the inverting element (IV4, IV5) and the delay time (D1) corresponding to the delay control circuit 214 have elapsed. Then, the PMOS transistor (PM3) can be turned on and the second power supply voltage (VDDQCH) can be provided to the node (N5). Therefore, the voltage level of the node (N5) gradually increases and the node (N5) can be precharged.

[0089] When the section during which the pixel signal (PX_OUT) is activated to a logic low level is short (that is, when the pulse width of the pixel signal (PX_OUT) is short), the section during which the node N5 is pulled down is shortened. In this case, the node (N5) may not be sufficiently pulled down and current may not flow between the common node (CN1) (that is, the node N5) and the PMOS transistor (PM3).

[0090] According to an embodiment of the present disclosure, the delay signal (DLYB) can be maintained at a logic high level during the delay time (D1) corresponding to the delay control circuit 214. As a result, the PMOS transistor (PM3) can be kept turned off during the delay time (D1), and thus the time period (e.g., the time period from T13 to T14) during which the node (N5) is pulled down can be fully ensured.

[0091] Subsequently, when the voltage level of the node (N5) gradually increases from a logic low level and then transitions to a logic high level, the read signal (ROUT) may also transition to a logic high level (at time point T15). After a predetermined time has passed from the time point at which the read signal (ROUT) transitions to a logic high level, the delay signal (DLYB) may transition to a logic high level and the PMOS transistor (PM3) may be turned off (at time point T16).

[0092] Figure 7 Some embodiments of the present disclosure are illustrated. Figure 1 A diagram of the stacked structure of the image sensing device 10 is shown.

[0093] Reference Figure 7 , the image sensing device 10 may have a stacked structure in which the sensor chip 300 and the circuit chip 400 are vertically bonded to each other.

[0094] The sensor chip 300 and the circuit chip 400 may be electrically connected to each other through a connector (not shown) so that signals can communicate between the sensor chip 300 and the circuit chip 400 .

[0095] In the sensor chip 300, Figure 2 and Figure 3 The plurality of SPAD elements (SPAD_A to SPAD_D) shown may be arranged in a matrix shape. For example, the plurality of SPAD elements (SPAD_A to SPAD_D) may be arranged in a (2×2) matrix including rows and columns.

[0096] The circuit chip 400 may include Figure 2 and 3 The multiple quenching circuits (112, 112_1, 112_2, 112_3) and Figure 5 The readout circuit 210 shown. The plurality of quenching circuits (112, 112_1, 112_2, 112_3) included in the circuit chip 400 may be respectively connected to the plurality of SPAD elements (SPAD_A to SPAD_D) included in the sensor chip 300. In addition, the readout circuit 210 may be shared by the plurality of quenching circuits (112, 112_1, 112_2, 112_3).

[0097] The circuit chip 400 may include Figure 1 The pixel driver 200, the timing controller 220 and the light source driver 230 are shown. According to an embodiment, the circuit chip 400 may include a level shifter for generating a first power supply voltage (VDDAQCH) by level-shifting the second power supply voltage (VDDQCH) and other peripheral circuits.

[0098] Figure 8Some embodiments of the present disclosure are illustrated in Figure 7 Diagram of the logic array in the circuit chip shown.

[0099] The logic array may include the above-mentioned quenching circuit (112, 112_1, 112_2, 112_3), the readout circuit 210, the pixel driver 200, the timing controller 220, the light source driver 230, the level shifter and other peripheral circuits, but the scope or spirit of the disclosed technology is not limited thereto, and will be referred to below. Figure 8 The arrangement relationship of the quenching circuit 112 is described in detail in the embodiment of the present invention.

[0100] Reference Figure 8 , the quenching circuit 112 may be provided in the circuit chip 400 .

[0101] For example, the circuit chip 400 may include a plurality of quenching circuits 112 that are continuously arranged in a two-dimensional (2D) matrix structure. That is, the plurality of quenching circuits 112 may be continuously arranged in a row direction and a column direction.

[0102] In some embodiments, the quenching circuits 112 of the (12×12) matrix arranged in rows and columns may be grouped into a single macroarray (denoted by '1MP'). In the single macroarray 1MP, 144 (=12×12) quenching circuits 112 may share the readout circuit 210. In the circuit chip 400, the macroarray (1MP) may be continuously arranged in the row direction and the column direction. As an example, the (14×10) matrix of the macroarray (1MP) may be arranged in rows and columns.

[0103] For the convenience of description and better understanding of the disclosed technology, the above-mentioned embodiment of the present disclosure discloses that the quenching circuit 112 constitutes a macro array unit in which (12×12) quenching circuits 112 are arranged and (14×10) macro arrays are arranged, but it is not limited to this, and it should be noted that without departing from the scope of the disclosed technology, the number of quenching circuits and the number of macro arrays can also be fully changed to other numbers.

[0104] Fig. 9 is an example Figure 7 and Figure 8 Schematic diagram of the layout structure of the macro array and readout circuit within the circuit chip shown.

[0105] Reference Fig. 9 , the number of macroarrays (MP) can be set to 140 (=14×10), and the (14×10) macroarrays can be Figure 8 As shown, the circuit chip 400 is arranged. The readout circuit 210 may be arranged on one side (eg, the upper side) and the other side (eg, the lower side) of the macro array (MP), respectively.

[0106] For the convenience of description, the readout circuit 210 arranged on one side (upper side) of the macro array (MP) will be defined as the first readout circuit (MPRO1) hereinafter. As an example, the first readout circuit (MPRO1) may include 280 macro cells (MC). One readout circuit 210 is defined as a 'macro cell'. Here, four macro cells (MC1 to MC4) may be grouped into a macro cell group (MCG). The macro cell group (MCG) may be repeatedly arranged in a row direction on one side of the circuit chip 400.

[0107] In addition, the readout circuit 210 disposed on the other side (lower side) of the macro array (MP) will be defined as a second readout circuit (MPRO2) hereinafter. As an example, the second readout circuit (MPRO2) may include 280 macro cells (MC). Here, the four macro cells (MC1 to MC4) may be grouped into a macro cell group (MCG). The macro cell group (MCG) may be repeatedly arranged in a row direction on the other side of the circuit chip 400.

[0108] As an example, four macro cells (MC1 to MC4) may be allocated to each macro array (1MP). Therefore, when the total number of macro arrays (MP) is 140, a total of 560 macro cells can be arranged in the circuit chip 400, and the 560 macro cells (MC) are divided into two halves in such a manner that 280 macro cells are arranged on the upper side of the circuit chip and the remaining 280 macro cells are arranged on the lower side of the circuit chip 400.

[0109] Although the embodiments of the present disclosure disclose that the total number of macro cells is set to 560 for the convenience of description and better understanding of the disclosed technology, other embodiments are possible, and it should be noted that the number of macro cells (MC) can be fully changed without departing from the scope or spirit of the disclosed technology.

[0110] Fig.10 Some embodiments of the present disclosure are illustrated. Figure 7 SPAD devices and Fig. 9 Diagram of the routing structure of the readout circuit.

[0111] Reference Fig.10 , SPAD devices can include such as Figure 7 A plurality of SPAD elements (SPAD_A to SPAD_D) are shown. In addition, four macro cells (MC1 to MC4) may constitute a macro cell group (MCG) and may be repeatedly arranged in a row direction.

[0112] from Fig.10It can be seen that the letters (A, B, C, D) marked on the macro cells (MC1, MC2, MC3, MC4) can correspond to the letters (A, B, C, D) marked on the SPAD elements (SPAD_A, SPAD_B, SPAD_C, SPAD_D), and the macro cells (MC) and SPAD elements (SPAD) with the same letters can be routed to each other. For example, one macro cell (MC) can process the output signals of a total of 144 SPAD elements (SPAD). That is, when a total of 144 quenching circuits 112 are used (each quenching circuit 112 is as shown in FIG. 1 ), the output signals of the 144 SPAD elements (SPAD) can be processed. Figure 2 As shown), drain terminals (ie, pixel signal (PX_OUT) output terminals) of the 144 NMOS transistors (NM6) may be commonly connected to each other through a common node (CN1).

[0113] For example, the outputs of the quenching circuit 122 corresponding to 144 SPAD elements (SPAD_A) may be connected to each other through a common node (CN1), and the sensed pixel signal (PX_OUT) may be read out through a macro cell 'MC1(A)'. The outputs of the quenching circuit 122_1 corresponding to 144 SPAD elements (SPAD_B) may be connected to each other through a common node (CN2), and the sensed pixel signal (PX_OUT) may be read out through a macro cell 'MC2(B)'. The outputs of the quenching circuit 122_2 corresponding to 144 SPAD elements (SPAD_C) may be connected to each other through a common node (CN3), and the sensed pixel signal (PX_OUT) may be read out through a macro cell 'MC3(C)'.

[0114] The outputs of the quenching circuits 122_3 corresponding to the 144 SPAD elements (SPAD_D) may be connected to each other through one common node (CN4), and the sensed pixel signal (PX_OUT) can be read out through one macro cell 'MC4(D)'.

[0115] As is apparent from the above description, an image sensing device according to some embodiments of the present disclosure can be configured to have a short dead time in a small area.

[0116] The embodiments of the present disclosure may provide various effects that can be recognized directly or indirectly.

[0117] Although a number of exemplary embodiments have been described, it will be appreciated that modifications and enhancements to the disclosed embodiments and other embodiments can be devised based on what is described and / or illustrated in this disclosure.

[0118] CROSS-REFERENCE TO RELATED APPLICATIONS

[0119] This patent application claims priority to and the benefit of Korean Patent Application No. 10-2023-0134953, filed on October 11, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. An image sensing device, comprising: a plurality of light receiving elements each generating a sensing voltage corresponding to the current pulse based on photons reflected from the target object; a plurality of quenching circuits corresponding to respective light receiving elements and each outputting a pixel signal by controlling the sensing voltage from a corresponding one of the light receiving elements; as well as A readout circuit is shared by the plurality of quenching circuits and generates a readout signal by controlling a delay time of the pixel signal.

2. The image sensing device according to claim 1, wherein: Each of the light receiving elements is a single photon avalanche diode SPAD element that generates the current pulse by detecting the photon.

3. The image sensing device according to claim 1, wherein: The quenching circuit comprises: an enable transistor connected between a ground voltage input terminal and a sensing node to which the current pulse is applied and receiving a quenching enable signal through a gate terminal of the enable transistor; a first logic operation circuit, which outputs a first quenching signal by performing a logic operation on the signal of the sensing node and an inverted signal of the quenching enable signal; a first inverting circuit, wherein the first inverting circuit outputs a second quenching signal by inverting the first quenching signal; a delay circuit, the delay circuit outputting a third quenching signal by delaying the second quenching signal; a pulse generating circuit, the pulse generating circuit generating a single-shot pulse signal based on the second quenching signal and the third quenching signal; and An output circuit generates the pixel signal based on the one-shot pulse signal and an output enable signal.

4. The image sensing device according to claim 3, wherein: The first logic operation circuit is driven by a first power supply voltage, and The first inverter circuit and the delay circuit are driven by a second power supply voltage lower than the first power supply voltage.

5. The image sensing device according to claim 3, wherein: The third quenching signal transitions to a logic low level in synchronization with a rising edge of the second quenching signal and transitions to a logic high level in synchronization with a falling edge of the second quenching signal.

6. The image sensing device according to claim 3, wherein: The pulse generating circuit comprises: a pull-down transistor receiving the third quenching signal through a gate terminal of the pull-down transistor, a source terminal and a drain terminal of the pull-down transistor being connected to the ground voltage input terminal; and A second logic operation circuit is configured to output the single-shot pulse signal by performing a logic operation on the second quenching signal and the third quenching signal.

7. The image sensing device according to claim 6, wherein: The delay circuit further adjusts the delay time of the second quenching signal. The pull-down transistor also adjusts the slope of the third quenching signal, and The pulse generating circuit further adjusts the pulse width of the single-shot pulse signal according to the adjusted delay time and the adjusted slope.

8. The image sensing device according to claim 3, wherein: The output circuit comprises: a third logic operation circuit that generates an output signal by performing a logic operation on the one-shot pulse signal and the output enable signal; and A driving element is connected between the output terminal of the pixel signal and the ground voltage input terminal, and receives the output signal from the third logic operation circuit through a gate terminal of the driving element.

9. The image sensing device according to claim 3, wherein: The quenching circuit further comprises: a bias transistor connected between the enable transistor and the ground voltage input terminal and receiving a quenching bias voltage through a gate terminal of the bias transistor; a clamp transistor connected between the sensing node and the ground voltage input terminal and receiving a ground voltage through a gate terminal of the clamp transistor; a recharge transistor connected between the sensing node and the ground voltage input terminal and receiving a recharge signal through a gate terminal of the recharge transistor; and A pre-charge transistor is connected between a first power supply voltage and the sensing node and receives the quenching enable signal through a gate terminal of the pre-charge transistor.

10. The image sensing device according to claim 1, wherein: The plurality of quenching circuits output corresponding pixel signals to a single common node connected to an input terminal of the readout circuit.

11. The image sensing device according to claim 1, wherein: The readout circuit comprises: a driving circuit that precharges the first node with a second power supply voltage based on the bias signal and the delay signal; a plurality of delay elements that output the readout signal by delaying the signal of the first node; and A delay control circuit outputs the delayed signal by delaying the readout signal from the plurality of delay elements.

12. The image sensing device according to claim 11, wherein: The driving circuit comprises: a first drive transistor connected between an input terminal of the second power supply voltage and the first node and receiving the bias signal through a gate terminal of the first drive transistor; and A second driving transistor is connected between the input terminal of the second power supply voltage and the first node and receives the delayed signal through a gate terminal of the second driving transistor.

13. The image sensing device according to claim 12, wherein: the first driving transistor becomes conductive according to the bias signal to precharge the first node to a voltage level of the second power supply voltage, The driving circuit pulls the first node down to a ground voltage level according to the pixel signal, and After a delay time from turning on of the first driving transistor, the second driving transistor becomes turned on according to the delay signal to pull up the first node to the voltage level of the second power supply voltage.

14. The image sensing device according to claim 11, wherein: The plurality of delay elements include: a first inverter, the first inverter inverting the signal of the first node; a second inverter that inverts an output signal of the first inverter to output an inverted signal of the output signal of the first inverter to the delay control circuit; and a third inverter that inverts the output signal of the first inverter to output an inverted signal of the output signal of the first inverter as the readout signal.

15. An image sensing device, comprising: Circuit chip; as well as a sensor chip stacked on an upper portion of the circuit chip, wherein the sensor chip includes a plurality of light receiving elements, each of which generates a current pulse by detecting a single photon reflected from a target object, and Wherein, the circuit chip comprises: a plurality of quenching circuits corresponding to the plurality of light receiving elements and outputting a plurality of pixel signals by respectively controlling sensing voltages corresponding to the current pulses; and A readout circuit is shared by the plurality of quenching circuits and generates a readout signal by reading out the plurality of pixel signals.

16. The image sensing device according to claim 15, wherein: The plurality of quenching circuits are grouped in units of macro arrays, and The macroarray is arranged in rows and columns within the circuit chip.

17. The image sensing device according to claim 15, wherein: The readout circuit comprises: a first readout circuit, the first readout circuit being disposed on one side of the circuit chip; and A second readout circuit is provided at the other side of the circuit chip.

18. The image sensing device according to claim 17, wherein: Each of the first readout circuit and the second readout circuit includes a plurality of macro cells, and At least one of the macrocells is shared by the plurality of quenching circuits.

19. The image sensing device according to claim 15, wherein: The plurality of quenching circuits output corresponding pixel signals to a single common node connected to an input terminal of the readout circuit.

20. The image sensing device according to claim 15, wherein: The plurality of light receiving elements are connected to the plurality of quenching circuits, respectively.

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