Power-on time sequence control circuit, monitoring method and device thereof and data acquisition board card

Abstract

According to the power-on time sequence control circuit, the monitoring method and device thereof and the data acquisition board card, the first controller sends the enable signal to control the power-on time sequence of each power supply track, the second controller monitors the state of each power supply track, the complexity of a hardware platform and the PCB design difficulty are reduced, and the software workload is reduced. The technical problems that in the prior art, an extra chip is added on an existing hardware platform, a CPLD is adopted to independently control the power-on time sequence of each power supply track, and an ADC is adopted to monitor the state of each power supply track in a board, so that the complexity of the hardware platform is high, the PCB design difficulty is large, and the software workload is large are solved.

Description

Technical Field

[0001] The present application relates to the field of data acquisition and processing circuits, and in particular to a power-on timing control circuit and a monitoring method, device, and data acquisition board. Background Art

[0002] With the development of data acquisition boards, the functional requirements for data acquisition boards are gradually increasing. Not only basic data acquisition capabilities are required, but also high-performance computing capabilities, storage capabilities, and board health status monitoring capabilities. Therefore, while retaining the original functional circuits, data acquisition boards introduce DSP coprocessors to implement specific algorithm calculations, SSD solid-state hard drive particles to back up and store original data, and MCUs powered by independent power supplies VCC to implement board health status monitoring.

[0003] In addition to the FPGA originally installed on the data acquisition board, the newly introduced DSP coprocessor and SSD solid state drive particles have strict requirements on the power-on timing. Accurate control of the power-on timing is crucial to ensure the stable operation of the processor. Any situation where the power supply is not in accordance with the demand may cause the processor to work abnormally, and even fail to start in severe cases. Therefore, it is necessary to provide a power-on timing control monitoring circuit to control the power-on timing and promptly detect and handle power link failures.

[0004] In the related technology, the existing electrical timing control circuit design scheme uses CPLD to individually control the power-on timing of each power rail, and uses ADC to monitor the status of each power rail in the board. This scheme requires adding additional chips to the existing hardware platform, which not only increases the complexity of the hardware platform, but also increases the difficulty of PCB design, while also bringing greater software workload. Summary of the invention

[0005] The present application provides a power-on timing control circuit and a monitoring method, device, and data acquisition board thereof to solve the problems of high complexity of the hardware platform, high difficulty in PCB design, and high software workload.

[0006] In a first aspect of an embodiment of the present application, a power-on timing control circuit is first provided, the power-on timing control circuit comprising: a first controller, a second controller, M load modules, and M power modules, each of the power modules comprising a different number of power chipsets, each of the power chipsets comprising at least one power chip, and M is a positive integer;

[0007] The i-th terminal pin of the first controller is connected to the enable terminal of the power chip in the first power chipset of the i-th power module;

[0008] Any two adjacent power chip groups in the i-th power module are connected in series, and the power chips contained in each power chip group in the i-th power module are connected in parallel;

[0009] The i-th terminal pin of the second controller is connected to the signal terminal of the power chip in the last power chip group of the i-th power module;

[0010] The signal ends of the power chips included in each power chipset in the i-th power module are connected to the pins of the i-th load module in a one-to-one correspondence, where i is 1, 2, 3, ..., M in sequence.

[0011] In an optional embodiment, each of the power modules includes a different number of resistors and power supplies;

[0012] The signal end of the power chip included in each power chip group in the i-th power module and the pin of the i-th load module are connected in series one by one through a resistor and a power supply.

[0013] In an optional implementation, the i-th terminal pin of the first controller sends an enable signal, and the enable signal is used to control the startup of the corresponding power module;

[0014] The enable terminal of the power chip in the first power chipset of the i-th power module receives the enable signal

[0015] In an optional implementation, the signal end of the power chip in the last power chip group of the i-th power module outputs a circuit signal;

[0016] The i-th pin of the second controller receives the circuit signal.

[0017] In a second aspect of the present embodiment, a monitoring method for a power-on timing control circuit is further provided, which is applied to the power-on timing control circuit described in any one of the first aspects above, and the method includes:

[0018] The first controller enables initialization;

[0019] The first controller controls M power modules to be enabled according to a preset enabling sequence, where M is a positive integer;

[0020] The i-th pin of the first controller sends an enable signal, wherein the enable signal is used to start each power chipset in each power module in sequence;

[0021] After the enable end of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is sequentially transmitted to the next power chipset;

[0022] The i-th terminal pin of the second controller determines whether the i-th power module is powered on normally by monitoring the signal terminal of the power chip in the last power chipset of the i-th power module, where i is 1, 2, 3, ..., M in sequence.

[0023] In an optional implementation, the i-th end of the second controller determines whether the i-th power module is powered on normally by monitoring the signal end of the power chip in the last power chipset of the i-th power module, including:

[0024] If the i-th terminal pin of the second controller detects a circuit signal outputted from the signal terminal of the power chip in the last power chipset, it is determined that the i-th power module is powered on normally;

[0025] If the i-th terminal pin of the second controller does not detect that the signal terminal of the power chip in the last power chipset outputs the circuit signal, it is determined that the i-th power module is abnormal.

[0026] In an optional implementation, if the i-th terminal pin of the second controller does not detect that the signal end of the power chip in the last power chipset outputs the circuit signal, then determining that the i-th power module is abnormal includes:

[0027] Re-monitoring, according to a preset time threshold, whether the signal end of the power chip in the last power chipset outputs the circuit signal;

[0028] If the i-th terminal pin of the second controller does not detect that the signal terminal of the power chip in the last power chipset outputs the circuit signal, it is determined that the i-th power module is a faulty power module, and the faulty power module is reported;

[0029] If the i-th terminal pin of the second controller detects that the signal terminal of the power chip in the last power chipset outputs the circuit signal, it is determined that the i-th power module is powered on normally.

[0030] In an optional embodiment, if the i-th terminal pin of the second controller monitors that the signal end of the power chip in the last power chipset outputs the circuit signal, then after determining that the i-th power module is powered on normally, the method further includes:

[0031] Reset the i-th load module.

[0032] In a third aspect of an embodiment of the present application, a monitoring device for a power-on timing control circuit is further provided, which is applied to the power-on timing control circuit described in any one of the first aspects above, and the device includes:

[0033] An initialization module, used for enabling initialization of the first controller;

[0034] A power control module, used for the first controller to control M power modules to be enabled according to a preset enabling sequence, where M is a positive integer;

[0035] A signal sending module, used for sending an enable signal through the i-th terminal pin of the first controller, wherein the enable signal is used for starting each power chipset in the power module in sequence;

[0036] A power enabling module, which is used for transmitting the output circuit signal to the next power chipset in sequence after the enabling end of the power chipset in the first power chipset of the i-th power module receives the enabling signal;

[0037] The power monitoring module is used for the i-th end pin of the second controller to determine whether the i-th power module is powered on normally by monitoring the signal end of the power chip in the last power chipset of the i-th power module, where i is 1, 2, 3, ..., M in sequence.

[0038] In a fourth aspect of the embodiments of the present application, a data acquisition board is further provided, characterized in that it includes a power-on timing control circuit as described in any one of the first aspects above.

[0039] In a fifth aspect of the embodiments of the present application, there is further provided an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0040] Memory, used to store computer programs;

[0041] The processor is used to implement the steps of the method for monitoring the power-on timing control circuit described in any one of the second aspects above when executing the program stored in the memory.

[0042] In the sixth aspect of the embodiments of the present application, a storage medium is further provided, wherein instructions are stored in the storage medium, and when the storage medium is run on a computer, the computer executes the steps of the method for monitoring the power-on timing control circuit described in any one of the second aspects above.

[0043] In a seventh aspect of the embodiments of the present application, a computer program product comprising instructions is also provided, which, when executed on a computer, enables the computer to execute the method for monitoring the power-on timing control circuit described in any one of the second aspects above.

[0044] The above technical solution provided by the embodiment of the present application controls the power-on timing of each power rail by sending an enable signal through the first controller, and monitors the status of each power rail through the second controller, thereby reducing the complexity of the hardware platform and the difficulty of PCB design, and reducing the software workload. It solves the technical problem in the prior art that an additional chip is added to the existing hardware platform, CPLD is used to control the power-on timing of each power rail separately, and ADC is used to monitor the status of each power rail in the board, resulting in high complexity of the hardware platform, high difficulty of PCB design, and high software workload. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0048] Figure 1 A schematic diagram of the structure of a power-on timing control circuit provided in an embodiment of the present application;

[0049] Figure 2 A schematic diagram of an implementation flow of a monitoring method for a power-on timing control circuit provided in an embodiment of the present application;

[0050] Figure 3 A schematic diagram of an implementation flow of another method for monitoring a power-on timing control circuit provided in an embodiment of the present application;

[0051] Figure 4 A schematic diagram of an implementation flow of another method for monitoring a power-on timing control circuit provided in an embodiment of the present application;

[0052] Figure 5 A schematic diagram of the structure of a monitoring device for a power-on timing control circuit provided in an embodiment of the present application;

[0053] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0055] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0056] In order to solve the technical problems in the prior art that an additional chip is added to the existing hardware platform, a CPLD is used to individually control the power-on timing of each power rail, and an ADC is used to monitor the status of each power rail in the board, resulting in high complexity of the hardware platform, high difficulty in PCB design, and high software workload. The present application uses a power-on timing control circuit and its monitoring method, device, and data acquisition board, controls the power-on timing of each power rail by sending an enable signal through a first controller, and monitors the status of each power rail through a second controller, thereby reducing the complexity of the hardware platform and the difficulty of PCB design, and reducing the software workload.

[0057] like Figure 1 As shown, it is a schematic diagram of the structure of a power-on timing control circuit provided in an embodiment of the present application. The power-on timing control circuit 18 includes: a first controller 10, a second controller 11, M load modules 12, and M power modules 13, each power module includes a different number of power chipsets 14, each power chipset includes at least one power chip 15, each of the power modules includes a different number of resistors 16 and power supplies 17, and M is a positive integer.

[0058] The i-th terminal pin of the first controller 10 is connected to the enable terminal of the power chip 15 in the first power chip group 14 of the i-th power module 13 .

[0059] Any two adjacent power chip groups 14 in the i-th power module 13 are connected in series, and the power chips 15 contained in each power chip group 14 in the i-th power module 13 are connected in parallel.

[0060] The i-th terminal pin of the second controller 11 is connected to the signal terminal of the power chip 15 in the last power chip group 14 of the i-th power module 13 .

[0061] The signal ends of the power chips 15 included in each power chip group 14 in the i-th power module 13 are connected to the pins of the i-th load module 12 in a one-to-one correspondence, where i is 1, 2, 3, . . . , M in sequence.

[0062] The signal end of the power chip 15 included in each power chip group 14 in the above-mentioned i-th power module 13 is connected one-to-one with the pin of the i-th load module 12, including being connected in series one-to-one through a resistor 16 and a power supply 17.

[0063] The i-th pin of the first controller 10 sends an enable signal to control the startup of the corresponding power module.

[0064] The enable terminal of the power chip 15 in the first power chipset 14 of the i-th power module 13 receives an enable signal.

[0065] In the embodiments of the present application, Figure 1 As shown, the enable pin at the i-th end of the first controller is connected to the enable end of the power chip 15-1-1 in the first power chipset 14-1 in the i-th power module 13, and the signal end of the power chip 15-1-1 is connected to the corresponding load module through the first resistor 16 and the first power supply 17. When the power chipset 14-1 outputs a voltage that meets the requirements, it will enable the next power chipset 14-2 through the signal end of the power chipset 15-1-1, and so on, until the last power chipset 14-n is enabled, and the signal end of the power chipset 15-n-1 is connected to the i-th end pin of the second controller 11.

[0066] The above technical solution provided by the embodiment of the present application controls the power-on timing of each power rail by sending an enable signal through the first controller, and monitors the status of each power rail through the second controller, thereby reducing the complexity of the hardware platform and the difficulty of PCB design, and reducing the software workload. It solves the technical problem in the prior art that an additional chip is added to the existing hardware platform, CPLD is used to control the power-on timing of each power rail separately, and ADC is used to monitor the status of each power rail in the board, resulting in high complexity of the hardware platform, high difficulty of PCB design, and high software workload.

[0067] like Figure 2 FIG. 1 is a schematic diagram of an implementation flow of a monitoring method for a power-on timing control circuit provided in an embodiment of the present application, which may specifically include the following steps:

[0068] S201, the first controller enables initialization.

[0069] In an embodiment of the present application, the first controller may be a microcontroller MCU, including a processor, a memory, and an input / output interface, which may be used to control the startup sequence of the power module and monitor the power status. The first control unit enables initialization and may be prepared to output an enable signal to the corresponding power module, thereby ensuring that subsequent power supply and control can be executed smoothly. This embodiment of the present application is not limited to this.

[0070] For example, the MCU may be enabled and initialized so that it can smoothly output an enable signal to the corresponding power module.

[0071] S202: The first controller controls M power modules to be enabled according to a preset enabling sequence, where M is a positive integer.

[0072] In an embodiment of the present application, the preset enabling sequence is set according to the startup sequence of the load module, which can ensure that the power-on sequence of the power module matches the startup requirements of the load module, thereby more effectively ensuring the power-on stability of the entire system and the smooth operation of the load. The first controller controls the enabling of M power modules according to the preset enabling sequence.

[0073] For example, when M is 3, for the load module FPGA, the load module DSP, and the load module SSD, among the three load modules, since the load module FPGA needs to be powered on first to ensure the correct loading of its internal logic and configuration, the power module powered by the FPGA needs to be powered on first. Since the load module DSP and the load module SSD do not have a direct startup dependency, the first controller can flexibly choose which module to enable first, so the first controller can first enable the power module corresponding to the load module FPGA, and then enable the power module corresponding to the load module DSP or the load module SSD.

[0074] S203, the i-th terminal pin of the first controller sends an enable signal, where the enable signal is used to start each power chipset in each power module in sequence.

[0075] In an embodiment of the present application, the first controller sends enable signals one by one through the i-th end pin corresponding to the first controller according to a preset enable sequence, thereby starting each power chipset corresponding to the corresponding power module. The enable signal can be a level signal (such as a high level or a low level), a pulse signal or other signal type, which is not limited to the embodiment of the present application.

[0076] For example, when M is 3, for the load module FPGA, the load module DSP, and the load module SSD, among the three load modules, since the load module FPGA needs to be powered on first to ensure the correct loading of its internal logic and configuration, the power module powered by the FPGA needs to be powered on first. Since the load module DSP and the load module SSD do not have a direct startup dependency, the first controller can flexibly choose which module to enable first, so the first controller can first enable the power module corresponding to the load module FPGA, and then enable the power module corresponding to the load module DSP or the load module SSD. Therefore, the first end enable pin of the first controller first sends an enable signal to the power module corresponding to the load module FPGA, the second end enable pin of the first controller sends an enable signal to the power module corresponding to the load module DSP, and finally the third end enable pin of the first controller sends an enable signal to the power module corresponding to the load module SSD.

[0077] S204, after the enable end of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is transmitted to the next power chipset in sequence.

[0078] In the embodiment of the present application, each power chipset contains at least one power chip, and in each power module, the power chip enable terminal in the first power chipset receives an enable signal, and the power chip in the first power chipset starts to work, and then outputs a circuit signal to the next power chipset in sequence. The circuit signal can be a level signal (such as a high level or a low level), a pulse signal, or other signal types, which is not limited in the embodiment of the present application.

[0079] For example, assume that the i-th power module contains three power chipsets, namely, power chipset A, power chipset B, and power chipset C. When the enable signal of the first controller reaches and activates the power chip in power chipset A, power chipset A will start working and output a circuit signal. Then it will be transmitted to power chipset B, and then the power chip in power chipset B will also start working after receiving the signal, and continue to transmit the circuit signal to power chipset C. Therefore, the power chipsets in the entire power module will be started in sequence according to the preset enable sequence.

[0080] S205, the i-th end pin of the second controller determines whether the i-th power module is powered on normally by monitoring the signal end of the power chip in the last power chipset of the i-th power module, where i is 1, 2, 3, ..., M.

[0081] In the embodiment of the present application, the i-th terminal pin of the second controller determines whether the i-th power module is normally powered on by monitoring the signal terminal of the power chip in the last power chipset of the i-th power module, where i is 1, 2, 3, ..., M. The second controller may be a single-chip microcomputer, which is not limited in the embodiment of the present application.

[0082] For example, the i-th terminal pin of the single-chip computer determines whether the i-th power module is powered on normally or not by monitoring the signal terminal of the power chip in the last power chipset of the i-th power module.

[0083] Through the above description of the technical solution provided by the embodiment of the present application, the first controller enables initialization, and the first controller controls M power modules to be enabled according to a preset enabling sequence, where M is a positive integer. The i-th end pin of the first controller sends an enable signal, and the enable signal is used to sequentially start each power chipset in each power module. After the enable end of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is sequentially transmitted to the next power chipset, and the i-th end pin of the second controller determines whether the i-th power module is normally powered on by monitoring the signal end of the power chip in the last power chipset of the i-th power module, where i is 1, 2, 3, ..., M. In this way, by monitoring the signal end of the power chip in the last power chipset of the i-th power module through the i-th end pin of the second controller, it is determined whether the i-th power module is normally powered on, so as to realize the control of the power-on timing and timely discovery and processing of power link failures.

[0084] like Figure 3 FIG. 1 is a schematic diagram of an implementation flow of another method for monitoring a power-on timing control circuit provided in an embodiment of the present application, which may specifically include the following steps:

[0085] S301, the first controller enables initialization.

[0086] In the embodiment of the present application, this step is similar to the above-mentioned step S201, and the embodiment of the present application will not be described one by one here.

[0087] S302: The first controller controls M power modules to be enabled according to a preset enabling sequence, where M is a positive integer.

[0088] In the embodiment of the present application, this step is similar to the above-mentioned step S202, and the embodiment of the present application will not be described one by one here.

[0089] S303, the i-th terminal pin of the first controller sends an enable signal, where the enable signal is used to start each power chipset in each power module in sequence.

[0090] In the embodiment of the present application, this step is similar to the above-mentioned step S203, and the embodiment of the present application will not be described one by one here.

[0091] S304, after the enable end of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is transmitted to the next power chipset in sequence.

[0092] In the embodiment of the present application, this step is similar to the above-mentioned step S204, and the embodiment of the present application will not be described one by one here.

[0093] S305: If the i-th terminal pin of the second controller detects a circuit signal output from the signal terminal of the power chip in the last power chipset, it is determined that the i-th power module is powered on normally.

[0094] In the embodiment of the present application, when the i-th terminal pin of the second controller detects the output circuit signal of the signal terminal of the power chip in the last power chipset, it is determined that the i-th power module is powered on normally.

[0095] For example, for the power modules corresponding to the load module FPGA, load module DSP, and load module SSD, if the signal end of the last group of power chips in the power modules corresponding to the load module FPGA and the load module DSP outputs a circuit signal, then the power modules corresponding to the load module FPGA and the load module DSP are powered on normally.

[0096] In addition, after determining that the i-th power supply module is powered on normally, a reset operation may be performed on the i-th load module.

[0097] In an embodiment of the present application, the i-th load module can be reset by sending a reset signal to the i-th load module. The reset signal can be a level signal, a pulse signal, or other signal types. After receiving the reset signal, the i-th load module can clear internal registers, reset the state machine, turn off unnecessary power consumption units, etc., to ensure that the i-th load module can start running from a clean and initialized state. The embodiment of the present application is not limited to this.

[0098] S306: If the i-th terminal pin of the second controller does not detect the signal terminal output circuit signal of the power chip in the last power chipset, it is determined that the i-th power module is abnormal.

[0099] In the embodiment of the present application, when the i-th end pin of the second controller does not detect the signal end output circuit signal of the power chip in the last power chipset, it is determined that the i-th power module exists.

[0100] For example, for the power modules corresponding to the load module FPGA, load module DSP, and load module SSD, if the signal end of the last group of power chips in the power modules corresponding to the load module FPGA and the load module DSP does not output a circuit signal, then the power modules corresponding to the load module FPGA and the load module DSP are abnormal.

[0101] If the ith power module has an abnormality, such as Figure 4 FIG. 1 is a schematic diagram of an implementation flow of another method for monitoring a power-on timing control circuit provided in an embodiment of the present application, which may specifically include the following steps:

[0102] S401, based on a preset time threshold, re-monitoring whether a signal terminal of a power chip in the last power chipset outputs a circuit signal.

[0103] In the embodiment of the present application, when the i-th end pin of the second controller fails to detect that the signal end of the power chip in the last power chipset does not output a circuit signal for the first time, it is determined that the power module is abnormal, and the signal end of the power chip in the last power chipset is re-monitored to see whether the circuit signal is output according to the preset time threshold. The preset time threshold refers to the preset interval time for the first monitoring of the power-on timing control circuit, judging that the power module is abnormal, and then performing the second monitoring of the power-on timing control circuit, which can be 100ms, 200ms, or 300ms, and the embodiment of the present application does not limit this.

[0104] For example, when the first end pin of the second controller fails to detect for the first time that the signal end of the power chip in the last power chipset does not output a circuit signal, it is determined that an abnormality exists in the power module. The preset time threshold is 100ms. After the first monitoring is completed, a delay of 100ms is performed to re-monitor whether the signal end of the power chip in the last power chipset outputs a circuit signal.

[0105] S402: If the i-th end pin of the second controller does not detect the signal end output circuit signal of the power chip in the last power chipset, the i-th power module is determined to be a faulty power module, and the faulty power module is reported.

[0106] In an embodiment of the present application, after a preset time threshold is delayed, the i-th end pin of the second controller is used to detect whether the signal end of the power chip in the last power chipset outputs a circuit signal. If the signal end of the power chip in the last power chipset outputs a circuit signal, the i-th power module is determined to be a faulty power module, and the faulty power module is reported to facilitate subsequent repair of the faulty power module.

[0107] For example, when the first end pin of the second controller fails to detect for the first time that the signal end of the power chip in the last power chipset does not output a circuit signal, it is determined that there is an abnormality in the power module. The preset time threshold is 100ms. After the first monitoring is completed, it is delayed by 100ms and the signal end of the power chip in the last power chipset is re-monitored to see whether the circuit signal is output. If the circuit signal is still not detected, there is a circuit fault in the first power module. The first power module is a faulty power module and the faulty power module is reported to facilitate subsequent maintenance of the first power module.

[0108] S403: If the i-th terminal pin of the second controller detects a circuit signal outputted from the signal terminal of the power chip in the last power chipset, it is determined that the i-th power module is powered on normally.

[0109] In the embodiment of the present application, when the i-th terminal pin of the second controller detects the output circuit signal of the signal terminal of the power chip in the last power chipset, it is determined that the i-th power module is powered on normally.

[0110] For example, for the power modules corresponding to the load module FPGA, load module DSP, and load module SSD, if the signal end of the last group of power chips in the power modules corresponding to the load module FPGA and the load module DSP outputs a circuit signal, then the power modules corresponding to the load module FPGA and the load module DSP are powered on normally.

[0111] In addition, after determining that the i-th power supply module is powered on normally, a reset operation may be performed on the i-th load module.

[0112] In an embodiment of the present application, the i-th load module can be reset by sending a reset signal to the i-th load module. The reset signal can be a level signal, a pulse signal, or other signal types. After receiving the reset signal, the i-th load module can clear internal registers, reset the state machine, turn off unnecessary power consumption units, etc., to ensure that the i-th load module can start running from a clean and initialized state. The embodiment of the present application is not limited to this.

[0113] Corresponding to the above method embodiment, the present application embodiment also provides a monitoring device for a power-on timing control circuit, such as Figure 5 As shown, as an example Figure 5 The device shown can be applied to any of the power-on timing control circuit monitoring methods in the above-mentioned application embodiments. The device may include an initialization module 501, a power control module 502, a signal sending module 503, a power enabling module 504, and a power detection module 505.

[0114] Initialization module 501, used for enabling initialization of the first controller;

[0115] A signal sending module 502, used for sending an enable signal through the i-th terminal pin of the first controller, the enable signal being used for starting each power chipset in the power module in sequence;

[0116] A power enabling module 503, which is used for, after the enabling end of the power chip in the first power chipset of the i-th power module receives the enabling signal, the output circuit signal is sequentially transmitted to the next power chipset;

[0117] The power monitoring module 504 is used for the i-th end pin of the second controller to determine whether the i-th power module is powered on normally by monitoring the signal end of the power chip in the last power chipset of the i-th power module, where i is 1, 2, 3, ..., M.

[0118] An embodiment of the present application also provides a data acquisition board, comprising the power-on timing control circuit described in any one of the above embodiments.

[0119] The present application also provides an electronic device, such as Figure 6 As shown, it includes a processor 601, a communication interface 602, a memory 603 and a communication bus 604, wherein the processor 601, the communication interface 602, and the memory 603 communicate with each other through the communication bus 604.

[0120] Memory 603, used for storing computer programs;

[0121] In one embodiment of the present application, the processor 601, when used to execute the program stored in the memory 603, implements the following steps:

[0122] The first controller is enabled and initialized. The first controller controls M power modules to be enabled according to a preset enable sequence, where M is a positive integer. The i-th end pin of the first controller sends an enable signal, and the enable signal is used to start each power chipset in each power module in sequence. After the enable end of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is transmitted to the next power chipset in sequence. The i-th end pin of the second controller determines whether the i-th power module is powered on normally by monitoring the signal end of the power chip in the last power chipset of the i-th power module, where i is 1, 2, 3, and M respectively.

[0123] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0124] The communication interface is used for communication between the above electronic device and other devices.

[0125] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0126] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0127] In another embodiment provided in the present application, a storage medium is also provided, in which instructions are stored. When the storage medium is run on a computer, the computer executes the monitoring method of the power-on timing control circuit described in any of the above embodiments.

[0128] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute the method for monitoring the power-on timing control circuit described in any one of the above embodiments.

[0129] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a storage medium, or transmitted from one storage medium to another storage medium, for example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0130] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0131] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0132] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A power-on timing control circuit, characterized in that: The power-on timing control circuit comprises: a first controller, a second controller, M load modules, and M power modules, each of the power modules comprises a different number of power chipsets, each of the power chipsets comprises at least one power chip, and M is a positive integer; The i-th terminal pin of the first controller is connected to the enable terminal of the power chip in the first power chipset of the i-th power module; Any two adjacent power chip groups in the i-th power module are connected in series, and the power chips contained in each power chip group in the i-th power module are connected in parallel; The i-th terminal pin of the second controller is connected to the signal terminal of the power chip in the last power chip group of the i-th power module; The signal ends of the power chips included in each power chipset in the i-th power module are connected to the pins of the i-th load module in a one-to-one correspondence, where i is 1, 2, 3, and M in sequence.

2. The power-on timing control circuit according to claim 1, characterized in that: Each of the power modules includes a different number of resistors and power supplies; The signal end of the power chip included in each power chip group in the i-th power module and the pin of the i-th load module are connected in series one by one through a resistor and a power supply.

3. The power-on timing control circuit according to claim 1, characterized in that: The i-th terminal pin of the first controller sends an enable signal, and the enable signal is used to control the startup of the corresponding power module; The enable terminal of the power chip in the first power chipset of the i-th power module receives the enable signal.

4. The power-on timing control circuit according to claim 1, characterized in that: The signal end output circuit signal of the power chip in the last power chip group of the i-th power module; The i-th pin of the second controller receives the circuit signal.

5. A monitoring method for a power-on timing control circuit, characterized in that: Applied to the power-on timing control circuit according to any one of claims 1 to 4, the method comprises: The first controller enables initialization; The first controller controls M power modules to be enabled according to a preset enabling sequence, where M is a positive integer; The i-th pin of the first controller sends an enable signal, wherein the enable signal is used to start each power chipset in each power module in sequence; After the enable end of the power chip in the first power chipset of the i-th power module receives the enable signal, the output circuit signal is sequentially transmitted to the next power chipset; The i-th terminal pin of the second controller determines whether the i-th power module is powered on normally by monitoring the signal terminal of the power chip in the last power chipset of the i-th power module, where i is 1, 2, 3, ..., M in sequence.

6. The method according to claim 5, characterized in that The i-th end of the second controller determines whether the i-th power module is powered on normally by monitoring the signal end of the power chip in the last power chipset of the i-th power module, including: If the i-th terminal pin of the second controller detects a circuit signal outputted from the signal terminal of the power chip in the last power chipset, it is determined that the i-th power module is powered on normally; If the i-th terminal pin of the second controller does not detect that the signal terminal of the power chip in the last power chipset outputs the circuit signal, it is determined that the i-th power module is abnormal.

7. The method according to claim 6, characterized in that If the i-th terminal pin of the second controller does not detect that the signal terminal of the power chip in the last power chipset outputs the circuit signal, determining that the i-th power module is abnormal includes: Re-monitoring, according to a preset time threshold, whether the signal end of the power chip in the last power chipset outputs the circuit signal; If the i-th terminal pin of the second controller does not detect that the signal terminal of the power chip in the last power chipset outputs the circuit signal, it is determined that the i-th power module is a faulty power module, and the faulty power module is reported; If the i-th terminal pin of the second controller detects that the signal terminal of the power chip in the last power chipset outputs the circuit signal, it is determined that the i-th power module is powered on normally.

8. The method according to claim 6 or claim 7, characterized in that: If the i-th terminal pin of the second controller detects that the signal terminal of the power chip in the last power chipset outputs the circuit signal, then after determining that the i-th power module is powered on normally, the method further includes: Reset the i-th load module.

9. A monitoring device for a power-on timing control circuit, characterized in that: Applicable to the power-on timing control circuit according to any one of claims 1 to 4, the device comprising: An initialization module, used for enabling initialization of the first controller; A power control module, used for the first controller to control the M power modules to be enabled according to a preset enabling sequence, where M is a positive integer; A signal sending module, used for sending an enable signal through the i-th terminal pin of the first controller, wherein the enable signal is used for starting each power chipset in the power module in sequence; A power enabling module, which is used for transmitting the output circuit signal to the next power chipset in sequence after the enabling end of the power chipset in the first power chipset of the i-th power module receives the enabling signal; The power monitoring module is used for the i-th end pin of the second controller to determine whether the i-th power module is powered on normally by monitoring the signal end of the power chip in the last power chipset of the i-th power module, where i is 1, 2, 3, ..., M in sequence.

10. A data acquisition board, characterized in that: It comprises the power-on timing control circuit as claimed in any one of claims 1 to 4.

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