Dynamic power consumption management method of storage and calculation integrated chip and related equipment

Abstract

The invention relates to a dynamic power consumption management method and related equipment for a storage and calculation integrated chip, and the method comprises the following steps: carrying out the temperature data collection of a target chip, and obtaining a temperature distribution diagram of the target chip; performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution diagram and the target chip temperature distribution diagram to obtain a power consumption-temperature correlation matrix; performing power consumption management planning on the target chip based on the power consumption-temperature incidence matrix to obtain a dynamic power consumption management strategy; performing voltage frequency adjustment on the target chip based on the dynamic power consumption management strategy to obtain a voltage frequency control parameter; and performing power consumption management on the target chip based on the voltage frequency control parameter to obtain a chip power consumption management scheme, thereby solving the technical problem that a traditional optimization strategy based on a single parameter is difficult to meet the requirements of high efficiency and energy conservation due to a complex nonlinear relationship between power consumption and temperature.

Description

Technical Field

[0001] The present invention relates to the technical field of storage-computing integrated chips, and in particular to a dynamic power consumption management method of a storage-computing integrated chip and related equipment. Background Art

[0002] With the rapid development of information technology, the demand for performance of computing devices continues to increase. As an emerging technology, integrated storage and computing chips have shown great potential in improving data processing speed and efficiency. However, the high power consumption caused by this high performance has gradually become one of the bottlenecks restricting its development. Traditional power management methods often focus on optimization under static conditions, and have limited ability to adjust dynamic power consumption caused by load changes during operation. Especially with increasing integration, differences in working conditions in different areas of the chip may lead to local hotspots, which in turn affect overall performance and life. Therefore, it is particularly urgent to explore an effective power management solution that can adapt to the characteristics of integrated storage and computing chips.

[0003] In practical applications, storage and computing integrated chips not only need to process a large amount of data calculations, but also perform frequent data access operations, which requires the power management system to be able to respond to these complex and changing task requirements in real time. The current challenges include how to accurately obtain and analyze the power consumption distribution of each part of the chip, as well as the temperature change trend, so as to provide a reliable basis for power management. In addition, due to the complex nonlinear relationship between power consumption and temperature, traditional optimization strategies based on a single parameter are difficult to meet the requirements of high efficiency and energy saving. To this end, it is necessary to introduce advanced algorithms and technical means to achieve more refined and intelligent power consumption control.

[0004] In order to overcome the above difficulties, the researchers proposed a new dynamic power consumption management method for integrated storage and computing chips. This method realizes accurate monitoring of the power consumption and temperature distribution of the target chip by deploying on-chip sensor arrays and temperature sensor networks. On this basis, a mathematical model reflecting the interaction mechanism between the two was constructed using power consumption-temperature correlation analysis, and a flexible and effective power consumption management plan was formulated in combination with a multi-objective optimization algorithm. Finally, the specific adjustment of voltage and frequency was completed with the help of advanced technologies such as adaptive clock gating, forming a closed-loop control system. This method not only improves the accuracy and response speed of power consumption management, but also provides a new idea for solving the power consumption problem faced by integrated storage and computing chips. Summary of the invention

[0005] The main purpose of the present invention is to provide a dynamic power consumption management method and related equipment for a storage and computing integrated chip, which solves the technical problem that the traditional optimization strategy based on a single parameter is difficult to meet the requirements of high efficiency and energy saving due to the complex nonlinear relationship between power consumption and temperature.

[0006] To achieve the above object, the present invention provides a method for dynamic power consumption management of a storage and computing integrated chip, comprising the following steps: The power consumption data of the target chip is collected in real time through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip; wherein the storage and computing integrated chip is used as the target chip; Collecting temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip; Performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution map and the target chip temperature distribution map to obtain a power consumption-temperature correlation matrix; By using a multi-objective optimization algorithm, power consumption management planning is performed on the target chip based on the power consumption-temperature association matrix to obtain a dynamic power consumption management strategy; Based on the dynamic power management strategy, the voltage and frequency of the target chip are adjusted to obtain voltage and frequency control parameters; The power consumption of the target chip is managed based on the voltage and frequency control parameters through the adaptive clock gating technology to obtain a chip power consumption management solution.

[0007] Furthermore, the real-time power consumption data of the target chip is collected by a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip, including: The power consumption of the target chip is scanned and collected through a preset on-chip sensor array to obtain a power consumption feature set of the target chip; The target chip power consumption characteristic set is analyzed in the time domain by a preset piecewise linear interpolation algorithm to obtain power consumption timing characteristic data; wherein the power consumption timing characteristic data includes power consumption fluctuation period, power consumption peak moment and power consumption valley interval; Performing instantaneous frequency analysis on the power consumption timing characteristic data to obtain a power consumption spectrum distribution diagram; wherein the power consumption spectrum distribution diagram includes main frequency component characteristics, harmonic component characteristics, and mixed frequency component characteristics; Based on the Wigner-Ville distribution algorithm, a time-frequency joint analysis is performed on the power consumption spectrum distribution diagram to obtain the power consumption time-frequency characteristics; wherein the power consumption time-frequency characteristics include the power consumption frequency migration trajectory, the power consumption energy concentration area, and the power consumption transient mutation point; Through the conditional entropy estimation algorithm, the target chip is spatially mapped based on the power consumption time-frequency characteristics to obtain a target chip power consumption distribution map; wherein the target chip power consumption distribution map includes a high power consumption area location map, power consumption density contour lines, and a power consumption change trend map.

[0008] Furthermore, the temperature data of the target chip is collected through a temperature sensor network to obtain a temperature distribution diagram of the target chip, including: Real-time temperature data collection is performed on the target chip through a preset temperature sensor network to obtain a temperature sampling data set of the target chip; wherein the temperature sampling data set includes a temperature value, a timestamp, and a position coordinate of each sensor in the temperature sensor network; Performing noise filtering and data fusion on the temperature sampling data set to obtain a denoised temperature data sequence; Based on the finite element analysis method, the temperature field is reconstructed based on the denoised temperature data sequence to obtain a three-dimensional temperature field distribution of the target chip; wherein the three-dimensional temperature field distribution includes the temperature value of each point inside the target chip and the temperature gradient information; Performing hot spot identification on the three-dimensional temperature field distribution to obtain a hot spot distribution map of the target chip; wherein the hot spot distribution map includes a hot spot position, a hot spot temperature peak, and a hot spot area; The heat source power is estimated by using a reverse heat transfer analysis method on the hot spot area distribution map of the target chip to obtain the heat source power distribution data of the target chip; wherein the heat source power distribution data includes the power value and power density of each hot spot area; A temperature distribution map is generated based on the heat source power distribution data to obtain a target chip temperature distribution map; wherein the target chip temperature distribution map includes the temperature value of each computing unit and storage unit in the target chip, and is visually presented in the form of a color heat map.

[0009] Further, the power consumption-temperature correlation analysis is performed on the target chip based on the target chip power consumption distribution map and the target chip temperature distribution map to obtain a power consumption-temperature correlation matrix, including: Perform multi-scale decomposition on the target chip power consumption distribution map and the temperature distribution map through adaptive wavelet transform to obtain a power consumption-temperature feature component set, and perform local singular value decomposition on the power consumption-temperature feature component set to obtain a power consumption-temperature basis vector matrix; wherein the power consumption-temperature basis vector matrix includes a computing unit power consumption-temperature mapping matrix, a storage unit power consumption-temperature mapping coefficient, and an on-chip bus power consumption-temperature coupling factor; Based on the Hilbert-Huang transform, the power consumption-temperature basis vector matrix is ​​subjected to intrinsic mode decomposition to obtain a power consumption-temperature intrinsic component sequence, and a bispectral analysis is performed on the power consumption-temperature intrinsic component sequence to obtain a power consumption-temperature cross-spectral feature; wherein the power consumption-temperature cross-spectral feature includes a power consumption-temperature oscillation period, a power consumption-temperature phase difference, and a power consumption-temperature amplitude ratio; The power consumption-temperature cross-spectral characteristics are nonlinearly reconstructed by a preset local projection embedding algorithm to obtain a power consumption-temperature state space trajectory; Performing a time series correlation analysis based on the power consumption-temperature state space trajectory to obtain a power consumption-temperature coupling feature sequence, and performing transfer entropy calculation on the power consumption-temperature coupling feature sequence to obtain a power consumption-temperature causal network; Perform community detection on the power consumption-temperature causal network to obtain a power consumption-temperature coupling subgraph set, and perform spectral clustering analysis on the power consumption-temperature coupling subgraph set to obtain a power consumption-temperature associated region; wherein the power consumption-temperature associated region includes a strong coupling region identifier, a weak coupling region boundary, and a critical coupling region feature; Based on recursive quantization analysis, dynamic feature extraction is performed on the power consumption-temperature association region to obtain a power consumption-temperature time-varying feature set, and tensor decomposition is performed on the power consumption-temperature time-varying feature set to obtain a power consumption-temperature association matrix.

[0010] Furthermore, the multi-objective optimization algorithm is used to perform power management planning on the target chip based on the power consumption-temperature association matrix to obtain a dynamic power consumption management strategy, including: Performing singular value decomposition on the power consumption-temperature association matrix to obtain a power consumption-temperature feature vector set, and performing principal component analysis on the power consumption-temperature feature vector set to obtain power consumption-temperature principal component features; The power consumption-temperature principal component characteristics are optimized by a multi-objective genetic algorithm to obtain a power consumption-temperature Pareto optimal solution set; The power consumption-temperature objective function of the target chip is constructed by using the power consumption-temperature Pareto optimal solution set to obtain a multi-objective optimization function, and the multi-objective optimization function is solved by the Lagrange multiplier method to obtain a Lagrange multiplier vector; wherein the Lagrange multiplier vector includes a power consumption weight coefficient, a temperature weight coefficient, and a performance weight coefficient; Dynamically allocate power consumption budget to the target chip based on the Lagrange multiplier vector to obtain a power consumption budget allocation scheme, and optimize the power consumption budget allocation scheme based on game theory to obtain a Nash equilibrium point; wherein the Nash equilibrium point includes a computing unit power consumption budget, a storage unit power consumption budget, and a communication unit power consumption budget; Power consumption management planning is performed on the target chip based on the Nash equilibrium point to obtain a dynamic power consumption management strategy.

[0011] Further, the voltage and frequency of the target chip are adjusted based on the dynamic power management strategy to obtain voltage and frequency control parameters, including: Performing cluster analysis on the power consumption characteristics of the target chip through a dynamic power consumption management strategy to obtain a power consumption cluster set, and performing principal component analysis on the power consumption cluster set to obtain a power consumption feature vector; wherein the power consumption feature vector includes chip power consumption mean, power consumption variance, and power consumption peak feature parameters; Performing voltage regulation analysis on the target chip based on the power consumption characteristic vector to obtain a voltage regulation solution; Performing frequency configuration analysis on the target chip through the voltage regulation scheme to obtain a frequency configuration scheme; Based on the frequency control parameters, the target chip is subjected to power consumption allocation analysis to obtain a power consumption allocation scheme, and the power consumption allocation scheme is optimized by an ant colony algorithm to obtain power consumption allocation parameters; wherein the power consumption allocation parameters include a power consumption allocation ratio, a power consumption allocation threshold, and a power consumption allocation delay parameter; The voltage and frequency of the target chip are adjusted according to the power consumption allocation parameter to obtain a voltage and frequency control signal; The voltage and frequency of the target chip are adjusted based on the voltage and frequency control signal to obtain voltage and frequency control parameters.

[0012] Furthermore, the power consumption management of the target chip is performed based on the voltage and frequency control parameters by using the adaptive clock gating technology to obtain a chip power consumption management solution, including: Extracting the timing characteristics of the voltage frequency control parameters through the adaptive clock gating technology to obtain a clock adjustment scheme, and performing Fourier transform analysis on the clock adjustment scheme to obtain clock spectrum characteristics; wherein the clock spectrum characteristics include clock frequency components, clock phase offsets, and clock amplitude adjustment characteristic parameters; Based on the clock spectrum characteristics, the target chip is subjected to power consumption prediction analysis to obtain a power consumption prediction sequence; wherein the power consumption prediction sequence includes a power consumption timing mean, a power consumption fluctuation variance, and a power consumption peak characteristic parameter; Performing power consumption allocation planning on the target chip through the power consumption prediction sequence to obtain a power consumption allocation strategy, and performing parameter analysis on the power consumption allocation strategy to obtain a power consumption allocation control parameter; Dynamically adjusting the voltage and frequency of the target chip based on the power consumption allocation control parameter to obtain a voltage and frequency configuration scheme, and converting the voltage and frequency configuration scheme into an instruction to obtain a voltage and frequency control instruction; Power consumption management is performed on the target chip based on the voltage and frequency control instruction to obtain a chip power consumption management solution.

[0013] The present invention also provides a dynamic power consumption management device for a storage-computing integrated chip, comprising: The first acquisition module is used to collect real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip; wherein the storage and computing integrated chip is used as the target chip; A second acquisition module is used to collect temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip; An analysis module, configured to perform a power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution diagram and the target chip temperature distribution diagram, and obtain a power consumption-temperature correlation matrix; A generation module, used to perform power management planning on the target chip based on the power consumption-temperature association matrix through a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy; An adjustment module, used to adjust the voltage and frequency of the target chip based on the dynamic power management strategy to obtain voltage and frequency control parameters; The management module is used to perform power consumption management on the target chip based on the voltage and frequency control parameters through an adaptive clock gating technology to obtain a chip power consumption management solution.

[0014] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0015] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0016] The dynamic power consumption management method of the storage and computing integrated chip provided by the present invention comprises the following steps: collecting real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip; wherein the storage and computing integrated chip is used as the target chip; collecting temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip; performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution diagram and the target chip temperature distribution diagram to obtain a power consumption-temperature correlation matrix; performing power consumption management planning on the target chip based on the power consumption-temperature correlation matrix through a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy; adjusting the voltage and frequency of the target chip based on the dynamic power consumption management strategy to obtain voltage and frequency control parameters; performing power consumption management on the target chip based on the voltage and frequency control parameters through an adaptive clock gating technology to obtain a chip power consumption management solution, thereby solving the technical problem that the traditional optimization strategy based on a single parameter is difficult to meet the requirements of high efficiency and energy saving due to the complex nonlinear relationship between power consumption and temperature, realizing in-depth power consumption-temperature correlation analysis using the power consumption distribution diagram and the temperature distribution diagram, and constructing a detailed power consumption-temperature correlation matrix. This correlation analysis helps to more deeply understand the complex relationship between the two, and then formulate a more scientific and reasonable power management strategy to ensure that the chip temperature is controlled while optimizing power consumption, avoiding technical effects such as performance degradation or hardware damage caused by local overheating. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the steps of a dynamic power consumption management method of a storage and computing integrated chip in one embodiment of the present invention; Figure 2 It is a structural block diagram of a dynamic power consumption management device for a storage and computing integrated chip in one embodiment of the present invention; Figure 3 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0018] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] like Figure 1 As shown, Figure 1 It is a schematic diagram of the steps of a dynamic power consumption management method of a storage and computing integrated chip in one embodiment of the present invention; In one embodiment of the present invention, a method for dynamic power consumption management of a storage and computing integrated chip is provided, comprising the following steps: Step S1, collect real-time power consumption data of a target chip through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip; wherein a storage and computing integrated chip is used as the target chip.

[0021] Specifically, the step of "collecting real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution map of the target chip; wherein the storage and computing integrated chip is used as the target chip" mentioned above is the basis for implementing the dynamic power management method. In order to achieve this process, it is first necessary to integrate a series of specially designed sensors on the storage and computing integrated chip, which constitute the so-called on-chip sensor array. The on-chip sensor array can monitor the current consumption of various areas inside the chip and collect power consumption data with extremely high time resolution. For example, in a high-performance server environment, the storage and computing integrated chip may be responsible for processing a large number of concurrent requests and data exchanges. At this time, the on-chip sensor array will continue to track the changes in power consumption during the execution of different computing tasks. Next, as the data is continuously collected, the system will process these raw data and generate an intuitive power consumption distribution map. This map reflects the power consumption characteristics of the chip in a specific time period in detail, including which areas are in a high-load state and which areas are relatively idle. For the above-mentioned server application scenario, when some cores are running complex algorithms at full capacity, while other parts may only maintain basic operations, the power consumption distribution map will show obvious power consumption concentration areas and low power consumption areas. Furthermore, the power consumption distribution map is not only a simple visual display, it also provides a basis for subsequent more in-depth analysis. By analyzing these power consumption data, potential problem points or optimization opportunities can be found, such as whether there are unnecessary high-power activities, or whether it is possible to save energy by adjusting the working mode. In addition, since the characteristics of the storage and computing integrated chip are that it integrates storage units and computing units, the power consumption distribution map can also help identify hot spots with high storage access frequency and how they affect the overall power consumption level. In summary, by carefully laying out the preset on-chip sensor array and effectively utilizing the obtained data, we can accurately draw the power consumption distribution map of the target chip, the storage and computing integrated chip, without affecting normal operations, thereby laying a solid foundation for further implementation of precise power consumption management and performance optimization. This not only helps to improve the energy efficiency of the system, but also ensures stable and reliable operation in various complex application scenarios.

[0022] Step S2, collecting temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip.

[0023] Specifically, the process of "collecting temperature data of the target chip through the temperature sensor network to obtain the temperature distribution map of the target chip" mentioned above is an important part of monitoring the working status of the storage and computing integrated chip. In order to achieve this goal, a carefully designed temperature sensor network needs to be deployed inside and around the chip. These temperature sensors are distributed in key areas of the chip, including computing units, storage units, and data paths between the two, to ensure that the temperature changes of each part can be fully covered and accurately reflected. For example, in a high-performance server environment, the storage and computing integrated chip undertakes a large number of concurrent requests and complex data processing tasks, and the temperature sensor network will continuously record the temperature fluctuations of each area during the execution of different computing tasks. As the temperature data continues to accumulate, the system will analyze and process the collected information to generate a detailed temperature distribution map of the target chip. This picture not only intuitively shows the temperature gradient on the chip surface, but also reveals the direction and intensity of the heat flow, allowing engineers to clearly identify which areas are heat sources and where there are heat dissipation bottlenecks. For the aforementioned server application scenario, when some cores generate heat due to high-intensity computing, the temperature distribution map can show the specific location of these hot spots, and also indicate the relatively low-temperature idle areas, which helps to understand the dynamic characteristics of heat transfer inside the chip. Furthermore, the temperature distribution map is not only a static image display, but also a dynamic monitoring tool. By real-time tracking of temperature data, the system can promptly detect abnormal temperature rise and take preventive measures to avoid overheating leading to performance degradation or hardware damage. In addition, combined with the power consumption distribution map, the correlation between power consumption and temperature can be studied in more depth, providing an important reference for subsequent optimization algorithms. For example, if a computing unit has an unreasonable high temperature under high load, it may mean that the operating frequency of the unit is too high or the power supply voltage is improperly set, then the corresponding parameters can be adjusted to improve this situation. In short, by building and utilizing a temperature sensor network, we can accurately draw the temperature distribution map of the target chip, i.e., the storage-computing integrated chip, without affecting normal computing, thereby laying a solid foundation for achieving efficient power consumption management and thermal management strategies. This not only helps to improve the energy efficiency of the system, but also ensures stable and reliable operation in various complex application scenarios. For example, in applications in high-performance servers, this precise temperature monitoring and control capability is particularly important.

[0024] Step S3, performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution diagram and the target chip temperature distribution diagram to obtain a power consumption-temperature correlation matrix.

[0025] Specifically, the process of performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution map and the target chip temperature distribution map to obtain the power consumption-temperature correlation matrix is ​​the core link in the dynamic power consumption management method. This process not only relies on the detailed power consumption and temperature data obtained in the previous steps, but also requires the use of advanced data analysis technology to reveal the complex relationship between the two. Specifically, in a high-performance server environment, when the storage and computing integrated chip runs a large number of concurrent requests and complex data processing tasks, the power consumption and temperature information of each area of ​​the chip has been collected through the preset on-chip sensor array and temperature sensor network. After this information is sorted into intuitive power consumption distribution maps and temperature distribution maps, the next task is to deeply explore the intrinsic connection between the two. In order to realize the power consumption-temperature correlation analysis, it is first necessary to match the corresponding points in the power consumption distribution map and the temperature distribution map to ensure that each power consumption measurement value can find the corresponding temperature measurement value. For example, in the process of the computing unit performing high-intensity operations, if it is found that the power consumption of a certain area increases significantly, and the temperature of the area also rises accordingly, then it can be preliminarily judged that there is a positive correlation between the two. However, this relationship is not always linear, because factors such as heat conduction, diffusion, and external cooling conditions will affect the final temperature performance. Therefore, further analysis requires the use of mathematical modeling methods to consider the influence of more variables and build a model that can accurately describe the nonlinear relationship between power consumption and temperature. After establishing the preliminary correlation model, researchers will use multidimensional statistical analysis and other advanced algorithms to optimize the model parameters so that the power consumption-temperature correlation matrix can more accurately reflect the actual situation. This matrix is ​​not just a static result display, it also provides an important decision-making basis for subsequent power management and thermal management strategies. For example, in the above server application scenario, if the temperature of some computing units under a specific workload is found to be abnormally high according to the power consumption-temperature correlation matrix, it may be caused by insufficient heat dissipation design or improper power consumption management. At this time, the operating frequency or voltage settings of these units can be adjusted based on the information provided by the matrix, thereby effectively reducing the temperature and avoiding potential performance bottlenecks or hardware failure risks. In addition, the power consumption-temperature correlation matrix can also be used to guide the design and optimization of future chips. By studying the trends of power consumption and temperature changes under different operating conditions, engineers can identify which design factors are most likely to cause excessive power consumption or poor heat dissipation, and propose improvement plans accordingly. In summary, through in-depth analysis of the power consumption distribution map and temperature distribution map of the target chip, we can not only establish a detailed power consumption-temperature correlation matrix, but also provide a scientific basis for achieving efficient power consumption control and thermal management, ensuring the stability and reliability of the system in various complex application scenarios, such as applications in high-performance servers. This precise correlation analysis capability is particularly critical.

[0026] Step S4, performing power consumption management planning on the target chip based on the power consumption-temperature association matrix through a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy.

[0027] Specifically, the process of planning the power management of the target chip based on the power consumption-temperature association matrix through a multi-objective optimization algorithm and obtaining a dynamic power consumption management strategy is a key step to ensure that the storage and computing integrated chip can achieve high performance and low power consumption in complex application scenarios such as high-performance servers. This process relies on the previously constructed power consumption-temperature association matrix, which records in detail the complex relationship between the power consumption and temperature of each part of the chip, providing a solid data foundation for the subsequent optimization. When faced with the diversity and uncertainty in actual operation, the multi-objective optimization algorithm can comprehensively consider multiple mutually restrictive factors, such as performance requirements, power consumption limitations, and temperature control, to find the optimal solution. Specifically, in a high-performance server environment, the storage and computing integrated chip may process a large number of concurrent requests and complex computing tasks at the same time. At this point, through the previous analysis of the power consumption distribution map and the temperature distribution map, it has been clarified which areas are prone to become hot spots, and the correlation between these hot spots and power consumption. Based on this, the multi-objective optimization algorithm begins to play a role, and it will dynamically adjust the working state of each computing unit according to the current task load and the information provided by the power consumption-temperature association matrix. For example, if a computing unit consumes high power and its temperature rises rapidly when performing a specific type of task, the optimization algorithm may choose to reduce the unit's operating frequency or assign tasks to other relatively low-temperature areas to balance the overall power consumption and temperature distribution. Furthermore, the multi-objective optimization algorithm is not limited to static configuration, but continuously monitors the state changes of the chip and responds in real time. As the workload changes, some previously inactive areas may suddenly take on more computing tasks, resulting in a sudden increase in power consumption and temperature. At this time, the optimization algorithm will quickly re-evaluate the power consumption-temperature status of the entire system and adjust the strategy accordingly to ensure that the overall performance is not affected by local overheating. In addition, considering the reliability and energy consumption costs under long-term operation, the optimization algorithm will also introduce some forward-looking indicators, such as predicting future load trends and corresponding power consumption changes, making preparations in advance, and avoiding unnecessary high power consumption periods. In order to achieve the above functions, the optimization algorithm usually combines machine learning technology to continuously improve the accuracy and efficiency of decision-making through learning and pattern recognition of historical data. For example, in a high-performance server scenario, over time, the system accumulates a large amount of power consumption and temperature data, from which the optimization algorithm can learn the most effective power management solution under different task combinations, thereby forming a set of adaptive dynamic power management strategies. This strategy can not only minimize power consumption while ensuring performance, but also effectively prevent hardware failures caused by overheating and improve system stability and reliability. In short, through the application of multi-objective optimization algorithms, we can develop a more intelligent and flexible dynamic power management strategy based on the power consumption-temperature correlation matrix, providing strong support for high-performance servers and other similar application scenarios.

[0028] Step S5: adjusting the voltage and frequency of the target chip based on the dynamic power consumption management strategy to obtain voltage and frequency control parameters.

[0029] Specifically, the process of adjusting the voltage and frequency of the target chip based on the dynamic power management strategy to obtain the voltage and frequency control parameters is one of the key links to achieve high performance and low power consumption of the storage and computing integrated chip. This process is closely dependent on the dynamic power management strategy previously formulated by the multi-objective optimization algorithm. The strategy comprehensively considers multiple factors such as power consumption, temperature and performance requirements, and provides clear guidance for specific voltage and frequency adjustment. In a high-performance server environment, when the storage and computing integrated chip processes a large number of concurrent requests and complex computing tasks, voltage and frequency adjustment can ensure that the system meets performance requirements while reducing unnecessary power consumption as much as possible and maintaining a safe operating temperature. Specifically, after determining the dynamic power management strategy, the next step is to convert these strategies into actual operating instructions, namely, voltage and frequency control parameters. This involves accurately adjusting the power supply voltage and operating frequency of each working unit inside the target chip. For example, according to the power consumption-temperature association matrix analysis results and the current task load, if a computing unit is in a high load state and the temperature is close to the critical value, then the dynamic power management strategy may indicate to appropriately reduce its operating frequency, while fine-tuning the power supply voltage to ensure that the performance is not greatly affected. This adjustment is not static, but will be dynamically updated as the task changes to ensure that the best voltage and frequency combination can be found at any time. To achieve this, programmable power management and clock control systems are usually introduced during the chip design phase, allowing the voltage and frequency parameters to be flexibly set at the software level. In actual applications, these control systems will adjust the working state of each computing unit in real time according to the instructions issued by the dynamic power management strategy. For example, in a high-performance server scenario, when it is detected that certain areas have risen too fast due to high-intensity computing, the system can automatically reduce the operating frequency of those areas and adjust the supply voltage according to pre-set rules, thereby quickly alleviating local hot spots. At the same time, for relatively idle or low-load areas, their operating frequency can be appropriately increased to speed up the completion of the remaining tasks, or the voltage can be reduced to save energy. In addition, in order to ensure the safety and effectiveness of voltage and frequency regulation, the entire process will be strictly monitored. By continuously collecting data feedback from the on-chip sensor array and temperature sensor network, the system can respond to any abnormal conditions in a timely manner, such as excessive voltage fluctuations or temperatures exceeding the safe range, and then take emergency measures to protect the hardware from damage. In summary, adjusting the voltage and frequency of the target chip based on the dynamic power management strategy not only helps to optimize the balance between performance and power consumption, but also effectively prevents potential failures caused by overheating, providing a more intelligent and reliable solution for high-performance servers and other similar application scenarios. In this way, we can significantly improve the energy efficiency of the system without affecting normal operations, ensuring its long-term stable and reliable operation.

[0030] Step S6, performing power consumption management on the target chip based on the voltage and frequency control parameters by using an adaptive clock gating technology to obtain a chip power consumption management solution.

[0031] Specifically, the process of performing power consumption management on the target chip based on the voltage and frequency control parameters through adaptive clock gating technology and obtaining a chip power consumption management solution is the last link for the storage and computing integrated chip to achieve a balance between high performance and low power consumption in a high-performance server environment. This process is based on all the previous steps, that is, firstly, detailed power consumption and temperature data are collected through the on-chip sensor array and temperature sensor network, then the power consumption-temperature association matrix is ​​constructed, and then a dynamic power consumption management strategy is formulated using a multi-objective optimization algorithm, and finally the voltage and frequency parameters are adjusted according to these strategies. On this basis, the adaptive clock gating technology further refines the clock signal inside the chip to ensure that each computing unit is activated only when it is really needed, thereby minimizing static power consumption. Specifically, in a high-performance server, when the storage and computing integrated chip performs complex data processing tasks, the workloads in different areas may vary greatly. Some computing units may be under high load, while others are relatively idle or only undertake minor tasks. In this case, through the adaptive clock gating technology, it is possible to dynamically determine which clock signals should be turned on or off according to the voltage and frequency control parameters. For example, if a computing unit currently has no tasks or its workload is very small, the system can temporarily turn off the clock signal of the unit, putting it into a low-power standby mode until a new task arrives. On the contrary, for those computing units that are in a busy state, the clock signal is kept normally supplied to ensure that performance is not affected. In addition, adaptive clock gating technology can also respond to real-time changing working conditions and provide more flexible power management. As the task load changes, the system will continuously re-evaluate the needs of each computing unit and adjust the clock gating strategy accordingly. For example, in a high-performance server scenario, when it is detected that some areas become idle due to task completion, the adaptive clock gating technology will immediately stop sending clock signals to these areas to avoid unnecessary power consumption. At the same time, for the areas that are about to receive new tasks, the system prepares the required clock resources in advance to ensure that the tasks can be started quickly and executed efficiently. In order to ensure that this dynamic adjustment does not have a negative impact on the overall performance, adaptive clock gating technology is usually combined with an intelligent prediction algorithm to identify potential changes in task requirements in advance. This not only allows timely response to actual situations, but also foresee possible load fluctuations in the future and prepare in advance. For example, when processing large-scale concurrent requests, the system may predict the upcoming traffic peak based on historical data and current trends, and activate the clock signals of related computing units in advance to ensure sufficient processing power to cope with the upcoming tasks. In short, through adaptive clock gating technology, the power consumption of the target chip is managed based on the voltage and frequency control parameters, which can not only further reduce static power consumption and improve the energy efficiency of the system, but also ensure stable performance in various complex application scenarios.This approach provides a more intelligent and sophisticated power management solution for high-performance servers, enabling storage and computing integrated chips to effectively control energy consumption, extend hardware life, and reduce heat dissipation pressure while meeting high performance requirements. In this way, we can significantly improve the overall operation of the system without affecting computing efficiency, ensuring that it can serve complex computing tasks stably and reliably in the long term.

[0032] In a specific embodiment, the real-time power consumption data of the target chip is collected through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip, including: The power consumption of the target chip is scanned and collected through a preset on-chip sensor array to obtain a power consumption feature set of the target chip; The target chip power consumption characteristic set is analyzed in the time domain by a preset piecewise linear interpolation algorithm to obtain power consumption timing characteristic data; wherein the power consumption timing characteristic data includes power consumption fluctuation period, power consumption peak moment and power consumption valley interval; Performing instantaneous frequency analysis on the power consumption timing characteristic data to obtain a power consumption spectrum distribution diagram; wherein the power consumption spectrum distribution diagram includes main frequency component characteristics, harmonic component characteristics, and mixed frequency component characteristics; Based on the Wigner-Ville distribution algorithm, a time-frequency joint analysis is performed on the power consumption spectrum distribution diagram to obtain the power consumption time-frequency characteristics; wherein the power consumption time-frequency characteristics include the power consumption frequency migration trajectory, the power consumption energy concentration area, and the power consumption transient mutation point; Through the conditional entropy estimation algorithm, the target chip is spatially mapped based on the power consumption time-frequency characteristics to obtain a target chip power consumption distribution map; wherein the target chip power consumption distribution map includes a high power consumption area location map, power consumption density contour lines, and a power consumption change trend map.

[0033] Specifically, the process of collecting real-time power consumption data of the target chip through the preset on-chip sensor array to obtain the target chip power consumption distribution map is a complex and sophisticated technical implementation. First, the system will use the preset on-chip sensor array to perform a comprehensive power consumption scan and collection on the target chip. This process aims to capture the power consumption characteristics of the chip at different time points and form a target chip power consumption feature set containing detailed power consumption information. For example, in a high-performance server environment, the storage and computing integrated chip may need to process a large number of concurrent requests. The sensor array will record the power consumption of each computing unit and storage unit during these operations to ensure that no critical data is missed. Next, in order to more deeply understand the change law of power consumption characteristics over time, the system uses a preset piecewise linear interpolation algorithm to perform time domain analysis on the obtained target chip power consumption feature set. This step can reveal time series feature data such as the fluctuation period of power consumption, the peak moment of power consumption, and the valley interval of power consumption. Taking a high-performance server as an example, when certain computing tasks are intensively executed, the power consumption may have a significant peak, and drop to a valley during the task interval. By accurately measuring these time series features, future power consumption requirements can be better predicted and managed. Furthermore, in order to explore the frequency domain characteristics of power consumption changes, the system performs instantaneous frequency analysis on the above power consumption timing characteristic data to generate a power consumption spectrum distribution diagram. This diagram not only shows the characteristics of the main frequency component, but also reveals the characteristics of the harmonic component and the mixed frequency component, which is crucial for understanding complex power consumption behavior. For example, in a high-performance server, if a computing unit frequently switches its working state, its power consumption spectrum may show significant harmonic components, which provides important reference information for the optimization algorithm and helps identify which operations may cause unnecessary high power consumption. In order to more comprehensively grasp the spatiotemporal characteristics of power consumption, the system performs a time-frequency joint analysis of the power consumption spectrum distribution diagram based on the Wigner-Ville distribution algorithm. In this way, the time-frequency characteristics of power consumption including the power consumption frequency migration trajectory, the power consumption energy concentration area, and the power consumption transient mutation point can be obtained. This means that we can track how power consumption evolves with time and frequency, and find out those specific events or operation modes that have a greater impact on the overall power consumption. For example, in a high-performance server scenario, when a new batch of tasks begins to execute, we can quickly locate the cause of the sudden increase in power consumption through time-frequency joint analysis, and then take measures to optimize it. Finally, in order to transform these rich power consumption characteristics into intuitive spatial mapping results, the system uses the conditional entropy estimation algorithm to perform spatial mapping of the target chip based on the power consumption time-frequency characteristics, and finally obtains the target chip power consumption distribution map. This map includes the high power consumption area location map, power consumption density contour lines, and power consumption change trend map, allowing engineers to see the power consumption status of each part of the chip at a glance.For example, in high-performance server applications, by observing the power consumption distribution graph, we can clearly identify which computing units or storage areas are under high load and where there is energy saving potential, thus providing strong support for subsequent power consumption management and performance optimization. In summary, through the above series of steps, from the collection of power consumption feature sets to the generation of power consumption distribution graphs, we not only achieve in-depth analysis of the power consumption state of the target chip, but also find a scientific basis for the balance between high performance and low power consumption. This method ensures that the power consumption performance of the system can be accurately controlled and optimized without affecting normal operations, providing strong guarantees for high-performance servers and other similar application scenarios.

[0034] In a specific embodiment, the temperature data of the target chip is collected through a temperature sensor network to obtain a temperature distribution diagram of the target chip, including: Real-time temperature data collection is performed on the target chip through a preset temperature sensor network to obtain a temperature sampling data set of the target chip; wherein the temperature sampling data set includes a temperature value, a timestamp, and a position coordinate of each sensor in the temperature sensor network; Performing noise filtering and data fusion on the temperature sampling data set to obtain a denoised temperature data sequence; Based on the finite element analysis method, the temperature field is reconstructed based on the denoised temperature data sequence to obtain a three-dimensional temperature field distribution of the target chip; wherein the three-dimensional temperature field distribution includes the temperature value of each point inside the target chip and the temperature gradient information; Performing hot spot identification on the three-dimensional temperature field distribution to obtain a hot spot distribution map of the target chip; wherein the hot spot distribution map includes a hot spot position, a hot spot temperature peak, and a hot spot area; The heat source power is estimated by using a reverse heat transfer analysis method on the hot spot area distribution map of the target chip to obtain the heat source power distribution data of the target chip; wherein the heat source power distribution data includes the power value and power density of each hot spot area; A temperature distribution map is generated based on the heat source power distribution data to obtain a target chip temperature distribution map; wherein the target chip temperature distribution map includes the temperature value of each computing unit and storage unit in the target chip, and is visually presented in the form of a color heat map.

[0035] Specifically, the process of collecting temperature data of the target chip through the temperature sensor network to obtain the temperature distribution map of the target chip is a systematic and multi-step technical implementation. First, in order to ensure the accuracy and comprehensiveness of the temperature data, it is necessary to collect real-time temperature data of the target chip through the preset temperature sensor network, so as to obtain the temperature sampling data set of the target chip. In a high-performance server environment, the storage and computing integrated chip may bear multiple concurrent requests and complex data processing tasks at the same time, which makes the working status of different areas inside it very different and the temperature change is also very complex. Therefore, each sensor in the temperature sensor network not only records the temperature value at its respective position, but also comes with accurate timestamp and location coordinate information. For example, in a typical high-performance server application scenario, these sensors are distributed in key positions such as computing units, storage units, and data paths between the two to ensure that the temperature changes of the entire chip surface and each point inside can be captured. Next, due to the inevitable existence of various interference factors in the actual environment, the collected temperature data may contain noise. In order to solve this problem, the system will perform noise filtering and data fusion processing on the temperature sampling data set, the purpose is to remove outliers and random fluctuations, and obtain a smoother and more stable denoised temperature data sequence. This process is crucial to improving the reliability of subsequent analysis results. For example, in high-performance servers, when some sensors are affected by external electromagnetic interference or short-term ambient temperature fluctuations, inaccurate readings may be generated. Advanced filtering algorithms and data fusion technology can effectively eliminate these interferences to ensure that the final temperature data truly reflects the actual working status of the chip. Based on the above denoised temperature data sequence, the next step is to use the finite element analysis method to reconstruct the temperature field and generate the three-dimensional temperature field distribution of the target chip. This method can accurately simulate the heat conduction process inside the chip and provide detailed information including the temperature value of each point and the temperature gradient. In the high-performance server environment, the three-dimensional temperature field distribution of the storage and computing integrated chip provides important clues for understanding how heat is transferred and accumulated inside the chip. For example, when a computing unit is under high load for a long time, the temperature of the area will gradually rise and diffuse to the surrounding area through heat conduction. Through finite element analysis, we can clearly see the temperature propagation path and its influence range, which is very helpful for formulating effective heat dissipation strategies. On this basis, the system further identifies the hotspot area of ​​the three-dimensional temperature field distribution and obtains the hotspot area distribution map of the target chip. This step aims to highlight specific areas with abnormally high temperatures, so-called "hot spots", and describe in detail the location, temperature peak, and coverage area of ​​the hot spots. In high-performance server applications, identifying these hot spots helps to discover potential risk points in a timely manner and take necessary preventive measures.For example, if a computing unit becomes a hotspot due to continuous high-intensity computing, performance degradation or even hardware damage caused by overheating can be avoided by adjusting task allocation or optimizing the cooling system. In order to better understand the root cause of hotspot formation, the system uses the reverse heat transfer analysis method to estimate the heat source power of the hotspot area distribution map and obtain the heat source power distribution data of the target chip. This analysis can not only reveal which operations or design factors lead to local high temperatures, but also quantify the power value and density of each hotspot area. In high-performance server scenarios, by estimating the heat source power, engineers can better evaluate whether the current workload settings are reasonable and whether there is unnecessary power consumption waste. For example, if the access frequency of a storage unit is too high, causing it to become a hotspot, then it is possible to consider optimizing the data access mode and reducing unnecessary read and write operations, thereby reducing power consumption and temperature. Finally, based on the heat source power distribution data, the system generates a temperature distribution map and finally obtains the target chip temperature distribution map. This map not only intuitively shows the temperature values ​​of each computing unit and storage unit in the target chip, but also visualizes it in the form of a color heat map, so that users can see at a glance which areas have higher temperatures and which areas are relatively low. In the application of high-performance servers, such temperature distribution maps play an irreplaceable role in monitoring the health status of the system, optimizing power management strategies, and guiding future chip design. For example, by observing the temperature distribution map, operation and maintenance personnel can quickly locate areas where there may be heat dissipation problems, and adjust the server configuration or maintenance plan accordingly to ensure that the system always operates within a safe and reliable temperature range. In summary, through a series of fine processing and analysis of the data collected by the temperature sensor network, we can not only construct a detailed three-dimensional temperature field distribution, but also identify hot spots and conduct in-depth research on their causes. The target chip temperature distribution map finally generated provides a solid scientific basis for achieving a balance between high efficiency and low power consumption, ensuring that the stability and reliability of the system are maximized without affecting normal operations. This method provides a strong guarantee for high-performance servers and other similar application scenarios, enabling complex data centers to effectively control energy consumption and heat dissipation pressure while maintaining high performance.

[0036] In a specific embodiment, the power consumption-temperature correlation analysis of the target chip is performed based on the target chip power consumption distribution map and the target chip temperature distribution map to obtain a power consumption-temperature correlation matrix, including: Perform multi-scale decomposition on the target chip power consumption distribution map and the temperature distribution map through adaptive wavelet transform to obtain a power consumption-temperature feature component set, and perform local singular value decomposition on the power consumption-temperature feature component set to obtain a power consumption-temperature basis vector matrix; wherein the power consumption-temperature basis vector matrix calculates a unit power consumption-temperature mapping matrix, a storage unit power consumption-temperature mapping coefficient, and an on-chip bus power consumption-temperature coupling factor; Based on the Hilbert-Huang transform, the power consumption-temperature basis vector matrix is ​​subjected to intrinsic mode decomposition to obtain a power consumption-temperature intrinsic component sequence, and a bispectral analysis is performed on the power consumption-temperature intrinsic component sequence to obtain a power consumption-temperature cross-spectral feature; wherein the power consumption-temperature cross-spectral feature includes a power consumption-temperature oscillation period, a power consumption-temperature phase difference, and a power consumption-temperature amplitude ratio; The power consumption-temperature cross-spectral characteristics are nonlinearly reconstructed by a preset local projection embedding algorithm to obtain a power consumption-temperature state space trajectory; Performing a time series correlation analysis based on the power consumption-temperature state space trajectory to obtain a power consumption-temperature coupling feature sequence, and performing transfer entropy calculation on the power consumption-temperature coupling feature sequence to obtain a power consumption-temperature causal network; Perform community detection on the power consumption-temperature causal network to obtain a power consumption-temperature coupling subgraph set, and perform spectral clustering analysis on the power consumption-temperature coupling subgraph set to obtain a power consumption-temperature associated region; wherein the power consumption-temperature associated region includes a strong coupling region identifier, a weak coupling region boundary, and a critical coupling region feature; Based on recursive quantization analysis, dynamic feature extraction is performed on the power consumption-temperature association region to obtain a power consumption-temperature time-varying feature set, and tensor decomposition is performed on the power consumption-temperature time-varying feature set to obtain a power consumption-temperature association matrix.

[0037] Specifically, in order to realize the power consumption-temperature correlation analysis of the target chip based on the power consumption distribution map of the target chip and the temperature distribution map of the target chip, and finally obtain the power consumption-temperature correlation matrix, the whole process is a multi-step complex analysis process. First, the system performs multi-scale decomposition on the power consumption distribution map and the temperature distribution map of the target chip through adaptive wavelet transform. This process aims to capture the relationship characteristics between power consumption and temperature from different time scales, so as to obtain a power consumption-temperature feature component set containing multiple levels of information. In the application scenario of high-performance servers, different functional areas (such as computing units, storage units, and on-chip buses) inside the storage and computing integrated chip may show different power consumption and temperature characteristics due to changes in task load. Adaptive wavelet transform can reveal the changing laws of these characteristics at different time scales, so that we can understand the working status of each area more accurately. Next, the system performs local singular value decomposition (SVD) on the obtained power consumption-temperature feature component set to extract the basis vector that best reflects the essential relationship between power consumption and temperature, and form a power consumption-temperature basis vector matrix. This matrix not only contains the power consumption-temperature mapping matrix of the computing unit and the power consumption-temperature mapping coefficient of the storage unit, but also covers the power consumption-temperature coupling factor of the on-chip bus. For example, in a high-performance server environment, when a computing unit generates a lot of power consumption due to intensive tasks, the temperature near it will also rise. Through local SVD, we can quantify this direct connection between power consumption and temperature, laying the foundation for subsequent more in-depth analysis. In addition, for the storage unit, frequent data read and write operations will lead to increased power consumption and temperature rise; for the on-chip bus, changes in data transmission rate and frequency will also affect its power consumption level and thermal conduction efficiency. Then, the intrinsic mode decomposition (EMD) of the power consumption-temperature basis vector matrix is ​​performed based on the Hilbert-Huang transform (HHT). HHT is a method suitable for non-stationary signal processing. It can decompose the complex power consumption-temperature basis vector matrix into a series of physically meaningful intrinsic mode functions (IMFs), namely the so-called power consumption-temperature intrinsic component sequences. These intrinsic component sequences reflect the different oscillation modes between power consumption and temperature that evolve over time. Furthermore, by performing bispectral analysis on the power consumption-temperature intrinsic component sequence, the power consumption-temperature cross-spectral characteristics can be obtained, including the power consumption-temperature oscillation period, the power consumption-temperature phase difference, and the power consumption-temperature amplitude ratio. For example, during the operation of a high-performance server, certain periodic load changes may cause regular power consumption fluctuations in specific computing units or storage units, which will also affect their temperature changes accordingly. Through bispectral analysis, we can discover the periodicity and synchronization information hidden behind the data, which is crucial to understanding the relationship between power consumption and temperature.Subsequently, the preset local projection embedding algorithm is used to perform nonlinear dynamic reconstruction on the power consumption-temperature mutual spectrum characteristics to construct the power consumption-temperature state space trajectory. This method can help us intuitively see the evolution path of power consumption and temperature in the high-dimensional state space and reveal the complex nonlinear interaction between the two. In a high-performance server environment, when multiple computing units work together, the interaction between their power consumption and temperature may form a complex dynamic pattern. Through the state space trajectory, we can track the development process of this dynamic pattern and provide a basis for further analysis. Based on the above power consumption-temperature state space trajectory, the system will perform time series correlation analysis to extract the power consumption-temperature coupling feature sequence. This sequence contains the correlation information between power consumption and temperature over time. Next, the power consumption-temperature causal network can be constructed by transferring entropy calculation. Transfer entropy is a method to measure the direction and intensity of information flow between two random variables. Here it is used to evaluate the causal relationship between power consumption and temperature. For example, in a high-performance server, if the power consumption of a computing unit increases before the temperature of the adjacent area increases, it means that the former may be one of the causes of the latter. By constructing a causal network, we can more clearly understand the causal link between power consumption and temperature. To further analyze the power-temperature causal network, the system performs community detection on the network and divides it into different sets of power-temperature coupling subgraphs. Each subgraph represents a relatively independent power-temperature coupling region. By performing spectral clustering analysis on these subgraph sets, the power-temperature correlation region is finally obtained. These correlation regions include strong coupling region identification, weak coupling region boundary and critical coupling region features. In high-performance server applications, this helps to identify which regions have the most significant mutual influence between power consumption and temperature, which regions have weaker influence, and regions with critical transition points. For example, there may be a strong power-temperature coupling between a computing unit and its adjacent storage unit, while other components far away from it show a weaker degree of coupling. Finally, based on recursive quantization analysis, dynamic feature extraction is performed on the power-temperature correlation region to generate a power-temperature time-varying feature set. This method can capture the trend and pattern of power consumption and temperature changes over time. Then, through tensor decomposition, the power-temperature time-varying feature set can be comprehensively analyzed from a multi-dimensional perspective, and the power-temperature correlation matrix is ​​finally obtained. This matrix comprehensively describes the interaction between power consumption and temperature between various parts of the target chip, and provides an important reference for optimizing design, fault prediction, and performance improvement. For example, in high-performance servers, engineers can use the power consumption-temperature correlation matrix to develop more effective cooling strategies to ensure stable system operation while minimizing energy consumption. In summary, through the above series of steps, we can deeply explore the complex relationship between power consumption and temperature in the target chip, not only revealing their correlation in static structure, but also discovering their interaction in dynamic behavior.This process provides strong scientific support for power management, thermal design optimization and reliability enhancement in high-performance servers and other similar application scenarios. In this way, we can maximize the energy efficiency of the system without affecting normal operations, ensuring that it can serve complex computing tasks stably and reliably in the long term.

[0038] In a specific embodiment, the multi-objective optimization algorithm is used to perform power management planning on the target chip based on the power consumption-temperature association matrix to obtain a dynamic power consumption management strategy, including: Performing singular value decomposition on the power consumption-temperature association matrix to obtain a power consumption-temperature feature vector set, and performing principal component analysis on the power consumption-temperature feature vector set to obtain power consumption-temperature principal component features; The power consumption-temperature principal component characteristics are optimized by a multi-objective genetic algorithm to obtain a power consumption-temperature Pareto optimal solution set; The power consumption-temperature objective function of the target chip is constructed by using the power consumption-temperature Pareto optimal solution set to obtain a multi-objective optimization function, and the multi-objective optimization function is solved by the Lagrange multiplier method to obtain a Lagrange multiplier vector; wherein the Lagrange multiplier vector includes a power consumption weight coefficient, a temperature weight coefficient, and a performance weight coefficient; Dynamically allocate power consumption budget to the target chip based on the Lagrange multiplier vector to obtain a power consumption budget allocation scheme, and optimize the power consumption budget allocation scheme based on game theory to obtain a Nash equilibrium point; wherein the Nash equilibrium point includes a computing unit power consumption budget, a storage unit power consumption budget, and a communication unit power consumption budget; Power consumption management planning is performed on the target chip based on the Nash equilibrium point to obtain a dynamic power consumption management strategy.

[0039] Specifically, in order to implement power management planning for the target chip based on the power consumption-temperature association matrix and finally obtain a dynamic power consumption management strategy, the whole process is a complex process that combines multiple advanced mathematical and optimization techniques. First, the system needs to perform singular value decomposition (SVD) on the power consumption-temperature association matrix. This process aims to extract the most essential relationship characteristics between power consumption and temperature, thereby obtaining a power consumption-temperature feature vector set. In the application scenario of high-performance servers, this decomposition can help us identify which factors have the greatest impact on power consumption and temperature, and which regions have the most significant interactions. For example, in a typical storage-computing integrated chip, the working status of different functional modules such as computing units, storage units, and on-chip buses will directly affect its power consumption and heat generation. Through singular value decomposition, we can reveal the characteristic changes at these different levels, so that we can more accurately capture the power consumption and temperature patterns in each region. Next, the obtained power consumption-temperature feature vector set is subjected to principal component analysis (PCA) to obtain the power consumption-temperature principal component features. Principal component analysis is a dimensionality reduction technique that can reduce data dimensions while retaining the most information, allowing us to focus on the key factors that have the greatest impact on power consumption and temperature. Taking a high-performance server as an example, when a computing unit generates a lot of power consumption due to performing intensive tasks, the temperature near it will also rise. Through principal component analysis, we can quantify the direct connection between power consumption and temperature, and extract the most important eigenvectors from it, providing a basis for subsequent deeper optimization. Then, the system uses a multi-objective genetic algorithm (MOGA) to optimize the power consumption-temperature principal component characteristics and obtain the power consumption-temperature Pareto optimal solution set. The multi-objective genetic algorithm is a search method that simulates natural selection and genetic mechanisms. It can simultaneously consider multiple conflicting goals, such as minimizing power consumption, controlling temperature, and maximizing performance, to find a set of optimal solutions. In a high-performance server environment, this means that we need to reduce power consumption as much as possible and maintain a safe operating temperature while ensuring that system performance is not affected. Through the multi-objective genetic algorithm, a series of possible solutions can be explored, each of which finds the best balance between power consumption, temperature, and performance to form a Pareto optimal solution set. Based on the above power consumption-temperature Pareto optimal solution set, the system further constructs the power consumption-temperature objective function, that is, the multi-objective optimization function. This function comprehensively considers multiple target variables such as power consumption, temperature, and performance, and reflects their importance by assigning different weight coefficients to these variables. Specifically, the Lagrange multiplier method is used to solve the multi-objective optimization function, and finally obtains the Lagrange multiplier vector. This vector includes the power consumption weight coefficient, the temperature weight coefficient, and the performance weight coefficient, which determine the importance of each target in the optimization process.For example, during the operation of a high-performance server, if the current task has high performance requirements, the performance weight coefficient can be appropriately increased; when the load is light, more attention can be paid to power consumption and temperature control, and other weight coefficients can be adjusted accordingly. With the Lagrange multiplier vector, the system dynamically allocates power budgets to the target chip according to its guidance and generates a power budget allocation plan. This plan specifies the power budgets of various parts such as computing units, storage units, and communication units in detail. In order to ensure the effective use of resources, it is also necessary to optimize the resource competition strategy based on game theory for the power budget allocation plan to find the Nash equilibrium point. The Nash equilibrium point refers to a multi-participant system in which each participant's strategy is the best response to the strategies of other participants, and no party is willing to unilaterally change its strategy. In high-performance server applications, this means finding a resource allocation method that allows all computing units, storage units, and communication units to work efficiently within their power budgets without causing performance degradation or overheating problems due to resource competition. For example, the Nash equilibrium point optimized by game theory will instruct certain computing units to take on more tasks within a specific time window, while allowing other areas to enter a low-power standby state, thereby minimizing overall energy consumption. Finally, based on the Nash equilibrium point, the system formulates a detailed power management plan and forms a dynamic power management strategy. This strategy not only takes into account the needs of the current task, but also takes into account the stability and reliability in long-term operation. For example, in a high-performance server, when it is detected that the temperature of some areas rises too fast due to high-intensity computing, the dynamic power management strategy may indicate to appropriately reduce the operating frequency of the area, while fine-tuning the power supply voltage to ensure that the performance is not greatly affected. At the same time, for relatively idle or low-load areas, their operating frequency can be appropriately increased to speed up the completion of the remaining tasks, or the voltage can be reduced to save energy. In summary, through a series of steps such as singular value decomposition, principal component analysis, and multi-objective genetic algorithm optimization of the power consumption-temperature association matrix, we can not only reveal the complex relationship between the power consumption and temperature inside the target chip, but also formulate a scientific and reasonable dynamic power management strategy on this basis. This method ensures that the energy efficiency ratio of the system is maximized without affecting normal computing, ensuring that it can serve complex computing tasks stably and reliably in the long term. In this way, we can achieve a perfect balance between high efficiency and low power consumption in high-performance servers and other similar application scenarios, providing a strong guarantee for complex data centers. For example: suppose that in a high-performance server cluster, at a certain moment, multiple virtual machines are executing complex computing tasks, causing the power consumption of some computing units to increase sharply and the temperature to rise accordingly. At this time, through the above power consumption-temperature correlation analysis and optimization process, the system can quickly identify which computing units are in a high-load state and adjust the operating frequency and supply voltage of these units according to the pre-set power consumption-temperature Pareto optimal solution set.At the same time, the optimization of resource competition strategies based on game theory can help determine the optimal power budget allocation for each computing unit, storage unit, and communication unit, ensuring the effective use of resources without causing overheating or other performance issues. The resulting dynamic power management strategy will ensure that the entire server cluster maintains a low power consumption level and stable temperature distribution while meeting high performance requirements, thereby extending the hardware life and improving the overall efficiency of the system.

[0040] In a specific embodiment, the voltage and frequency of the target chip are adjusted based on the dynamic power management strategy to obtain voltage and frequency control parameters, including: Performing cluster analysis on the power consumption characteristics of the target chip through a dynamic power consumption management strategy to obtain a power consumption cluster set, and performing principal component analysis on the power consumption cluster set to obtain a power consumption feature vector; wherein the power consumption feature vector includes chip power consumption mean, power consumption variance, and power consumption peak feature parameters; Performing voltage regulation analysis on the target chip based on the power consumption characteristic vector to obtain a voltage regulation solution; Performing frequency configuration analysis on the target chip through the voltage regulation scheme to obtain a frequency configuration scheme; Based on the frequency control parameters, the target chip is subjected to power consumption allocation analysis to obtain a power consumption allocation scheme, and the power consumption allocation scheme is optimized by an ant colony algorithm to obtain power consumption allocation parameters; wherein the power consumption allocation parameters include a power consumption allocation ratio, a power consumption allocation threshold, and a power consumption allocation delay parameter; The voltage and frequency of the target chip are adjusted according to the power consumption allocation parameter to obtain a voltage and frequency control signal; The voltage and frequency of the target chip are adjusted based on the voltage and frequency control signal to obtain voltage and frequency control parameters.

[0041] Specifically, in order to achieve voltage and frequency adjustment of the target chip based on the dynamic power management strategy and finally obtain the voltage and frequency control parameters, the whole process involves a series of complex data analysis and optimization steps. First, the system needs to cluster the power consumption characteristics of the target chip through the dynamic power management strategy to identify the regions or working modes with similar power consumption behaviors and form a set of power consumption clusters. This process is particularly important in high-performance server environments because different computing tasks may cause significant differences in power consumption of various parts inside the target chip. For example, when processing large-scale concurrent requests, some computing units may be under high load while other parts are relatively idle. By clustering these power consumption characteristics, we can divide the chip into several power consumption clusters, each of which represents a group of regions or operating modes with similar power consumption characteristics. Next, the principal component analysis (PCA) is performed on the obtained power consumption cluster set to extract the key feature vectors that best reflect the power consumption changes. These power consumption feature vectors contain important parameters such as chip power consumption mean, power consumption variance, and power consumption peak, which can help us understand the differences between various power consumption clusters and their internal connections more deeply. For example, in a typical high-performance server application scenario, the average power consumption of a computing unit is high and fluctuates greatly, which may mean that the unit undertakes more intensive computing tasks; while the peak power consumption of another storage unit is low but relatively stable, indicating that it is mainly responsible for data reading and writing operations. Through principal component analysis, we can quantify these characteristics and provide a scientific basis for subsequent voltage regulation. Based on the above power consumption feature vector, the system further performs voltage regulation analysis on the target chip to formulate a specific voltage regulation scheme. This scheme aims to reasonably adjust the power supply voltage according to the current task requirements and power consumption characteristics to achieve the purpose of both ensuring performance and reducing energy consumption. For example, during the operation of a high-performance server, if it is detected that the power consumption of a computing unit continues to increase, then sufficient processing power can be ensured by appropriately increasing its power supply voltage; on the contrary, for those areas with low power consumption or in an idle state, the voltage can be reduced to save power. This dynamic adjustment not only helps to optimize the instantaneous power consumption performance, but also prolongs the hardware life and reduces the heat dissipation pressure. After the voltage regulation scheme is obtained, the system continues to perform frequency configuration analysis on the target chip through the voltage regulation scheme to generate a frequency configuration scheme. The frequency configuration scheme takes into account the working characteristics and task load of different computing units, and determines the optimal frequency at which each unit should run. In a high-performance server environment, this means flexibly adjusting the working frequency of each computing unit according to the needs of different computing tasks. For example, when certain tasks require a quick response, the relevant computing unit may be set to a higher frequency to speed up processing; while during periods with fewer tasks or non-critical periods, the frequency can be appropriately reduced to save energy.In addition, frequency configuration needs to be coordinated with voltage regulation to ensure a good match between the two and avoid power consumption surge or overheating caused by high frequency. Based on the frequency control parameters, the system performs power distribution analysis on the target chip and obtains a power distribution plan. This plan specifies parameters such as the power distribution ratio, threshold and delay between the computing unit, storage unit and other functional modules. In order to ensure the effective use of resources and achieve the best power management effect, the system also uses the ant colony algorithm to optimize the power distribution plan and obtain more refined power distribution parameters. The ant colony algorithm is a heuristic search method that simulates the foraging behavior of ants in nature. It can find the global optimal solution in a complex multi-dimensional space. In high-performance server applications, the ant colony algorithm can help us identify which areas have the most reasonable power distribution and where there is room for optimization. For example, the power distribution plan optimized by the ant colony algorithm may instruct some computing units to take on more tasks within a specific time window, while allowing other areas to enter a low-power standby state, thereby minimizing overall energy consumption. Finally, based on the optimized power distribution parameters, the system adjusts the voltage and frequency of the target chip, generates a voltage and frequency control signal, and adjusts the actual voltage and frequency control parameters accordingly. This process ensures that all adjustment measures can be accurately applied to the target chip, so that it can meet performance requirements while minimizing power consumption and maintaining a safe operating temperature. For example, in a high-performance server, when it is detected that the temperature of certain areas rises too fast due to high-intensity computing, the dynamic power management strategy will instruct to appropriately reduce the operating frequency of the area, while fine-tuning the supply voltage to ensure that the performance is not greatly affected. At the same time, for relatively idle or low-load areas, their operating frequency can be appropriately increased to speed up the completion of the remaining tasks, or the voltage can be reduced to save energy. In summary, through a series of steps such as cluster analysis, principal component analysis, voltage regulation analysis, and frequency configuration analysis of the power consumption characteristics of the target chip, we can not only reveal the complex relationship between power consumption and frequency inside the chip, but also formulate a scientific and reasonable voltage and frequency adjustment plan on this basis. This method ensures that the energy efficiency ratio of the system is maximized without affecting normal computing, ensuring that it can serve complex computing tasks stably and reliably for a long time. In this way, we can achieve a perfect balance between high efficiency and low power consumption in high-performance servers and other similar application scenarios, providing a strong guarantee for complex data centers. For example: suppose that in a high-performance server cluster, at a certain moment, multiple virtual machines are executing complex computing tasks, causing the power consumption of some computing units to increase sharply and the temperature to rise accordingly. At this time, through the above power consumption feature analysis and optimization process, the system can quickly identify which computing units are in a high-load state and adjust the operating frequency and supply voltage of these units according to the pre-set power consumption feature vector.At the same time, the power consumption allocation scheme optimized by the ant colony algorithm can help determine the optimal power consumption budget allocation for each computing unit, storage unit, and communication unit, ensuring the effective use of resources without causing overheating or other performance problems. The resulting voltage and frequency control parameters will ensure that the entire server cluster maintains a low power consumption level and stable temperature distribution while meeting high performance requirements, thereby extending the hardware life and improving the overall efficiency of the system.

[0042] In a specific embodiment, the power consumption management of the target chip is performed based on the voltage and frequency control parameters by using the adaptive clock gating technology to obtain a chip power consumption management solution, including: Extracting the timing characteristics of the voltage frequency control parameters through the adaptive clock gating technology to obtain a clock adjustment scheme, and performing Fourier transform analysis on the clock adjustment scheme to obtain clock spectrum characteristics; wherein the clock spectrum characteristics include clock frequency components, clock phase offsets, and clock amplitude adjustment characteristic parameters; Based on the clock spectrum characteristics, the target chip is subjected to power consumption prediction analysis to obtain a power consumption prediction sequence; wherein the power consumption prediction sequence includes a power consumption timing mean, a power consumption fluctuation variance, and a power consumption peak characteristic parameter; Performing power consumption allocation planning on the target chip through the power consumption prediction sequence to obtain a power consumption allocation strategy, and performing parameter analysis on the power consumption allocation strategy to obtain a power consumption allocation control parameter; Dynamically adjusting the voltage and frequency of the target chip based on the power consumption allocation control parameter to obtain a voltage and frequency configuration scheme, and converting the voltage and frequency configuration scheme into an instruction to obtain a voltage and frequency control instruction; Power consumption management is performed on the target chip based on the voltage and frequency control instruction to obtain a chip power consumption management solution.

[0043] Specifically, in order to achieve power consumption management of the target chip through adaptive clock gating technology and finally obtain a chip power consumption management solution, the whole process is a complex process that combines multiple advanced technologies and algorithms. First, the system needs to use adaptive clock gating technology to extract the timing characteristics of the voltage and frequency control parameters to develop a clock adjustment plan. This process aims to capture the changing rules of the clock signal of the target chip under different working conditions, including its frequency, phase, amplitude and other characteristics. For example, in a high-performance server environment, when the storage and computing integrated chip processes a large number of concurrent requests, some computing units may be in a high-load state, while other parts are relatively idle. By extracting the timing characteristics of the voltage and frequency control parameters of these areas, we can identify which computing units have more frequent working modes and which are more stable. Based on this information, the system can generate a specific clock adjustment plan to ensure that each computing unit is activated only when it is really needed, reducing unnecessary static power consumption. Next, in order to have a deeper understanding of the frequency domain characteristics of the clock signal, the system will perform Fourier transform analysis on the formulated clock adjustment plan to obtain the clock spectrum characteristics. This step can reveal the frequency components, phase offsets, and amplitude adjustment characteristic parameters in the clock signal, helping us better understand the relationship between clock behavior and power consumption. For example, in a high-performance server, if a computing unit frequently switches working states, its clock signal may show significant harmonic components or phase fluctuations. Through Fourier transform analysis, we can quantify these characteristics and provide an important basis for subsequent power consumption prediction. In addition, this frequency domain analysis can also help identify potential unstable factors, such as clock jitter or noise interference, and take measures to eliminate them in advance. Based on the above clock spectrum characteristics, the system further performs power consumption prediction analysis on the target chip to obtain a power consumption prediction sequence. This sequence contains characteristic parameters such as the power consumption time series mean, power consumption fluctuation variance, and power consumption peak, which reflect the power consumption change trend of the target chip in the future. In high-performance server application scenarios, this prediction analysis is crucial for optimizing resource allocation and preventing overheating. For example, if a computing unit is about to enter a high-load state based on power consumption prediction, the system can appropriately adjust its power supply voltage and operating frequency before the task starts to ensure that performance is not affected while minimizing power consumption. At the same time, for those areas that are expected to remain in a low load or idle state, they can enter a low-power standby mode in advance to save power. With the power consumption prediction sequence, the system will plan its power consumption allocation and formulate a specific power consumption allocation strategy. This strategy specifies in detail the power consumption allocation ratio, threshold and delay parameters between each computing unit, storage unit and other functional modules. In order to ensure the effective use of resources and achieve the best power consumption management effect, the system also needs to analyze the parameters of the power consumption allocation strategy to obtain more refined power consumption allocation control parameters.For example, in a high-performance server, the power allocation control parameters may instruct some computing units to take on more tasks within a specific time window, while putting other areas into a low-power standby state, thereby minimizing overall energy consumption. In addition, these control parameters may also include some forward-looking indicators, such as predicting future load trends and corresponding power consumption changes, making preparations in advance, and avoiding unnecessary high-power consumption periods. Based on the power allocation control parameters, the system dynamically adjusts the voltage and frequency of the target chip and generates a voltage and frequency configuration scheme. This scheme comprehensively considers the current task requirements, power consumption prediction results, and power allocation strategies to determine the optimal operating voltage and frequency for each computing unit. In order to ensure that all adjustment measures can be accurately applied to the target chip, the system also needs to convert the voltage and frequency configuration scheme into instructions to obtain specific voltage and frequency control instructions. These instructions will directly guide the operation at the hardware level to ensure that each computing unit can operate under the most appropriate conditions. For example, in a high-performance server, when it is detected that the temperature of some areas rises too fast due to high-intensity computing, the dynamic power management strategy will instruct to appropriately reduce the operating frequency of the area, while fine-tuning the supply voltage to ensure that performance is not greatly affected. At the same time, for relatively idle or low-load areas, their operating frequency can be appropriately increased to speed up the completion of remaining tasks, or the voltage can be reduced to save energy. Finally, based on the voltage and frequency control instructions, the system manages the power consumption of the target chip to form a complete chip power consumption management solution. This solution not only covers the entire process from clock signal adjustment to voltage and frequency dynamic adjustment, but also ensures that all operations are performed without affecting normal operations, thereby maximizing the energy efficiency of the system. For example, in high-performance servers, this refined power consumption management can not only effectively reduce the overall energy consumption, but also significantly improve the reliability and stability of the system, extend the hardware life, and reduce the heat dissipation pressure. In summary, through a series of steps such as adaptive clock gating technology, timing feature extraction, and Fourier transform analysis, we can not only reveal the complex relationship between the power consumption and frequency of the target chip, but also formulate a scientific and reasonable power consumption management solution on this basis. This method ensures the perfect balance between high efficiency and low power consumption in high-performance servers and other similar application scenarios, and provides a strong guarantee for complex data centers. For example: Suppose that in a high-performance server cluster, multiple virtual machines are performing complex computing tasks at a certain moment, resulting in a sharp increase in the power consumption of some computing units and a rise in temperature. At this time, through the above-mentioned clock gating technology and frequency domain analysis, the system can quickly identify which computing units are in a high-load state, and adjust the clock signal frequency and phase of these units according to the pre-set clock spectrum characteristics. At the same time, based on the results of power consumption prediction analysis, the system can plan power consumption allocation strategies in advance to ensure the effective use of resources without causing overheating or other performance problems.The resulting voltage and frequency control instructions will ensure that the entire server cluster maintains a low power consumption level and a stable temperature distribution while meeting high performance requirements, thereby extending the hardware life and improving the overall efficiency of the system. For example, for those computing units that are expected to continue to work at high loads, the system may maintain a higher operating frequency and supply voltage; while for areas that are about to enter an idle state, the frequency and voltage can be quickly reduced to enter a low power consumption mode to save energy.

[0044] The above describes the dynamic power consumption management method of the storage and computing integrated chip in the embodiment of the present invention. The following describes the dynamic power consumption management device of the storage and computing integrated chip in the embodiment of the present invention. Figure 2 , an embodiment of a dynamic power consumption management device for a storage-computing integrated chip in an embodiment of the present invention includes: The first acquisition module 21 is used to collect real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip; wherein the storage and computing integrated chip is used as the target chip; A second acquisition module 22 is used to collect temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip; An analysis module 23 is used to perform a power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution diagram and the target chip temperature distribution diagram to obtain a power consumption-temperature correlation matrix; A generating module 24 is used to perform power management planning on the target chip based on the power consumption-temperature association matrix through a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy; An adjustment module 25, configured to adjust the voltage and frequency of the target chip based on the dynamic power management strategy to obtain voltage and frequency control parameters; The management module 26 is used to perform power consumption management on the target chip based on the voltage and frequency control parameters by using an adaptive clock gating technology to obtain a chip power consumption management solution.

[0045] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, which will not be repeated here.

[0046] Reference Figure 3 The present invention also provides a computer device in an embodiment, wherein the internal structure of the computer device can be as follows: Figure 3As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0047] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0048] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0049] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0050] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0051] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A dynamic power consumption management method for a storage and computing integrated chip, characterized in that: The following steps are involved: The power consumption data of the target chip is collected in real time through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip; wherein the storage and computing integrated chip is used as the target chip; Collecting temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip; Performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution map and the target chip temperature distribution map to obtain a power consumption-temperature correlation matrix; By using a multi-objective optimization algorithm, power consumption management planning is performed on the target chip based on the power consumption-temperature association matrix to obtain a dynamic power consumption management strategy; Based on the dynamic power management strategy, the voltage and frequency of the target chip are adjusted to obtain voltage and frequency control parameters; The power consumption of the target chip is managed based on the voltage and frequency control parameters through the adaptive clock gating technology to obtain a chip power consumption management solution.

2. The method for dynamic power consumption management of a storage and computing integrated chip according to claim 1, characterized in that: The real-time power consumption data of the target chip is collected by a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip, including: The power consumption of the target chip is scanned and collected through a preset on-chip sensor array to obtain a power consumption feature set of the target chip; The target chip power consumption characteristic set is analyzed in the time domain by a preset piecewise linear interpolation algorithm to obtain power consumption timing characteristic data; wherein the power consumption timing characteristic data includes power consumption fluctuation period, power consumption peak moment and power consumption valley interval; Performing instantaneous frequency analysis on the power consumption timing characteristic data to obtain a power consumption spectrum distribution diagram; wherein the power consumption spectrum distribution diagram includes main frequency component characteristics, harmonic component characteristics, and mixed frequency component characteristics; Based on the Wigner-Ville distribution algorithm, a time-frequency joint analysis is performed on the power consumption spectrum distribution diagram to obtain the power consumption time-frequency characteristics; wherein the power consumption time-frequency characteristics include the power consumption frequency migration trajectory, the power consumption energy concentration area, and the power consumption transient mutation point; Through the conditional entropy estimation algorithm, the target chip is spatially mapped based on the power consumption time-frequency characteristics to obtain a target chip power consumption distribution map; wherein the target chip power consumption distribution map includes a high power consumption area location map, power consumption density contour lines, and a power consumption change trend map.

3. The dynamic power consumption management method of the storage and computing integrated chip according to claim 1, characterized in that: The step of collecting temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip includes: Real-time temperature data collection is performed on the target chip through a preset temperature sensor network to obtain a temperature sampling data set of the target chip; wherein the temperature sampling data set includes a temperature value, a timestamp, and a position coordinate of each sensor in the temperature sensor network; Performing noise filtering and data fusion on the temperature sampling data set to obtain a denoised temperature data sequence; Based on the finite element analysis method, the temperature field is reconstructed based on the denoised temperature data sequence to obtain a three-dimensional temperature field distribution of the target chip; wherein the three-dimensional temperature field distribution includes the temperature value of each point inside the target chip and the temperature gradient information; Performing hot spot identification on the three-dimensional temperature field distribution to obtain a hot spot distribution map of the target chip; wherein the hot spot distribution map includes a hot spot position, a hot spot temperature peak, and a hot spot area; The heat source power is estimated by using a reverse heat transfer analysis method on the hot spot area distribution map of the target chip to obtain the heat source power distribution data of the target chip; wherein the heat source power distribution data includes the power value and power density of each hot spot area; A temperature distribution map is generated based on the heat source power distribution data to obtain a target chip temperature distribution map; wherein the target chip temperature distribution map includes the temperature value of each computing unit and storage unit in the target chip, and is visually presented in the form of a color heat map.

4. The method for dynamic power consumption management of a storage and computing integrated chip according to claim 1, characterized in that: The performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution map and the target chip temperature distribution map to obtain a power consumption-temperature correlation matrix includes: Perform multi-scale decomposition on the target chip power consumption distribution map and the temperature distribution map through adaptive wavelet transform to obtain a power consumption-temperature feature component set, and perform local singular value decomposition on the power consumption-temperature feature component set to obtain a power consumption-temperature basis vector matrix; wherein the power consumption-temperature basis vector matrix includes a computing unit power consumption-temperature mapping matrix, a storage unit power consumption-temperature mapping coefficient, and an on-chip bus power consumption-temperature coupling factor; Based on the Hilbert-Huang transform, the power consumption-temperature basis vector matrix is ​​subjected to intrinsic mode decomposition to obtain a power consumption-temperature intrinsic component sequence, and a bispectral analysis is performed on the power consumption-temperature intrinsic component sequence to obtain a power consumption-temperature cross-spectral feature; wherein the power consumption-temperature cross-spectral feature includes a power consumption-temperature oscillation period, a power consumption-temperature phase difference, and a power consumption-temperature amplitude ratio; The power consumption-temperature cross-spectral characteristics are nonlinearly reconstructed by a preset local projection embedding algorithm to obtain a power consumption-temperature state space trajectory; Performing a time series correlation analysis based on the power consumption-temperature state space trajectory to obtain a power consumption-temperature coupling feature sequence, and performing transfer entropy calculation on the power consumption-temperature coupling feature sequence to obtain a power consumption-temperature causal network; Perform community detection on the power consumption-temperature causal network to obtain a power consumption-temperature coupling subgraph set, and perform spectral clustering analysis on the power consumption-temperature coupling subgraph set to obtain a power consumption-temperature associated region; wherein the power consumption-temperature associated region includes a strong coupling region identifier, a weak coupling region boundary, and a critical coupling region feature; Based on recursive quantization analysis, dynamic feature extraction is performed on the power consumption-temperature association region to obtain a power consumption-temperature time-varying feature set, and tensor decomposition is performed on the power consumption-temperature time-varying feature set to obtain a power consumption-temperature association matrix.

5. The method for dynamic power consumption management of a storage and computing integrated chip according to claim 1, characterized in that: The method of performing power management planning on the target chip based on the power consumption-temperature association matrix by using a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy includes: Performing singular value decomposition on the power consumption-temperature association matrix to obtain a power consumption-temperature feature vector set, and performing principal component analysis on the power consumption-temperature feature vector set to obtain power consumption-temperature principal component features; The power consumption-temperature principal component characteristics are optimized by a multi-objective genetic algorithm to obtain a power consumption-temperature Pareto optimal solution set; The power consumption-temperature objective function of the target chip is constructed by using the power consumption-temperature Pareto optimal solution set to obtain a multi-objective optimization function, and the multi-objective optimization function is solved by the Lagrange multiplier method to obtain a Lagrange multiplier vector; wherein the Lagrange multiplier vector includes a power consumption weight coefficient, a temperature weight coefficient, and a performance weight coefficient; Dynamically allocate power consumption budget to the target chip based on the Lagrange multiplier vector to obtain a power consumption budget allocation scheme, and optimize the power consumption budget allocation scheme based on game theory to obtain a Nash equilibrium point; wherein the Nash equilibrium point includes a computing unit power consumption budget, a storage unit power consumption budget, and a communication unit power consumption budget; Power consumption management planning is performed on the target chip based on the Nash equilibrium point to obtain a dynamic power consumption management strategy.

6. The method for dynamic power consumption management of a storage and computing integrated chip according to claim 1, characterized in that: The step of adjusting the voltage and frequency of the target chip based on the dynamic power management strategy to obtain voltage and frequency control parameters includes: Performing cluster analysis on the power consumption characteristics of the target chip through a dynamic power consumption management strategy to obtain a power consumption cluster set, and performing principal component analysis on the power consumption cluster set to obtain a power consumption feature vector; wherein the power consumption feature vector includes chip power consumption mean, power consumption variance, and power consumption peak feature parameters; Performing voltage regulation analysis on the target chip based on the power consumption characteristic vector to obtain a voltage regulation solution; Performing frequency configuration analysis on the target chip through the voltage regulation scheme to obtain a frequency configuration scheme; Based on the frequency control parameters, the target chip is subjected to power consumption allocation analysis to obtain a power consumption allocation scheme, and the power consumption allocation scheme is optimized by an ant colony algorithm to obtain power consumption allocation parameters; wherein the power consumption allocation parameters include a power consumption allocation ratio, a power consumption allocation threshold, and a power consumption allocation delay parameter; The voltage and frequency of the target chip are adjusted according to the power consumption allocation parameter to obtain a voltage and frequency control signal; The voltage and frequency of the target chip are adjusted based on the voltage and frequency control signal to obtain voltage and frequency control parameters.

7. The method for dynamic power consumption management of a storage and computing integrated chip according to claim 1, characterized in that: The method of performing power consumption management on the target chip based on the voltage and frequency control parameters by using the adaptive clock gating technology to obtain a chip power consumption management solution includes: Extracting the timing characteristics of the voltage frequency control parameters through the adaptive clock gating technology to obtain a clock adjustment scheme, and performing Fourier transform analysis on the clock adjustment scheme to obtain clock spectrum characteristics; wherein the clock spectrum characteristics include clock frequency components, clock phase offsets, and clock amplitude adjustment characteristic parameters; Based on the clock spectrum characteristics, the target chip is subjected to power consumption prediction analysis to obtain a power consumption prediction sequence; wherein the power consumption prediction sequence includes a power consumption timing mean, a power consumption fluctuation variance, and a power consumption peak characteristic parameter; Performing power consumption allocation planning on the target chip through the power consumption prediction sequence to obtain a power consumption allocation strategy, and performing parameter analysis on the power consumption allocation strategy to obtain a power consumption allocation control parameter; Dynamically adjusting the voltage and frequency of the target chip based on the power consumption allocation control parameter to obtain a voltage and frequency configuration scheme, and converting the voltage and frequency configuration scheme into an instruction to obtain a voltage and frequency control instruction; Power consumption management is performed on the target chip based on the voltage and frequency control instruction to obtain a chip power consumption management solution.

8. A dynamic power consumption management device for a storage and computing integrated chip, characterized in that: include: The first acquisition module is used to collect real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip; wherein the storage and computing integrated chip is used as the target chip; A second acquisition module is used to collect temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip; An analysis module, configured to perform a power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution diagram and the target chip temperature distribution diagram, and obtain a power consumption-temperature correlation matrix; A generation module, used to perform power management planning on the target chip based on the power consumption-temperature association matrix through a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy; An adjustment module, used to adjust the voltage and frequency of the target chip based on the dynamic power management strategy to obtain voltage and frequency control parameters; The management module is used to perform power consumption management on the target chip based on the voltage and frequency control parameters through an adaptive clock gating technology to obtain a chip power consumption management solution.

9. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images