Separating logical-to-physical mappings

Abstract

The invention relates to separating logical-to-physical mappings. A memory system may separate an L2P map based on one or more characteristics of data associated with the L2P map. The memory system may determine whether a logical address included in a write command is associated with a first characteristic, a second characteristic, or some other characteristic. The memory system may write the L2P map to a first memory cell block, a second memory cell block, or some other memory cell block based on a determined characteristic of the L2P map. The blocks of memory cells to which the L2P mapping is written may include other mappings having data with the same (or similar) characteristics.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 776,215 filed by Tiwari et al. on July 17, 2024, entitled “SEGREGATING LOGICAL TO PHYSICAL MAPPINGS,” and U.S. patent application No. 63 / 543,205 filed by Tiwari et al. on October 9, 2023, entitled “SEGREGATING LOGICAL TO PHYSICAL MAPPINGS,” each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference.

[0003] The technical field relates to one or more systems for memory, including separation of logical to physical mapping. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long time, even in the absence of external power. Memory cells configured in a volatile configuration lose their stored state when disconnected from the external power source. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a memory system including volatile memory and nonvolatile memory; and a controller associated with a memory device, wherein the controller is configured to cause the apparatus to: receive at the memory system a write command including data and a logical address corresponding to a physical address associated with the memory system; determine, based at least in part on receiving the write command, whether the logical address is associated with a first characteristic, wherein the first characteristic is associated with a number of access operations performed on the logical address satisfying a threshold; and write a mapping between the logical address and the corresponding physical address to a first memory cell block of the memory system based at least in part on determining that the logical address is associated with the first characteristic.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive at a memory system a write command including data and a logical address corresponding to a physical address associated with the memory system; determine, based at least in part on receiving the write command, whether the logical address is associated with a first characteristic, wherein the first characteristic is associated with a number of access operations performed on the logical address satisfying a threshold; and write a mapping between the logical address and the corresponding physical address to a first memory cell block of the memory system based at least in part on determining that the logical address is associated with the first characteristic.

[0008] A method is described. The method may include: receiving, at a memory system, a write command including data and a logical address corresponding to a physical address associated with the memory system; determining, based at least in part on receiving the write command, whether the logical address is associated with a first characteristic, wherein the first characteristic is associated with a number of access operations performed on the logical address satisfying a threshold; and writing a mapping between the logical address and the corresponding physical address to a first memory cell block of the memory system based at least in part on determining that the logical address is associated with the first characteristic. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting split logical to physical mapping according to examples disclosed herein is presented.

[0010] Figure 2 An example of a system supporting split logical to physical mapping according to examples disclosed herein is presented.

[0011] Figure 3 An example of a process flow supporting separation logical to physical mapping according to examples disclosed herein is presented.

[0012] Figure 4 A block diagram of a memory system supporting split logical to physical mapping according to examples disclosed herein is shown.

[0013] Figure 5 A flow chart illustrating one or several methods supporting split logical to physical mapping according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0014] Some memory systems may utilize a logical-to-physical (L2P) mapping to define one or more address relationships (e.g., translations) between logical block addresses (LBAs) (e.g., received from a host) and physical block addresses (PBAs) (e.g., of the memory system). Data corresponding to the L2P mapping may be associated with one or more characteristics. For example, the data may be associated with a number of access operations performed within a duration (e.g., a temperature characteristic). A first characteristic (e.g., a first temperature) may correspond to data associated with a relatively high number of access operations (e.g., hot data), and a second characteristic (e.g., a second temperature) may correspond to data associated with a relatively low number of access operations (e.g., cold data).

[0015] However, in some systems, storing a mixture of data associated with the first characteristic and the second characteristic in the same memory block may result in performing additional maintenance operations (e.g., obsolete item collection operations), which may result in reduced system endurance, reduced quality of service (QoS), increased write amplification, increased latency, and other similar effects. Therefore, the memory system may separate (e.g., organize, partition) data associated with the first characteristic and data associated with the second characteristic. However, the memory system may not separate the L2P mapping (e.g., L2P data) based on the first characteristic and the second characteristic, which may result in similar effects on the memory system.

[0016] According to aspects described herein, a memory system may separate (e.g., organize, partition) L2P mappings based on a characteristic (e.g., temperature characteristic) of data corresponding to the L2P mappings. In some instances, the temperature characteristic may correspond to a number of access operations associated with the L2P mappings. The memory system may access (e.g., open) a first memory block to store L2P mappings associated with a first characteristic (e.g., hot data, more frequently accessed data) and access a second memory block to store L2P mappings associated with a second characteristic (e.g., cold data, less frequently accessed data). In some instances, the memory system may store an indication of a corresponding number of access operations (e.g., modify access operations) associated with each L2P mapping, which may help maintain the separation of L2P data. Separating L2P mappings based on the first characteristic and the second characteristic may reduce the number of maintenance operations performed, improve overall system durability, and improve quality of service, among other benefits.

[0017] In addition to being applied in the memory systems described herein, the techniques for separating L2P mappings may also be implemented generally to improve the performance of various electronic devices and systems, including games. Some electronic device applications, including games and other high-performance applications, may be associated with relatively high processing requirements while also benefiting from relatively fast response times to improve the user experience. Thus, it may be desirable to increase processing speed, reduce response time, or otherwise improve electronic device performance. Implementation of the techniques described herein may improve electronic device performance by increasing memory access speeds, which may reduce processing or latency times, improve response times, or otherwise improve the user experience, among other benefits.

[0018] In addition to being applied in the memory systems described herein, the techniques for separating L2P mappings may also be generally implemented to support artificial intelligence applications. As the use of artificial intelligence increases to support machine learning, analysis, decision making, or other related applications, electronic devices that support artificial intelligence applications and processes may be desired. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes and may benefit from memory devices that can effectively and efficiently store relatively large amounts of data or access stored data relatively quickly. Implementation of the techniques described herein may improve electronic device performance by increasing memory access speeds, which may reduce processing or latency times, improve response times, or otherwise improve user experience, among other benefits.

[0019] First, in reference Figure 1 Features of the present disclosure are described in the context of a system. Figures 2 to 3 Features of the present disclosure are described in the context of systems and process flows. Figure 4 and 5 These and other features of the present disclosure are further illustrated and described in the context of device diagrams and flow diagrams related to split L2P mapping.

[0020] Figure 1 An example of a system 100 supporting split logical to physical mapping according to examples disclosed herein is shown. The system 100 includes a host system 105 coupled with a memory system 110. The system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device including a memory and a processing device.

[0021] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0022] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0023] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate (e.g., exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105) via the physical host interface using an associated protocol. Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0024] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicated with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled and communicated with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and the one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses (eg, data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105 .

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refreshes, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when it is read from or written to the memory device 130, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0029] although Figure 1 The example of the memory system 110 in has been illustrated as including the memory system controller 115, but in some cases, the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115. In general, in some cases, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] The memory device 130 may include one or more non-volatile memory cell arrays. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistance random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more volatile memory cell arrays. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated in FIG. 1 , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b .

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells (MLCs) when configured to store two bits of information each, three-level cells (TLCs) when configured to store three bits of information each, quad-level cells (QLCs) when configured to store four bits of information each, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a number of groups of blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof) but may be erased at a second granularity (e.g., at a block granularity). That is, a page 175 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and a block 170 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, a NAND memory cell may be erased before it may be overwritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 is erased.

[0037] In some cases, to update some data within a block 170 while leaving other data within the block 170 unchanged, the memory device 130 may copy the unchanged data to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., local controller 135) or the memory system controller 115 may mark or otherwise indicate the data remaining in the old block 170 as invalid or obsolete and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) of the data with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old block 170, for example, due to latency or loss considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory unit of the memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory system controller 115.

[0038] In some cases, an L2P mapping table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that may be outdated because a newer or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of this data stored on the memory device 130. A page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0039] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, trash collection, scrubbing, block scanning, health monitoring, or other or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. In order to avoid waiting until all pages 175 in a block 170 have invalid data before erasing and reusing the block 170, an algorithm called "trash collection" may be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations. Trash collection may refer to a set of media management operations that include, for example: selecting a block 170 containing valid and invalid data; selecting a page 175 in a block containing valid data; copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170); marking the data in the previously selected page 175 as invalid; and erasing the selected block 170. Thus, the number of blocks 170 that have been erased may be increased so that more blocks 170 are available to store subsequent data (eg, data subsequently received from the host system 105).

[0040] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0041] The system 100 may include any number of non-transitory computer-readable media that support the split logical-to-physical mapping. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0042] According to aspects described herein, the memory system 110 may separate (e.g., organize, partition) L2P mappings based on temperature characteristics of data corresponding to the L2P mappings. The temperature characteristics may correspond to the number of access operations associated with the L2P mappings. The memory system may open a first block of the memory device 130 to store L2P mappings associated with a first characteristic (e.g., hot data, more frequently accessed data) and open a second block of the memory device 130 to store L2P mappings associated with a second characteristic (e.g., cold data, less frequently accessed data). In some examples, the memory system 110 may store an indication of a corresponding number of access operations with each L2P mapping, which may help maintain the separation of the L2P data. Separating the L2P mappings based on the first characteristic and the second characteristic may reduce the number of maintenance operations performed, improve overall durability, and increase the QoS of the memory system 110, among other benefits.

[0043] Figure 2 An example of a system 200 supporting split L2P mapping according to examples disclosed herein is shown. The system 200 can implement various aspects of the system 100, as described in reference Figure 1 As described above. For example, the system 200 may include a host system 205 and a memory system 210, which may be instances of the host system 105 and the memory system 110. The system 200 may include the memory system 210 operable to communicate with the host system 205 via a memory system controller 215. For example, the memory system controller 215 may be operable to perform operations on the memory system 210 according to commands from the host system 205. The system 200 may illustrate a sequence of write commands 230 (e.g., received from the host system 205). Each write command 230 may include a corresponding LBA (e.g., LBA-a, LBA-b, etc.) and data associated with the LBA (e.g., Data-a, Data-b, etc.). The memory system 210 may separate (e.g., organize, partition) L2P mappings associated with the write commands 230 based on temperature characteristics of the data, which may reduce the number of maintenance operations performed, improve overall endurance, and increase QoS of the memory system 210, among other benefits.

[0044] The memory system 210 may include non-volatile memory 220 and volatile memory 225, which may be examples of corresponding memory devices 130, as described with reference to FIG. Figure 120. In some cases, the memory system controller 215 may receive one or more write commands 230 (e.g., from the host system 205). The memory system controller 215 may determine to write data associated with the write command 230 to a memory cell block in the non-volatile memory 220. The memory system controller 215 may determine the PBA of the memory cell block to write the data based on the LBA included in the write command 230. The association between the LBA and the PBA may define a mapping, which may be referred to as an L2P mapping 240. The memory system controller 215 may write the L2P mapping 240 to a memory cell block in the non-volatile memory 220 or the volatile memory 225.

[0045] In some cases, the L2P region corresponding to the L2P map 240 may be associated with one or more characteristics. In some cases, the one or more characteristics may correspond to the number of access operations associated with the LBA (e.g., an LBA that has undergone a certain number of access operations), the data, or both. The access operation may refer to an operation such as writing data, erasing data, refreshing data, or other such operations. As described herein, the L2P map 240 may be associated with a characteristic (e.g., a temperature characteristic) based on the number of access operations performed during a duration. For example, the number of access operations may be considered 'hot' based on the number satisfying a threshold for a duration (e.g., a first duration) and may be considered 'cold' based on the number failing to satisfy the threshold, satisfying a different threshold, or both. Additionally or alternatively, the number of access operations may be associated with other temperature characteristics (e.g., a warm characteristic) based on satisfying or failing to satisfy a certain threshold.

[0046] Additionally or alternatively, in some examples, the characteristic can be based on a duration between access operations. For example, the characteristic can be based on a duration between a first write operation and a second write operation to an L2P map, a duration between a write operation and an unmap operation (e.g., erase, invalidate) to L2P map 240, or the like. A relatively low duration between access operations can be associated with a first characteristic (e.g., a hot characteristic), and a relatively high duration between access operations can be associated with a second characteristic (e.g., a cold characteristic).

[0047] In some examples, first characteristic 260 (e.g., hot characteristic) may be associated with a relatively high number of access operations performed on L2P mapping 240 over a duration, and second characteristic 265 (e.g., cold characteristic) may be associated with a relatively low number of access operations performed on L2P mapping 240 over a duration. For example, first characteristic 260 may correspond to a number of access operations that satisfy a first threshold. Second characteristic 265 may correspond to a number of access operations that fail to satisfy the first threshold or satisfy a second threshold that is different from (e.g., less than) the first threshold, or both.

[0048] The first characteristic 260 and the second characteristic 265 may further relate to the validity associated with the data (e.g., the likelihood that the data will become invalid sooner or later). For example, the data associated with the second characteristic 265 may become invalid relatively sooner than the data associated with the first characteristic 260. Storing a mixture of data associated with the first characteristic 260 and the second characteristic 265 together in the same memory area may result in additional maintenance operations (e.g., additional obsolete item collection operations), which may negatively impact system endurance, increase latency and write amplification effects, and reduce the overall quality of service (QoS) of the memory system 210.

[0049] In some cases, this negative system effect may increase for a memory system 210 that stores data to QLC (e.g., due to lower relative endurance and performance compared to TLC or other cell types). To improve the efficiency of the memory system 210, the memory system controller 215 may separate data (e.g., host data) based on whether the data is associated with a first characteristic 260 (e.g., hot data) or associated with a second characteristic 265 (e.g., cold data). In addition, the memory system controller 215 may separate the L2P mappings 240 based on such temperature characteristics (e.g., based on the heat or temperature of the host data referenced by the L2P mappings 240), which may reduce the number of maintenance operations performed, improve overall endurance, and increase the QoS of the memory system 210, among other benefits.

[0050] According to aspects described herein, the memory system controller 215 may identify and separate (e.g., separate, partition, organize) the L2P map 240 based on a temperature characteristic of data (e.g., L2P zones) associated with the L2P map. As used herein, a temperature characteristic may refer to the number of access operations performed within a duration. A first characteristic (e.g., a first temperature) may correspond to data associated with a relatively high number of access operations (e.g., hot data), and a second characteristic (e.g., a second temperature) may correspond to data associated with a relatively low number of access operations (e.g., cold data). Additionally or alternatively, an access frequency may refer to a frequency at which access operations are performed. For example, access operations may be performed at a first access frequency (e.g., within a relatively short duration) or a second frequency (e.g., within a relatively long duration), among other possibilities.

[0051] The memory system controller 215 may open a plurality of blocks 235 (e.g., blocks of memory cells) for writing one or more L2P maps 240. For example, the memory system controller 215 may open a first block 235-a for writing an L2P map associated with a first characteristic 260 (e.g., hot data) and a second block 235-b for writing an L2P map 240 associated with a second characteristic 265 (e.g., cold data). The memory system controller 215 may open blocks 235 in the non-volatile memory 220 (as shown in the system 200), or open blocks 235 in the volatile memory 225 (not shown), or both. In some examples, the blocks 235-a and the blocks 235-b may share parity data 255 (e.g., exclusive-OR (XOR) parity data) to save space in the memory system 210 (e.g., in an SRAM).

[0052] The memory system controller 215 may receive a write command 230-a and a write command 230-b. The write command 230-a may include an LBA-a and Data-a that may be associated with a first characteristic 260 (e.g., hot data), and the write command 230-b may include an LBA-b and Data-b that may be associated with a second characteristic 265 (e.g., cold data). In some cases, the host system 205 may include an indication (e.g., a tag) of whether the write command 230 is associated with the first characteristic 260 or the second characteristic 265 or some other temperature characteristic. Additionally or alternatively, the memory system controller 215 may determine the temperature characteristic associated with the write command 230 based on monitoring the number of access operations associated with the LBA during a duration of time.

[0053] The memory system controller 215 may determine that LBA-a and Data-a are associated with the first characteristic 260 and determine that LBA-b and Data-b are associated with the second characteristic 265. The memory system controller 215 may write Data-a to the memory cell corresponding to PBA 0 and write Data-b to the memory cell corresponding to PBA 1. Based on the association of LBA-a with the first characteristic 260 and the association of LBA-b with the second characteristic 265, the memory system controller 215 may store the first L2P map 240 (e.g., corresponding to Data-a) to the block 235-a and the second L2P map (e.g., corresponding to Data-b) to the block 235-b. Thus, the memory system controller 215 may store the first L2P map 240 and the second L2P map 240 to different blocks 235 based on the temperature characteristics of their respective L2P zones. Similarly, the memory system controller 215 may determine that LBA-d / Data-d, LBA-f / Data-f, and LBA-g / Data-g are associated with the first characteristic 260 and determine that LBA-c / Data2 and LBA-e / Data-e are associated with the second characteristic 265. Therefore, the memory system controller 215 may write the corresponding L2P mappings 240 for Data-d, Data-f, and Data-g to block 235-a and the corresponding L2P mappings 240 for Data-c and Data-e to block 235-b.

[0054] In some examples, writing the L2P map 240 may include writing L2P data 245 (which may be an association between an LBA and a corresponding PBA) and an indication 250 (e.g., Indication-a). The indication 250 may include a number (e.g., a count) of access operations associated with an L2P zone (e.g., a 4 kilobyte (KiB) zone, a 2KiB zone, etc.) corresponding to the L2P map 240. Additionally or alternatively, the memory system controller 215 may write the indication 250 to a dedicated block (not shown) or may store the indication 250 as metadata with the associated L2P map 240 (e.g., to block 235-a, block 235-b, some other block). The memory system controller 215 may monitor the number of access operations associated with the L2P data 245 and may update the indication 250 based on the monitoring.

[0055] Additionally or alternatively, the memory system controller 215 may receive a command to update the indication 250. In some examples, the memory system controller 215 may update whether the L2P map 240 is associated with the first characteristic 260, the second characteristic 265, or some other characteristic based on the update indication 250. For example, the L2P map 240 with the indication 250 may be associated with the second characteristic 265. The memory system controller 215 may receive a command to update the indication 250, and the memory system controller 215 may determine to move the L2P map 240 to a different location (e.g., to the block 235-a) based on the update indication 250.

[0056] In some examples, the memory system controller 215 may also monitor the number of L2P maps 240 associated with each temperature characteristic in a given L2P table (e.g., a 4KiB table) (e.g., a storage count). Storing the number of L2P maps 240 associated with each temperature may use a relatively low amount of storage space in the memory system 210 (e.g., due to the file system segmenting flag data every 2 megabytes (MB)). For example, the memory system controller 215 may use one or more bits (e.g., 10 bits) to store the number of L2P maps 240 associated with each temperature (e.g., hot, cold, or some other temperature) of the L2P table. The one or more bits may be stored with the L2P map 240 (e.g., with an upper level L2P pointer), as metadata, or any combination thereof.

[0057] In some examples, the L2P table may be stored to the non-volatile memory 220. That is, due to storage constraints of the volatile memory 225, a portion of the L2P table may be stored to the volatile memory 225 and the complete L2P table (e.g., the full L2P table) may be stored to the non-volatile memory. In some instances, the L2P mapping stored to the volatile memory 225 may be used to update the L2P table stored to the non-volatile memory 220, and vice versa. For example, the L2P table stored to the non-volatile memory 220 may be updated with the L2P mapping 240 (and corresponding indication 250) stored to the block 235 of the volatile memory 225. The indication 250 may be stored so that when the mapping is loaded from the non-volatile memory 220 to the volatile memory 225, the corresponding L2P mapping 240 may be stored to the block 235 based on the corresponding characteristics (e.g., whether the associated data is hot or cold).

[0058] In some examples, the memory system controller 215 may perform or manage maintenance operations on the block 235-a and the block 235-b separately. Examples of maintenance operations may be obsolete collection operations, L2P compression operations, data cache operations (e.g., hot data cache), and L2P pre-reading techniques, among other operations. As described herein, separating the L2P mappings may enable the memory system controller 215 to perform such maintenance operations on the memory cell block 335-a and the memory cell block 335-b separately to improve efficiency. For example, the indication 250 may enable the obsolete collection operations to more efficiently separate data based on temperature characteristics.

[0059] Separating the L2P map 240 may further enable the memory system 210 to maintain frequently accessed L2P maps 240 (e.g., hot L2P maps) in the volatile memory 225 (e.g., SRAM), which may improve overall QoS. For example, the memory system controller 215 may determine to maintain the block 235-a in the volatile memory 225 and may store the block 235-b in the non-volatile memory 220 based on temperature characteristics. Separating the L2P map 240 between different blocks 235 may provide other benefits, such as reducing write amplification, reducing excessive write operations (e.g., improving total terabytes written (TBW)), enabling wear leveling operations (e.g., static garbage collection), and other benefits, which may improve endurance and improve the QoS of the memory system 210.

[0060] Figure 3 An example of a process flow 300 for supporting split L2P mapping according to examples disclosed herein is shown. The process flow 300 may illustrate reference Figure 2 For example, process flow 300 may depict operations at host system 305 and memory system 310, which may be instances of host system 205 and memory system 210, respectively, as described in reference to FIG. Figure 2 According to the operations described herein, the memory system 310 may include a memory system controller 315, a first memory cell block 335-a, and a second memory cell block 335-b. The memory system 310 may separate (e.g., organize, partition) L2P mappings associated with write commands based on temperature characteristics of the data, which may reduce the number of maintenance operations performed, improve overall endurance, and increase QoS of the memory system 310, among other benefits.

[0061] In the following description of the process flow 300, methods, techniques, processes, and operations may be performed in a different order or at a different time. In addition, certain operations may be omitted from the process flow 300, or other operations may be added to the process flow 300.

[0062] At 320, a write command may be received. In some examples, the memory system 310 (e.g., the memory system controller 315) may receive a write command that includes data and a logical address (e.g., an LBA) corresponding to a physical address (e.g., a PBA) associated with the memory system 310. The command may be received from the host system 305 and the data in the write command may be host data desired for storage at the memory system 310. The data, the LBA, or both may be related to a temperature characteristic (e.g., a reference Figure 2 In some examples, a write command (e.g., from the host system 305) may indicate that the logical address is associated with a first characteristic (e.g., a hot temperature characteristic), a second characteristic (e.g., a cold temperature characteristic), or some other characteristic (e.g., a different temperature characteristic). For example, the host system 305 may indicate the data temperature characteristic (e.g., a stream identifier (ID)) via a field in the write command (e.g., a group ID field).

[0063] In some examples, the write command at 320 may include an update command to update the number of access operations associated with the logical address. For example, the memory system controller 315 may receive a command (e.g., an update command included in the write command) based on writing (e.g., previously writing) a mapping between a logical address and a corresponding physical address to the first memory cell block 335-a, the second memory cell block 335-b, or some other block.

[0064] At 325, a number of access operations associated with the logical address may be determined. The access operation may be a read operation, a write operation, an erase operation, a refresh operation, or some other such operation. In some examples, the memory system controller 315 may determine the number of access operations associated with the logical address included in the write command. For example, the memory system controller 315 may determine the number of access operations associated with the LBA received at 320. In some examples, the memory system controller 315 may determine the number of access operations based on information received in the write command received at 320 (e.g., a stream ID) or based on other information at the memory system 310 (e.g., heuristic information or pre-existing information). In some examples, an updated number of access operations associated with the logical address may be determined. For example, the memory system controller 315 may determine the updated number of access operations associated with the logical address based on receiving a command (e.g., a write command at 320).

[0065] At 330, it may be determined whether the logical address is associated with a first characteristic, a second characteristic, or some other characteristic. For example, the memory system controller 315 may determine whether the logical address is associated with a first characteristic, a second characteristic, or some other characteristic based on receiving the write command at 320. The first characteristic may include that the logical address has undergone a first threshold number of access operations, and the second characteristic may include that the logical address has undergone a second threshold number of access operations that is different than the first threshold number of access operations. The first characteristic may be associated with a number of access operations performed on the logical address satisfying a threshold. The threshold may include a number of access operations performed within a duration.

[0066] In some examples, the memory system controller 315 may determine whether the logical address is associated with the first characteristic or the second characteristic based on whether the number of access operations satisfies a threshold. For example, the logical address may be associated with the first characteristic based on the number of access operations satisfying the threshold, and the logical address may be associated with the second characteristic based on the number of access operations failing to satisfy the threshold. Additionally or alternatively, the memory system controller 315 may determine that the logical address is associated with the second characteristic based on determining that the logical address is not associated with the first characteristic or determining that the number of access operations satisfies a different threshold.

[0067] In some examples, the memory system controller 315 may determine whether the logical address is associated with the first characteristic, the second characteristic, or some other characteristic based on receiving a command (e.g., an indication) from the host system 305 at 320. Additionally or alternatively, the memory system controller 315 may determine whether the logical address is associated with the first characteristic, the second characteristic, or some other characteristic based on monitoring a number of access operations associated with the logical address.

[0068] At 340, the mapping may be written to the first memory cell block 335-a. In some examples, the memory system controller 315 may write the mapping between the logical address and the corresponding physical address to the first memory cell block 335-a of the memory system 310 based on determining at 330 that the logical address is associated with the first characteristic. In some examples, exclusive OR (XOR) parity data may be shared between the first memory cell block 335-a and the second memory cell block 335-b based on the memory system controller 315 writing the mapping between the logical address and the corresponding physical address to the first memory cell block 335-a, the second memory cell block 335-b, or both.

[0069] At 345, an indication of the number of access operations may be written to the first memory cell block 335-a. For example, the memory system controller 315 may write the indication of the number of access operations associated with the logical address to the first memory cell block 335-a based on writing the mapping between the logical address and the corresponding physical address to the first memory cell block 335-a. In some examples, the indication of the updated number of access operations may be written based on determining the updated number of access operations associated with the logical address at 325. In some examples, the memory system controller 315 may determine to move (e.g., rewrite) the L2P mapping associated with the updated number of access operations to a different memory cell block in the memory system 310 based on the updated number of access operations. In some instances, the memory system controller 315 may write an indication of the number of access operations (e.g., or an updated number of access operations) as metadata to the first memory cell block 335-a (e.g., as a flag in an L2P table in a spare bit of a NAND page along with the L2P data) or as data (e.g., a pointer to the data) to the first memory cell block 335-a (e.g., as a bitmap in a memory page different from the L2P data) or to a different memory cell block (not shown) of the memory system 310.

[0070] At 350, a mapping between the logical addresses and the corresponding physical addresses may be written to the second memory cell block 335-b. In some examples, the memory system controller 315 may write the mapping between the logical addresses and the corresponding physical addresses to the second memory cell block 335-b of the memory system 310 based on determining at 330 that the logical addresses are associated with the second characteristic. In some examples, exclusive-OR (XOR) parity data may be shared between the second memory cell block 335-b and the first memory cell block 335-a based at least in part on the memory system controller 315 writing the mapping between the logical addresses and the corresponding physical addresses.

[0071] At 355, an indication of the number of access operations associated with the logical address may be written to the second memory cell block 335-b. For example, the memory system controller 315 may write the indication of the number of access operations associated with the logical address to the memory cell 335-b based on writing the mapping between the logical address and the corresponding physical address to the second memory cell block 335-b. In some examples, the indication of the updated number of access operations may be written based on determining the updated number of access operations associated with the logical address at 325. In some examples, the memory system controller 315 may determine to move (e.g., rewrite) the L2P mapping associated with the updated number of access operations to a different memory cell block in the memory system 310 based on the updated number of access operations. In some instances, the memory system controller 315 may write an indication of the number of access operations as metadata to the second memory cell block 335-b (e.g., as a flag in an L2P table in a spare bit of a NAND page along with the L2P data) or as data (e.g., a pointer to the data) to the second memory cell block 335-b (e.g., as a bitmap in a different memory page than the L2P data) or to a different memory cell block (not shown) of the memory system 310.

[0072] Separating L2P mappings between different blocks 335 can provide benefits to the memory system 310, such as reducing write amplification, reducing excessive write operations (e.g., improving total terabytes written (TBW)), enabling wear leveling operations (e.g., static garbage collection), and other benefits, which can improve durability and increase the QoS of the memory system 310.

[0073] Figure 4 A block diagram 400 is shown of a memory system 420 supporting split L2P mapping according to examples disclosed herein. The memory system 420 may be a reference Figures 1 to 3 Memory system 420 or its various components may be examples of means for performing various aspects of the split L2P mapping described herein. For example, memory system 420 may include receiving component 425, determining component 430, mapping component 435, writing component 440, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0074] The receiving component 425 may be configured as or otherwise support means for receiving, at a memory system, a write command including data and a logical address corresponding to a physical address associated with the memory system. The determining component 430 may be configured as or otherwise support means for determining, based on receiving the write command, whether the logical address is associated with a first characteristic, wherein the first characteristic is associated with a number of access operations performed on the logical address satisfying a threshold. The mapping component 435 may be configured as or otherwise support means for writing a mapping between the logical address and the corresponding physical address to a first memory cell block of the memory system based on determining that the logical address is associated with the first characteristic.

[0075] In some examples, determining component 430 may be configured to or otherwise support means for determining that the logical address is associated with the second characteristic based on determining that the logical address is not associated with the first characteristic. In some examples, mapping component 435 may be configured to or otherwise support means for writing a mapping between the logical address and the corresponding physical address to a second memory cell block of the memory system based on determining that the logical address is associated with the second characteristic.

[0076] In some examples, the write component 440 may be configured to or otherwise support means for writing a first indication of the number of access operations associated with the logical address to the memory system based on writing a mapping between the logical address and the corresponding physical address to the second memory cell block. In some examples, the first indication of the number of access operations is written as metadata to the second memory cell block or the third memory cell block of the memory system.

[0077] In some examples, mapping component 435 may be configured to or otherwise support means for sharing exclusive-OR (XOR) parity data between a first block of memory cells and a second block of memory cells based on writing a mapping between logical addresses and corresponding physical addresses to the first block of memory cells.

[0078] In some examples, write component 440 may be configured to or otherwise support means for writing a second indication of the number of access operations associated with the logical address based on writing a mapping between the logical address and the corresponding physical address to the first memory cell block, wherein the second indication of the number of access operations is written as metadata to the first memory cell block or the fourth memory cell block of the memory system.

[0079] In some examples, to support determining whether the logical address is associated with the first characteristic, determination component 430 can be configured or otherwise support means for determining a number of access operations associated with the logical address included in the write command.

[0080] In some examples, the determining component 430 may be configured to or otherwise support means for determining whether the number of access operations satisfies a threshold, wherein the logical address is associated with a first characteristic based on the number of access operations satisfying the threshold, and wherein the logical address is associated with a second characteristic based on the number of access operations failing to satisfy the threshold. In some examples, the first characteristic includes that the logical address has undergone a first number of access operations. In some examples, the second characteristic includes that the logical address has undergone a second number of access operations that is different from the first number of access operations. In some examples, the threshold includes the number of access operations performed within a duration.

[0081] In some examples, receiving component 425 may be configured or otherwise support means for receiving a command based on writing a mapping between a logical address and a corresponding physical address to a first block of memory cells. In some examples, determining component 430 may be configured or otherwise support means for determining an updated number of access operations associated with the logical address based on receiving the command. In some examples, writing component 440 may be configured or otherwise support means for writing a third indication of the updated number of access operations associated with the logical address to a fifth block based on determining the updated number of access operations.

[0082] In some examples, receiving component 425 can be configured or otherwise support means for receiving a command indicating that the logical address is associated with the first characteristic, wherein determining whether the logical address is associated with the first characteristic is based on receiving the command.

[0083] In some examples, mapping component 435 may be configured to or otherwise support means for writing a mapping between a logical address and a corresponding physical address and a fourth indication of a number of access operations associated with the logical address to a non-volatile memory of the memory system based at least in part on determining that the logical address is associated with the first characteristic.

[0084] In some examples, mapping component 435 may be configured to or otherwise support means for loading a mapping between logical addresses and corresponding physical addresses and a fourth indication of a number of access operations associated with the logical address into a sixth block of the memory system based at least in part on writing the mapping to a non-volatile memory, wherein the mapping is loaded into the sixth block based at least in part on the fourth indication.

[0085] Figure 5 A flowchart illustrating a method 500 for supporting split L2P mapping according to an example disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 500 may be implemented by reference to Figures 1 to 4The wireless memory system may perform the described functions. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the wireless memory system may use dedicated hardware to perform aspects of the described functions.

[0086] At 505, the method may include receiving, at a memory system, a write command including data and a logical address corresponding to a physical address associated with the memory system. Operation 505 may be performed according to examples disclosed herein. In some examples, aspects of operation 505 may be described with reference to Figure 4 The receiving component 425 described above performs the above steps.

[0087] At 510, the method may include determining whether the logical address is associated with a first characteristic based on receiving the write command, wherein the first characteristic is associated with a number of access operations performed on the logical address satisfying a threshold. Operation 510 may be performed according to examples disclosed herein. In some examples, aspects of operation 510 may be described with reference to Figure 4 The determination component 430 described performs.

[0088] At 515, the method may include writing a mapping between the logical address and the corresponding physical address to a first memory cell block of the memory system based on determining that the logical address is associated with the first characteristic. Operation 515 may be performed according to examples disclosed herein. In some examples, aspects of operation 515 may be described by reference to Figure 4 The mapping component 435 described performs.

[0089] In some examples, an apparatus described herein may perform one or several methods, such as method 500. An apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0090] Aspect 1: A method, apparatus, or non-transitory computer-readable medium includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving, at a memory system, a write command including data and a logical address corresponding to a physical address associated with the memory system; determining, based at least in part on receiving the write command, whether the logical address is associated with a first characteristic, wherein the first characteristic is associated with a number of access operations performed on the logical address satisfying a threshold; and writing a mapping between the logical address and the corresponding physical address to a first memory cell block of the memory system based at least in part on determining that the logical address is associated with the first characteristic.

[0091] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: determining that the logical address is associated with a second characteristic based at least in part on determining that the logical address is not associated with the first characteristic; and writing the mapping between the logical address and the corresponding physical address to a second memory cell block of the memory system based at least in part on determining that the logical address is associated with the second characteristic.

[0092] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of Aspect 2, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for writing a first indication of the number of access operations associated with the logical address to the memory system based at least in part on writing the mapping between the logical address and the corresponding physical address to the second memory cell block.

[0093] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of aspect 3, wherein the first indication of the number of access operations is written as metadata to the second memory unit block or third memory unit block of the memory system.

[0094] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 2 to 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for sharing exclusive-OR (XOR) parity data between the first memory cell block and the second memory cell block based at least in part on writing the mapping between the logical address and the corresponding physical address to the first memory cell block.

[0095] Aspect 6: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: writing a second indication of the number of access operations associated with the logical address based at least in part on writing the mapping between the logical address and the corresponding physical address to the first memory cell block, wherein the second indication of the number of access operations is written as metadata to the first memory cell block or a fourth memory cell block of the memory system.

[0096] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, wherein determining whether the logical address is associated with the first characteristic includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining the number of access operations associated with the logical address included in the write command.

[0097] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of Aspect 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining whether the number of access operations satisfies the threshold, wherein the logical address is associated with the first characteristic at least in part based on the number of access operations satisfying the threshold, and wherein the logical address is associated with a second characteristic at least in part based on the number of access operations failing to satisfy the threshold.

[0098] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 7 to 8, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: receiving a command based at least in part on writing the mapping between the logical address and the corresponding physical address to the first memory unit block; determining an updated number of access operations associated with the logical address based at least in part on receiving the command; and writing a third indication of the updated number of access operations associated with the logical address to a fifth block based at least in part on determining the updated number of access operations associated with the logical address.

[0099] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a command indicating that the logical address is associated with the first characteristic, wherein determining whether the logical address is associated with the first characteristic is based at least in part on receiving the command.

[0100] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 10, wherein the first characteristic includes that the logical address has undergone a first number of access operations and the second characteristic includes that the logical address has undergone a second number of access operations different from the first number of access operations.

[0101] Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 11, wherein the threshold comprises a number of access operations performed within a duration.

[0102] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 12, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for writing the mapping between the logical address and the corresponding physical address and a fourth indication of the number of access operations associated with the logical address to a non-volatile memory of the memory system based at least in part on determining that the logical address is associated with the first characteristic.

[0103] Aspect 14: The method, apparatus, or non-transitory computer-readable medium of Aspect 13, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: loading the mapping between the logical address and the corresponding physical address and the fourth indication of the number of access operations associated with the logical address into a sixth block of the memory system based at least in part on writing the mapping to the non-volatile memory, wherein the mapping is loaded into the sixth block based at least in part on the fourth indication.

[0104] It should be noted that the described techniques include possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0105] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0106] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0107] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open circuit relationship between components (where signals cannot currently pass between components via conductive paths) to a closed circuit relationship between components (where signals can pass between components via conductive paths). If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0108] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between components, then they are isolated from each other. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0109] The terms "if," "when," "based on," or "based at least in part on" may be used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a connection between conditional actions, conditional processes, or parts of processes, the terms may be interchangeable.

[0110] The term "responsive to" may refer to one condition or action occurring at least in part, if not entirely, as a result of a prior condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occurring after the first condition or action).

[0111] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action occurring directly due to a previous condition or action. In some instances, a first condition or action may be performed and a second condition or action may occur directly due to a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed and a second condition or action may occur directly due to a previous condition or action, so that no other intermediate conditions or actions occur between an earlier condition or action and the second condition or action or a limited number of one or more intermediate steps or actions occur between an earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on", "at least partially based on" or "in response to" some other step, action, event or condition and performed may be performed in addition or alternatively (e.g., in an alternative instance) "directly in response to" or "directly in response to" this other action or condition.

[0112] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0113] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0114] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "superior to other examples". The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0115] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0116] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0117] For example, the various illustrative blocks and components described herein in connection with the present disclosure may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0118] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0119] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices or can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory media. Moreover, any connection is appropriately referred to as computer-readable media. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave), then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0120] The description herein is provided to enable persons skilled in the art to make or use the present disclosure. Persons skilled in the art will appreciate various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: A memory system including a volatile memory and a non-volatile memory; and a controller associated with the memory device, wherein the controller is configured to cause the apparatus to: receiving, at the memory system, a write command including data and a logical address corresponding to a physical address associated with the memory system; determining, based at least in part on receiving the write command, whether the logical address is associated with a first characteristic, wherein the first characteristic is associated with a number of access operations performed on the logical address satisfying a threshold; and A mapping between the logical address and the corresponding physical address is written to a first block of memory cells of the memory system based at least in part on determining that the logical address is associated with the first characteristic.

2. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: determining that the logical address is associated with a second characteristic based at least in part on determining that the logical address is not associated with the first characteristic; and The mapping between the logical address and the corresponding physical address is written to a second block of memory cells of the memory system based at least in part on determining that the logical address is associated with the second characteristic.

3. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: A first indication of a number of access operations associated with the logical address is written to the memory system based at least in part on writing the mapping between the logical address and the corresponding physical address to the second block of memory cells. 4 . The apparatus of claim 3 , wherein the first indication of the number of access operations is written as metadata to the second memory cell block or a third memory cell block of the memory system.

5. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: Exclusive OR (XOR) parity data is shared between the first block of memory cells and the second block of memory cells based at least in part on writing the mapping between the logical addresses and the corresponding physical addresses to the first block of memory cells.

6. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: Writing a second indication of a number of access operations associated with the logical address based at least in part on writing the mapping between the logical address and the corresponding physical address to the first memory cell block, wherein the second indication of the number of access operations is written as metadata to the first memory cell block or a fourth memory cell block of the memory system.

7. The apparatus of claim 1 , wherein determining whether the logical address is associated with the first characteristic is configured to cause the apparatus to: A number of access operations associated with the logical address included in the write command is determined.

8. The apparatus of claim 7, wherein the controller is further configured to cause the apparatus to: A determination is made as to whether the number of access operations satisfies the threshold, wherein the logical address is associated with the first characteristic based at least in part on the number of access operations satisfying the threshold, and wherein the logical address is associated with a second characteristic based at least in part on the number of access operations failing to satisfy the threshold.

9. The apparatus of claim 7, wherein the controller is further configured to cause the apparatus to: receiving a command based at least in part on writing the mapping between the logical addresses and the corresponding physical addresses to the first block of memory cells; determining an update number of access operations associated with the logical address based at least in part on receiving the command; and A third indication of the updated number of access operations associated with the logical address is written to a fifth block based at least in part on determining the updated number of access operations.

10. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: A command is received indicating that the logical address is associated with the first characteristic, wherein determining whether the logical address is associated with the first characteristic is based at least in part on receiving the command.

11. The apparatus of claim 1, wherein: The first characteristic includes that the logical address has undergone a first number of access operations, and The second characteristic includes that the logical address has undergone a second number of access operations different than the first number of access operations.

12. The apparatus of claim 1, wherein the threshold comprises a number of access operations performed within a duration.

13. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: The mapping between the logical address and the corresponding physical address and a fourth indication of a number of access operations associated with the logical address are written to the nonvolatile memory of the memory system based at least in part on determining that the logical address is associated with the first characteristic.

14. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: The mapping between the logical addresses and the corresponding physical addresses and the fourth indication of the number of access operations associated with the logical addresses are loaded to a sixth block of the memory system based at least in part on writing the mapping to the non-volatile memory, wherein the mapping is loaded to the sixth block based at least in part on the fourth indication.

15. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving, at a memory system, a write command including data and a logical address corresponding to a physical address associated with the memory system; determining, based at least in part on receiving the write command, whether the logical address is associated with a first characteristic, wherein the first characteristic is associated with a number of access operations performed on the logical address satisfying a threshold; and A mapping between the logical address and the corresponding physical address is written to a first block of memory cells of the memory system based at least in part on determining that the logical address is associated with the first characteristic.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determining that the logical address is associated with a second characteristic based at least in part on determining that the logical address is not associated with the first characteristic; and The mapping between the logical address and the corresponding physical address is written to a second block of memory cells of the memory system based at least in part on determining that the logical address is associated with the second characteristic.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A first indication of a number of access operations associated with the logical address is written to the memory system based at least in part on writing the mapping between the logical address and the corresponding physical address to the second block of memory cells.

18. The non-transitory computer-readable medium of claim 17, wherein the first indication of the number of access operations is written as metadata to the second or third memory cell block of the memory system.

19. The non-transitory computer-readable medium of claim 16, wherein the instructions are further executable by the processor to: Exclusive OR (XOR) parity data is shared between the first block of memory cells and the second block of memory cells based at least in part on writing the mapping between the logical addresses and the corresponding physical addresses to the first block of memory cells.

20. A method comprising: receiving, at a memory system, a write command including data and a logical address corresponding to a physical address associated with the memory system; determining, based at least in part on receiving the write command, whether the logical address is associated with a first characteristic, wherein the first characteristic is associated with a number of access operations performed on the logical address satisfying a threshold; and A mapping between the logical address and the corresponding physical address is written to a first block of memory cells of the memory system based at least in part on determining that the logical address is associated with the first characteristic.

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