Dynamic data migration method and system in storage chip

Abstract

The invention provides a dynamic data migration method and system in a storage chip, and relates to the technical field of data processing.The method comprises the steps that the reading frequency and the writing frequency of each data page are predicted; determining a read-write frequency predicted value of each data page; judging whether the read-write frequency predicted value of each data page is smaller than a preset read-write frequency or not; if yes, determining the data page as a cold page; otherwise, determining the data page as a standard hot page; judging whether the time interval between the last access time and the current time of each data page is greater than the time interval between the last two accesses or not; if yes, determining the data page as a potential hot page; cold pages in the dynamic random access memory and hot pages in the nonvolatile random access memory are put into a candidate page list, and the hot pages comprise standard hot pages and potential hot pages; in order to improve the access response time and reduce the energy consumption, each candidate page in the candidate page list is migrated.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a method and system for dynamic data migration in a storage chip. Background Art

[0002] Memory chips are key components of many computing and embedded systems, and their reliability directly affects the overall stability of the system. Currently, memory chips are mainly divided into two types: volatile (such as dynamic random access memory) and non-volatile (such as flash memory, phase change memory).

[0003] Volatile memory is characterized by fast data read speed and the ability to quickly respond to the system's storage and access needs. Therefore, it is widely used in scenarios that require high-performance computing, such as memory and cache. However, a significant disadvantage of volatile memory is that it requires continuous power supply to retain data. Once the power is cut off, all stored data will be lost. In contrast, non-volatile memory does not require continuous power to maintain data and can retain information for a long time in the event of a power outage. Therefore, it is very useful in applications that need to save data for a long time. However, the main disadvantage of non-volatile memory is the slow speed of data reading and writing. Especially in scenarios with high-frequency read and write operations, its performance may not be comparable to that of volatile memory.

[0004] With the increase in computing demand and the advent of the big data era, how to balance the high speed of volatile memory with the high energy efficiency and data retention capabilities of non-volatile memory has become a research hotspot. Hybrid storage architectures are gradually emerging, combining volatile and non-volatile memory to give full play to the advantages of both, improving system performance, energy efficiency and data reliability.

[0005] In order to fully utilize the advantages of volatile and non-volatile memories and mitigate their negative effects, data migration is often required. The basic idea is to migrate hot data to volatile memories and cold data to non-volatile memories.

[0006] Traditional data migration methods mainly determine whether data is hot data or cold data based on its historical access frequency, and then migrate hot data to volatile memory and cold data to non-volatile memory.

[0007] However, traditional data migration methods mainly rely on the historical access frequency of data and cannot predict future data access patterns. If the data access pattern changes in the future (for example, cold data becomes hot or hot data becomes cold), the system cannot respond in advance, resulting in performance optimization delays or migration decision failures. Summary of the invention

[0008] In order to solve the technical problem that traditional data migration methods mainly rely on the historical access frequency of data and cannot predict future data access patterns, and if the data access pattern changes in the future (for example, cold data becomes hot or hot data becomes cold), the system cannot respond in advance, resulting in performance optimization delays or migration decision failures, the present invention provides a dynamic data migration method and system in a storage chip.

[0009] The technical solution provided by the embodiment of the present invention is as follows: First aspect: A method for dynamic data migration in a memory chip provided by an embodiment of the present invention is applied to a hybrid memory chip, wherein the hybrid memory chip includes a dynamic random access memory and a non-volatile random access memory, and the method includes: S1: Obtain the read frequency and write frequency of each data page in the past period of time; S2: predict the read frequency and write frequency of each data page; S3: Summarize the read frequency prediction value and the write frequency prediction value to determine the read and write frequency prediction value of each data page; S4: determining whether the predicted read / write frequency value of each data page is less than the preset read / write frequency; if so, determining the data page as a cold page; otherwise, determining the data page as a standard hot page; S5: Determine whether the time interval between the last access to each data page and the current time is greater than the time interval between the two most recent accesses; if so, determine the data page as a potential hot page; S6: putting the cold pages in the dynamic random access memory and the hot pages in the non-volatile random access memory into a candidate page list, wherein the hot pages include the standard hot pages and the potential hot pages; S7: Migrating each candidate page in the candidate page list with the goal of improving access response time and reducing energy consumption.

[0010] Second aspect: An embodiment of the present invention provides a dynamic data migration system in a storage chip, comprising: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the method for dynamic data migration in a storage chip as described in the first aspect is implemented.

[0011] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least: (1) In the present invention, the read frequency and write frequency of each data page are predicted, and then the hot and cold states of the data are reasonably judged, and cold pages, standard hot pages, and potential hot pages are accurately distinguished. The system can respond in advance and dynamically adjust the storage location and data migration strategy to improve the memory performance after migration.

[0012] (2) In the present invention, with the goal of improving access response time and reducing energy consumption, each candidate page in the candidate page list is migrated, which can reduce unnecessary energy waste and further improve memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of a flow chart of a method for dynamic data migration in a storage chip provided by an embodiment of the present invention; Figure 2 A schematic diagram of the structure of a dynamic data migration system in a storage chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0016] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0017] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0018] Reference Manual Attached Figure 1 , shows a schematic flow chart of a dynamic data migration method in a storage chip provided by an embodiment of the present invention.

[0019] The embodiment of the present invention provides a method for dynamic data migration in a storage chip applied to a hybrid storage chip, wherein the hybrid storage chip includes a dynamic random access memory and a non-volatile random access memory. Dynamic random access memory (DRAM) is a volatile memory that stores data through capacitors, and each storage unit consists of a transistor and a capacitor. The charging of the capacitor represents "1" and the discharging represents "0". Since the capacitor will gradually discharge, DRAM needs to be refreshed periodically (usually every few milliseconds) to ensure that the data is not lost. This also brings about a certain amount of power consumption. Non-volatile random access memory (NVRAM) is different from DRAM in that it can still save the stored data after power failure. Common NVRAMs include flash memory (Flash), phase change memory (PCM), magnetoresistive memory (MRAM) and ferroelectric memory (FRAM).

[0020] The processing flow of the dynamic data migration method in the storage chip may include the following steps: S1: Obtain the reading frequency and writing frequency of each data page in the past period of time.

[0021] Among them, a data page is a basic storage unit in a computer system, and is particularly widely used in operating systems and storage management.

[0022] S2: Predict the read frequency and write frequency of each data page.

[0023] In a possible implementation, S2 specifically includes: adaptively selecting between a flat prediction strategy and a regression prediction strategy to predict a reading frequency and a writing frequency of a data page.

[0024] Optionally, the flat prediction strategy is specifically: using the read frequency at this time point as the predicted value of the read frequency at the next time point, and using the write frequency at this time point as the predicted value of the write frequency at the next time point.

[0025] It should be noted that the flat prediction strategy does not require complex calculations, but directly uses the current read and write frequencies to predict future read and write frequencies. Therefore, this method is very efficient in environments with limited computing resources, especially in systems with high real-time requirements, where migration decisions can be made quickly and system overhead can be reduced.

[0026] Optionally, the regression prediction strategy is specifically: The least squares method is used to perform linear regression fitting on the reading frequency series of the data page in the past period of time: , Among them, fr i represents the reading frequency at the i-th time point, x i represents the time of the i-th time point, β0 represents the intercept parameter, β1 represents the slope parameter, ε i represents the reading frequency error term at the i-th time point, and the reading frequency error term satisfies the Gaussian distribution.

[0027] According to the linear regression fitting results, the predicted value of the reading frequency at the next time point is determined.

[0028] The least squares method is used to perform linear regression fitting on the write frequency series of the data page in the past period of time: , Among them, fw i represents the writing frequency at the i-th time point, x i represents the time of the i-th time point, α0 represents the intercept parameter, α1 represents the slope parameter, τ i represents the write frequency error term at the i-th time point, and the write frequency error term satisfies the Gaussian distribution.

[0029] According to the linear regression fitting result, the predicted value of the write frequency at the next time point is determined.

[0030] It should be noted that the advantage of using the least squares method for linear regression fitting is that it can capture trend changes, improve prediction accuracy, reduce the impact of noise, and provide a stronger basis for future data page migration decisions.

[0031] Furthermore, although there are many more accurate prediction algorithms, such as neural networks, etc., these algorithms have a very large amount of computation and are not suitable for data migration in the present invention.

[0032] The advantage of the flat prediction strategy is that it is simple to calculate and respond quickly. It is suitable for scenarios with relatively stable access frequency and can effectively save system resources. However, its disadvantage is that it cannot capture the changing trend of access frequency and is difficult to cope with dynamic or drastically changing access patterns. The advantage of the regression prediction strategy is that it can capture the trend changes of data access by fitting historical data, with higher prediction accuracy, and is suitable for scenarios with linear changes in access frequency. However, its calculation complexity is high, which may increase the calculation burden of the system, and is not as simple as the flat prediction when the data fluctuates in the short term.

[0033] In a possible implementation, S2 specifically includes sub-steps S201 to S206: S201: At the i-th time point, a flat prediction strategy and a regression prediction strategy are respectively used to predict the reading frequency and the writing frequency of the data page.

[0034] S202: Counting the errors when the reading frequency is predicted using the flat prediction strategy and the regression prediction strategy at the i-th time point.

[0035] S203: Using the one with the smaller error as the prediction strategy for the reading frequency at the i+1th time point, and determining a predicted value of the reading frequency at the i+1th time point.

[0036] S204: Counting the errors when the write frequency is predicted using the flat prediction strategy and the regression prediction strategy at the i-th time point.

[0037] S205: Using the one with the smaller error as the prediction strategy for the write frequency at the i+1th time point, and determining a predicted value of the write frequency at the i+1th time point.

[0038] S206: Return to S202 and iterate.

[0039] In the present invention, the system can adaptively choose between flat prediction and regression prediction according to different data access patterns. When the access pattern is stable, the flat prediction strategy can provide accurate predictions quickly and with low computational overhead; when the access pattern changes, the regression prediction strategy can capture data trend changes and provide better prediction results. It effectively combines the advantages of the two strategies and can select the optimal solution based on real-time errors, which not only improves the accuracy of the prediction, but also reduces unnecessary computational burden, ensuring efficient operation of the system under dynamic workloads.

[0040] S3: Summarize the predicted read frequency values ​​and the predicted write frequency values ​​to determine the predicted read and write frequency values ​​of each data page.

[0041] Optionally, the predicted read frequency value and the predicted write frequency value may be simply and directly added to obtain the predicted read and write frequency values ​​of each data page.

[0042] S4: Determine whether the predicted read / write frequency value of each data page is less than the preset read / write frequency. If so, determine the data page as a cold page. Otherwise, determine the data page as a standard hot page.

[0043] Among them, those skilled in the art can set the preset reading and writing frequency according to actual conditions, and the present invention does not limit it.

[0044] In the present invention, by simply comparing with a preset frequency threshold, data pages can be quickly classified as cold pages or standard hot pages. This threshold-based classification method has low computational complexity, can quickly complete the classification, and helps maintain efficient processing under a large number of data pages.

[0045] S5: Determine whether the time interval between the last access to each data page and the current time is greater than the time interval between the two most recent accesses. If so, determine the data page as a potential hot page.

[0046] In the present invention, when the interval between the last access and the current time is greater than the interval between the previous two accesses, it indicates that the access frequency of the page is increasing and may become hot data in the future. By identifying this trend, the system can take measures in advance to migrate these pages to high-speed memory and optimize future access response time.

[0047] S6: Put the cold pages in the dynamic random access memory and the hot pages in the non-volatile random access memory into the candidate page list.

[0048] Among them, hot pages include standard hot pages and potential hot pages.

[0049] S7: Migrate each candidate page in the candidate page list with the goal of improving access response time and reducing energy consumption.

[0050] In a possible implementation, S7 specifically includes sub-steps S701 to S703: S701: Sort the candidate pages in the candidate page list.

[0051] Optionally, S701 specifically includes: S7011: Calculate the comprehensive read and write frequency prediction value of each candidate page in the candidate page list: , Among them, f k represents the comprehensive read and write frequency prediction value of the kth candidate page, fr k represents the predicted reading frequency of the kth candidate page, fw k represents the predicted value of the write frequency of the kth candidate page, η i Indicates the balance parameter of the i-th memory unit storing the k-th candidate page.

[0052] , Among them, tr i Indicates the time required for the i-th memory unit to read a page, tw i Indicates the time required for the i-th memory unit to write a page.

[0053] Among them, the introduction of the balance parameter is adjusted according to the read and write time of different memory units, so that the calculation of the comprehensive read and write frequency can better reflect the characteristics of different memory media. For example, some memories may have a fast read speed and a slow write speed (such as NVRAM), while other memories may have similar speeds (such as DRAM). By adjusting the weights of read and write, the system can handle data allocation of different storage units more flexibly and improve the utilization efficiency of storage resources.

[0054] S7012: Arrange the candidate pages in the candidate page list in descending order according to the order of the comprehensive read / write frequency prediction values ​​from high to low.

[0055] In the present invention, by calculating the comprehensive read and write frequency prediction value of each page, the system can simultaneously consider the frequency of reading and writing, thereby more accurately reflecting the importance of each page. For pages that need to be frequently accessed, especially pages that have both read and write operations, this method can capture their high-frequency usage characteristics and avoid focusing on only one operation while ignoring another operation.

[0056] S702: According to the sorting result, determine the potential benefits of migrating each candidate page to other memory units in terms of access response time and energy consumption.

[0057] Optionally, the potential benefits are: , Among them, P ijk represents the potential benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, BT ijk represents the access response time benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, BE ijk represents the energy consumption benefit of migrating the kth candidate page from the i-th memory unit to the j-th memory unit.

[0058] It should be noted that by calculating the access response time benefit and the energy consumption benefit and multiplying the two to calculate the total potential benefit, the system can find a balance between improving the access response speed and reducing the energy consumption.

[0059] , Among them, BT ijk represents the access response time benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, T ik represents the access response time of placing the kth candidate page in the i-th memory cell, T jk represents the access response time of placing the kth candidate page in the jth memory cell, CT ijkIt represents the migration time of migrating the k-th candidate page from the i-th memory unit to the j-th memory unit.

[0060] , Among them, T ik represents the access response time of placing the kth candidate page in the i-th memory cell, fr k represents the predicted reading frequency of the kth candidate page, tr i represents the time required for the i-th memory unit to read a page, fw k represents the predicted value of the write frequency of the kth candidate page, tw i Indicates the time required for the i-th memory unit to write a page.

[0061] , Among them, CT ijk represents the migration time of migrating the kth candidate page from the ith memory unit to the jth memory unit, tr i represents the time required for the i-th memory unit to read a page, tw j Indicates the time required for the jth memory cell to write a page.

[0062] It should be noted that by calculating the access response time benefit, the system can prioritize the migration of data pages with high access frequency to storage units that can significantly reduce access latency. This method can effectively improve the system's response speed to frequently accessed pages, thereby reducing access latency and optimizing user experience.

[0063] , Among them, BE ijk represents the energy consumption benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, E ik represents the access response energy consumption of placing the kth candidate page in the i-th memory cell, E jk represents the access response energy consumption of placing the kth candidate page in the jth memory cell, CE ijk represents the migration energy consumption of migrating the kth candidate page from the i-th memory unit to the j-th memory unit.

[0064] , Among them, E ik represents the energy consumption of placing the kth candidate page in the i-th memory cell, er i represents the energy consumption required for the i-th memory unit to read a page, ew i represents the energy consumption required to write a page to the i-th memory unit, ts irepresents the idle time of the i-th memory unit, e s Indicates the idle energy consumption per unit time.

[0065] , Among them, CE ijk represents the migration energy consumption of migrating the kth candidate page from the ith memory unit to the jth memory unit, er i represents the energy consumption required for the i-th memory unit to read a page, ew j represents the energy consumption required for writing a page to the jth memory cell.

[0066] It should be noted that by calculating the energy benefits, the system can prioritize the migration of pages that can significantly save energy. This helps reduce the energy consumption of high-power storage units, reduce the overall energy consumption of the system, and extend the service life of storage devices.

[0067] S703: Migrate the candidate page to the memory unit with the greatest potential benefit.

[0068] In the present invention, by sorting the candidate pages, the system can give priority to those pages with higher frequencies, ensuring that these pages can be migrated to faster memories (such as DRAM) in a timely manner, thereby reducing the delay in data access. The priority migration of high-frequency data can significantly improve the overall response speed of the system. By identifying and migrating low-frequency pages to memories with lower power consumption (such as NVRAM), the system can effectively reduce the pressure on high-power memories and reduce the energy consumption caused by their continuous operation. This strategy can optimize the overall energy efficiency of the system.

[0069] In a possible implementation, S7 specifically includes: with the goal of improving access response time and reducing energy consumption, determining the best migration plan through the fireworks algorithm, and migrating each candidate page in the candidate page list.

[0070] Among them, the Fireworks Algorithm (FWA) is an optimization algorithm based on heuristic search. It simulates the random distribution and concentrated search process during fireworks explosion. It generates multiple possible migration paths by simulating the process of fireworks explosion, and evaluates the pros and cons of each solution through the fitness function to find the optimal solution to the problem.

[0071] Specifically, with the goal of improving access response time and reducing energy consumption, the fitness function of the fireworks algorithm is constructed: , Among them, f represents the fitness function, X represents the migration plan, , x ijk represents the migration decision parameter, when When , it means that the kth candidate page is migrated from the i-th memory unit to the j-th memory unit. , it means that the kth candidate page has not been migrated from the ith memory unit to the jth memory unit, P ijk represents the potential benefit of migrating the kth candidate page from the i-th memory unit to the j-th memory unit.

[0072] Initialize the fireworks individual. Each fireworks individual is composed of multiple dimensional components. Each fireworks individual represents a feasible page migration plan, and each component represents a migration decision parameter.

[0073] Perform explosion operations on each individual firework: , S i = C S [ f max -f( x i )+ε] ∑ i=1 N [ f max -f( x i )]+ε , Among them, A i represents the explosion radius of the i-th firework, x i represents the i-th firework individual, f represents the fitness function, N represents the total number of firework individuals, min represents the minimum value, ε represents the hyperparameter to avoid division by zero, C A Indicates the explosion radius adjustment factor, S i represents the number of explosion sparks of the i-th firework, max represents the maximum value, C S Indicates the explosion spark number adjustment factor.

[0074] In the present invention, the explosion radius is adjusted according to the fitness function value of the individual. For fireworks individuals with poor fitness, the explosion radius is larger, which means that these individuals will generate more dispersed sparks, thereby conducting a wider global search. Individuals with better fitness have a smaller explosion radius, and will focus on searching the local space for detailed development. By adjusting the explosion radius, the algorithm can take into account both global search and local optimization, avoiding falling into the local optimal solution.

[0075] Furthermore, the number of generated sparks is related to the fitness of the individual. Individuals with better fitness generate fewer sparks, reducing over-search in high fitness areas; while individuals with poorer fitness generate more sparks, which helps to increase the search density and improve the global search capability.

[0076] Limit the number of explosion sparks generated by explosion operation: , in, represents the number of explosion sparks of the i-th firework after restriction processing, S max Indicates the maximum explosion spark number, S minIndicates the minimum number of explosion sparks.

[0077] In the present invention, by limiting the number of explosion sparks of each firework individual, especially setting the maximum number of sparks, individuals with poor fitness are prevented from generating too many sparks. This can prevent the explosion operation from generating excessive sparks, thereby controlling the computational complexity of the algorithm and reducing unnecessary consumption of computing resources.

[0078] Displace the fireworks explosion according to the explosion radius: , Among them, y ijk represents the j-th dimension component of the k-th explosion spark produced by the i-th firework individual, x ij represents the j-th dimension component in the i-th firework individual, Indicates a range from 0 to A ij Pick a random number between ij Represents the j-th dimension component in the explosion radius of the i-th firework individual.

[0079] , Among them, x rj represents the j-th dimension component of a randomly selected firework individual, x gsj represents the j-th dimension component of the global optimal firework individual, x lsj represents the j-th dimensional component of the optimal fireworks individual in the previous iteration, λ1 represents the weight of the random fireworks individual, λ2 represents the weight of the global optimal fireworks individual, λ3 represents the weight of the optimal fireworks individual in the previous iteration, γ represents the displacement coefficient, and f s It represents the variance of the fitness values ​​of all fireworks individuals, and f0 represents the preset variance value.

[0080] Among them, those skilled in the art can set the size of the preset variance value f0 according to actual conditions, and the present invention does not limit it.

[0081] It should be noted that when the fitness variance is less than the preset variance value, the search is more inclined to global exploration, ensuring diversified search paths through the influence of random individuals and optimal individuals; when the fitness variance is greater than the preset variance value, the search is more inclined to focus on local optimization to increase the convergence speed of the search.

[0082] In the present invention, by combining random fireworks individuals, global optimal individuals and historical optimal individuals, the explosion radius can be dynamically adjusted to ensure that both extensive global search and detailed development in local areas can be carried out at different search stages. The addition of random fireworks increases the breadth of global search, while the global optimal and historical optimal individuals ensure the accuracy of local development.

[0083] Randomly select some fireworks individuals, generate a random number, and determine whether the random number is less than the mutation probability. If so, perform Gaussian mutation operation: , in, represents the jth dimension component of the i-th firework individual after Gaussian mutation, x ij represents the j-th dimensional component in the i-th firework individual, and e represents a random number that satisfies a Gaussian distribution with a mean of 1 and a variance of 1.

[0084] Among them, those skilled in the art can set the size of the mutation probability according to actual conditions, and the present invention does not limit it.

[0085] In the present invention, through the Gaussian mutation operation, the search of individuals in the solution space is no longer limited to the original search path, but a certain randomness is introduced, so that the algorithm can jump out of the current search area and expand the search range. This method can effectively avoid falling into the local optimal solution and enhance the global search capability.

[0086] Map each firework: , in, represents the j-th dimension component in the i-th firework individual after the mapping operation, L j Indicates the lower limit of the j-th dimension, U j Represents the upper limit of the j-th dimension, and % represents the modulo operation.

[0087] In the present invention, through mapping operations, it is ensured that the solution of each dimension is within the given upper and lower limits, which can prevent the solution from crossing the boundary during the search process and ensure that the solution is in the predefined valid solution space, thereby improving the effectiveness of the solution, making the search process more focused, reducing the search in irrelevant or invalid areas, and thus improving the search efficiency.

[0088] Perform a selection operation on each firework individual, and the probability of each firework individual being selected is: , , Among them, P represents the selection probability, D represents the sum of the distances between the current individual and other individuals except itself, d represents the Euclidean distance between two individuals, and N represents the total number of firework individuals.

[0089] In the present invention, by calculating the distance between each firework individual and other individuals and determining the selection probability according to the sum of the distances, individuals with larger distances (i.e. solutions that are significantly different from other individuals) have a greater probability of being selected. This can increase the diversity of solutions, prevent the population from becoming homogenous, and ensure that the search process does not focus on a certain area too early.

[0090] Determine whether the current number of iterations has reached the maximum number of iterations. If so, output the page migration plan represented by the firework individual with the highest fitness as the best migration plan. Otherwise, return to continue iterating.

[0091] In the present invention, the migration schemes of different pages are evaluated by the fireworks algorithm, so that frequently accessed hot data can be preferentially migrated to faster memory, reducing the delay of data access and improving the response speed of the system. Cold data can be migrated to storage units with lower power consumption, thereby reducing the burden of high-power memory and reducing the overall energy consumption of the system.

[0092] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0093] (1) In the present invention, the read frequency and write frequency of each data page are predicted, and then the hot and cold states of the data are reasonably judged, and cold pages, standard hot pages, and potential hot pages are accurately distinguished. The system can respond in advance and dynamically adjust the storage location and data migration strategy to improve the memory performance after migration.

[0094] (2) In the present invention, with the goal of improving access response time and reducing energy consumption, each candidate page in the candidate page list is migrated, which can reduce unnecessary energy waste and further improve memory performance.

[0095] Reference Manual Attached Figure 2 , showing a schematic structural diagram of a dynamic data migration system in a storage chip provided by the present invention.

[0096] The present invention further provides a system 20 for dynamic data migration in a storage chip, which is applied to the above-mentioned method for dynamic data migration in a storage chip, comprising:

[0097] Processor 201.

[0098] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201, the dynamic data migration method in the memory chip of the method embodiment is implemented.

[0099] The dynamic data migration system 20 in a storage chip provided by the present invention can execute the above-mentioned dynamic data migration method in a storage chip and achieve the same or similar technical effects. To avoid repetition, the present invention will not elaborate on them.

[0100] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0101] (1) In the present invention, the read frequency and write frequency of each data page are predicted, and then the hot and cold states of the data are reasonably judged, and cold pages, standard hot pages, and potential hot pages are accurately distinguished. The system can respond in advance and dynamically adjust the storage location and data migration strategy to improve the memory performance after migration.

[0102] (2) In the present invention, with the goal of improving access response time and reducing energy consumption, each candidate page in the candidate page list is migrated, which can reduce unnecessary energy waste and further improve memory performance.

[0103] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0104] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0105] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0106] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0107] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0108] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0109] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0110] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0111] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0112] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0113] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0114] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0115] An embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method for dynamic data migration in a storage chip as described in the method embodiment is implemented.

[0116] A computer-readable storage medium provided by the present invention can implement the steps and effects of the dynamic data migration method in the storage chip of the above method embodiment. To avoid repetition, the present invention will not go into details.

[0117] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0118] (1) In the present invention, the read frequency and write frequency of each data page are predicted, and then the hot and cold states of the data are reasonably judged, and cold pages, standard hot pages, and potential hot pages are accurately distinguished. The system can respond in advance and dynamically adjust the storage location and data migration strategy to improve the memory performance after migration.

[0119] (2) In the present invention, with the goal of improving access response time and reducing energy consumption, each candidate page in the candidate page list is migrated, which can reduce unnecessary energy waste and further improve memory performance.

[0120] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0121] There are a few points to note:

[0122] (1) The drawings of the embodiments of the present invention only involve structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0123] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0124] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0125] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for dynamic data migration in a storage chip, characterized in that: Applied to a hybrid memory chip, the hybrid memory chip includes a dynamic random access memory and a non-volatile random access memory, the method includes: S1: Obtain the read frequency and write frequency of each data page in the past period of time; S2: predict the read frequency and write frequency of each data page; S3: Summarize the read frequency prediction value and the write frequency prediction value to determine the read and write frequency prediction value of each data page; S4: determining whether the predicted read / write frequency value of each data page is less than the preset read / write frequency; if so, determining the data page as a cold page; otherwise, determining the data page as a standard hot page; S5: Determine whether the time interval between the last access to each data page and the current time is greater than the time interval between the two most recent accesses; if so, determine the data page as a potential hot page; S6: putting the cold pages in the dynamic random access memory and the hot pages in the non-volatile random access memory into a candidate page list, wherein the hot pages include the standard hot pages and the potential hot pages; S7: Migrating each candidate page in the candidate page list with the goal of improving access response time and reducing energy consumption.

2. The method for dynamic data migration in a storage chip according to claim 1, characterized in that: The S2 is specifically: Adaptively select between a flat prediction strategy and a regression prediction strategy to predict the read frequency and write frequency of data pages.

3. The method for dynamic data migration in a storage chip according to claim 2, characterized in that: The S2 specifically includes: S201: At the i-th time point, a flat prediction strategy and a regression prediction strategy are respectively used to predict the reading frequency and the writing frequency of the data page; S202: Counting the errors when the reading frequency is predicted by using the flat prediction strategy and the regression prediction strategy at the i-th time point respectively; S203: using the one with the smaller error as the prediction strategy for the reading frequency at the i+1th time point, and determining the predicted value of the reading frequency at the i+1th time point; S204: Counting the errors when the write frequency is predicted by using the flat prediction strategy and the regression prediction strategy at the i-th time point respectively; S205: adopting the one with the smaller error as the prediction strategy for the write frequency at the i+1th time point, and determining the predicted value of the write frequency at the i+1th time point; S206: Return to S202 and iterate.

4. The method for dynamic data migration in a storage chip according to claim 3, characterized in that: The flat prediction strategy is specifically as follows: The reading frequency at this time point is used as the predicted value of the reading frequency at the next time point; The write frequency at this time point is used as the predicted value of the write frequency at the next time point.

5. The method for dynamic data migration in a storage chip according to claim 3, characterized in that: The regression prediction strategy is specifically as follows: The least squares method is used to perform linear regression fitting on the reading frequency series of the data page in the past period of time: ， Among them, fr i represents the reading frequency at the i-th time point, x i represents the time of the i-th time point, β0 represents the intercept parameter, β1 represents the slope parameter, ε i represents a reading frequency error term at the i-th time point, wherein the reading frequency error term satisfies a Gaussian distribution; According to the linear regression fitting results, the predicted value of the reading frequency at the next time point is determined; The least squares method is used to perform linear regression fitting on the write frequency series of the data page in the past period of time: ， Among them, fw i represents the writing frequency at the i-th time point, x i represents the time of the i-th time point, α0 represents the intercept parameter, α1 represents the slope parameter, τ i represents a write frequency error term at the i-th time point, wherein the write frequency error term satisfies a Gaussian distribution; According to the linear regression fitting result, the predicted value of the write frequency at the next time point is determined.

6. The method for dynamic data migration in a storage chip according to claim 1, characterized in that: The S7 specifically includes: S701: sorting the candidate pages in the candidate page list; S702: According to the sorting result, determine the potential benefits of migrating each candidate page to other memory units in terms of access response time and energy consumption; S703: Migrate the candidate page to the memory unit with the greatest potential benefit.

7. The method for dynamic data migration in a storage chip according to claim 6, characterized in that: The S701 specifically includes: S7011: Calculate the comprehensive read / write frequency prediction value of each candidate page in the candidate page list: ， Among them, f k represents the comprehensive read and write frequency prediction value of the kth candidate page, fr k represents the predicted reading frequency of the kth candidate page, fw k represents the predicted value of the write frequency of the kth candidate page, η i represents the balance parameter of the i-th memory cell storing the k-th candidate page; ， Among them, tr i Indicates the time required for the i-th memory unit to read a page, tw i represents the time required for the i-th memory unit to write a page; S7012: Arrange the candidate pages in the candidate page list in descending order according to the order of the comprehensive read / write frequency prediction values ​​from high to low.

8. The method for dynamic data migration in a storage chip according to claim 6, characterized in that: The potential benefits are as follows: ， Among them, P ijk represents the potential benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, BT ijk represents the access response time benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, BE ijk represents the energy consumption benefit of migrating the kth candidate page from the i-th memory unit to the j-th memory unit.

9. The method for dynamic data migration in a storage chip according to claim 1, characterized in that: The S7 is specifically: With the goal of improving access response time and reducing energy consumption, the best migration plan is determined by the fireworks algorithm, and each candidate page in the candidate page list is migrated.

10. A dynamic data migration system in a storage chip, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the method for dynamic data migration in a memory chip as described in any one of claims 1 to 9 is implemented.

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