Ferroelectric storage array and preparation method thereof, memory and electronic equipment

Abstract

The invention provides a ferroelectric storage array and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and aims to enlarge a read-write data window of the memory and reduce power consumption of the memory. The ferroelectric storage array comprises a plurality of storage units, each storage unit comprises a ferroelectric capacitor and a transistor, the ferroelectric capacitor comprises a first electrode and a second electrode which are oppositely arranged, and a ferroelectric layer and an insertion layer which are located between the first electrode and the second electrode. An insertion layer can be arranged between the ferroelectric layer and the first electrode, or between the ferroelectric layer and the second electrode, or between the ferroelectric layer and the first electrode and between the ferroelectric layer and the second electrode. The intercalation layer comprises electric dipoles, and the electric dipoles are distributed on the two opposite surfaces of the intercalation layer in the direction from the first electrode to the second electrode. The ferroelectric memory array can be applied to a ferroelectric random access memory to realize reading and writing of data.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a ferroelectric memory array and a preparation method thereof, a memory, and an electronic device. Background Art

[0002] Ferroelectric Random Access Memory (FeRAM), as a new type of memory, has attracted widespread attention due to its non-volatility of stored data, fast access rate, low read and write voltage, and low power consumption.

[0003] Typically, a ferroelectric random access memory includes a ferroelectric capacitor, which includes two electrodes disposed opposite to each other and a ferroelectric layer disposed between the two electrodes. Currently, mainstream materials for the ferroelectric layer include hafnium oxide-based ferroelectric materials, which still have ferroelectric properties at a relatively small thickness.

[0004] Based on the above architecture, how to increase the read and write data window of the memory and reduce the power consumption of the memory has become an urgent problem to be solved in the field. Summary of the invention

[0005] The embodiments of the present application provide a ferroelectric memory array and a method for preparing the same, a memory, and an electronic device, aiming to increase the read and write data window of the memory and reduce the power consumption of the memory.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a ferroelectric memory array is provided, which can be a two-dimensional structure or a three-dimensional structure. Furthermore, the ferroelectric memory array can be applied to a ferroelectric random access memory, a ferroelectric field effect transistor memory, or a ferroelectric tunnel junction memory to realize reading and writing of data.

[0008] The ferroelectric memory array includes a plurality of memory cells arranged in an array, each memory cell includes a ferroelectric capacitor and a transistor, and the ferroelectric capacitor includes a first electrode and a second electrode arranged opposite to each other, and a ferroelectric layer and an intercalation layer located between the first electrode and the second electrode. An intercalation layer may be provided between the ferroelectric layer and the first electrode, and an intercalation layer may also be provided between the ferroelectric layer and the second electrode, or an intercalation layer may be provided between the ferroelectric layer and the first electrode and between the ferroelectric layer and the second electrode. When the first electrode and the second electrode do not receive a voltage signal, the intercalation layer includes an electric dipole, that is, the intercalation layer can generate an electric dipole according to its material properties in the absence of an external electric field, and the electric dipole is distributed on two opposite surfaces of the intercalation layer along the direction from the first electrode to the second electrode.

[0009] In the above-mentioned embodiments of the present application, an intercalation layer is provided between the ferroelectric layer and the electrode (the first electrode or the second electrode), and electric dipoles are distributed on two opposite surfaces of the intercalation layer along the direction from the first electrode to the second electrode, and the electric dipoles can generate an electric field. In the process of preparing the ferroelectric layer, under the guidance of the electric field generated by the electric dipole, the polarization axis of the ferroelectric material of the ferroelectric layer is arranged along the electric field direction of the electric dipole, which is conducive to improving the spontaneous polarization characteristics of the ferroelectric material.

[0010] Moreover, when the external electric field generated by the first electrode and the second electrode is reversed, the electric dipoles in the intercalation layer can undergo charge migration in response to the reversal of the external electric field, thereby increasing the amount of polarization charge. The total amount of polarization induced current is equal to the induced current generated by the polarization of the ferroelectric material and the induced current of the electric dipole, thereby increasing the residual polarization intensity of the ferroelectric material and the distinction between positive and negative polarization states, and increasing the read and write data window of the memory equipped with the ferroelectric capacitor.

[0011] In addition, ferroelectric materials undergo ferroelectric flipping under the action of an inverted external electric field. The electric field generated by the electric dipole can serve as a "depolarization electric field" to assist the ferroelectric flipping, thereby improving the efficiency of the ferroelectric flipping and reducing the coercive field of the ferroelectric material. The external electric field required for the ferroelectric flipping is reduced, thereby reducing the operating voltage of the ferroelectric capacitor, which is beneficial to reducing the power consumption of the memory.

[0012] In some embodiments, the intercalation layer includes at least one first sub-intercalation layer and at least one second sub-intercalation layer, and the first sub-intercalation layer and the second sub-intercalation layer are alternately arranged in a direction from the first electrode to the second electrode. The dielectric constant of the material of the first sub-intercalation layer is different from the dielectric constant of the material of the second sub-intercalation layer, and the dielectric constant of the material at the surface where the first sub-intercalation layer intersects with the second sub-intercalation layer changes. The first sub-intercalation layer and the second sub-intercalation layer are stacked in a superlattice manner, so that two opposite surfaces of the first sub-intercalation layer generate electric dipoles, and two opposite surfaces of the second sub-intercalation layer generate electric dipoles.

[0013] In some embodiments, the intercalation layer is doped with elements, and the doped elements include at least one of niobium, titanium, hafnium, zirconium, lanthanum, yttrium, strontium, silicon, germanium, tantalum or tungsten. By doping the intercalation layer with elements, the intrinsic parameters of the material of the intercalation layer can be changed, so that high-concentration, low-energy-level defects are introduced into the material to generate electric dipoles in the intercalation layer.

[0014] In some embodiments, the material of the intercalation layer includes a piezoelectric material. According to the piezoelectric effect, when the intercalation layer is subjected to pressure, two opposite surfaces of the intercalation layer will generate electric dipoles.

[0015] In some embodiments, the material of the intercalation layer includes a pyroelectric material, which is also a piezoelectric material. Pyroelectric materials can generate electric dipoles when heated or pressed.

[0016] In some embodiments, the material of the intercalation layer includes a ferroelectric material, which is a branch of a pyroelectric material. Therefore, the ferroelectric material can generate an electric dipole when heated or pressed. In addition, during the process of depositing the ferroelectric material to form the intercalation layer, an electric dipole may also be generated in the intercalation layer.

[0017] In addition, the above-mentioned piezoelectric materials, pyroelectric materials or ferroelectric materials all have a negative capacitance effect, and these materials all belong to negative capacitance materials. According to the negative capacitance effect, when the first electrode and the second electrode receive a voltage signal and generate an external electric field, the electrons in the intercalation layer will migrate to the surface of the intercalation layer under the action of the external electric field. The surface is distributed with negative charges, and the other surface opposite to the surface is distributed with positive charges, thereby generating electric dipoles on the two opposite surfaces of the intercalation layer.

[0018] In some embodiments, the material of the intercalation layer may include at least one of a piezoelectric material, a pyroelectric material, a ferroelectric material, or a negative capacitance material. In the absence of an external electric field, the intercalation layer may generate an electric dipole according to the respective material properties.

[0019] In some embodiments, the material of the intercalation layer includes at least one of titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, barium oxide, cerium oxide, gadolinium oxide, aluminum oxide, hafnium oxide, zirconium oxide, silicon nitride, titanium nitride, niobium nitride, tantalum nitride, hafnium nitride, zirconium nitride, strontium titanate, barium titanate, lanthanum aluminate, lithium niobate, or lithium tantalate.

[0020] In some embodiments, the thickness of the intercalation layer ranges from 0.5 nm to 5 nm. Compared with the thickness of the ferroelectric layer, the thickness of the intercalation layer is thinner, which can reduce the voltage division effect of the intercalation layer and avoid the operating voltage of the ferroelectric capacitor being too high due to the setting of the intercalation layer.

[0021] In some embodiments, the first electrode and the second electrode are both planar electrodes, and the first electrode, the ferroelectric layer, the intercalation layer and the second electrode are stacked. The ferroelectric capacitor is a two-dimensional planar structure with a simple structure and is easy to prepare.

[0022] In some embodiments, the first electrode is a planar electrode, the second electrode is a columnar electrode, the second electrode passes through the first electrode, the ferroelectric layer and the intercalation layer are arranged around the second electrode, and the ferroelectric capacitor is a three-dimensional vertical structure, which can reduce its occupied area in the plane, thereby increasing the number of ferroelectric capacitors per unit area in the plane, thereby increasing the number of storage units per unit area, which is beneficial to improving the storage density of the ferroelectric memory.

[0023] In some embodiments, the thermal expansion coefficient of the material of the first electrode is different from the thermal expansion coefficient of the material of the second electrode. During the annealing and crystallization of the ferroelectric layer, the high temperature will cause the first electrode and the second electrode to expand. Due to the different thermal expansion coefficients of the two materials, the deformations produced by the two are different, which can generate an interaction force. In the case where the intercalation layer uses a piezoelectric material, the interaction force is applied to the intercalation layer, which can generate an electric dipole in the intercalation layer.

[0024] In a second aspect, a method for preparing a ferroelectric memory array is provided, the method comprising: sequentially forming a first electrode, a ferroelectric layer, and a second electrode, the first electrode and the second electrode being arranged opposite to each other, and the ferroelectric layer being located between the first electrode and the second electrode. After forming the first electrode and before forming the ferroelectric layer, an intercalation layer is also formed. And / or, after forming the ferroelectric layer and before forming the second electrode, an intercalation layer is also formed. The intercalation layer includes an electric dipole, and the electric dipole is distributed on two opposite surfaces of the intercalation layer along the direction from the first electrode to the second electrode.

[0025] The preparation method provided by the above embodiment of the present application sequentially forms a first electrode, a ferroelectric layer, and a second electrode, and forms an intercalation layer between the first electrode and the ferroelectric layer, and between the ferroelectric layer and the second electrode. Electric dipoles are distributed on two opposite surfaces of the intercalation layer in the direction from the first electrode to the second electrode, and the electric dipoles can generate an electric field.

[0026] In the process of forming the ferroelectric layer, under the guidance of the electric field generated by the electric dipole, the polarization axis of the ferroelectric material of the ferroelectric layer is arranged along the electric field direction of the electric dipole, which is beneficial to improving the spontaneous polarization characteristics of the ferroelectric material.

[0027] In a third aspect, a memory is provided, which includes the ferroelectric memory array in any of the above embodiments, and a controller electrically connected to the ferroelectric memory array.

[0028] In a fourth aspect, an electronic device is provided, such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. The electronic device includes a circuit board and the memory in the above embodiment, and the memory is electrically connected to the circuit board.

[0029] It can be understood that the beneficial effects that can be achieved by the memory and electronic device provided by the above embodiments of the present application can refer to the beneficial effects of the ferroelectric memory array mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0031] Figure 1 An architecture diagram of an electronic device provided in an embodiment of the present application;

[0032] Figure 2 An exploded diagram of an electronic device provided in an embodiment of the present application;

[0033] Figure 3 An architectural diagram of a ferroelectric random access memory provided in an embodiment of the present application;

[0034] Figure 4 A circuit diagram of a storage unit provided in an embodiment of the present application;

[0035] Figure 5 A structural diagram of a ferroelectric capacitor in the related art;

[0036] Figure 6 to Figure 8 Structural diagrams of various ferroelectric capacitors provided in embodiments of the present application;

[0037] Fig. 9 and Fig.10 A hysteresis loop diagram of a ferroelectric capacitor provided in an embodiment of the present application;

[0038] Fig.11 and Fig.12 Structural diagrams of various ferroelectric capacitors provided in embodiments of the present application;

[0039] Figures 13A to 13E A diagram of the steps of preparing a ferroelectric capacitor provided in an embodiment of the present application;

[0040] Figures 14A to 14E A diagram of the steps of preparing a ferroelectric capacitor provided in an embodiment of the present application;

[0041] Fig.15 A three-dimensional structural diagram of a ferroelectric capacitor provided in an embodiment of the present application;

[0042] Figures 16A to 16G A diagram of the steps for preparing a ferroelectric capacitor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0044] Some embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, a radar, an aerospace equipment, and a vehicle-mounted device, etc., and may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0045] Figure 1 An architectural diagram of an electronic device provided in accordance with an embodiment of the present application.

[0046] See also Figure 1 The electronic device 1 includes: a storage device 11, a processor 12, an input device 13, an output device 14 and other components. Those skilled in the art can understand that Figure 1 The architecture of the electronic device 1 shown in the figure does not constitute a limitation on the electronic device 1, and the electronic device 1 may include, for example Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0047] The storage device 11 is used to store software programs and modules. The storage device 11 mainly includes a program storage area and a data storage area, wherein the program storage area can store and back up an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.), etc. In addition, the storage device 11 includes an external memory 111 and an internal memory 112. The data stored in the external memory 111 and the internal memory 112 can be transmitted to each other.

[0048] The external memory 111 may include, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 112 may include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a resistance random access memory (RRAM), a phase change random access memory (PCRAM), a ferroelectric random access memory (FeRAM), a ferroelectric field effect transistor (FeFET) memory, a ferroelectric tunnel junction (FTJ) memory, a NAND flash memory, etc.

[0049] The processor 12 is the control center of the electronic device 1. It uses various interfaces and lines to connect various parts of the entire electronic device 1. By running or executing software programs and / or modules stored in the storage device 11, and calling data stored in the storage device 11, it executes various functions of the electronic device 1 and processes data, thereby monitoring the electronic device 1 as a whole. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (AP), a modem processor, a graphics processor (GPU), etc. Among them, different processing units may be independent devices or integrated into one or more processors. For example, the processor 12 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and an application program, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 12. The above-mentioned application processor may be, for example, a central processing unit (CPU). Figure 1 In the example, the processor 12 is a CPU, which may include an operator 121 and a controller 122. The operator 121 obtains data stored in the internal memory 112, processes the data stored in the internal memory 112, and generally sends the processed result back to the internal memory 112. The controller 122 may control the operator 121 to process the data, and the controller 122 may also control the external memory 111 and the internal memory 112 to read or write data.

[0050] The input device 13 is used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device. For example, the input device 13 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect the user's touch operations on or near the touch screen (such as the user's operation on or near the touch screen using any suitable object or accessory such as a finger, stylus, etc.), and drive the corresponding connection device according to a pre-set program. The controller 122 in the above-mentioned processor 12 can also control the input device 13 to receive input signals or not receive input signals. In addition, the input digital or character information received by the input device 13, and the key signal input related to the user settings and function control of the electronic device can be stored in the internal memory 112.

[0051] The output device 14 is used to output the input of the input device 13 and the signal corresponding to the data stored in the internal memory 112. For example, the output device 14 outputs a sound signal or a video signal. The controller 122 in the processor 12 can also control the output device 14 to output a signal or not output a signal.

[0052] It should be noted that Figure 1 The thick arrows in the figure are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, the single arrow between the input device 13 and the internal memory 112 indicates that the data received by the input device 13 is transmitted to the internal memory 112. For another example, the double arrows between the operator 121 and the internal memory 112 indicate that the data stored in the internal memory 112 can be transmitted to the operator 121, and the data processed by the operator 121 can be transmitted to the internal memory 112. Figure 1 The thin arrows in the figure represent components that can be controlled by the controller 122. For example, the controller 122 can control the external memory 111, the internal memory 112, the operator 121, the input device 13, the output device 14, and the like.

[0053] In order to further explain the structure of the electronic device 1 , the following is an exemplary introduction using the electronic device 1 as a mobile phone as an example.

[0054] Figure 2 An exploded diagram of an electronic device provided in an embodiment of the present application.

[0055] See also Figure 2 The electronic device 1 may further include a middle frame 15, a rear shell 16, and a display screen 17. The rear shell 16 and the display screen 17 are located on opposite sides of the middle frame 15, and the middle frame 15 and the display screen 17 are disposed inside the rear shell 16. The middle frame 15 includes a carrier plate 150 for carrying the display screen 17, and a frame 151 surrounding the carrier plate 150.

[0056] Continue to see Figure 2 The electronic device 1 may further include a circuit board 18 , which is disposed on a side of the carrier board 150 close to the rear shell 16 . The storage device 11 in the electronic device 1 may be disposed on the circuit board 18 , and the memory in the storage device 11 is electrically connected to the circuit board 18 .

[0057] The following embodiments are described by taking a ferroelectric random access memory as an example. Figure 3 This is an architectural diagram of a ferroelectric random access memory provided in an embodiment of the present application.

[0058] See also Figure 3 The ferroelectric random access memory includes a ferroelectric memory array 210, a decoder 220, a driver 230, a timing controller 240, a buffer 250 and an input / output interface 260. The ferroelectric memory array 210 includes a plurality of memory cells 200 arranged in an array.

[0059] Figure 4 A circuit diagram of a storage unit provided in an embodiment of the present application.

[0060] See also Figure 4 The memory cell 200 includes a circuit architecture based on a ferroelectric capacitor. The memory cell 200 has a 1T1C (1-Transistor-1-Capacitor) structure, that is, the memory cell 200 includes a transistor T and a ferroelectric capacitor C. The source of the transistor T is electrically connected to the bit line (Bit Line, BL), the drain is electrically connected to an electrode of the ferroelectric capacitor C, the gate is electrically connected to the word line (Word Line, WL), and the other electrode of the ferroelectric capacitor C is electrically connected to the plate line (Plate Line, PL). The circuit architecture of the memory cell 200 in the embodiment of the present application is not limited to this.

[0061] Based on this, the decoder 220 can decode according to the received address to determine the storage unit 200 in the ferroelectric storage array 210 that needs to be accessed. The driver 230 is used to generate a control signal according to the decoding result output by the decoder 220, and the control signal is transmitted to the gate of the transistor T in the storage unit 200 through the word line WL to control the transistor T to be turned on or off, thereby achieving access to the specified storage unit 200. The buffer 250 receives the data signal output by the storage unit 200, and is used to cache the data signal, for example, First-In First-Out (FIFO) can be used for caching. The timing controller 240 is used to control the timing of the buffer 250, and control the driver 230 to drive the ferroelectric storage array 210. The input and output interface 260 is used to transmit data signals, such as receiving data signals or sending data signals.

[0062] The ferroelectric memory array 210 , decoder 220 , driver 230 , timing controller 240 , buffer 250 and input / output interface 260 may be integrated into one chip or may be integrated into multiple chips.

[0063] The working principle of ferroelectric random access memory is introduced below in combination with the structure of ferroelectric capacitors.

[0064] Figure 5 FIG. 4 is a structural diagram of a ferroelectric capacitor in the related art.

[0065] See also Figure 5 The ferroelectric capacitor C' comprises a first electrode 01' and a second electrode 02' which are arranged opposite to each other, and a ferroelectric film 03' arranged between the first electrode 01' and the second electrode 02'. The ferroelectric capacitor C' has a metal-insulator-metal (Metal-Insulator-Metal) MIM structure. The ferroelectric film 03' comprises a ferroelectric material, and the ferroelectric material has a spontaneous polarization characteristic.

[0066] Specifically, the ferroelectric material has ferroelectric phase crystals. When the first electrode 01' and the second electrode 02' receive a voltage signal and generate an external electric field, the external electric field is applied to the ferroelectric film 03', and the central atoms of the orthorhombic phase unit cell in the ferroelectric material move along the external electric field and stop at a low energy state, and the polarization state can be, for example, a "0" storage state. A large number of central atoms move and couple in the unit cell to form ferroelectric domains, and the ferroelectric domains will form polarized charges under the action of the external electric field.

[0067] Ferroelectric materials have a coercive field (Ec). When the external electric field generated by the first electrode 01' and the second electrode 02' is reversed and is greater than the coercive field, the central atom moves in the unit cell along the direction of the external electric field and stops at another low-energy state. This polarization state can be, for example, a "1" storage state, that is, the ferroelectric domain is directionally flipped under the action of the reversed external electric field.

[0068] The polarization charge energy formed by the ferroelectric domains before and after the external electric field is reversed is different. This positive and negative polarization state will cause the ferroelectric capacitor C' to charge and discharge and generate current, which can then be recognized by an external sensing amplifier to determine whether the storage unit 200 is in a storage state of "0" or "1", thereby realizing the reading or writing of data by the ferroelectric random access memory.

[0069] Moreover, when the external electric field is removed, the polarization state of the ferroelectric material can be maintained, making the ferroelectric random access memory non-volatile in storing data.

[0070] However, after multiple directional flips, the polarization intensity of the ferroelectric domain will decrease. Specifically, the ferroelectric random access memory will perform a large number of edit / erase operations when reading and writing data. The ferroelectric domains in the ferroelectric layer 03' are constantly flipped. After multiple cycles, the remnant polarization (Pr) of the ferroelectric domains in the ferroelectric layer 03' decreases, and the coercive field increases. The smaller the remnant polarization, the smaller the amount of polarization charge, resulting in the "0" or "1" two states becoming closer and closer, and the distinction between the positive and negative polarization states of the ferroelectric layer 03' decreases, and finally becomes difficult to distinguish, increasing the error rate of reading and writing data in the ferroelectric random access memory equipped with the ferroelectric capacitor C'. In addition, the larger the coercive field, the larger the external electric field used for reversal, and the larger the operating voltage of the ferroelectric capacitor C', resulting in higher power consumption of the memory, lower read / write life, and poor anti-interference ability.

[0071] To solve the above problems, an embodiment of the present application provides a ferroelectric capacitor. Figure 6 to Figure 8 Structural diagrams of various ferroelectric capacitors provided in embodiments of the present application.

[0072] See also Figure 6 The ferroelectric capacitor C includes a first electrode 01 and a second electrode 02 that are oppositely disposed, and a ferroelectric layer 03 and an intercalation layer 04 that are located between the first electrode 01 and the second electrode 02 .

[0073] The ferroelectric capacitor C can have a two-dimensional planar structure, wherein the first electrode 01 and the second electrode 02 are both planar electrodes, and the two planar electrodes are arranged opposite to each other. The first electrode 01, the ferroelectric layer 03, the intercalation layer 04 and the second electrode 02 are arranged in a stacked manner, and the ferroelectric capacitor C has a simple structure and is easy to prepare.

[0074] Exemplarily, the materials of the first electrode 01 and the second electrode 02 may include at least one of titanium nitride, tantalum nitride, and tungsten.

[0075] Exemplarily, the material of the ferroelectric layer 03 includes a hafnium oxide-based fluorite material, and the hafnium oxide-based fluorite material may include hafnium zirconium oxide (HZO), hafnium silicon oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium lanthanum oxide, hafnium zirconium cerium oxide, hafnium yttrium oxide, hafnium zirconium gadolinium oxide, etc. Compared with traditional ferroelectric materials, hafnium oxide-based materials have stable ferroelectric switching properties, which can improve the charge and discharge performance of the ferroelectric capacitor C.

[0076] In addition, the preparation process of the ferroelectric layer 03 using hafnium oxide-based fluorite material has good compatibility with the preparation process of complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, referred to as CMOS), and can reduce the thickness of the ferroelectric layer 03 to ten nanometers or even less than ten nanometers, and can maintain the spontaneous polarization characteristics of the ferroelectric layer 03, which is conducive to the miniaturization of the ferroelectric capacitor C.

[0077] See also Figure 6 The intercalation layer 04 may be disposed between the ferroelectric layer 03 and the first electrode 01, which is equivalent to inserting the intercalation layer 04 between the ferroelectric layer 03 and the first electrode 01. The number of the intercalation layers 04 is not limited and may be one or more.

[0078] See also Figure 7 The intercalation layer 04 may also be disposed between the ferroelectric layer 03 and the second electrode 02, which is equivalent to inserting the intercalation layer 04 between the ferroelectric layer 03 and the second electrode 02. The number of the intercalation layers 04 is not limited and may be one or more.

[0079] See also Figure 8 The intercalation layer 04 can be arranged between the ferroelectric layer 03 and the first electrode 01, or between the ferroelectric layer 03 and the second electrode 02. This is equivalent to inserting the intercalation layer 04 between the ferroelectric layer 03 and the first electrode 01, or between the ferroelectric layer 03 and the second electrode 02.

[0080] In the case where the first electrode 01 and the second electrode 02 do not receive a voltage signal, the above-mentioned intercalation layer 04 includes an electric dipole, that is, the intercalation layer 04 can generate an electric dipole according to its material properties in the absence of an external electric field (hereinafter described according to the material selection of the intercalation layer 04), and the electric dipole is a system composed of two point charges of equal magnitude and opposite signs. For example, along the direction from the first electrode 01 to the second electrode 02, that is, along the direction Z, the intercalation layer 04 includes two opposite surfaces, and the positively charged point charges and the negatively charged point charges are respectively distributed near the two surfaces of the intercalation layer 04. An electric field can be generated between the positively charged point charges and the negatively charged point charges, and the direction of the electric field can be, for example, along the direction Z. Therefore, there is a potential difference between the opposite ends of the intercalation layer 04 along the direction Z.

[0081] For example, see Figure 8When an intercalation layer 04 is provided between the ferroelectric layer 03 and the first electrode 01, and between the ferroelectric layer 03 and the second electrode 02, the positive point charges in the upper intercalation layer 04 and the negative point charges in the lower intercalation layer 04 can be combined to form a "long-range" electric dipole. Similarly, the negative point charges in the upper intercalation layer 04 and the positive point charges in the lower intercalation layer 04 can also be combined to form a "long-range" electric dipole. The "long-range" electric dipole can generate an electric field. Therefore, there is also a potential difference between the upper intercalation layer 04 and the lower intercalation layer 04.

[0082] The ferroelectric capacitor C provided in the above-mentioned embodiment of the present application is formed by inserting an intercalation layer 04 between the ferroelectric layer 03 and the electrode (the first electrode 01 or the second electrode 02). The intercalation layer 04 can form an electric dipole at its interface, and the electric dipole can generate an electric field. In the process step (crystallization) of preparing the ferroelectric layer 03, under the guidance of the electric field generated by the electric dipole, the polarization axis of the ferroelectric material is arranged along the electric field direction of the electric dipole, which is beneficial to improving the spontaneous polarization characteristics of the ferroelectric material.

[0083] Moreover, when the external electric field generated by the first electrode 01 and the second electrode 02 is reversed, the electric dipoles in the intercalation layer 04 can undergo charge migration in response to the reversal of the external electric field, thereby increasing the amount of polarization charge. The total amount of polarization induced current is equal to the induced current generated by the polarization of the ferroelectric material and the induced current of the electric dipole, thereby increasing the residual polarization intensity, increasing the distinction between the positive and negative polarization states of the ferroelectric layer 03, and increasing the window for reading and writing data of the ferroelectric random access memory equipped with the ferroelectric capacitor C, which is particularly important for small-size devices with high-density integration.

[0084] In addition, the intercalation layer 04 can also generate more electric dipoles in response to an external electric field. The ferroelectric domains are directionally flipped under the action of the reversed external electric field. The electric field generated by the electric dipoles can serve as a "depolarization electric field" to assist the ferroelectric domain flipping, thereby improving the efficiency of the ferroelectric domain flipping and reducing the coercive field of the ferroelectric material. The external electric field required for the ferroelectric domain to flip is reduced, thereby reducing the operating voltage of the ferroelectric capacitor C, which is beneficial to reducing the power consumption of the memory.

[0085] To verify the above conclusion, the hysteresis loops of a ferroelectric capacitor without an intercalation layer and a ferroelectric capacitor with an intercalation layer can be tested and compared.

[0086] Fig. 9 and Fig.10 The hysteresis loop diagram of the ferroelectric capacitor provided in the embodiment of the present application, wherein the horizontal axis is the electric field strength generated by the first electrode 01 and the second electrode 02, the unit is "MV / cm"; the vertical axis is the residual polarization strength of the ferroelectric layer, the unit is "μC / cm 2"; Curve "1" is the hysteresis loop of the ferroelectric capacitor without an intercalation layer; Curve "2" is the hysteresis loop of the ferroelectric capacitor with an intercalation layer.

[0087] See also Fig. 9 The maximum value of the residual polarization intensity corresponding to curve "2" is greater than the maximum value of the residual polarization intensity corresponding to curve "1", which means that the degree of differentiation between the positive and negative polarization states of the ferroelectric layer in the ferroelectric capacitor with an intercalation layer is greater than the degree of differentiation between the positive and negative polarization states of the ferroelectric layer in the ferroelectric capacitor without an intercalation layer, thus indicating that the setting of the intercalation layer can increase the window for reading and writing data.

[0088] See also Fig.10 When the residual polarization intensity is 0, the maximum value of the electric field intensity corresponding to curve "2" is smaller than the maximum value of the electric field intensity corresponding to curve "2", indicating that the coercive field Ec of the ferroelectric layer in the ferroelectric capacitor with an intercalation layer is smaller than the coercive field Ec of the ferroelectric layer in the ferroelectric capacitor without an intercalation layer. This shows that the setting of the intercalation layer can reduce the coercive field of the ferroelectric layer, and the electric field intensity of the external electric field required for ferroelectric switching is reduced.

[0089] Next, the configuration of the intercalation layer 04 and how to form an electric dipole are introduced.

[0090] Insert 04 can be a single film layer, please continue to see Figure 6 to Figure 8 The material of the intercalation layer 04 may include a piezoelectric material. According to the piezoelectric effect, for example, along the direction Z, when the intercalation layer 04 is subjected to pressure, two opposite surfaces of the intercalation layer 04 will generate electric dipoles.

[0091] Alternatively, the material of the intercalation layer 04 may include a pyroelectric material, whose crystal does not have central symmetry, and the pyroelectric material is also a piezoelectric material. The pyroelectric material can generate electric dipoles when heated or pressed.

[0092] Alternatively, the material of the intercalation layer 04 may include ferroelectric material, which is a branch of pyroelectric material. Therefore, ferroelectric material can generate electric dipoles when heated or pressed. In addition, in the process of depositing ferroelectric material to form the intercalation layer 04, electric dipoles may also be generated in the intercalation layer 04.

[0093] In addition, the above-mentioned piezoelectric materials, pyroelectric materials or ferroelectric materials all have a negative capacitance effect, and these materials all belong to negative capacitance materials. According to the negative capacitance effect, when the first electrode 01 and the second electrode 02 receive a voltage signal and generate an external electric field, the electrons in the intercalation layer 04 will migrate to the surface of the intercalation layer 04 under the action of the external electric field. The surface is distributed with negative charges, and the other surface opposite to the surface is distributed with positive charges, thereby generating electric dipoles on the two opposite surfaces of the intercalation layer 04.

[0094] In some embodiments, the material of the intercalation layer 04 may include one or more of piezoelectric material, pyroelectric material, ferroelectric material or negative capacitance material. In the absence of an external electric field, the intercalation layer 04 may generate an electric dipole according to its respective material properties.

[0095] In some embodiments, the thermal expansion coefficient of the material of the first electrode 01 is different from the thermal expansion coefficient of the material of the second electrode 02. During the annealing and crystallization process of the ferroelectric layer 03, the high temperature will cause the first electrode 01 and the second electrode 02 to expand. Since the thermal expansion coefficients of the two materials are different, the deformations produced by the two are different, which can generate an interaction force along the direction Z. The interaction force can be applied to the intercalation layer 04 to generate an electric dipole in the intercalation layer 04.

[0096] Exemplarily, the material of one of the first electrode 01 and the second electrode 02 includes titanium nitride, and the material of the other includes tungsten. The thermal expansion coefficients of titanium nitride and tungsten are different.

[0097] Alternatively, in some embodiments, the main material of the intercalation layer 04 includes a piezoelectric material, a pyroelectric material, or a ferroelectric material. In this case, the intercalation layer 04 is also doped with elements, and the doped elements may include at least one of niobium, titanium, hafnium, zirconium, lanthanum, yttrium, strontium, silicon, germanium, tantalum, or tungsten. By doping elements into the intercalation layer 04, the intrinsic parameters of the material of the intercalation layer 04 can be changed, so that high-concentration, low-energy-level defects are introduced into the material to generate an electric dipole in the intercalation layer 04, thereby generating a potential difference at the opposite ends of the intercalation layer 04.

[0098] Exemplarily, the main material of the intercalation layer 04 may include one or more of titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, barium oxide, cerium oxide, gadolinium oxide, aluminum oxide, hafnium oxide, zirconium oxide, silicon nitride, titanium nitride, niobium nitride, tantalum nitride, hafnium nitride, zirconium nitride, strontium titanate, barium titanate, lanthanum aluminate, lithium niobate or lithium tantalate.

[0099] Exemplarily, the thickness of the intercalation layer 04 may range from 0.5 nm to 5 nm, for example, the thickness of the intercalation layer 04 is 0.5 nm, 1 nm, 2 nm, 2.5 nm, 3 nm, 4 nm or 5 nm. Compared with the thickness of the ferroelectric layer 03, the thickness of the intercalation layer 04 is thinner, which can reduce the voltage-dividing effect of the intercalation layer 04 and avoid the operating voltage of the ferroelectric capacitor C being too high due to the setting of the intercalation layer 04.

[0100] The intercalation layer 04 can also be a composite film layer. Fig.11 and Fig.12 Structural diagrams of various ferroelectric capacitors provided in embodiments of the present application.

[0101] See also Fig.11 and Fig.12The intercalation layer 04 includes at least one first sub-intercalation layer 04a and at least one second sub-intercalation layer 04b. Along the direction from the first electrode 01 to the second electrode 02, for example, along the direction Z, the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are alternately arranged.

[0102] The thickness of the first sub-intercalation layer 04a and the thickness of the second sub-intercalation layer 04b may be the same or different, and the figure shows the case where the thickness of the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are the same. The number of the first sub-intercalation layer 04a and the number of the second sub-intercalation layer 04b may be the same or different, and the figure shows the case where the number of the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are the same, that is, the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are arranged in pairs.

[0103] For example, see Fig.11 The intercalation layer 04 includes a first sub-intercalation layer 04a and a second sub-intercalation layer 04b, and the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are stacked.

[0104] For example, see Fig.12 The intercalation layer 04 includes a plurality of first sub-intercalation layers 04a and a plurality of second sub-intercalation layers 04b, and the first sub-intercalation layers 04a and the second sub-intercalation layers 04b are alternately stacked.

[0105] Furthermore, the dielectric constant of the material of the first sub-interlayer 04a is different from the dielectric constant of the material of the second sub-interlayer 04b, and the dielectric constant of the material at the surface where the first sub-interlayer 04a contacts the second sub-interlayer 04b changes. The first sub-interlayer 04a and the second sub-interlayer 04b are stacked in a superlattice manner, and along the direction Z, electric dipoles are generated on the two opposite surfaces of the first sub-interlayer 04a, and electric dipoles are generated on the two opposite surfaces of the second sub-interlayer 04b.

[0106] The first sub-intercalation layer 04a and the second sub-intercalation layer 04b are arranged alternately. At the surfaces where the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are in contact, positive charges and negative charges attract each other. The charges distributed at the surface of the first sub-intercalation layer 04a away from the second sub-intercalation layer 04b are opposite in positive and negative charge to the charges distributed at the surface of the second sub-intercalation layer 04b away from the first sub-intercalation layer 04a, and can be combined to form a "long-range" electric dipole.

[0107] From the overall perspective of the stacking structure of intercalation layer 04, the charges distributed on the top surface of the uppermost sub-intercalation layer in the stacking structure are opposite in positive and negative charge to the charges distributed on the bottom surface of the lowermost sub-intercalation layer in the stacking structure, and can be combined to form a "long-range" electric dipole, so that electric dipoles are generated on the top and bottom surfaces of intercalation layer 04, thereby generating an electric potential difference at the opposite ends of intercalation layer 04.

[0108] Exemplarily, the material of the first sub-intercalation layer 04a may include titanium oxide, and the material of the second sub-intercalation layer 04b may include niobium oxide. The dielectric constants of titanium oxide and niobium oxide are different, so that the two are stacked in a superlattice manner, so that electric dipoles are generated on the two opposite surfaces of the first sub-intercalation layer 04a, and electric dipoles are generated on the two opposite surfaces of the second sub-intercalation layer 04b.

[0109] The present application embodiment provides Figure 8 The preparation method of the ferroelectric capacitor C is shown in Figures 13A to 13E A diagram of the steps for preparing a ferroelectric capacitor provided in an embodiment of the present application.

[0110] See also Fig.13A , forming a first electrode 01.

[0111] For example, a chemical vapor deposition (CVD) process may be used to deposit a metal material on a substrate (silicon wafer), and the metal material may include tungsten, for example, to form the first electrode 01 . The thickness of the first electrode 01 may be 50 nm.

[0112] Since the first electrode 01 is located on the substrate and at the bottom of the ferroelectric capacitor C, the first electrode 01 may also be referred to as a “bottom electrode”.

[0113] See also Fig. 13B , forming an intercalation layer 04, which includes an electric dipole. The electric dipole can generate an electric field. Therefore, along the direction Z, there is an electric potential difference between the opposite ends of the intercalation layer 04.

[0114] Exemplarily, a physical vapor deposition (PVD) process can be used to deposit a strontium titanate material above the first electrode 01. At the same time, niobium elements are doped into the strontium titanate material to change the intrinsic parameters of the strontium titanate material, so as to introduce high-concentration, low-energy-level defects into the material to generate electric dipoles in the intercalation layer 04. The thickness of the intercalation layer 04 can be 2 nm.

[0115] See also Fig. 13C , forming a ferroelectric layer 03.

[0116] For example, an atomic layer deposition (ALD) process may be used to deposit hafnium and zirconium on the intercalation layer 04, wherein the mass ratio of hafnium to zirconium is 1:1, so as to form a hafnium zirconium oxide (chemical formula: Hf 0.5 Zr 0.5 O2) has a ferroelectric layer 03, and the thickness of the ferroelectric layer 03 can be 10 nm.

[0117] During the process of forming the ferroelectric layer 03 , the material of the ferroelectric layer 03 will crystallize. Under the guidance of the electric field generated by the electric dipole, the polarization axis of the material can be arranged along the electric field direction of the electric dipole, which is beneficial to improving the spontaneous polarization characteristics of the material.

[0118] See also Fig.13D The same method can be used to form an intercalation layer 04 on the ferroelectric layer 03.

[0119] See also Fig.13E , forming a second electrode 02.

[0120] For example, a chemical vapor deposition process may be used to deposit tungsten on the substrate to form the second electrode 02 .

[0121] Alternatively, a physical vapor deposition process may be used to deposit titanium nitride material on the substrate to form the second electrode 02 .

[0122] The thickness of the second electrode 02 may be 50 nm. Since the second electrode 02 is located on the top of the ferroelectric capacitor C, the second electrode 02 may also be referred to as a “top electrode”.

[0123] Continue to see Fig.13E After the structure shown in the figure is formed, the structure is subjected to rapid thermal annealing so that the material of the ferroelectric layer 03 is crystallized to form a ferroelectric phase crystal. In this process, the electric field generated by the electric dipole can also guide the polarization axis of the material to be arranged along the direction of the electric field.

[0124] The preparation method provided in the above embodiment of the present application sequentially forms the first electrode 01, the ferroelectric layer 03 and the second electrode 02, and forms an intercalation layer 04 between the first electrode 01 and the ferroelectric layer 03, and forms an intercalation layer 04 between the ferroelectric layer 03 and the second electrode 02.

[0125] By doping elements into the intercalation layer 04, the intrinsic parameters of the material are changed, and high-concentration, low-energy-level defects are introduced into the material to generate electric dipoles in the intercalation layer 04. The electric dipoles can generate an electric field. During the crystallization process of the ferroelectric material of the ferroelectric layer 03, the electric field generated by the electric dipoles can guide the polarization axis of the ferroelectric material to be arranged along the direction of the electric field, which is beneficial to improving the spontaneous polarization characteristics of the ferroelectric material.

[0126] The present application also provides Fig.12 The preparation method of the ferroelectric capacitor C is shown in Figures 14A to 14E A diagram of the steps for preparing a ferroelectric capacitor provided in an embodiment of the present application.

[0127] See also Fig.14A , forming the first electrode 01, the preparation method is the same as mentioned above.

[0128] See also Fig. 14B, forming an intercalation layer 04, which includes an electric dipole. The electric dipole can generate an electric field. Therefore, along the direction Z, there is an electric potential difference between the opposite ends of the intercalation layer 04.

[0129] For example, an atomic layer deposition process may be used to deposit a niobium oxide material on the first electrode 01 to form a second sub-intercalation layer 04b. Then, an atomic layer deposition process may be used to deposit a titanium oxide material on the second sub-intercalation layer 04b to form a first sub-intercalation layer 04a. In this way, the second sub-intercalation layer 04b and the first sub-intercalation layer 04a are alternately formed, and the second sub-intercalation layer 04b and the first sub-intercalation layer 04a are stacked to form an intercalation layer 04, and the thickness of the intercalation layer 04 may be 2nm.

[0130] Alternatively, the first sub-intercalation layer 04a may be first formed on the first electrode 01, and then the second sub-intercalation layer 04b may be formed on the first sub-intercalation layer 04a, so that the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are alternately formed, which is not limited in the embodiments of the present application.

[0131] The dielectric constants of titanium oxide and niobium oxide are different, so the second sub-intercalation layer 04b and the first sub-intercalation layer 04a are stacked in a superlattice manner, so that electric dipoles are generated on two opposite surfaces of the first sub-intercalation layer 04a and electric dipoles are generated on two opposite surfaces of the second sub-intercalation layer 04b.

[0132] See also Fig. 14C , forming a ferroelectric layer 03, the preparation method is the same as mentioned above, and similarly, in the process of forming the ferroelectric layer 03, the material of the ferroelectric layer 03 will crystallize, and under the guidance of the electric field generated by the electric dipole, the polarization axis of the material can be arranged along the electric field direction of the electric dipole, which is beneficial to improving the spontaneous polarization characteristics of the material.

[0133] See also Fig.14D The same method can be used to alternately form the second sub-intercalation layer 04b and the first sub-intercalation layer 04a on the ferroelectric layer 03 to form the intercalation layer 04.

[0134] See also Fig.14E , forming the second electrode 02, the preparation method is the same as mentioned above.

[0135] Continue to see Fig.14E After the structure shown in the figure is formed, it is also necessary to perform rapid thermal annealing treatment on the structure so that the material of the ferroelectric layer 03 is crystallized to form a ferroelectric phase crystal. During this process, the electric field generated by the electric dipole can also guide the polarization axis of the material to be arranged along the direction of the electric field.

[0136] The preparation method provided in the above embodiment of the present application sequentially forms the first electrode 01, the ferroelectric layer 03 and the second electrode 02, and forms an intercalation layer 04 between the first electrode 01 and the ferroelectric layer 03, and forms an intercalation layer 04 between the ferroelectric layer 03 and the second electrode 02.

[0137] The second sub-intercalation layer 04b and the first sub-intercalation layer 04a are alternately formed, and the second sub-intercalation layer 04b and the first sub-intercalation layer 04a are stacked to form the intercalation layer 04. The dielectric constants of the materials of the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are different, and the dielectric constant of the intersection of the first sub-intercalation layer 04a and the second sub-intercalation layer 04b changes, so that electric dipoles are generated on the two opposite surfaces of the first sub-intercalation layer 04a, and electric dipoles are generated on the two opposite surfaces of the second sub-intercalation layer 04b. The electric dipole can generate an electric field. During the crystallization process of the ferroelectric material of the ferroelectric layer 03, the electric field generated by the electric dipole can guide the polarization axis of the ferroelectric material to be arranged along the direction of the electric field, which is beneficial to improve the spontaneous polarization characteristics of the ferroelectric material.

[0138] The ferroelectric capacitor C provided in the embodiment of the present application may also have a three-dimensional vertical structure. Fig.15 A three-dimensional structural diagram of a ferroelectric capacitor provided in an embodiment of the present application.

[0139] See also Fig.15 The first electrode 01 of the ferroelectric capacitor C is a planar electrode, the second electrode 02 is a columnar electrode, the first electrodes 01 and the dielectric layer L alternately form a stacked structure, a plurality of first electrodes 01 form a step surface T, and the first electrode 01 is externally connected through its step surface T. The second electrode 02 penetrates the first electrode 01 and the dielectric layer L in the stacked structure, the side surface of the second electrode 02 is opposite to the first electrode 01, and the ferroelectric layer 03 and the intercalation layer 04 are arranged around the side surface of the second electrode 02 to separate the first electrode 01 from the second electrode 02.

[0140] Exemplarily, an intercalation layer 04 is disposed between the ferroelectric layer 03 and the first electrode 01 , and between the ferroelectric layer 03 and the second electrode 02 . Each intercalation layer 04 may be the single film layer described above, or may be a composite film layer.

[0141] Exemplarily, the materials of the first electrode 01 and the second electrode 02 both include tungsten. The ferroelectric capacitor C further includes a third electrode 05, the material of the third electrode 05 includes titanium nitride, the third electrode 05 may be located between the second electrode 02 and the intercalation layer 04, and the third electrode 05 and the second electrode 02 form a composite electrode.

[0142] The ferroelectric capacitor C adopts the above-mentioned three-dimensional vertical structural design, which can reduce its occupied area in the XY plane, thereby increasing the number of ferroelectric capacitors C set per unit area in the XY plane, thereby increasing the number of storage units 200 set per unit area, which is beneficial to improving the storage density of the ferroelectric memory.

[0143] Based on the 1T1C structure of the memory cell 200, the memory cell 200 includes a ferroelectric capacitor C and a transistor T. The first electrode 01 of the ferroelectric capacitor C is a planar electrode, and the second electrode 02 is a columnar electrode. In this case, the second electrode 02 is electrically connected to the transistor T through a contact column, that is, the columnar electrode of the ferroelectric capacitor C is electrically connected to the transistor T to form the memory cell 200.

[0144] The embodiments of the present application also provide Fig.15 The preparation method of the ferroelectric capacitor C is shown in Figures 16A to 16G A diagram of the steps for preparing a ferroelectric capacitor provided in an embodiment of the present application.

[0145] See also Fig.16A , dielectric layers L and first electrodes 01 are alternately formed, the total thickness of the dielectric layers L and the first electrodes 01 may be 100 nm, and the dielectric layers L may separate two adjacent first electrodes 01 to insulate the two adjacent first electrodes 01 .

[0146] Illustratively, an etching process may be used to etch the dielectric layer L and the first electrode 01 , so that the plurality of first electrodes 01 form a step surface T.

[0147] See also Fig. 16B , forming a via hole H penetrating the first electrode O1 and the dielectric layer L.

[0148] For example, an etching process may be used to etch the first electrode 01 and the dielectric layer L to form a via hole H penetrating the two. The diameter of the via hole H may be 50 nm.

[0149] See also Fig. 16B and Fig. 16C , an intercalation layer 04 is formed on the side wall of the via hole H.

[0150] Exemplarily, the intercalation layer 04 is a single film layer, and tantalum oxide material can be deposited on the side wall of the via H. At the same time, niobium element is doped into the tantalum oxide material to change the intrinsic parameters of the tantalum oxide material, so that high-concentration, low-energy-level defects are introduced into the material to generate electric dipoles in the intercalation layer 04. The thickness of the intercalation layer 04 can be 2 nm.

[0151] The intercalation layer 04 may also be a composite membrane layer, and its preparation method is the same as described above.

[0152] See also Fig.16D A ferroelectric layer 03 is formed on the inner side of the intercalation layer 04. The preparation method is the same as described above. The thickness of the ferroelectric layer 03 can be, for example, 10 nm.

[0153] See also Fig.16E An intercalation layer 04 is formed on the inner side of the ferroelectric layer 03. The preparation method is the same as described above. The thickness of the intercalation layer 04 can also be 2 nm, for example.

[0154] See also Fig.16F , a third electrode 05 is formed on the inner side of the insertion layer 04 .

[0155] Exemplarily, a titanium nitride material may be deposited on the inner side of the intercalation layer 04 to form the third electrode 05 , and the thickness of the third electrode 05 may be 5 nm.

[0156] See also Figure 16G , the second electrode 02 is formed on the inner side of the third electrode 05 .

[0157] The preparation method provided in the above-mentioned embodiment of the present application first forms a first electrode 01, then forms a via H penetrating the first electrode 01, forms a ferroelectric layer 03 and an intercalation layer 04 on the side wall of the via H, and finally forms a second electrode 02 on the inner side of the ferroelectric layer 03. The second electrode 02 penetrates the first electrode 01 to form a three-dimensional ferroelectric capacitor C.

[0158] In addition, the intercalation layer 04 in the ferroelectric capacitor C provided in the embodiment of the present application can also be applied to various three-dimensional vertical opening structures, such as 3D DRAM, 3D RRAM, 3D PCRAM, 3D FeRAM, 3D NAND, etc., and can also be applied to field effect transistors with vertical channels.

[0159] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A ferroelectric memory array, characterized in that: A plurality of memory cells are arranged in an array, wherein the memory cells include ferroelectric capacitors and transistors; The ferroelectric capacitor comprises: A first electrode and a second electrode arranged opposite to each other; a ferroelectric layer, disposed between the first electrode and the second electrode; at least one intercalation layer disposed between the ferroelectric layer and the first electrode, and / or between the ferroelectric layer and the second electrode; Wherein, when the first electrode and the second electrode do not receive voltage signals, the intercalation layer includes electric dipoles, and the electric dipoles are distributed on two opposite surfaces of the intercalation layer along the direction from the first electrode to the second electrode.

2. The ferroelectric memory array according to claim 1, characterized in that: The intercalation layer includes at least one first sub-intercalation layer and at least one second sub-intercalation layer; Along the direction from the first electrode to the second electrode, the first sub-intercalation layer and the second sub-intercalation layer are alternately arranged; The dielectric constant of the material of the first sub-intercalation layer is different from the dielectric constant of the material of the second sub-intercalation layer.

3. The ferroelectric memory array according to claim 1 or 2, characterized in that: The intercalation layer is doped with an element, and the element includes at least one of niobium, titanium, hafnium, zirconium, lanthanum, yttrium, strontium, silicon, germanium, tantalum or tungsten.

4. The ferroelectric memory array according to any one of claims 1 to 3, characterized in that: The material of the intercalation layer includes piezoelectric material.

5. The ferroelectric memory array according to any one of claims 1 to 4, characterized in that: The material of the intercalation layer includes pyroelectric material.

6. The ferroelectric memory array according to any one of claims 1 to 5, characterized in that: The material of the intercalation layer includes ferroelectric material.

7. The ferroelectric memory array according to any one of claims 1 to 6, characterized in that: The material of the intercalation layer includes at least one of titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, barium oxide, cerium oxide, gadolinium oxide, aluminum oxide, hafnium oxide, zirconium oxide, silicon nitride, titanium nitride, niobium nitride, tantalum nitride, hafnium nitride, zirconium nitride, strontium titanate, barium titanate, lanthanum aluminate, lithium niobate or lithium tantalate.

8. The ferroelectric memory array according to any one of claims 1 to 7, characterized in that: The thickness of the intercalation layer ranges from 0.5 nm to 5 nm.

9. The ferroelectric memory array according to any one of claims 1 to 8, characterized in that: The first electrode and the second electrode are both planar electrodes, and the first electrode, the ferroelectric layer, the insertion layer and the second electrode are stacked.

10. The ferroelectric memory array according to any one of claims 1 to 8, characterized in that: The first electrode is a planar electrode, and the second electrode is a columnar electrode; The second electrode penetrates the first electrode, and the ferroelectric layer and the insertion layer are both arranged around the second electrode.

11. The ferroelectric memory array according to any one of claims 1 to 10, characterized in that: The thermal expansion coefficient of the material of the first electrode is different from the thermal expansion coefficient of the material of the second electrode.

12. A method for preparing a ferroelectric memory array, characterized in that: include: forming a first electrode, a ferroelectric layer and a second electrode in sequence, wherein the first electrode and the second electrode are arranged opposite to each other, and the ferroelectric layer is located between the first electrode and the second electrode; Wherein, after forming the first electrode and before forming the ferroelectric layer, an intercalation layer is further formed; and / or, after forming the ferroelectric layer and before forming the second electrode, an intercalation layer is further formed; The intercalation layer includes electric dipoles, and along the direction from the first electrode to the second electrode, the electric dipoles are distributed on two opposite surfaces of the intercalation layer.

13. A memory, characterized in that: include: The ferroelectric memory array according to any one of claims 1 to 11; A controller is electrically connected to the ferroelectric memory array.

14. An electronic device, characterized in that: include: Circuit boards; The memory as claimed in claim 13, electrically connected to the circuit board.

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