A method and system for dynamic data migration in a storage chip

Abstract

The present invention provides a method and system for dynamic data migration in a memory chip, relating to the field of data processing technology. The method comprises: predicting the read frequency and write frequency of each data page; determining a predicted read / write frequency value of each data page; judging whether the predicted read / write frequency value of each data page is less than a preset read / write frequency; if so, determining the data page as a cold page; otherwise, determining the data page as a standard hot page; judging whether the time interval between the last access to each data page and the current time is greater than the time interval between the two most recent accesses; if so, determining the data page as a potential hot page; placing cold pages in a dynamic random access memory and hot pages in a non-volatile random access memory into a candidate page list, wherein the hot pages include standard hot pages and potential hot pages; and migrating each candidate page in the candidate page list with the goal of improving access response time and reducing energy consumption.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a method and system for dynamic data migration in a storage chip. Background Art

[0002] Memory chips are key components of many computing and embedded systems, and their reliability directly impacts the overall stability of the system. Currently, memory chips are primarily categorized as volatile (such as dynamic random access memory) and non-volatile (such as flash memory and phase-change memory).

[0003] Volatile memory is characterized by fast data read speeds and the ability to quickly respond to the system's storage and access needs. Therefore, it is widely used in scenarios requiring high-performance computing, such as memory and cache. However, a significant disadvantage of volatile memory is that it requires continuous power to retain data. Once the power is cut off, all stored data will be lost. In contrast, non-volatile memory does not require continuous power to maintain data and can retain information for a long time in the event of a power outage. Therefore, it is very useful in applications that need to save data for a long time. However, the main disadvantage of non-volatile memory is the slow speed of data reading and writing. Especially in scenarios with high-frequency read and write operations, its performance may not be comparable to that of volatile memory.

[0004] With increasing computing demands and the advent of the big data era, balancing the high speed of volatile memory with the high energy efficiency and data retention capabilities of non-volatile memory has become a research hotspot. Hybrid storage architectures are gradually emerging, combining volatile and non-volatile memory to leverage their respective strengths, improving system performance, energy efficiency, and data reliability.

[0005] In order to fully utilize the advantages of volatile and non-volatile memories while mitigating their negative effects, data migration is often necessary. The basic idea is to migrate hot data to volatile memories and cold data to non-volatile memories.

[0006] Traditional data migration methods mainly determine whether data is hot or cold based on its historical access frequency, and then migrate hot data to volatile memory and cold data to non-volatile memory.

[0007] However, traditional data migration methods mainly rely on the historical access frequency of data and cannot predict future data access patterns. If the data access pattern changes in the future (for example, cold data becomes hot or hot data becomes cold), the system cannot respond in advance, resulting in performance optimization delays or migration decision failures. Summary of the Invention

[0008] In order to solve the technical problem that traditional data migration methods mainly rely on the historical access frequency of data and cannot predict future data access patterns, if the data access pattern changes in the future (for example, cold data becomes hot or hot data becomes cold), the system cannot respond in advance, resulting in performance optimization delays or migration decision failures, the present invention provides a dynamic data migration method and system in a storage chip.

[0009] The technical solutions provided by the embodiments of the present invention are as follows:

[0010] First aspect:

[0011] An embodiment of the present invention provides a method for dynamic data migration in a memory chip, which is applied to a hybrid memory chip including a dynamic random access memory (DRAM) and a non-volatile random access memory (NVRAM). The method includes:

[0012] S1: Obtain the read frequency and write frequency of each data page in the past period of time;

[0013] S2: Predict the read and write frequencies of each data page;

[0014] S3: Summarize the predicted read frequency values ​​and the predicted write frequency values ​​to determine the predicted read and write frequency values ​​of each data page;

[0015] S4: Determine whether the predicted read / write frequency value of each data page is less than the preset read / write frequency; if so, determine the data page as a cold page; otherwise, determine the data page as a standard hot page;

[0016] S5: Determine whether the time interval between the last access to each data page and the current time is greater than the time interval between the two most recent accesses; if so, determine the data page as a potential hot page;

[0017] S6: putting the cold pages in the dynamic random access memory and the hot pages in the non-volatile random access memory into a candidate page list, wherein the hot pages include the standard hot pages and the potential hot pages;

[0018] S7: Migrating each candidate page in the candidate page list with the goal of improving access response time and reducing energy consumption.

[0019] Second aspect:

[0020] An embodiment of the present invention provides a dynamic data migration system in a storage chip, comprising:

[0021] processor;

[0022] A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the dynamic data migration method in the memory chip as described in the first aspect is implemented.

[0023] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0024] (1) In the present invention, the read frequency and write frequency of each data page are predicted, and then the hot and cold status of the data is reasonably judged, and cold pages, standard hot pages, and potential hot pages are accurately distinguished. The system can respond in advance and dynamically adjust the storage location and data migration strategy to improve the memory performance after migration.

[0025] (2) In the present invention, with the goal of improving access response time and reducing energy consumption, each candidate page in the candidate page list is migrated, which can reduce unnecessary energy waste and further improve memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic diagram of a flow chart of a method for dynamic data migration in a memory chip provided by an embodiment of the present invention;

[0028] Figure 2 A schematic structural diagram of a dynamic data migration system in a storage chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0030] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as an "exemplary" in the present invention should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete manner. Furthermore, in the embodiments of the present invention, "and / or" can mean both or either of the two.

[0031] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0032] Reference Manual Figure 1 , shows a schematic flow chart of a dynamic data migration method in a storage chip provided by an embodiment of the present invention.

[0033] An embodiment of the present invention provides a method for dynamic data migration in a memory chip, applied to a hybrid memory chip comprising dynamic random access memory (DRAM) and non-volatile random access memory (NVRAM). DRAM is a type of volatile memory that stores data using capacitors. Each storage cell consists of a transistor and a capacitor. A charged capacitor represents a "1," and a discharged capacitor represents a "0." Because the capacitor gradually discharges, DRAM requires periodic refresh operations (typically every few milliseconds) to ensure data is not lost. This also results in a certain amount of power consumption. Unlike DRAM, non-volatile random access memory (NVRAM) retains stored data even after power is removed. Common NVRAMs include flash memory, phase-change memory (PCM), magnetoresistive RAM (MRAM), and ferroelectric RAM (FRAM).

[0034] The processing flow of the dynamic data migration method in the storage chip may include the following steps:

[0035] S1: Obtain the read frequency and write frequency of each data page in the past period of time.

[0036] Among them, a data page is a basic storage unit in a computer system and is widely used in operating systems and storage management.

[0037] S2: Predict the read frequency and write frequency of each data page.

[0038] In a possible implementation, S2 specifically includes: adaptively selecting between a flat prediction strategy and a regression prediction strategy to predict the read frequency and write frequency of the data page.

[0039] Optionally, the flat prediction strategy specifically includes: using the read frequency at this time point as the predicted read frequency value at the next time point, and using the write frequency at this time point as the predicted write frequency value at the next time point.

[0040] It's important to note that the flat prediction strategy doesn't require complex calculations; it simply uses the current read and write frequencies to predict future read and write frequencies. Therefore, this approach is highly efficient in environments with limited computing resources, especially in systems with high real-time requirements, enabling rapid migration decisions and reducing system overhead.

[0041] Optionally, the regression prediction strategy is specifically:

[0042] Use the least squares method to perform linear regression fitting on the reading frequency series of the data page in the past period of time:

[0043] ,

[0044] Among them, fr i Indicates the reading frequency at the i-th time point, x i represents the time of the i-th time point, β0 represents the intercept parameter, β1 represents the slope parameter, ε i represents the reading frequency error term at the i-th time point, and the reading frequency error term satisfies the Gaussian distribution.

[0045] According to the linear regression fitting results, the predicted value of the reading frequency at the next time point is determined.

[0046] Use the least squares method to perform linear regression fitting on the write frequency series of the data page in the past period of time:

[0047] ,

[0048] Among them, fw i represents the writing frequency at the i-th time point, x i represents the time of the i-th time point, α0 represents the intercept parameter, α1 represents the slope parameter, τ i represents the write frequency error term at the i-th time point, and the write frequency error term satisfies the Gaussian distribution.

[0049] According to the linear regression fitting result, the predicted value of the write frequency at the next time point is determined.

[0050] It should be noted that the advantage of using the least squares method for linear regression fitting is that it can capture trend changes, improve prediction accuracy, reduce the impact of noise, and provide a stronger basis for future data page migration decisions.

[0051] Furthermore, although there are many more accurate prediction algorithms, such as neural networks, these algorithms have a very large amount of computation and are not suitable for the data migration in the present invention.

[0052] The advantages of the flat prediction strategy are its simple calculation and fast response, making it suitable for scenarios with relatively stable access frequencies and effectively conserving system resources. However, its disadvantage is that it cannot capture changing trends in access frequencies and is difficult to cope with dynamic or drastically changing access patterns. The advantage of the regression prediction strategy is that it can capture changing trends in data access by fitting historical data, resulting in higher prediction accuracy and being suitable for scenarios with linear changes in access frequencies. However, its high computational complexity may increase the system's computational burden, making it less convenient than the flat prediction strategy for short-term data fluctuations.

[0053] In a possible implementation, S2 specifically includes sub-steps S201 to S206:

[0054] S201: At the i-th time point, a flat prediction strategy and a regression prediction strategy are respectively used to predict the read frequency and the write frequency of the data page.

[0055] S202: Counting the errors when predicting the reading frequency using the flat prediction strategy and the regression prediction strategy at the i-th time point.

[0056] S203: Using the one with the smaller error as the prediction strategy for the reading frequency at the i+1th time point, and determining a predicted value of the reading frequency at the i+1th time point.

[0057] S204: Counting the errors when the write frequency is predicted using the flat prediction strategy and the regression prediction strategy at the i-th time point.

[0058] S205: Using the one with the smaller error as the prediction strategy for the write frequency at the (i+1)th time point, and determining a predicted value of the write frequency at the (i+1)th time point.

[0059] S206: Return to S202 and iterate.

[0060] In this invention, the system adaptively selects between flat prediction and regression prediction based on different data access patterns. When access patterns are stable, the flat prediction strategy provides accurate predictions quickly and with low computational overhead. When access patterns change, the regression prediction strategy captures changing data trends and provides better prediction results. This effectively combines the advantages of both strategies, selecting the optimal solution based on real-time error, improving prediction accuracy while reducing unnecessary computational overhead, ensuring efficient system operation under dynamic workloads.

[0061] S3: Summarize the predicted read frequency values ​​and the predicted write frequency values ​​to determine the predicted read and write frequency values ​​of each data page.

[0062] Optionally, the predicted read frequency value and the predicted write frequency value may be simply and directly added together to obtain the predicted read and write frequency value of each data page.

[0063] S4: Determine whether the predicted read / write frequency value of each data page is less than the preset read / write frequency. If so, determine the data page as a cold page. Otherwise, determine the data page as a standard hot page.

[0064] Among them, those skilled in the art can set the preset reading and writing frequency according to actual conditions, and the present invention does not limit it.

[0065] In this invention, a simple comparison with a preset frequency threshold allows data pages to be quickly classified as either cold or standard hot. This threshold-based classification approach has low computational complexity and can quickly complete the classification, helping to maintain efficient processing even with large numbers of data pages.

[0066] S5: Determine whether the time interval between the last access to each data page and the current time is greater than the time interval between the two most recent accesses. If so, determine the data page as a potential hot page.

[0067] In this invention, when the interval between the last access and the current time is greater than the interval between the two previous accesses, it indicates that the page's access frequency is accelerating and may become future hot data. By identifying this trend, the system can take proactive measures to migrate these pages to high-speed memory, optimizing future access response times.

[0068] S6: Put the cold pages in the dynamic random access memory and the hot pages in the non-volatile random access memory into the candidate page list.

[0069] Among them, hot pages include standard hot pages and potential hot pages.

[0070] S7: Migrate each candidate page in the candidate page list with the goal of improving access response time and reducing energy consumption.

[0071] In a possible implementation, S7 specifically includes sub-steps S701 to S703:

[0072] S701: Sort the candidate pages in the candidate page list.

[0073] Optionally, S701 specifically includes:

[0074] S7011: Calculate the comprehensive read and write frequency prediction value of each candidate page in the candidate page list:

[0075] ,

[0076] Among them, f k represents the comprehensive read and write frequency prediction value of the kth candidate page, fr k represents the predicted reading frequency of the kth candidate page, fw k represents the predicted value of the write frequency of the kth candidate page, η i Indicates the balance parameter of the i-th memory cell storing the k-th candidate page.

[0077] ,

[0078] Among them, tr iIndicates the time required for the i-th memory unit to read a page, tw i Indicates the time required for writing a page to the i-th memory unit.

[0079] The introduction of a balancing parameter adjusts the read and write times of different memory cells, allowing the calculation of the combined read and write frequency to better reflect the characteristics of different memory media. For example, some memory devices may have fast read speeds and slow write speeds (such as NVRAM), while others may have similar speeds (such as DRAM). By adjusting the read and write weights, the system can more flexibly handle data allocation among different memory cells, improving the efficiency of storage resource utilization.

[0080] S7012: Arrange the candidate pages in the candidate page list in descending order according to the order of the comprehensive read and write frequency prediction values ​​from high to low.

[0081] By calculating a comprehensive read and write frequency prediction for each page, the system can simultaneously consider both read and write frequencies, thereby more accurately reflecting the importance of each page. For frequently accessed pages, especially those that experience both read and write operations, this method can capture their high-frequency usage and avoid focusing on one operation while ignoring the other.

[0082] S702: According to the sorting results, potential benefits of migrating each candidate page to other memory units in terms of access response time and energy consumption are determined in sequence.

[0083] Optionally, the potential benefits are:

[0084] ,

[0085] Among them, P ijk represents the potential benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, BT ijk represents the access response time benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, BE ijk represents the energy consumption benefit of migrating the kth candidate page from the i-th memory unit to the j-th memory unit.

[0086] It should be noted that by calculating the access response time benefit and the energy consumption benefit and multiplying the two to calculate the total potential benefit, the system can find a balance between improving the access response speed and reducing energy consumption.

[0087] ,

[0088] Among them, BT ijkrepresents the access response time benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, T ik represents the access response time of placing the kth candidate page in the i-th memory unit, T jk represents the access response time of placing the kth candidate page in the jth memory cell, CT ijk represents the migration time of migrating the k-th candidate page from the i-th memory unit to the j-th memory unit.

[0089] ,

[0090] Among them, T ik represents the access response time of placing the kth candidate page in the i-th memory unit, fr k represents the predicted reading frequency of the kth candidate page, tr i represents the time required for the i-th memory unit to read a page, fw k represents the predicted value of the write frequency of the kth candidate page, tw i Indicates the time required for writing a page to the i-th memory unit.

[0091] ,

[0092] Among them, CT ijk represents the migration time of migrating the kth candidate page from the ith memory unit to the jth memory unit, tr i Indicates the time required for the i-th memory unit to read a page, tw j Indicates the time required to write a page to the jth memory unit.

[0093] It's important to note that by calculating access response time benefits, the system can prioritize migrating frequently accessed data pages to storage locations that significantly reduce access latency. This approach effectively improves system response speed for frequently accessed pages, thereby reducing access latency and optimizing the user experience.

[0094] ,

[0095] Among them, BE ijk represents the energy consumption benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, E ik represents the access response energy consumption of placing the kth candidate page in the i-th memory cell, E jk represents the access response energy consumption of placing the kth candidate page in the jth memory cell, CE ijk represents the migration energy consumption of migrating the kth candidate page from the i-th memory unit to the j-th memory unit.

[0096] ,

[0097] Among them, E ik represents the energy consumption of placing the kth candidate page in the i-th memory cell, er i represents the energy consumption required for the i-th memory unit to read a page, ew i represents the energy consumption required to write a page to the i-th memory unit, ts i Indicates the idle time of the i-th memory unit, e s Indicates the idle energy consumption per unit time.

[0098] ,

[0099] Among them, CE ijk represents the migration energy consumption of migrating the kth candidate page from the ith memory unit to the jth memory unit, er i represents the energy consumption required for the i-th memory unit to read a page, ew j represents the energy consumption required for writing a page to the jth memory unit.

[0100] It should be noted that by calculating energy efficiency, the system can prioritize migrating pages that can significantly save energy. This helps reduce the energy consumption of high-power storage units, lowering the overall energy consumption of the system and extending the life of the storage device.

[0101] S703: Migrate the candidate page to the memory unit with the greatest potential benefit.

[0102] In this invention, by sorting candidate pages, the system can prioritize those with higher frequency, ensuring that these pages can be promptly migrated to faster memory (such as DRAM), thereby reducing data access latency. Prioritizing the migration of high-frequency data can significantly improve the overall system response speed. By identifying and migrating low-frequency pages to lower-power memory (such as NVRAM), the system can effectively reduce the pressure on high-power memory and reduce the energy consumption caused by its continued operation. This strategy can optimize the overall energy efficiency of the system.

[0103] In a possible implementation, S7 specifically includes: with the goal of improving access response time and reducing energy consumption, determining the best migration solution through the fireworks algorithm, and migrating each candidate page in the candidate page list.

[0104] Among them, the Fireworks Algorithm (FWA) is an optimization algorithm based on heuristic search. It simulates the random distribution and concentrated search process during a firework explosion. By simulating the firework explosion process, it generates multiple possible migration paths and evaluates the pros and cons of each solution through a fitness function to find the optimal solution to the problem.

[0105] Specifically, with the goal of improving access response time and reducing energy consumption, the fitness function of the Fireworks algorithm is constructed:

[0106] ,

[0107] Among them, f represents the fitness function, X represents the migration plan, , x ijk represents the migration decision parameter, when When , it means that the kth candidate page is migrated from the ith memory unit to the jth memory unit. When , it means that the kth candidate page has not been migrated from the ith memory unit to the jth memory unit, P ijk represents the potential benefit of migrating the kth candidate page from the i-th memory unit to the j-th memory unit.

[0108] Initialize the fireworks individual. Each fireworks individual consists of multiple dimensional components. Each fireworks individual represents a feasible page migration plan, and each component represents a migration decision parameter.

[0109] Perform explosion operations on each individual firework:

[0110] ,

[0111] S i = C S [ f max -f( x i )+ε] ∑ i=1 N [ f max -f( x i )]+ε ,

[0112] Among them, A i represents the explosion radius of the i-th firework individual, x i represents the i-th firework individual, f represents the fitness function, N represents the total number of firework individuals, min represents the minimum value, ε represents the hyperparameter to avoid division by zero, C A Indicates the explosion radius adjustment coefficient, S i represents the number of explosion sparks of the i-th firework individual, max represents the maximum value, C S Indicates the explosion spark number adjustment coefficient.

[0113] In this invention, the explosion radius is adjusted based on the fitness function value of each individual firework. For firework individuals with poor fitness, the explosion radius is larger, meaning they generate more dispersed sparks, leading to a wider global search. Individuals with better fitness have a smaller explosion radius, focusing their search on a local space and conducting detailed development. By adjusting the explosion radius, the algorithm can balance global search and local optimization, avoiding being trapped in a local optimum.

[0114] Furthermore, the number of sparks generated is related to the fitness of the individual. Individuals with better fitness generate fewer sparks, reducing over-search in high-fitness areas; while individuals with poorer fitness generate more sparks, which helps increase the search density and improve global search capabilities.

[0115] Limit the number of explosion sparks generated by explosion operations:

[0116] ,

[0117] in, S represents the number of explosion sparks of the i-th firework after restriction processing, max Indicates the maximum number of explosion sparks, S min Indicates the minimum number of explosion sparks.

[0118] In the present invention, by limiting the number of explosion sparks of each firework individual, especially setting a maximum number of sparks, it is possible to avoid individuals with poor fitness from generating too many sparks. This can prevent the explosion operation from generating excessive sparks, thereby controlling the computational complexity of the algorithm and reducing unnecessary consumption of computing resources.

[0119] Displace the fireworks explosion according to their explosion radius:

[0120] ,

[0121] Among them, y ijk represents the j-th dimension component of the k-th explosion spark produced by the i-th firework individual, x ij represents the j-th dimension component in the i-th firework individual, Indicates that the range is from 0 to A ij Pick a random number between ij Represents the j-th dimension component in the explosion radius of the i-th firework individual.

[0122] ,

[0123] Among them, x rj represents the j-th dimension component of a randomly selected firework individual, x gsj represents the j-th dimension component of the global optimal fireworks individual, x lsjrepresents the j-th dimension component of the optimal fireworks individual in the previous iteration, λ1 represents the weight of the random fireworks individual, λ2 represents the weight of the global optimal fireworks individual, λ3 represents the weight of the optimal fireworks individual in the previous iteration, γ represents the displacement coefficient, f s It represents the variance of the fitness values ​​of all fireworks individuals, and f0 represents the preset variance value.

[0124] Among them, those skilled in the art can set the size of the preset variance value f0 according to actual conditions, and the present invention does not limit it.

[0125] It should be noted that when the fitness variance is less than the preset variance value, the search is more inclined to global exploration, ensuring diversified search paths through the influence of random individuals and optimal individuals; when the fitness variance is greater than the preset variance value, the search is more inclined to focus on local optimization to improve the convergence speed of the search.

[0126] In this invention, by combining random fireworks individuals, global optimal individuals, and historical optimal individuals, the explosion radius can be dynamically adjusted, ensuring both extensive global search and detailed local exploration at different search stages. The addition of random fireworks increases the breadth of the global search, while the global optimal and historical optimal individuals ensure the accuracy of local exploration.

[0127] Randomly select some fireworks individuals, generate a random number, and determine whether the random number is less than the mutation probability. If so, perform Gaussian mutation operation:

[0128] ,

[0129] in, represents the jth dimension component of the i-th firework individual after Gaussian mutation, x ij represents the j-th dimension component in the i-th firework individual, and e represents a random number that satisfies the Gaussian distribution with mean 1 and variance 1.

[0130] Among them, those skilled in the art can set the size of the mutation probability according to actual conditions, and the present invention does not limit it.

[0131] In this paper, through the Gaussian mutation operation, the individual search in the solution space is no longer limited to the original search path. Instead, a certain degree of randomness is introduced, allowing the algorithm to jump out of the current search area and expand the search range. This method can effectively avoid being trapped in the local optimal solution and enhance the global search capability.

[0132] Perform mapping operations on each individual firework:

[0133] ,

[0134] in, represents the j-th dimension component in the i-th firework individual after the mapping operation, L j Indicates the lower limit of the j-th dimension, U j Indicates the upper limit of the j-th dimension, and % indicates the modulo operation.

[0135] In the present invention, through mapping operations, it is ensured that the solution of each dimension is within the given upper and lower limits, which can prevent the solution from crossing the boundary during the search process and ensure that the solution is in the predefined valid solution space, thereby improving the effectiveness of the solution, making the search process more focused, reducing searches in irrelevant or invalid areas, and thus improving search efficiency.

[0136] Perform a selection operation on each firework individual, and the probability of each firework individual being selected is:

[0137] ,

[0138] ,

[0139] Among them, P represents the selection probability, D represents the sum of the distances between the current individual and other individuals except itself, d represents the Euclidean distance between two individuals, and N represents the total number of firework individuals.

[0140] In this method, by calculating the distance between each individual firework and the others and determining the selection probability based on the sum of these distances, individuals with larger distances (i.e., solutions that are significantly different from the others) have a greater probability of being selected. This increases the diversity of solutions, prevents the population from becoming homogenized, and ensures that the search process doesn't prematurely converge on a single area.

[0141] Determine whether the current iteration count has reached the maximum. If so, output the page migration solution represented by the firework individual with the highest fitness as the optimal migration solution. Otherwise, return to continue iterating.

[0142] In this paper, the fireworks algorithm is used to evaluate the migration plans of different pages. This allows frequently accessed hot data to be preferentially migrated to faster memory, reducing data access latency and improving system responsiveness. Cold data is migrated to lower-power storage units, thereby reducing the burden on high-power memory and overall system energy consumption.

[0143] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0144] (1) In the present invention, the read frequency and write frequency of each data page are predicted, and then the hot and cold status of the data is reasonably judged, and cold pages, standard hot pages, and potential hot pages are accurately distinguished. The system can respond in advance and dynamically adjust the storage location and data migration strategy to improve the memory performance after migration.

[0145] (2) In the present invention, with the goal of improving access response time and reducing energy consumption, each candidate page in the candidate page list is migrated, which can reduce unnecessary energy waste and further improve memory performance.

[0146] Reference Manual Figure 2 , showing a structural schematic diagram of a dynamic data migration system in a storage chip provided by the present invention.

[0147] The present invention further provides a system 20 for dynamic data migration in a storage chip, which is applied to the above-mentioned method for dynamic data migration in a storage chip, comprising:

[0148] Processor 201.

[0149] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201 , the method for dynamic data migration in a memory chip according to the method embodiment is implemented.

[0150] The dynamic data migration system 20 in a storage chip provided by the present invention can execute the above-mentioned dynamic data migration method in a storage chip and achieve the same or similar technical effects. To avoid repetition, the present invention will not elaborate on them.

[0151] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0152] (1) In the present invention, the read frequency and write frequency of each data page are predicted, and then the hot and cold status of the data is reasonably judged, and cold pages, standard hot pages, and potential hot pages are accurately distinguished. The system can respond in advance and dynamically adjust the storage location and data migration strategy to improve the memory performance after migration.

[0153] (2) In the present invention, with the goal of improving access response time and reducing energy consumption, each candidate page in the candidate page list is migrated, which can reduce unnecessary energy waste and further improve memory performance.

[0154] It should be understood that the processor in the embodiments of the present invention may be a central processing unit (CPU), but may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0155] It should also be understood that the memory in the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0156] The above embodiments can be implemented in whole or in part via software, hardware (e.g., circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are fully or partially performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired means (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. The semiconductor media can be a solid-state drive.

[0157] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. A and B can be singular or plural. Furthermore, the character " / " as used herein generally indicates an "or" relationship between the associated objects, but it may also indicate an "and / or" relationship. For specific understanding, please refer to the context.

[0158] In this disclosure, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, "at least one of a, b, or c" can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0159] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0160] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0161] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0162] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of the device or unit, which can be electrical, mechanical or other forms.

[0163] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0164] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0165] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media that can store program code, such as USB flash drives, mobile hard drives, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical disks.

[0166] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the method for dynamic data migration in a storage chip as described in the method embodiment is implemented.

[0167] The computer-readable storage medium provided by the present invention can implement the steps and effects of the dynamic data migration method in the storage chip of the above method embodiment. To avoid repetition, the present invention will not elaborate on them.

[0168] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0169] (1) In the present invention, the read frequency and write frequency of each data page are predicted, and then the hot and cold status of the data is reasonably judged, and cold pages, standard hot pages, and potential hot pages are accurately distinguished. The system can respond in advance and dynamically adjust the storage location and data migration strategy to improve the memory performance after migration.

[0170] (2) In the present invention, with the goal of improving access response time and reducing energy consumption, each candidate page in the candidate page list is migrated, which can reduce unnecessary energy waste and further improve memory performance.

[0171] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

[0172] There are a few points to note:

[0173] (1) The drawings of the embodiments of the present invention only relate to the structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0174] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present invention are exaggerated or reduced, that is, these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly on" or "under" the other element or intervening elements may be present.

[0175] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to form new embodiments.

[0176] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for dynamic data migration in a storage chip, characterized in that: Applied to a hybrid memory chip, the hybrid memory chip includes a dynamic random access memory and a non-volatile random access memory, the method includes: S1: Obtain the read frequency and write frequency of each data page in the past period of time; S2: Predict the read and write frequencies of each data page; S3: Summarize the predicted read frequency values ​​and the predicted write frequency values ​​to determine the predicted read and write frequency values ​​of each data page; S4: Determine whether the predicted read / write frequency value of each data page is less than the preset read / write frequency; if so, determine the data page as a cold page; otherwise, determine the data page as a standard hot page; S5: Determine whether the time interval between the last access to each data page and the current time is greater than the time interval between the two most recent accesses; if so, determine the data page as a potential hot page; S6: putting the cold pages in the dynamic random access memory and the hot pages in the non-volatile random access memory into a candidate page list, wherein the hot pages include the standard hot pages and the potential hot pages; S7: Migrating each candidate page in the candidate page list with the goal of improving access response time and reducing energy consumption; Wherein, the S7 specifically includes: S701: Sort the candidate pages in the candidate page list; The S701 specifically includes: S7011: Calculate the comprehensive read and write frequency prediction value of each candidate page in the candidate page list; S7012: Arrange the candidate pages in the candidate page list in descending order according to the order of the comprehensive read / write frequency prediction values; S702: Determine, in order according to the sorting results, the potential benefits of migrating each candidate page to other memory units in terms of access response time and energy consumption; The potential benefits are specifically: ； Among them, P ijk represents the potential benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, BT ijk represents the access response time benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, BE ijk represents the energy consumption benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit; ； Among them, BT ijk represents the access response time benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, T ik represents the access response time of placing the kth candidate page in the i-th memory unit, T jk represents the access response time of placing the kth candidate page in the jth memory cell, CT ijk represents the migration time of migrating the kth candidate page from the ith memory unit to the jth memory unit; ； Among them, T ik represents the access response time of placing the kth candidate page in the i-th memory unit, fr k represents the predicted reading frequency of the kth candidate page, tr i represents the time required for the i-th memory unit to read a page, fw k represents the predicted value of the write frequency of the kth candidate page, tw i Indicates the time required for writing a page to the i-th memory unit; ； Among them, CT ijk represents the migration time of migrating the kth candidate page from the ith memory unit to the jth memory unit, tr i Indicates the time required for the i-th memory unit to read a page, tw j represents the time required for the jth memory unit to write a page; ； Among them, BE ijk represents the energy consumption benefit of migrating the kth candidate page from the ith memory unit to the jth memory unit, E ik represents the access response energy consumption of placing the kth candidate page in the i-th memory cell, E jk represents the access response energy consumption of placing the kth candidate page in the jth memory cell, CE ijk represents the migration energy consumption of migrating the kth candidate page from the i-th memory unit to the j-th memory unit; ； Among them, E ik represents the energy consumption of placing the kth candidate page in the i-th memory cell, er i represents the energy consumption required for the i-th memory unit to read a page, ew i represents the energy consumption required to write a page to the i-th memory unit, ts i Indicates the idle time of the i-th memory unit, e s Indicates the idle energy consumption per unit time; ； Among them, CE ijk represents the migration energy consumption of migrating the kth candidate page from the ith memory unit to the jth memory unit, er i represents the energy consumption required for the i-th memory unit to read a page, ew j represents the energy consumption required to write a page to the jth memory unit; S703: Migrate the candidate page to the memory unit with the greatest potential benefit.

2. The method for dynamic data migration in a memory chip according to claim 1, wherein: The S2 is specifically: Adaptively select between a flat prediction strategy and a regression prediction strategy to predict the read and write frequencies of data pages.

3. The method for dynamic data migration in a memory chip according to claim 2, wherein: The S2 specifically includes: S201: At the i-th time point, a flat prediction strategy and a regression prediction strategy are used to predict the read frequency and write frequency of the data page; S202: Counting the errors when the reading frequency is predicted using the flat prediction strategy and the regression prediction strategy at the i-th time point respectively; S203: Using the one with the smaller error as the prediction strategy for the reading frequency at the i+1th time point, and determining a predicted value of the reading frequency at the i+1th time point; S204: Counting the errors when the write frequency is predicted using the flat prediction strategy and the regression prediction strategy at the i-th time point respectively; S205: Using the one with the smaller error as the prediction strategy for the write frequency at the i+1th time point, and determining a predicted value of the write frequency at the i+1th time point; S206: Return to S202 and iterate.

4. The method for dynamic data migration in a memory chip according to claim 3, wherein: The specific flat prediction strategy is: The reading frequency at this time point is used as the predicted value of the reading frequency at the next time point; The write frequency at this time point is used as the predicted value of the write frequency at the next time point.

5. The method for dynamic data migration in a memory chip according to claim 3, wherein: The regression prediction strategy is specifically as follows: Use the least squares method to perform linear regression fitting on the reading frequency series of the data page in the past period of time: ； Among them, fr i Indicates the reading frequency at the i-th time point, x i represents the time of the i-th time point, β0 represents the intercept parameter, β1 represents the slope parameter, ε i represents the reading frequency error term at the i-th time point, and the reading frequency error term satisfies the Gaussian distribution; According to the linear regression fitting results, the predicted value of the reading frequency at the next time point is determined; Use the least squares method to perform linear regression fitting on the write frequency series of the data page in the past period of time: ； Among them, fw i represents the writing frequency at the i-th time point, x i represents the time of the i-th time point, α0 represents the intercept parameter, α1 represents the slope parameter, τ i represents a write frequency error term at the i-th time point, wherein the write frequency error term satisfies a Gaussian distribution; According to the linear regression fitting result, the predicted value of the write frequency at the next time point is determined.

6. The method for dynamic data migration in a memory chip according to claim 1, wherein: The S7 is specifically: With the goal of improving access response time and reducing energy consumption, the best migration plan is determined by using the fireworks algorithm, and each candidate page in the candidate page list is migrated.

7. A dynamic data migration system in a storage chip, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the method for dynamic data migration in a memory chip according to any one of claims 1 to 6 is implemented.

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