Binary translation method and device, electronic equipment and readable storage medium

Abstract

The invention discloses a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the steps that a translation result of each basic block is obtained from a cache of a translator and executed; when it is detected that a preset position in the translation result contains a target instruction, execution of the translation result is stopped; the target instruction is used for triggering writing in the preset position when it is detected that updating operation is carried out on the basic block; and when the translation result change is not detected in the cache, translating the basic block after the updating operation is executed, so as to obtain a corresponding correction result after the basic block is updated, and continuing to execute the correction result. The problem that in the prior art, cached basic block codes are not matched with actual codes after updating operation, code execution errors occur when the cached basic block codes are executed, and then translation accuracy is affected can be solved.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and specifically relates to a binary translation method, device, electronic device and readable storage medium. Background Art

[0002] Binary translation can convert instructions of one instruction set architecture (ISA) into instructions of another ISA. During the binary translation process, the program of the source architecture platform can be translated according to the different instruction set architecture platforms, so that the application program of the source architecture platform can run on another target architecture platform.

[0003] In the related art, the source program is sometimes implemented using self-modifying code. Since the self-modifying code allows the original machine instructions in the memory to be directly modified or new machine instructions to be added through memory access instructions, the memory content corresponding to the basic block code in the source program is directly modified during runtime, resulting in a mismatch between the cached basic block code and the actual code after the update operation, causing code execution errors when executing the cached basic block code, which in turn affects the accuracy of the translation. Summary of the invention

[0004] The present application aims to provide a binary translation method, device, electronic device and readable storage medium, which at least solves the problem that the cached basic block code in the prior art does not match the actual code after the update operation, resulting in code execution errors when executing the cached basic block code, thereby affecting the accuracy of the translation.

[0005] In order to solve the above technical problems, this application is implemented as follows: In a first aspect, an embodiment of the present application provides a binary translation method, comprising: Get the translation result of each basic block from the translator's cache and execute it; When it is detected that a preset position in the translation result contains a target instruction, the execution of the translation result is stopped; the target instruction is a trigger write to the preset position when an update operation is detected for the basic block; When no change of the translation result is detected in the cache, the basic block after the update operation is performed is translated to obtain a corresponding correction result after the basic block is updated and continue to be executed.

[0006] In a second aspect, the embodiment of the present application further provides a binary translation device, including: An acquisition module, used for acquiring the translation result of each basic block from the cache of the translator and executing it; A stop module, configured to stop executing the translation result when it is detected that a preset position in the translation result contains a target instruction; the target instruction is a trigger write to the preset position when an update operation is detected for the basic block; The execution module is used to translate the basic block after the update operation is performed when the translation result change is not detected in the cache, so as to obtain the corresponding correction result after the basic block is updated and continue to execute.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the method described in the first aspect.

[0008] In a fourth aspect, an embodiment of the present application further provides a readable storage medium, which, when instructions in the readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method described in the first aspect.

[0009] In summary, in the binary translation method of this embodiment, when it is detected that the basic block is updated, the target instruction can be written to the preset position in the translation result, and when it is detected that the preset position in the translation result contains the target instruction during the execution of the basic block, the execution of the current translation result is stopped, so that when the source program updates the basic block through the self-modifying code and causes invalidation, the instructions in the basic block can be updated to avoid continuing to execute the translation result of the invalid basic block, effectively prevent code execution errors, improve the reliability of program execution, and continue to translate only when it is detected that the basic block is updated and the translation result is not updated. In this way, the existing translation results can be cached, unnecessary repeated translation work can be reduced, the execution efficiency can be improved, and the code can be updated in time when it changes, ensuring the accuracy of the translation. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of a binary translation provided by the background technology of this application; Figure 2 is a flowchart of a binary translation method provided in an embodiment of the present application; Figure 3 is a schematic diagram of a target instruction replacement provided by an embodiment of the present application; Figure 4 It is a schematic diagram of a binary program execution provided by an embodiment of the present application; Figure 5 is a flowchart of another binary translation method provided in an embodiment of the present application; Figure 6is a block diagram of a binary translation device provided in an embodiment of the present application; Figure 7 is a block diagram of an electronic device according to an exemplary embodiment; Figure 8 It is a block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0011] The memory training method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0012] Before introducing the binary translation method, device, electronic device and readable storage medium provided by the present application, the application scenarios involved in each embodiment of the present application are first introduced. The present application can be applied to the scenario of running the source program corresponding to the source architecture platform on the target architecture platform.

[0013] At present, there are many differences in the instructions that can be supported by hardware designs of different instruction set architectures (ISA), which leads to incompatibility between executable files compiled based on one ISA and other platforms. Binary translation technology can translate the source program of the source architecture platform according to the different instruction set architecture platforms, so that the source program corresponding to the source architecture platform can run on another target architecture platform.

[0014] In an embodiment of the present application, the source architecture platform is also referred to as a client architecture platform, and the target architecture platform is also referred to as a host architecture platform or a local machine architecture platform. The processor of the source architecture platform may be a processor based on a first instruction set architecture. The processor of the target architecture platform may be a processor based on a second instruction set architecture. The second instruction set architecture is a different instruction set architecture from the first instruction set architecture. For example, the first instruction set architecture is a complex instruction set (CISC) architecture, and the second instruction set architecture is a reduced instruction set (RISC) architecture, such as the first instruction set architecture is an x86 (complex instruction set) instruction set architecture, and the second instruction set architecture is an arm (reduced instruction set) instruction set architecture; for another example, the first instruction set architecture is a reduced instruction set architecture, and the second instruction set architecture is a complex instruction set architecture, such as the first instruction set architecture is an arm instruction set architecture, and the second instruction set architecture is an x86 instruction set architecture.

[0015] The source program is an application developed based on a source architecture platform (client architecture platform). That is, the source program is a program developed based on a first instruction set architecture, and therefore, the source program can run normally on the client architecture platform. The target architecture platform (host architecture platform) is a machine platform to which the source program is desired to be transplanted. The source program can be run on the client architecture platform using source binary code. The source binary code is an executable code based on a first instruction set architecture, referred to herein as source code (or client code). If it is desired to run the source program on a target architecture platform, the source binary code needs to be translated into a target binary code. The target binary code is an executable code (or host code) based on a second instruction set architecture, so that the target binary code can be run on the target architecture platform. That is, the source program can be run in a binary translation environment in the target architecture platform through binary translation technology.

[0016] Among them, binary translation adopts the "translate while running" method, translating the client architecture instructions into host architecture instructions and running them at runtime. After the translator can read the binary file, it usually translates and executes it according to the granularity of basic blocks (TB); Figure 1 As shown, an executable program developed based on a client architecture platform can be read from the executable program in a reading manner, and the basic block to be executed can be searched for the translation result corresponding to the basic block to be executed in the code cache area. If the basic block is not found, the basic block is translated, the translated translation result is stored in the code cache area, and the translated translation result is executed. If the translation result is found, the translation result of the basic block can be directly executed.

[0017] In the related art, the source program can sometimes be implemented using self-modifying code. However, since the self-modifying code allows the original machine instructions in the memory to be directly modified or new machine instructions to be added through memory access instructions, the memory content corresponding to the basic block code in the source program is directly modified during runtime, resulting in a mismatch between the cached basic block code and the actual code after the update operation, causing code execution errors when executing the cached basic block code, which in turn affects the accuracy of the translation.

[0018] In order to solve the above problems, the present application provides a binary translation method, device, electronic device and readable storage medium, which can write the target instruction to the preset position in the translation result when detecting that the basic block has been updated, and stop executing the current translation result when detecting that the preset position in the translation result contains the target instruction during the execution of the basic block, so that when the source program updates the basic block through the self-modifying code and causes invalidation, the instructions in the basic block can be updated to avoid continuing to execute the translation result of the invalid basic block, effectively prevent code execution errors, improve the reliability of program execution, and continue to translate only when it is detected that the basic block has been updated and the translation result has not been continued to be updated. In this way, the existing translation results can be cached, unnecessary repeated translation work can be reduced, the execution efficiency can be improved, and it can be updated in time when the code changes to ensure the accuracy of the translation.

[0019] The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0020] Figure 2 : is a flowchart of a binary translation method provided in an embodiment of the present application, the method comprising the following steps: Step 101, obtain the translation result of each basic block from the cache of the translator and execute it.

[0021] In this step, during the execution of multiple basic blocks included in the binary program, the translation result of each basic block can be obtained from the cache, and the instructions included in the translation result can be executed.

[0022] The source program may represent an application developed based on a source architecture platform (client architecture platform). That is, the source program is a program developed based on a first instruction set architecture and includes a plurality of basic blocks, where the basic block refers to a sequence of instructions executed sequentially in the source program.

[0023] First, when it is necessary to run the source program developed based on the source architecture platform on the target architecture platform, for each basic block included in the source program, the source architecture instructions in the basic block can be translated into target architecture instructions in real time according to the instructions actually executed on the basic block.

[0024] For example, the source architecture platform can be represented as an x86 architecture platform, the target architecture platform can be represented as another architecture platform, and the binary program can be represented as an x86 program. When an x86 program developed based on the x86 architecture platform is run on another architecture platform, a basic block in the x86 program can be executed for the instructions in the basic block.

[0025] For example, a basic block instruction included in an x86 program can be represented as follows: MOV EAX,5; assign the immediate value 5 to the EAX register; MOV EBX,3; assign the immediate value 3 to the EBX register; ADD EAX,EBX; Add the values ​​of EAX and EBX and store the result in EAX; MOV DWORD PTR [0x1000],EAX; stores the value of EAX to the memory address [0x1000].

[0026] Since the register naming and instruction format in the instruction set of another architecture platform are different from those of x86, the general registers of another architecture platform can be set to a0, a1, etc. When translating the basic block instruction into an instruction that can be executed on another architecture platform, the translation result corresponding to the basic block can be expressed as follows: li a0,5; load the immediate value 5 into the a0 register; li a1,3; load the immediate value 3 into the a1 register; add a0,a0,a1; add the values ​​of a0 and a1 and store the result in a0; sd a0,0x1000; stores the value of a0 to memory address 0x1000.

[0027] Considering that the basic block may be called repeatedly in the binary program, in this step, before executing the basic block, a search may be first performed in the cache to determine whether the cache has already cached a translated translation result.

[0028] For each of the basic blocks, when it is determined that the translation result of the basic block has been cached in the cache, the translation result of each of the basic blocks can be obtained from the cache, and the instructions included in the translation result can be executed.

[0029] The cache is a temporary storage area or data structure that can be used to store the translation results of the translated basic blocks so that they can be quickly accessed when needed, thereby avoiding repeated translation and improving the execution efficiency of the program.

[0030] In this embodiment, each basic block has a unique identifier, which can usually be determined based on the starting address, length and other characteristics of the basic block in the program. For example, in an x86 program, a basic block may start from memory address 0x1000 and contain 10 instructions, so this starting address 0x1000 can be used as the identifier of the basic block. In the cache, a suitable data structure can be used to store the translation results of the basic block, for example, a hash table, an array or other data structure can be used to store the translation results, so that the identifier of the basic block can be used as an index to access the cache to obtain the translation results of each basic block from the cache. For example, when using a hash table, the starting address of the basic block 0x1000 can be used as an index, and the translation result of the basic block can be quickly located through hash_table[0x1000].

[0031] When the translation result is obtained, the instructions included in the translation result may be executed.

[0032] For example, the obtained translation result (ie, the instruction sequence of the target architecture) can first be loaded into the instruction cache or instruction queue of the target architecture platform so that the processor of the target architecture platform can read and execute these instructions in sequence.

[0033] For example, in a specific architecture, the instructions included in the translation result can be loaded into the instruction fetch stage of the instruction pipeline, waiting for subsequent decoding, execution, etc. Among them, the specific decoding, execution, etc. operations can be carried out in the manner of the prior art, and the details are not repeated here.

[0034] Step 102: when it is detected that the preset position in the translation result contains the target instruction, stop executing the translation result.

[0035] The target instruction is an instruction for triggering writing to the preset location when an update operation is detected for the basic block.

[0036] In this step, during the execution of the instruction, the plurality of instructions included in the translation result may be firstly detected to determine whether the preset position in the translation result contains the target instruction.

[0037] Optionally, the instructions in the instruction sequence can be executed sequentially in the order of the instruction sequence corresponding to the basic block translation result. When the instruction at the preset position is to be executed, the instruction at the preset position can be compared with a predefined target instruction. If they are completely matched, it is determined that the target instruction is detected.

[0038] The target instruction may be a specific instruction that does not conflict with instructions in the instruction set of the host architecture. This instruction will not appear in the normal program flow, and once it appears, it indicates that the basic block is being updated. For example, in the host architecture, the four-byte code 0xdeadbeef can be selected as the custom target instruction.

[0039] Then, when it is determined that the instruction at the preset position is consistent with the predefined target instruction, the operation of stopping execution can be triggered.

[0040] For example, the target instruction can be pre-defined as a special instruction under the host architecture, for example, it can be defined as 0xdeadbeef, which is an instruction that will not appear in the normal program flow. Once it appears, it indicates that the basic block is updated. In addition, for a basic block translation result containing multiple instructions, the preset position corresponding to the target instruction to be detected can be determined by setting an offset. In this embodiment, the instruction position with an offset of 5 is set as the preset position. In other words, counting starts from the starting instruction of the translation result, and the position of the 6th instruction is the preset place to be detected. The detection is performed according to the preset position, and then it is determined whether the preset position corresponds to the target instruction to control whether the subsequent instructions continue to be executed.

[0041] For example, the instruction sequence corresponding to the translation result of a basic block can be as follows: Offset Instructions 0LI R0,5; 1LI R2,3; 2ADD R0,R0,R2; 3LI R3,10; 4SUB R3,R3,R2; 50xdeadbeef;#preset position; 6MUL R0,R0,R3; 7SD R0,0x1000.

[0042] From the instruction sequence of the above translation result, it can be seen that when the program executes the instruction corresponding to the preset position with an offset of 5, the instruction is detected as 0xdeadbeef through instruction reading, which is consistent with the pre-defined target instruction. At this time, the program can trigger the stop execution operation and no longer continue to execute subsequent instructions (such as MUL R0, R0, R3 and SDR0, 0x1000).

[0043] In a possible implementation, the preset position may also be the first position in the translation result, so that the instruction at the first position in the translation result as the preset position may be replaced by the target instruction, and when it is detected that the first position in the translation result contains the target instruction, the execution of the target instruction is stopped from the first position of the translation result.

[0044] Optionally, the preset position may also be located at any position in the instruction sequence. In the present application, the position of the preset position in the instruction sequence is not limited.

[0045] In some embodiments, when an update operation is detected for the basic block, the target instruction can be written into the translation result; the preset flag of the basic block is changed from the first parameter to the second parameter, and the jump address stored in the basic block before the update operation is cleared in the basic block lookup table at each level.

[0046] The first parameter indicates that no update operation has been performed in the basic block, and the second parameter indicates that the code in the basic block has been updated.

[0047] Optionally, the basic block can be checked by instruction tracing to determine whether an update operation has been performed. The execution of each instruction is tracked using debugging tools or specific functions of the processor. If an instruction is found to have written to the memory area where the code is located, then self-modifying code may have occurred.

[0048] For example, in the x86 architecture, you can use the debug registers and related debug instructions to set breakpoints and observe memory accesses. In an example using the debug registers (DR0 - DR7) of the x86 architecture, you can set a data breakpoint to monitor write operations to a specific memory area. When a write operation is performed to this area, the processor will trigger a debug exception (#DB), which can then be caught by a custom exception handler to report the self-modifying code situation.

[0049] In one possible implementation, the preset flag bit of the basic block may be a character bit in the basic block structure for storing a validity mark, wherein the basic block structure may be a data structure for storing various information related to the basic block, such as the starting address, ending address, included instructions, jump information, validity mark, etc. of the basic block.

[0050] And during the execution of the binary program, the jump relationship between basic blocks may be cached and optimized, for example, the target address of certain jumps may be recorded in the basic block lookup table at each level so that the target address can be quickly located when the same jump is executed later. However, when the basic block is invalidated due to an update operation, the previous jump optimization information may no longer apply. If these invalid jump optimization caches continue to be used, the program may jump to the wrong location, causing the program to crash or produce wrong results. Therefore, it is necessary to clear the jump address stored in the basic block lookup table at each level before the update operation to ensure that subsequent jump operations can be performed based on the latest and valid basic block information.

[0051] In some scenarios where code logic needs to be dynamically adjusted according to different inputs or runtime conditions, self-modifying code allows the program to generate and execute specific code at runtime, thereby achieving more efficient calculations. For example, the compiler dynamically generates specific algorithm code based on the characteristics of the data at runtime. For example, in matrix multiplication, if the size of the matrix is ​​small, the compiler can use self-modifying code to generate an inline, highly optimized multiplication function, avoiding the overhead of function calls and improving calculation efficiency.

[0052] When the basic block is implemented using self-modifying code, the basic block can change the behavior of the program at runtime. For example, if the basic block is used to implement a simple loop, the initial number of loops is 10. However, during the running process, the program needs to change the number of loops to 20 according to a certain condition. At this time, the program can update the number of loops parameter in the loop control instruction from 10 to 20 by means of self-modifying code, thereby changing the execution logic of the basic block.

[0053] When the update operation in the basic block involves reading and writing memory, a memory access conflict may occur if multiple basic blocks or threads access and modify the same memory area at the same time. For example, in a multi-threaded environment, if one thread is updating a variable in a basic block and another thread is reading the variable at the same time, this may cause data inconsistency and make the operation result in the basic block invalid.

[0054] Also, when the update operation in the basic block violates the memory protection mechanism, such as writing to the read-only memory area, the basic block will be invalid. In order to protect important data and code, the operating system will set different access permissions for the memory area. If the program attempts to violate these permissions to perform operations, an exception will be triggered, making the basic block unable to execute normally.

[0055] Therefore, in the above case, when the basic block is invalidated due to the update operation, the previous jump optimization information may no longer be applicable. If these invalid jump optimization caches continue to be used, the program may jump to the wrong location, causing the program to crash or produce wrong results. Therefore, it is necessary to clear the jump address stored in the basic block before the update operation in the cache to ensure that subsequent jump operations can be performed based on the latest and valid basic block information.

[0056] Step 103, when no change of the translation result is detected in the cache, the basic block after the update operation is performed is translated to obtain a corresponding correction result after the basic block is updated and continue to execute.

[0057] The cache is a temporary storage area or data structure in the translator, which can be used to store the translation results of the translated basic blocks so as to quickly access them when needed, thus avoiding repeated translation and improving the execution efficiency of the program.

[0058] In this step, since the code of the basic block may be updated during the binary translation process corresponding to the source program, when such an update is detected by instruction tracking and the execution of the current translation result is stopped, it can be determined whether there is a corresponding correction result after the update in the cache. If there is no such update in the cache, it means that such an update rarely occurs in the normal execution process of the program or it occurs for the first time, and it may be triggered by some specific external conditions, such as specific system events, extremely low probability user operation combinations, etc. Since the frequency of updates is extremely low, the cache has not had time to store the corresponding correction results after the update. Therefore, in this case, the updated basic block needs to be re-translated to obtain a new translation result and execute it to ensure that the program can run correctly based on the latest code logic.

[0059] For example, after stopping the execution of the current translation result, the correction result corresponding to the updated basic block can be searched in the cache based on the identifier of the basic block.

[0060] For example, in an x86 program, a basic block may start at memory address 0x1000 and contain 10 instructions, so the starting address 0x1000 can be used as a unique identifier for the basic block. Therefore, the identifier of the basic block can be used as an index to access the cache to obtain the corresponding correction results after each update of the basic block from the cache. In this embodiment, the cache uses a hash table to store the corresponding correction results after the update. When using the hash table, the starting address of the basic block 0x1000 can be used as an index, and the corresponding correction result after the basic block is updated can be quickly located through hash_table[0x1000].

[0061] By adopting the above technical solution, when the corresponding correction result of the basic block after update is not found in the cache, the updated basic block can be re-translated to obtain a new translation result and execute it to ensure that the program can run correctly based on the latest code logic.

[0062] In some embodiments, when a modified result corresponding to the updated basic block is detected in the cache, the modified result corresponding to the updated basic block is executed.

[0063] In this step, when the basic block is updated during the running of the binary program, the previous translation result may no longer be applicable, so the execution of the current translation result will be stopped. At this time, the cache will be searched for the corresponding correction result after the basic block is updated. If it can be detected in the cache, it means that the update of the basic block code follows a certain pattern or rule. For example, in some algorithms, the code of the basic block will be regularly updated according to the different stages of the input data. The cache system can learn and adapt to this stable update pattern, and store possible update results in the cache in advance, so that the cache can be quickly hit when the update is detected. The corresponding correction result after the update can be directly executed, avoiding the time and resource overhead caused by re-translating the basic block, and improving the execution efficiency of the program.

[0064] By adopting the above technical solution, when the corresponding correction result after the basic block is updated is found in the cache, the corresponding correction result after the update can be directly executed, avoiding the time and resource overhead caused by re-translating the basic block and improving the execution efficiency of the program.

[0065] In some embodiments, Figure 3 As shown, the following steps can be used to execute the translation result: S1, detecting in the cache the correction result corresponding to the basic block after being updated; S2, when no change of the translation result is detected in the cache, the basic block after the update operation is performed is translated to obtain a correction result corresponding to the update of the basic block, and S3 is executed; S3, executing the basic block to update the corresponding correction result; S4. When a change of the translation result is detected in the cache, the basic block is executed to obtain a corresponding correction result after the update.

[0066] In this way, when the corresponding correction result after the basic block is updated is not found in the cache, the updated basic block can be re-translated to obtain a new translation result and execute it to ensure that the program can run correctly based on the latest code logic. When the corresponding correction result after the basic block is updated is found in the cache, the corresponding correction result after the update can be directly executed, avoiding the time and resource overhead caused by re-translating the basic block and improving the execution efficiency of the program.

[0067] Considering that during the binary translation execution process, the execution stop signal may be generated in many ways, not only in the case of the specific target instruction mentioned above, but also in the case of memory access exception, which may trigger the execution stop signal. For example, when the program attempts to access an unallocated memory address, access memory beyond the boundary, or access a protected memory area, the hardware will generate an exception signal. For example, in the x86 architecture, accessing a page marked as invalid in the page table will trigger a Page Fault Exception, which will cause the program execution to stop.

[0068] In this case, in order to accurately respond to execution stop signals from different sources, it is necessary to decide whether to stop executing the translation result or to process according to the execution steps corresponding to the stop instruction based on whether the stop instruction that generates the execution stop signal is consistent with the target instruction. This can ensure that the program can run correctly in various situations.

[0069] In some embodiments, when the execution stop signal is detected, the stop instruction that generates the execution stop signal is first obtained; when the stop instruction is consistent with the target instruction, the execution of the translation result is stopped; or, when the stop instruction is inconsistent with the target instruction, the associated instruction corresponding to the stop instruction is obtained, and the associated instruction corresponding to the stop instruction is executed, thereby also achieving the effect of stopping the execution of the translation result.

[0070] For example, when a binary program based on the ARM architecture is translated to run on the RISC-V architecture, the instruction code corresponding to the target instruction can be set to 0xABCDABCD, which is a special code that does not appear in a normal ARM or RISC-V program as an invalid mark. Once the target instruction is displayed, it means that the basic block has been updated.

[0071] In a possible implementation, if an execution stop signal is detected and the instruction code corresponding to the stop instruction generating the signal is obtained as 0xABCDABCD, the stop instruction is compared with the target instruction 0xABCDABCD, and the two are consistent, then the execution of the translation result can be stopped.

[0072] In another possible implementation, during the process of executing the translation result of the program, if an execution stop signal is detected and the instruction code corresponding to the stop instruction that generates the signal is 0x12345678, the stop instruction is compared with the instruction code 0xABCDABCD corresponding to the target instruction. Among them, 0xABCDABCD is inconsistent with 0x12345678, indicating that although the basic block has not been updated, there are other situations that trigger the execution stop signal, such as memory access exceptions. At this time, according to the instruction code 0x12345678 corresponding to the stop instruction, the associated function corresponding to the instruction code 0x12345678 can be found and executed in the program, that is, jump to the error handler to deal with the current stop signal.

[0073] Specifically, the stop instruction can trigger a stop execution signal, and the processing function corresponding to the stop execution signal includes specific processing steps. Therefore, when the stop instruction is inconsistent with the target instruction, the execution steps corresponding to the processing function corresponding to the stop instruction can be obtained, and the execution steps included in the processing function can be executed.

[0074] In this embodiment, since each signal usually has a corresponding processing function in the program, the stop execution signal is also associated with a specific processing function, which includes a series of specific operation steps. These steps define the subsequent execution operations of the program after receiving the stop execution signal. For example, it may include saving the current program running status, cleaning up resources, closing related connections, and other operations.

[0075] For example, in a data processing program, the stop instruction can be used to end the execution of a thread under certain conditions. When it is detected that the stop instruction is inconsistent with the target instruction, the processing function corresponding to the stop instruction can be executed. The function may include execution steps such as saving unprocessed data and closing thread resources.

[0076] For example, a mapping table (such as a dictionary, array, etc.) can be used to store the association between the instruction code and the corresponding error handling function. When the stop signal is detected and the instruction code of the stop instruction is obtained, the corresponding error handling function is found and executed by querying the mapping table.

[0077] For example, in the case of using Python programming code as an example, the dictionary error_handler_mapping can be used to store the mapping relationship between the instruction code and the error handling function. After obtaining the instruction code of the stop instruction, the in operator is used to check whether the instruction code exists in the dictionary, and if so, the corresponding function is called.

[0078] And in the case of using C language programming code as an example, a structure ErrorHandlerMapping can be defined to store instruction codes and corresponding function pointers, and an array error_handler_mappings can be used to store all mapping relationships. In this way, the array can be traversed to find the item matching the stop instruction code and call the corresponding function.

[0079] In this way, execution stop signals from different sources can be handled flexibly, ensuring that the program can respond and handle correctly in various situations.

[0080] In the present application, through the above technical solution, when it is detected that the basic block is updated, the target instruction can be written to the preset position in the translation result, and when it is detected that the preset position in the translation result contains the target instruction during the execution of the basic block, the execution of the current translation result is stopped, so that when the source program updates the basic block through the self-modifying code and causes invalidation, the instructions in the basic block can be updated to avoid continuing to execute the translation result of the invalid basic block, effectively prevent code execution errors, improve the reliability of program execution, and only when it is detected that the basic block is updated and the translation result is not continued to be updated, the translation is continued. In this way, the existing translation results can be cached, unnecessary repeated translation work can be reduced, the execution efficiency can be improved, and the code can be updated in time when it changes, ensuring the accuracy of the translation.

[0081] Figure 4 A binary translation method provided in an embodiment of the present application comprises the following steps: Step 201, create the target instruction.

[0082] The target instruction is an instruction that triggers writing to the preset location when an update operation is detected for the basic block. The target instruction does not belong to the instruction set corresponding to the host architecture of the source program, and the encoding length of the target instruction is consistent with the encoding length of the instruction in the instruction set.

[0083] For example, the target instruction may be predefined as a special instruction under the host architecture, for example, it may be defined as 0xdeadbeef. This instruction, which will not appear in a normal program flow, may be used as an invalid marker. Once it appears, it indicates that the basic block is updated.

[0084] The target instruction is a special instruction created specifically to detect whether the basic block has been updated. It needs to meet the condition that it does not belong to the instruction set corresponding to the host architecture of the binary program. This is to ensure that the target instruction does not appear naturally during normal program execution, thus serving as a clear mark. At the same time, the encoding length of the target instruction also needs to be consistent with the encoding length of the instruction in the host architecture instruction set. This is done to avoid destroying the original code layout and execution process due to different instruction lengths.

[0085] For example, since the x86 architecture instruction set belongs to the complex instruction set computer (CISC) architecture, the encoding length of the instructions in the instruction set corresponding to the x86 architecture has greater flexibility and variability, and is not a fixed value, usually between 1-15 bytes. For example, a simple MOV AL, BL instruction may only require 1-2 bytes, while some complex string operation instructions may reach 5-10 bytes or even longer. Therefore, when the host architecture is the x86 architecture, the target instruction with an encoding length of 1-15 bytes can be created in advance, so as to avoid the destruction of the original code layout and execution process due to different instruction lengths.

[0086] Step 202: When it is detected that an update operation is performed on the basic block, the instruction at the first position in the translation result is replaced with the target instruction.

[0087] In this step, the basic block may be firstly detected to determine whether an update operation has been performed on the basic block.

[0088] Optionally, you can detect whether the basic block has been updated by: Method 1: Memory verification; When the binary program is loaded or initialized, a checksum value, such as a hash value, cyclic redundancy check code, etc., can be calculated for the memory area of ​​the basic block and saved. Then, during the program running, the checksum value of the memory area can be recalculated periodically or before and after key operations and compared with the previously saved checksum value. If the two are inconsistent, it means that the code in the memory may have been accidentally updated, indicating that an update operation has been performed on the basic block.

[0089] For example, for a memory area storing basic block code, its CRC32 check value is calculated as 0x12345678 and saved when the program starts. Then, after running for a period of time, the CRC32 check value of the memory area can be calculated again. If the CRC32 check value calculated again is 0x87654321, which is different from the previously saved 0x12345678, it means that the basic block has been updated.

[0090] Method 2: Code integrity check; The instructions in the basic block can be analyzed for syntax and semantics to check whether the format of the instructions is correct, whether the operands are legal, etc. If it is found that the instructions do not conform to the instruction set specification, it means that the basic block has been updated.

[0091] For example, in the x86 architecture, each instruction has a specific encoding format and operand requirements. If it is detected that the encoding of an instruction does not comply with the specification, or the operand exceeds the legal range, it is considered that an update operation has been performed on the basic block, rendering the basic block invalid.

[0092] Then, when it is detected that an update operation is performed on the basic block, the instruction at the first position in the translation result may be replaced with the preset target instruction.

[0093] Optionally, the cache address corresponding to the instruction at the first position may be obtained first; and then the instruction corresponding to the cache address may be replaced with the target instruction.

[0094] For example, the cache address corresponding to the first instruction in the cache can be obtained in a certain order (such as a logical order related to the storage order or the execution order), and then the original instruction stored in the cache corresponding to the address can be erased, and then the target instruction can be written. In this way, when the processor obtains an instruction from the cache address again, the replaced target instruction is executed.

[0095] By adopting the above technical solution, the instruction at the first position in the translation result can be replaced with the target instruction, and when it is detected that the first position in the translation result contains the target instruction, the execution of the instruction at the first position of the translation result is stopped.

[0096] For example, Figure 5 It shows how the basic blocks change before and after writing the target instructions in binary translation, such as Figure 5 As shown, Figure 3 The left part is before the target instruction is written, including basic block 1, in which instruction 1, instruction 2, instruction 3, and instruction n are written in sequence. The right part is after the target instruction is written, the original position of instruction 1 is used as the preset position to write the target instruction, and the corresponding positions of instruction 2, instruction 3, and instruction n remain unchanged.

[0097] When executing the translation result, the first position is where the binary program will be executed first. Therefore, the instruction position of the target instruction can be placed here so that it can be detected at the first time, and whether the translation result is valid can be quickly determined to avoid more errors and resource waste caused by executing invalid code. Compared with other positions, the first position is clear and fixed, and no additional complex logic is required to locate the preset position. No matter how many instructions the translation result contains, it can be checked directly from the first position, reducing the complexity of detection.

[0098] For example, when translating a binary program based on the x86 architecture (source architecture) to run on the host architecture, the host architecture has its own specific instruction set, such as ADD (immediate addition instruction), LD (load word instruction), MUL (multiplication instruction), etc. First, a target instruction can be created and its encoding is preset to 0xABCDABCD, which is not in the instruction set corresponding to the host architecture, and the encoding length can be set to 32 bits (4 bytes) consistent with the instruction set corresponding to the host architecture.

[0099] Among them, the basic block instruction sequence corresponding to the x86 architecture can be expressed as follows: Offset Instructions 0MOV EAX,5; assign the immediate value 5 to the EAX register; 1MOV EBX,3; assign the immediate value 3 to the EBX register; 2ADD EAX,EBX; Add the values ​​of EAX and EBX and store the result in EAX; 3MOV DWORD PTR [0x1000],EAX; Store the value of EAX to memory address [0x1000].

[0100] Then we can translate according to the correspondence between x86 instructions and host instructions. In the host architecture, general registers are usually represented by r0-r31. We can use r1 to replace EAX and r2 to replace EBX. We can use the LI (LoadImmediate) instruction to load immediate values ​​into registers. Generally, general registers are used. Here, the $t0 register (temporary register) is selected to correspond to EAX in x86; the $t1 register is selected to correspond to EBX, and the ADD instruction is used to implement addition operations between registers, adding $t0 and $t1, and storing the result back to $t0. Finally, the ST.D (StoreDoubleword) instruction can be used to store the register value to the specified memory address.

[0101] The translated host architecture basic block instruction sequence is as follows: Offset Instructions 0li r1, 5; Assign the immediate value 5 to the r1 register; 1li r2, 3; Assign the immediate value 3 to the r2 register; 2add r1, r1, r2; Add the values ​​of r1 and r2 and store the result in r1; 3st.d r1, 0x1000(r0); Store the value of r1 to memory address 0x1000.

[0102] Among them, li is a pseudo-instruction used in the host architecture to load an immediate value into a register. According to the size of the immediate value, the appropriate instruction combination can be used to load the immediate value 5 into register r1, which is equivalent to MOV EAX, 5 in the pre-translation instruction; add is the addition instruction of the host architecture, which adds the values ​​of registers r1 and r2 and stores the result in r1, corresponding to ADD EAX, EBX in the pre-translation instruction; st.d is a double-word storage instruction of the host architecture, which is used to store data in the register into memory. r0 is the zero register, and its value is always 0, so 0x1000 (r0) represents the memory address 0x1000, and the value of register r1 is stored at this memory address, corresponding to MOV DWORDPTR [0x1000], EAX in the pre-translation instruction.

[0103] The basic block can be detected by the detection method described above to determine whether the basic block has been updated. If it is determined that the basic block has been updated, the instruction at the first position in the translation result of the basic block can be replaced with the 0xABCDABCD instruction. The basic block instruction sequence corresponding to the host architecture platform after the replacement can be expressed as follows: Offset Instructions 00xABCDABCD; target instruction; 1li r2, 3; Assign the immediate value 3 to the r2 register; 2add r1, r1, r2; Add the values ​​of r1 and r2 and store the result in r1; 3st.d r1, 0x1000(r0); Store the value of r1 to memory address 0x1000.

[0104] With the above technical solution, when executing the translation result, since the first position is accessed first, the target instruction is placed here, and the validity check can be performed at the beginning of the execution process. Once the target instruction is found, the basic block can be immediately determined to be invalid, and the execution of the translation result can be stopped, thus avoiding invalid calculations and saving a lot of time.

[0105] Step 203, obtaining the translation result of each basic block from the cache of the translator and executing it.

[0106] In this step, during the execution of multiple basic blocks included in the binary program, the translation result of each basic block can be obtained from the cache, and the instructions included in the translation result can be executed.

[0107] Specifically, this step may refer to the above step 101, which will not be described in detail here.

[0108] Step 204 , when it is detected that the first position in the translation result contains the target instruction, the execution of the instruction is stopped from the first position of the translation result.

[0109] In this step, the instructions in the instruction sequence can be executed in sequence according to the order of the instruction sequence corresponding to the basic block translation result. When the instruction at the first position is to be executed, the instruction at the first position can be compared with the predefined target instruction. If they are completely matched, it is determined that the target instruction is detected.

[0110] Since the instructions exist in the computer in binary code form, the essence of comparison is to compare whether the two binary codes are exactly the same. Therefore, as long as the binary values ​​on each corresponding bit are the same, the two instructions are considered to match.

[0111] For example, using Python programming code as an example, you can define a target instruction target_instruction, then use the list translated_instructions to store the translated instruction sequence, and take out the first instruction first_instruction, compare it with the target instruction through the == operator, and if they are equal, it is determined that the target instruction is detected.

[0112] For example, as in step 202 above, when the binary program executes to this basic block, the first instruction will be checked first. If it is found that the first instruction is 0xABCDABCD, the program will immediately stop executing the current translation result.

[0113] In a possible implementation, if the instruction at the first position is found to be 0xABCDABCD, which is consistent with the predefined target instruction, the program can call a related function to trigger the operation of stopping the execution of the translation result and stop executing subsequent instructions (such as LW $t3,0($t2)).

[0114] Optionally, when it is detected that a preset position in the translation result contains a target instruction, if the target instruction is executed, an execution stop signal may be generated; and when the execution stop signal is detected, the execution of the translation result is stopped.

[0115] The stop signal may be represented as a SIGILL signal (illegal instruction signal).

[0116] For example, from the instruction sequence of the above translation result, when the program executes to the first position corresponding to the first instruction, it is found that the instruction is 0xABCDABCD, which is consistent with the pre-defined target instruction, indicating that the basic block has been updated. At this time, the program can output a SIGILL signal indicating stop execution to trigger the stop execution operation and no longer continue to execute subsequent instructions in the translation result (such as LW $t3,0($t2)).

[0117] Step 205: Detect the translation result change in the cache.

[0118] The cache is a temporary storage area or data structure that can be used to store the translation results of the translated basic blocks so that they can be quickly accessed when needed, thereby avoiding repeated translation and improving the execution efficiency of the program.

[0119] In a binary program, each basic block has its own unique identifier, which can usually be determined based on the starting address, length and other characteristics of the basic block in the program. For example, in an x86 program, a basic block may start at memory address 0x1000 and contain 10 instructions. Then this starting address 0x1000 can be used as a key identifier for the basic block. In the cache, a suitable data structure can be used to store the translation results of the basic block. For example, a hash table, array or other data structure can be used to store the translation results, so that the basic block identifier can be used as an index to access the cache to obtain the translation results of each basic block from the cache.

[0120] For example, the starting address of the correction result corresponding to the basic block after update can be used as an index, and the starting address can be set to 0x1000, and then the translation result of the basic block can be quickly located through hash_table[0x1000].

[0121] When no change of the translation result is detected in the cache, executing step 206; When a change in the translation result is detected in the cache, step 207 is executed; Step 206: translate the basic block after the update operation is performed to obtain a corresponding correction result after the basic block is updated and continue to execute.

[0122] In this step, if the corresponding correction result after the basic block is updated is not found in the cache, the updated basic block can be re-translated to obtain a new translation result and execute it to ensure that the program can run correctly based on the latest code logic.

[0123] For example, when a binary program based on the ARM architecture is translated to run on the RISC-V architecture, the binary program based on the ARM architecture includes a basic block, which is used to add two numbers, then multiply the result by a constant, store the product in memory, and finally perform a simple jump. Specifically, the instruction sequence corresponding to the basic block can be as follows: Offset Instructions 0ADD R3,R1,R2;R3=R1+R2, add the values ​​in R1 and R2, and store the result in R3; 1MOV R4,#5;R4=5, transfer the immediate value 5 to register R4; 2MUL R5,R3,R4;R5=R3*R4, multiply the values ​​in R3 and R4 and store the result in R5; 3STR R5,[R6];[R6]=R5, stores the value in R5 to the memory cell with R6 as the address.

[0124] In the RISC-V architecture, registers can be named x0-x31 for the following register mapping: ARM's R1 maps to RISC-V's x1, R2 maps to x2, R3 maps to x3, R4 maps to x4, R5 maps to x5, and R6 maps to x6.

[0125] Therefore, the RISC-V architecture instructions corresponding to the translation result of this basic block can be shown as follows: 0ADD x3,x1,x2;x3=x1+x2, add R1 and R2, and store the result in x3; 1LI x4,5;x4=5, load the immediate value 5 into register x4; 2MUL x5,x3,x4;x5=x3*x4, multiply R3 and R4, and store the result in x5; 3SW x5,0(x6); Store the value in x5 to the memory cell with x6 as the base address and offset 0.

[0126] However, if an update operation occurs in the basic block, that is, the addition operation is changed to a subtraction operation, the multiplication constant is changed, and the offset of the storage address is updated, the instruction sequence corresponding to the basic block can be as follows: Offset Instructions 0SUB R3,R1,R2;R3=R1-R2, subtract the values ​​in R1 and R2, and store the result in R3; 1MOV R4,#3;R4=3, transfer the immediate value 3 to register R4; 2MUL R5,R3,R4;R5=R3*R4, multiply the values ​​in R3 and R4 and store the result in R5; 3STR R5,[R6,#4];[R6+4]=R5, stores the value in R5 to the memory cell with address R6+4.

[0127] At this point, the RISC-V architecture instructions corresponding to the updated correction result of the basic block can be as follows: Offset Instructions 0SUB x3,x1,x2;x3=x1-x2, subtract R1 from R2, and store the result in x3; 1LI x4,3;x4=3, load the immediate value 3 into register x4; 2MUL x5,x3,x4;x5=x3*x4, multiply R3 and R4, and store the result in x5; 3SW x5,4(x6); Store the value in x5 to the memory unit with x6 as the base address and offset 4.

[0128] In the original instruction sequence, the first instruction "ADDR3, R1, R2; R3 = R1 + R2" is used to add the values ​​in R1 and R2, and store the result in R3. The corresponding instruction after translation is "ADD x3, x1, x2; x3 = x1 + x2". If the basic block is updated, the addition operation is changed to a subtraction operation. At this time, the first instruction will be updated to "SUB R3, R1, R2; R3 = R1-R2", which is used to subtract the values ​​in R1 and R2, and store the result in R3. The corresponding instruction after translation is "SUB x3, x1, x2; x3 = x1-x2". When the update operation of changing the addition operation to a subtraction operation is detected, the execution of the current translation result can be stopped. And it is determined in the cache whether there is a corresponding correction result after the update.

[0129] In this way, when such an update is detected and the execution of the current translation result is stopped, it can be determined whether there is a corresponding correction result after the update in the cache. In this embodiment, the correction result corresponding to the basic block after the update can be searched in the cache based on the identifier of the basic block. If there is no correction result in the cache, the updated basic block needs to be translated again to obtain a new translation result and execute it to ensure that the program can run correctly based on the latest code logic.

[0130] Step 207: When a change of the translation result is detected in the cache, the basic block is executed to obtain a corresponding correction result after the update.

[0131] In this step, when the basic block is updated during the running of the binary program, the previous translation result may no longer be applicable, so the current translation result will be stopped. At this time, the cache will be searched for the corresponding correction result after the basic block is updated. If it can be detected in the cache, the corresponding correction result after the update can be directly executed, avoiding the time and resource overhead caused by re-translating the basic block, and improving the execution efficiency of the program.

[0132] When the corresponding correction result after the basic block is updated is found in the cache, the corresponding correction result after the update can be directly executed, avoiding the time and resource overhead caused by re-translating the basic block, and improving the execution efficiency of the program.

[0133] By adopting the above technical solution, when it is detected that the basic block is updated, the target instruction can be written to the preset position in the translation result, and when it is detected that the preset position in the translation result contains the target instruction during the execution of the basic block, the execution of the current translation result is stopped. In this way, when the source program updates the basic block through the self-modifying code and causes it to be invalid, the instructions in the basic block can be updated to avoid continuing to execute the translation result of the invalid basic block, effectively prevent code execution errors, improve the reliability of program execution, and continue to translate only when it is detected that the basic block is updated and the translation result is not further updated. In this way, the existing translation results can be cached to reduce unnecessary repeated translation work, improve execution efficiency, and can be updated in time when the code changes to ensure the accuracy of the translation.

[0134] Figure 6 is a block diagram of a binary translation device provided in an embodiment of the present application, such as Figure 6 As shown, the device 300 includes: An acquisition module 301 is used to acquire the translation result of each basic block from the cache of the translator and execute it; A stop module 302 is used to stop executing the translation result when it is detected that a preset position in the translation result contains a target instruction; the target instruction is to trigger writing to the preset position when an update operation is detected for the basic block; The execution module 303 is used to translate the basic block after the update operation is performed when the translation result change is not detected in the cache, so as to obtain the corresponding correction result after the basic block is updated and continue to execute.

[0135] Optionally, the device further comprises: A creation module is used to create the target instruction; the target instruction does not belong to the instruction set corresponding to the host architecture of the source program, and the encoding length of the target instruction is consistent with the encoding length of the instruction in the instruction set; The replacement module is used to replace the instruction corresponding to the preset position with the target instruction when detecting that an update operation is performed on the basic block.

[0136] Optionally, the replacement module is used to replace the instruction corresponding to the first position in the translation result with the target instruction; The stop module 302 is used to stop execution from the first position.

[0137] Optionally, the replacement module includes: An acquisition submodule, used to acquire a cache address corresponding to the instruction at the preset position; The replacement submodule is used to replace the instruction corresponding to the cache address with the target instruction.

[0138] Optionally, the device further comprises: A writing module, used for modifying a preset flag bit of the basic block from a first parameter to a second parameter when detecting that an update operation is performed on the basic block; the first parameter indicates that the basic block has not been updated, and the second parameter indicates that the basic block has been updated; The clearing module is used to clear the jump addresses stored before the basic block is updated in the basic block lookup tables at all levels, so as to eliminate the jump information of the basic block before the update operation.

[0139] Optionally, the device further comprises: A generating module, used for triggering the generation of an execution stop signal when the execution reaches the preset position; The stop module is used to stop executing the translation result when the execution stop signal is detected.

[0140] Optionally, the stop module is used to obtain a stop instruction for generating the execution stop signal; when the stop instruction is consistent with the target instruction, stop executing the translation result; otherwise, obtain an associated function corresponding to the stop instruction and execute the associated function respectively.

[0141] In summary, this embodiment can write the target instruction to the preset position in the translation result when it is detected that the basic block is updated, and stop executing the current translation result when it is detected that the preset position in the translation result contains the target instruction during the execution of the basic block. In this way, when the source program updates the basic block through the self-modifying code and causes it to be invalid, the instructions in the basic block can be updated to avoid continuing to execute the translation result of the invalid basic block, effectively prevent code execution errors, improve the reliability of program execution, and continue to translate only when it is detected that the basic block is updated and the translation result is not further updated. In this way, the existing translation results can be cached to reduce unnecessary repeated translation work, improve execution efficiency, and can be updated in time when the code changes to ensure the accuracy of the translation.

[0142] Figure 7 1 is a block diagram of an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0143] Reference Figure 7 , the electronic device 500 may include one or more of the following components: a processing component 502 , a memory 504 , a power component 506 , a multimedia component 508 , an audio component 510 , an input / output interface 512 , a sensor component 514 , and a communication component 516 .

[0144] The processing component 502 generally controls the overall operation of the electronic device 500, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 502 may include one or more processors 520 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 502 may include one or more modules to facilitate the interaction between the processing component 502 and other components. For example, the processing component 502 may include a multimedia module to facilitate the interaction between the multimedia component 508 and the processing component 502.

[0145] The memory 504 is used to store various types of data to support the operation of the electronic device 500. Examples of such data include instructions for any application or method operating on the electronic device 500, contact data, phone book data, messages, pictures, multimedia, etc. The memory 504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0146] The power supply component 506 provides power to the various components of the electronic device 500. The power supply component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 500.

[0147] The multimedia component 508 includes a screen that provides an output interface between the electronic device 500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the demarcation of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 508 includes a front camera and / or a rear camera. When the electronic device 500 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0148] The audio component 510 is used to output and / or input audio signals. For example, the audio component 510 includes a microphone (MIC), and when the electronic device 500 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 504 or sent via the communication component 516. In some embodiments, the audio component 510 also includes a speaker for outputting audio signals.

[0149] The input / output interface 512 provides an interface between the processing component 502 and the peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0150] The sensor assembly 514 includes one or more sensors for providing various aspects of status assessment for the electronic device 500. For example, the sensor assembly 514 can detect the open / closed state of the electronic device 500, the relative positioning of components, such as the display and keypad of the electronic device 500, and the sensor assembly 514 can also detect the position change of the electronic device 500 or a component of the electronic device 500, the presence or absence of user contact with the electronic device 500, the orientation or acceleration / deceleration of the electronic device 500, and the temperature change of the electronic device 500. The sensor assembly 514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 514 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 514 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0151] The communication component 516 is used to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 516 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 516 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0152] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement a binary translation method provided in an embodiment of the present application.

[0153] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions, and the instructions can be executed by a processor 520 of an electronic device 500 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0154] Figure 86 is a block diagram of an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be provided as a server. Figure 8 The electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632 for storing instructions that can be executed by the processing component 622, such as an application. The application stored in the memory 632 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 622 is configured to execute instructions to perform a binary translation method provided in an embodiment of the present application.

[0155] The electronic device 600 may further include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input / output interface 658. The electronic device 600 may operate based on an operating system stored in the memory 632.

[0156] An embodiment of the present application also provides a computer program product, including a computer program, and a binary translation method implemented when the computer program is executed by a processor.

[0157] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0158] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A binary translation method, characterized in that: The method comprises: Get the translation result of each basic block from the translator's cache and execute it; When it is detected that a preset position in the translation result contains a target instruction, the execution of the translation result is stopped; the target instruction is a trigger write to the preset position when an update operation is detected for the basic block; When no change of the translation result is detected in the cache, the basic block after the update operation is performed is translated to obtain a corresponding correction result after the basic block is updated and continue to be executed.

2. The method according to claim 1, characterized in that The method further comprises: Creating the target instruction; the target instruction does not belong to the instruction set corresponding to the host architecture of the source program, and the encoding length of the target instruction is consistent with the encoding length of the instruction in the instruction set; When it is detected that an update operation is performed on the basic block, the instruction corresponding to the preset position is replaced by the target instruction.

3. The method according to claim 2, characterized in that The replacing the instruction corresponding to the preset position with the target instruction comprises: Replace the instruction corresponding to the first position in the translation result with the target instruction; The stopping of executing the translation result includes: Stops execution at the first position.

4. The method according to claim 2, characterized in that: The step of replacing the instruction corresponding to the preset position with the target instruction includes: Obtaining a cache address corresponding to the instruction at the preset position; The instruction corresponding to the cache address is replaced by the target instruction.

5. The method according to claim 1, characterized in that The method further comprises: When an update operation is detected for the basic block, a preset flag bit of the basic block is modified from a first parameter to a second parameter; the first parameter indicates that the basic block has not been updated, and the second parameter indicates that the basic block has been updated; The jump addresses stored before the basic block is updated are cleared in the basic block lookup tables of each level to eliminate the jump information of the basic block before the update operation is performed.

6. The method according to claim 1, characterized in that The method further comprises: If the execution reaches the preset position, a trigger is generated to generate an execution stop signal; When the execution stop signal is detected, the execution of the translation result is stopped.

7. The method according to claim 6, characterized in that When the execution stop signal is detected, stopping the execution of the translation result includes: Obtaining a stop instruction for generating the execution stop signal; When the stop instruction is consistent with the target instruction, the execution of the translation result is stopped; otherwise, the associated function corresponding to the stop instruction is obtained, and the associated functions are executed respectively.

8. A binary translation device, characterized in that: The device comprises: The acquisition module is used to obtain the translation result of each basic block from the translator's cache and execute it; A stop module, configured to stop executing the translation result when it is detected that a preset position in the translation result contains a target instruction; the target instruction is a trigger write to the preset position when an update operation is detected for the basic block; The execution module is used to translate the basic block after the update operation is performed when the translation result change is not detected in the cache, so as to obtain the corresponding correction result after the basic block is updated and continue to execute.

9. An electronic device, characterized in that: The method comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction implements the steps of the method according to any one of claims 1 to 7 when executed by the processor.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method as claimed in any one of claims 1 to 7.

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