SRAM (Static Random Access Memory)-based synchronous register updating mechanism group storage and loading method

Abstract

The invention provides a group storage and assembly loading method of a synchronous register updating mechanism based on an SRAM (Static Random Access Memory). The group storage and assembly loading method comprises a group storage method and an assembly loading method which are executed in sequence. The image sensor has the beneficial effects that the performance and the flexibility of the image sensor are remarkably improved by introducing an innovative method of group storage and group loading. The storage structure is optimized, the number of redundant registers is reduced, the area of a sensor is saved, meanwhile, the addresses and values of the registers are directly obtained through an SRAM, the step of I2C batch writing is omitted, and the updating speed of the registers is greatly increased. The capability of quickly switching to the optimal register configuration not only enhances the response capability of the system, but also ensures the flexibility under variable shooting conditions. Finally, the high-performance and high-sensitivity photosensitive effect is realized through the technical progress, and breakthrough progress is brought to the development of the image sensor technology.

Description

Technical Field

[0001] The invention belongs to the technical field of register group storage and group loading, and in particular to a group storage and group loading method based on a synchronous register update mechanism of an SRAM. Background Art

[0002] As the requirements for camera performance and sensitivity increase, it is critical to optimize the performance and flexibility of high-sensitivity CMOS image sensors. In the performance optimization process, the register values ​​at different gain levels play a decisive role in achieving the best performance. Therefore, the design of register sub-levels has become a core technology. The traditional approach is to increase the number of registers corresponding to the number of gain levels, such as reg_gain0, reg_gain1, etc., so that specific values ​​can be set for each register at each gain level to maintain optimal performance. Through the ISP (image signal processor) and I2C interface, the register value can be pre-written before the frame header gain takes effect, and the register can be updated to achieve precise gain control and performance optimization.

[0003] In addition, the ISP pre-configures a set of register values ​​through the I2C interface in different scenarios, and these values ​​can be updated to the registers before the frame header. However, with the growing demand for noise performance and sensitivity, this approach faces I2C rate limitations and the need to write a large number of registers. At the same time, a large number of registers will also increase the burden on the sensor area. Therefore, improving performance and flexibility while saving area has become a technical challenge in the field of high-sensitivity pixel design.

[0004] The traditional register update strategy relies on the number of gain gears to determine the number of registers, such as reg_gain0, reg_gain1, etc., so that specific values ​​can be set for each register at different gain gears to maintain optimal performance. In addition, in different application scenarios, a set of register values ​​are pre-configured through the I2C interface, which are triggered at the specified position before the frame header and updated to the register. Summary of the invention

[0005] In view of this, the present invention aims to propose a group storage and group loading method based on the synchronous register update mechanism of SRAM to solve at least one problem existing in the above-mentioned prior art.

[0006] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0007] A group storage and group loading method based on a synchronous register update mechanism of an SRAM, comprising a group storage method and a group loading method executed in sequence, wherein the group storage method comprises the following steps:

[0008] A1. Set the number of groups of registers stored in SRAM;

[0009] A2. Control the number of registers that each group can accommodate;

[0010] A3. Perform a storage operation on each group.

[0011] Furthermore, in step A2, the number of registers that each group can accommodate is controlled, including:

[0012] By adjusting the starting address of each register group in the SRAM, the starting address is set to group0_start_addr, group1_start_addr...groupN_start_addr, and the number of registers in group N is obtained by calculating the difference between groupN+1_start_addr and groupN_start_addr.

[0013] Furthermore, in step A3, a storage operation is performed on each group, including:

[0014] The initiation of the storage operation is controlled by register 0x318a[7:4], while register 0x318a[3:0] is used to control the access to the set group;

[0015] Writing the register address (0x318a) to 0x00 will trigger the register storage of group0, then hold_flag will be pulled high, turning off the chip select signal of the register, preventing I2C from writing to the register, thus stopping the update of the register value, and storing the register address and value in SRAM;

[0016] During the I2C register write process, i2c_wr_en is pulled high, sram_wen and sram_cen are pulled low, and the register address and register value are concatenated into a 24-bit value and then transmitted to sram_din;

[0017] When all registers of the current group have been stored, write the register address (0x318a) to 0x10, which will cause the hold_flag to be pulled low, allowing the sensor to continue with I2C read and write operations.

[0018] Furthermore, the group loading method includes six loading modes, namely: fast manual loading, delayed manual loading, fast automatic loading, delayed automatic loading, repeated loading and loading with gain, wherein the fast manual loading includes:

[0019] Setting the register address (0x318a) to 0x20 will trigger the loading of the register of group0; at this time, launch_flag is pulled high, and the input ports i2c_wr_en, i2c_addr, and i2c_data of the register are switched to grp_wr_en, grp_reg_addr, and grp_reg_data of the register;

[0020] When launch_flag is pulled high, grp_wr_en is also pulled high, sram_wen is pulled high, and sram_cen is pulled low, so that the SRAM enters the read state;

[0021] At this time, the value of sram_dout[23:8] is transmitted to grp_reg_addr, and the value of sram_dout[7:0] is transmitted to grp_reg_data;

[0022] When all registers in this group have been loaded, launch_flag will automatically go low, allowing the sensor to continue I2C read and write operations.

[0023] Further, the delayed manual loading includes:

[0024] The user is allowed to specify the position of N lines before a frame header, which takes effect at this inter-frame position; the register is updated at the specified inter-frame time.

[0025] Furthermore, the fast automatic loading and delayed automatic loading include:

[0026] Allows automatic loading at the inter-frame group loading position of each frame by setting the return group and the number of frames each group stays;

[0027] The start of fast auto-load and delayed auto-load is controlled by register 0x318a[7:4], and register 0x318a[3:0] is used to select the group to be loaded;

[0028] The automatic mode is controlled by register 0x318c, where bit [4] is used to enable the bank automatic switching mode and bits [3:0] are used to control which bank to return to.

[0029] Furthermore, the repeated loading continues in a loop until a new loading configuration is written, which is suitable for scenarios where the same register configuration needs to be repeated continuously.

[0030] Furthermore, the gain-dependent loading is used to process register values ​​under different gains. In this gain change mode, the system checks whether the gain has changed at the inter-frame group loading position of each frame.

[0031] If the gain changes, the system will determine which gear the current gain is in and load the corresponding group;

[0032] There are two settings for gain variation mode:

[0033] When the gain change mode is not enabled, each frame will be loaded according to the gain matching corresponding group, regardless of whether the gain actually changes;

[0034] When the gain change mode is turned on, the corresponding group will be loaded according to the gain match only when the gain actually changes.

[0035] An electronic device includes a processor and a memory that is communicatively connected to the processor and is used to store instructions executable by the processor, wherein the memory stores instructions that can be executed by the processor, and the instructions are executed by the processor, and the processor is used to execute the group storage and group loading method of the SRAM-based synchronous register update mechanism.

[0036] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the group storage and group loading method of the synchronous register update mechanism based on SRAM is implemented.

[0037] Compared with the prior art, the group storage and group loading method based on the SRAM synchronous register update mechanism described in the present invention has the following advantages:

[0038] The present invention discloses a group storage and group loading method based on a synchronous register update mechanism of SRAM. The present invention significantly improves the performance and flexibility of image sensors by introducing innovative methods of group storage and group loading. By optimizing the storage structure and reducing the number of redundant registers, the sensor area is saved. At the same time, the register address and value are directly obtained by SRAM, eliminating the step of I2C batch writing, which greatly improves the register update speed. This ability to quickly switch to the optimal register configuration not only enhances the responsiveness of the system, but also ensures flexibility under changing shooting conditions. Ultimately, these technological advances achieve high-performance and high-sensitivity photosensitivity effects, bringing breakthrough progress to the development of image sensor technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0040] Figure 1 A schematic diagram of a synchronization register update process according to an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of the loading position of a group between frames according to an embodiment of the present invention;

[0042] Figure 3 The figure is a flow chart of a group storage method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0044] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", and the like may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0045] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0046] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0047] like Figures 1 to 3 As shown, a group storage and group loading method based on a synchronous register update mechanism of SRAM includes a group storage method and a group loading method executed in sequence, and the group storage method includes:

[0048] This technology flexibly selects the number of groups according to project requirements and enables these groups to share the maximum depth bytes of SRAM. By adjusting the starting address of each group in SRAM, such as group0_start_addr, group1_start_addr...groupN_start_addr, the number of registers that each group can accommodate can be precisely controlled. Specifically, the number of registers in group N can be obtained by calculating the difference between groupN+1_start_addr and groupN_start_addr. Once the starting position of each group in SRAM is completed through register setting, storage operations can be started to each group. The start of the storage operation is controlled by register 0x318a[7:4], while register 0x318a[3:0] is used to control which specific group is accessed. For example, writing the register address (0x318a) to 0x00 will trigger the register storage of group0. At this time, hold_flag (store signal) will be pulled high, turning off the chip select signal of the register module, preventing I2C from writing to the register, thereby stopping the update of the register value and storing the register address and value in SRAM.

[0049] During the I2C write register process, i2c_wr_en (write enable) is pulled high, while sram_wen (SRAM write enable, low effective) and sram_cen (SRAM chip select enable, low effective) are pulled low, and the register address and register value are spliced ​​into a 24-bit value (16-bit address + 8-bit value), and then transmitted to sram_din (SRAM data input). When all registers of the current group are stored, the register address (0x318a) is written to 0x10, which will pull hold_flag (storage signal) low, allowing the sensor to continue I2C read and write operations. In this way, SRAM completes the storage of register addresses and values, and realizes efficient register updates and management.

[0050] The group loading method includes: when the register value needs to be updated, the present technology provides six flexible loading modes, including fast manual loading, delayed manual loading, fast automatic loading, delayed automatic loading, repeated loading and loading with gain. These modes allow the register address and value to be updated synchronously directly from the SRAM.

[0051] Fast manual loading is an immediate operation that updates the register address and value from SRAM to the register synchronously. This process is started by register 0x318a[7:4], while register 0x318a[3:0] is used to select the group to be loaded. For example, writing the register address (0x318a) to 0x20 will trigger the register loading of group0. At this time, launch_flag (loading signal) is pulled high, switching the input ports i2c_wr_en (write enable), i2c_addr (I2C address), and i2c_data (I2C data) of the register module to grp_wr_en (group write enable), grp_reg_addr (register address stored in group), and grp_reg_data (register value stored in group) of this module. When launch_flag is pulled high, grp_wr_en is also pulled high, sram_wen (SRAM write enable, low effective) is pulled high, and sram_cen (SRAM chip select enable, low effective) is pulled low, so that the SRAM enters the read state. At this time, the value of sram_dout[23:8] (SRAM output) is transmitted to grp_reg_addr, and the value of sram_dout[7:0] is transmitted to grp_reg_data. When all registers in this group are loaded, launch_flag will automatically decrease, allowing the sensor to continue I2C read and write operations. In this way, the register values ​​in the SRAM can be successfully updated.

[0052] The main difference between delayed manual loading and fast manual loading is the timing of loading. Fast manual loading takes effect immediately, while delayed manual loading allows the user to specify a position N lines before the frame header (the number of lines is adjustable and controlled by register GRP_launch_position) and takes effect at this inter-frame position. This means that the register update will not occur immediately, but will be performed at a specified inter-frame time, providing more flexibility to adapt to different shooting conditions or scenes. Auto-loading is an automated extension of manual loading, which allows automatic loading at the inter-frame group loading position of each frame by setting the return group and the number of frames to stay in each group. The start of auto-loading is also controlled by register 0x318a[7:4], and register 0x318a[3:0] is used to select the group to load. The automatic mode is controlled by register 0x318c, where bit [4] is used to enable the group automatic switching mode and bit [3:0] is used to control which group to return to. Unlike auto-loading, repeated loading has no concept of returning to the group, and it will continue to loop until a new load configuration is written. This method is suitable for scenes that need to repeat the same register configuration continuously.

[0053] Loading with gain is a special loading mode, which is specially used to process register values ​​under different gains. In this mode, the system will check whether the gain has changed at the group loading position between each frame. If the gain has changed, the system will determine which gear the current gain is in and load the corresponding group. There are two settings for gain change mode:

[0054] ①: When the gain change mode is not enabled, each frame will be loaded according to the gain matching corresponding group, regardless of whether the gain actually changes.

[0055] ②: When the gain change mode is turned on, the corresponding group will be loaded according to the gain match only when the gain actually changes.

[0056] The present invention also proposes an electronic device, comprising a processor and a memory that is communicatively connected to the processor and is used to store instructions executable by the processor, wherein the memory stores instructions that can be executed by the processor, and the instructions are executed by the processor, and the processor is used to execute the group storage and group loading method of the SRAM-based synchronous register update mechanism.

[0057] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the group storage and group loading method of the SRAM-based synchronous register update mechanism.

[0058] This method stores different register values ​​in the same register and directly obtains the register address and value from SRAM through a single I2C instruction, thus avoiding the need for I2C batch writing. This not only saves the number of registers and sensor area, but also allows for quick switching to the optimal register configuration, maintaining system flexibility while improving sensitivity.

[0059] The present invention proposes a group loading method for synchronous register update, which flexibly controls the number of registers that can be contained in each group by storing registers in groups in SRAM and adjusting the starting address of each group in SRAM. This loading method covers multiple modes such as fast manual loading, delayed manual loading, fast automatic loading, delayed automatic loading, repeated loading, and loading with gain. Through these diverse loading methods, the register address and value can be updated synchronously directly from SRAM, thereby providing the required flexibility, enabling the sensor to quickly adapt to different application requirements and quickly switch to the optimal register configuration to adapt to changing shooting conditions. In particular, the loading with gain method enables the sensor to manage gain changes more flexibly while saving area and improving performance under the growing trend of noise performance and sensitivity requirements. This design not only optimizes the performance of CMOS image sensors, but also meets the technical challenges faced by high-sensitivity pixel design, and realizes precise control and optimization of performance.

[0060] Example 1

[0061] 1. After the register configuration of each group is completed, a storage operation is performed to store the configuration of these registers into the SRAM corresponding to each group. The start and end of this process are controlled by specific registers. Specifically, the upper four bits ([7:4]) of register 0x318a are responsible for controlling the start and end of the storage operation, while the lower four bits ([3:0]) are used to specify which group is currently being accessed.

[0062] For example, write the following command through the I2C interface to manage the register storage operation of group 0:

[0063] i2c_write(0x318a,0x00) / / This instruction starts the register storage operation of group 0, by setting the value of register 0x318a to 0x00, activating the storage signal, and starting the storage process.

[0064] i2c_write(register1_addr,0x00) / / Write the address of the first register to group 0.

[0065] i2c_write(register2_addr,0x02) / / Write the address and value of the second register to group0. Here, it is assumed that the value of the register is 0x02.

[0066] i2c_write(0x318a,0x10) / This instruction ends the register storage operation of group 0 by setting the value of register 0x318a to 0x10 and turning off the storage signal to complete the storage process.

[0067] 2. Fast manual loading: It is implemented by writing specific values ​​to the control register 0x318a. Specifically, the upper four bits ([7:4]) of register 0x318a need to be written with a value of 0x2, which indicates a fast loading command, while the lower four bits ([3:0]) indicate the group number (0xX), which is used to specify the group to be loaded.

[0068] For example, to quickly manually load group 0, you can send the following command through the I2C interface:

[0069] i2c_write(0x318a,0x20) / / This instruction sets the value of register 0x318a to 0x20, where the upper four bits 0x2 represent the fast load command, and the lower four bits 0x0 represent the selection of group 0. After receiving this command, the sensor will immediately send the register configuration stored in group 0 to the target register to achieve fast update.

[0070] 3. Delayed manual loading: This can be achieved by writing a specific value to the control register 0x318a. Specifically, the upper four bits ([7:4]) of this register are set to 0x3, indicating that this is a delayed load command, and the lower four bits ([3:0]) are used to specify the group number (0xX) to be delayed loaded. Unlike fast loading, delayed manual loading allows register updates to be performed at specific inter-frame locations in each frame, thereby achieving a delayed effect.

[0071] For example, to manually load group 1 with a delay, the following command can be sent via the I2C interface:

[0072] i2c_write(0x318a,0x31) / / This instruction sets the value of register 0x318a to 0x31, where the upper four bits 0x3 represent the delayed load command, and the lower four bits 0x1 specify group 1. After receiving this command, the sensor will perform a register configuration update of group 1 at the inter-frame group load position of each frame to implement the required delayed load function.

[0073] Fast Auto-Load: It adds the ability to automatically return to a specified group based on fast manual loading. This feature is controlled by register 0x318c, where bit [4] is used to enable the group auto-switching mode and bits [3:0] are used to specify the group number to return to. If it is necessary to return to the specified group before reaching the highest group, the system will loop back to the starting group and continue incrementing until the specified return group is reached. For example, if the starting group is 2 and the return group is 1, the system will switch according to this rule (2->3->4->1).

[0074] The user can set the number of frames to stay for each group, which can be configured through the specified register. If the user sets it to 0 frames, the automatic loading will skip the group. The following is a specific operation example:

[0075] i2c_write(0x318c,0x12) / / Enable automatic switching mode (Bit[4] is set to 1) and set back to group 2 (Bit[3:0] is set to 2).

[0076] i2c_write(0x318d,0x04) / / Stay in group 0 for 4 frames.

[0077] i2c_write(0x318e,0x02) / / Stay in group 1 for 2 frames.

[0078] i2c_write(0x318f,0x01) / / Stay in group 2 for 1 frame.

[0079] i2c_write(0x3190,0x03) / / Stay in group 3 for 3 frames.

[0080] i2c_write(0x318a,0x23) / / Fast load group 3.

[0081] In this example, the sensor first quickly loads Group 3 and stays for 3 frames, then automatically switches to Group 0 and stays for 4 frames, then switches to Group 1 and stays for 2 frames, and finally switches to Group 2. This fast automatic loading mechanism provides a high degree of flexibility and automation, allowing the sensor to automatically switch between different register configuration groups according to the preset frame dwell time, optimizing the image processing process and improving the adaptability and efficiency of the system.

[0082] 4. Delayed automatic loading: This function combines the control method of delayed manual loading and the group number incrementing feature of automatic loading, allowing the system to automatically switch the group loading position to the next group between each frame until the user-specified return group number is reached. This function is also controlled by register 0x318c, where bit [4] is used to enable the group automatic switching mode and bits [3:0] are used to specify the group number to be returned to. If the user specifies a dwell time of 0 frames for a group, the group will be skipped and no loading operation will be performed.

[0083] example:

[0084] i2c_write(0x318c,0x12) / / Enable automatic switching mode (Bit[4] is set to 1) and set the final return to group 2 (Bit[3:0] is set to 2).

[0085] i2c_write(0x318d,0x04) / / Stay in group 0 for 4 frames.

[0086] i2c_write(0x318e,0x02) / / Stay in group 1 for 2 frames.

[0087] i2c_write(0x318f,0x01) / / Stay in group 2 for 1 frame.

[0088] i2c_write(0x3190,0x03) / / Stay in group 3 for 3 frames.

[0089] i2c_write(0x318a,0x30) / / Delay loading group 0.

[0090] In this example, the sensor first delays loading of Group 0 for 4 frames, then automatically switches to Group 1 for 2 frames, followed by Group 2 for 1 frame, and finally Group 3 for 3 frames. After completing the cycle of these groups, the system automatically returns to Group 2, forming a closed-loop automatic loading process.

[0091] 5. Repeated loading: This method allows the sensor to load multiple groups in a preset order, and this process can be repeated indefinitely until the system receives a new loading configuration. This mechanism is particularly suitable for scenarios where specific register configurations need to be repeated periodically, providing extremely high operational flexibility and automation.

[0092] In the specific implementation, the user can define the number of dwell frames for each group and whether to enable repeated loading by setting different registers. The following is an operation example:

[0093] i2c_write(0x318d,0x10) / / Stay in group 0 for 16 frames.

[0094] i2c_write(0x318e,0x00) / / Skip group 1 because the number of dwell frames is set to 0.

[0095] i2c_write(0x318f,0x20) / / Stay in group 2 for 32 frames.

[0096] i2c_write(0x3190,0x40) / / Stay in group 3 for 64 frames.

[0097] i2c_write(0x318c,0x30) / / Enable automatic switching mode (Bit[4] is set to 1) and enable repeated loading (Bit[5] is set to 1).

[0098] i2c_write(0x318a,0x20) / / Delay loading group 0.

[0099] In this example, the sensor first delays loading group 0 and stays for 16 frames, then because the number of stay frames of group 1 is 0, the system will skip group 1 and switch directly to group 2 and stay for 32 frames, and then group 3 and stay for 64 frames. After that, the system will return to group 0 and start the cycle again, forming a closed-loop repeated loading process.

[0100] This repetitive loading mechanism enables the sensor to cyclically switch between different register configuration groups according to the preset frame dwell time until the user writes a new loading configuration, optimizing the image processing flow and improving the adaptability and efficiency of the system. It is particularly suitable for scenarios that require periodic repetition of specific operations.

[0101] 6. Loading with gain: The loading with gain function of the present invention is designed for loading register values ​​under different gain conditions. It includes two gain change modes, allowing the sensor to dynamically adjust the register configuration according to the actual change of gain.

[0102] ①: When the gain change mode is not enabled, each group will match and load the corresponding register configuration according to the current gain value, regardless of whether the gain changes. To enable this mode, you need to set bit[1] of register 0x318b to 0 (turn off the gain change switch) and set bit[2] to 1 (start the gain load mode).

[0103] example:

[0104] i2c_write(0x318b,0x04) / / bit[2]:auto_again_launch_en

[0105] / / bit[1]:1'b1:launch@again change

[0106] 1'b0: launch group every frame

[0107] In this example, each frame will match and load the corresponding group according to the gain value.

[0108] ②: When the gain change mode is turned on, the system will match and load the corresponding register configuration according to the new gain value only when the gain value changes. To enable this mode, you need to set bit[1] of register 0x318b to 1 (turn on the gain change switch) and set bit[2] to 1 (start the load mode with gain). Example:

[0109] i2c_write(0x318b,0x06) / / bit[2]:auto_again_launch_en

[0110] / / bit[1]:1'b1:launch@again change

[0111] 1'b0: launch group every frame

[0112] In this example, only when the gain changes will the corresponding group be matched and loaded according to the gain.

[0113] This gain-loaded function enables the sensor to flexibly adapt to different lighting conditions and image quality requirements, and optimizes image signal processing by intelligently adjusting the register configuration, thereby improving the sensor's adaptability and image quality.

[0114] The key innovations of the present invention are: first, the group storage method, which involves a new register storage strategy that optimizes the storage structure by reducing the number of redundant registers. This method not only improves performance, but also saves sensor area, which is particularly important for high-sensitivity pixel design. The key to legal protection lies in the design and implementation of this storage method, and how it effectively solves the problems of limited number of registers and I2C rate bottleneck in traditional methods. Secondly, the group loading method is a new register update mechanism that obtains register addresses and values ​​directly from SRAM, eliminating the traditional steps of batch writing registers through I2C, thereby significantly improving the speed of register updates. The key to legal protection lies in the efficiency improvement of this update method and the reduction of dependence on I2C, as well as how it improves the responsiveness and data processing speed of the entire system.

[0115] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A group storage and group loading method based on a synchronous register update mechanism of SRAM, characterized in that: The invention comprises a group storage method and a group loading method which are executed in sequence, wherein the group storage method comprises the following steps: A1. Set the number of groups of registers stored in SRAM; A2. Control the number of registers that each group can accommodate; A3. Perform a storage operation on each group.

2. The group storage and group loading method based on the SRAM synchronous register update mechanism according to claim 1, characterized in that: In step A2, the number of registers that each group can accommodate is controlled, including: By adjusting the starting address of each register group in the SRAM, the starting address is set to group0_start_addr, group1_start_addr...groupN_start_addr, and the number of registers in group N is obtained by calculating the difference between groupN+1_start_addr and groupN_start_addr.

3. The group storage and group loading method based on the SRAM synchronous register update mechanism according to claim 1, characterized in that: In step A3, a storage operation is performed on each group, including: The initiation of the storage operation is controlled by register 0x318a[7:4], while register 0x318a[3:0] is used to control the access to the set group; Writing the register address (0x318a) to 0x00 will trigger the register storage of group0, then hold_flag will be pulled high, turning off the chip select signal of the register, preventing I2C from writing to the register, thus stopping the update of the register value, and storing the register address and value in SRAM; During the I2C register write process, i2c_wr_en is pulled high, sram_wen and sram_cen are pulled low, and the register address and register value are concatenated into a 24-bit value and then transmitted to sram_din; When all registers of the current group have been stored, write the register address (0x318a) to 0x10, which will cause the hold_flag to be pulled low, allowing the sensor to continue with I2C read and write operations.

4. The group storage and group loading method based on the SRAM synchronous register update mechanism according to claim 1, characterized in that: The group loading method includes six loading modes, namely: fast manual loading, delayed manual loading, fast automatic loading, delayed automatic loading, repeated loading and loading with gain. The fast manual loading includes: Setting the register address (0x318a) to 0x20 will trigger the loading of the register of group0; at this time, launch_flag is pulled high, and the input ports i2c_wr_en, i2c_addr, and i2c_data of the register are switched to grp_wr_en, grp_reg_addr, and grp_reg_data of the register; When launch_flag is pulled high, grp_wr_en is also pulled high, sram_wen is pulled high, and sram_cen is pulled low, so that the SRAM enters the read state; At this time, the value of sram_dout[23:8] is transmitted to grp_reg_addr, and the value of sram_dout[7:0] is transmitted to grp_reg_data; When all registers in this group have been loaded, launch_flag will automatically go low, allowing the sensor to continue I2C read and write operations.

5. The group storage and group loading method based on the SRAM synchronous register update mechanism according to claim 4, characterized in that: The delayed manual loading includes: The user is allowed to specify the position of N lines before a frame header, which takes effect at this inter-frame position; the register is updated at the specified inter-frame time.

6. The group storage and group loading method based on the SRAM synchronous register update mechanism according to claim 4, characterized in that: The fast automatic loading and delayed automatic loading include: Allows automatic loading at the inter-frame group loading position of each frame by setting the return group and the number of frames each group stays; The start of fast auto-load and delayed auto-load is controlled by register 0x318a[7:4], and register 0x318a[3:0] is used to select the group to be loaded; The automatic mode is controlled by register 0x318c, where bit[4] is used to enable the bank automatic switching mode and bits[3:0] are used to control which bank to return to.

7. The group storage and group loading method based on the SRAM synchronous register update mechanism according to claim 4, characterized in that: The repeated loading continues to cycle until a new loading configuration is written, which is suitable for scenarios where the same register configuration needs to be repeated continuously.

8. The group storage and group loading method based on the SRAM synchronous register update mechanism according to claim 4, characterized in that: The gain-with-load is used to process register values ​​under different gains. In this gain change mode, the system will check whether the gain changes at the group loading position between each frame. If the gain changes, the system will determine which gear the current gain is in and load the corresponding group; There are two settings for gain variation mode: When the gain change mode is not enabled, each frame will be loaded according to the gain matching corresponding group, regardless of whether the gain actually changes; When the gain change mode is turned on, the corresponding group will be loaded according to the gain match only when the gain actually changes.

9. An electronic device, comprising a processor and a memory connected to the processor for storing instructions executable by the processor, characterized in that: The memory stores instructions executable by the processor, and the instructions are executed by the processor. The processor is used to execute the group storage and group loading method of the SRAM-based synchronous register update mechanism as described in any one of claims 1-8.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the group storage and group loading method of the SRAM-based synchronous register update mechanism described in any one of claims 1 to 8 is implemented.

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