Branch prediction method and system for single-layer perceptron in asynchronous superscalar processor

Abstract

The invention discloses a single-layer perceptron branch prediction method and system in an asynchronous superscale processor, and in an asynchronous superscale processor architecture, a branch prediction top layer control module sends prediction data to a perceptron branch prediction module after receiving a prediction request signal and a data packet sent by a receiving instruction module; the perceptron branch prediction module loads historical data of a branch instruction and stores branch instruction information before instruction execution, performs weighting calculation by using the branch instruction information, judges whether the branch instruction jumps or not according to a weighting result, updates a historical record and a weight of the branch instruction information, and predicts whether the branch instruction jumps or not; and the prediction information is returned to the instruction fetching module for bidirectional instruction fetching, and correction information of various types of instructions in branch prediction is sent by the outgoing module. On the basis of asynchronous circuit design, by introducing a dynamic branch prediction method based on a perceptron and a two-way addressing mechanism, the instruction processing speed and prediction precision in a complex and dynamic branch mode are improved, and power consumption is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of processors, and in particular relates to a single-layer perceptron branch prediction method and system in an asynchronous superscalar processor. Background Art

[0002] Superscalar processors achieve significant improvements in processor performance by executing multiple instructions in the same clock cycle. Through multiple pipeline designs, superscalar architectures achieve instruction-level parallelism, which means increasing throughput without increasing the processor's main frequency.

[0003] However, traditional synchronous superscalar processors are increasingly constrained by synchronous clock limitations in terms of processing speed and energy consumption. The increase in clock frequency leads to higher power consumption and heat generation, making it more difficult to further optimize processor performance. With the increasing demand for high performance and low power consumption, asynchronous superscalar processors have gradually attracted attention. Asynchronous processors do not rely on global clock signals, but manage instruction scheduling and parallel processing of execution units based on event-driven methods. Unlike traditional synchronous architectures, asynchronous architectures can flexibly schedule instructions, reduce dependence on clock signals, and thus reduce the impact of clock jitter and clock offset on performance.

[0004] In the design of asynchronous superscalar processors, efficient branch prediction is of great significance to performance improvement. Traditional branch prediction techniques mainly include static prediction and dynamic prediction. Static prediction relies on fixed rules or simple statistical information to judge branch behavior and will not make adjustments based on runtime data. For example, static prediction usually assumes that all backward jump branch instructions will be executed, while forward jump branches will not be executed. Static prediction is simple to implement, but the prediction accuracy is low when dealing with complex branch patterns, which makes it difficult to meet the high performance requirements of modern processors. Dynamic prediction records the branch behavior history at runtime and adjusts the prediction strategy according to the previous actual jump situation; a two-bit saturated counter is the most basic dynamic predictor. Each branch instruction corresponds to a two-bit counter, which predicts the branch behavior based on the previous few times. When the prediction is correct, the counter accumulates or decreases, which is equivalent to forming a "signal strength" to determine the future branch direction.

[0005] In recent years, in order to improve prediction accuracy, perceptron branch prediction algorithms have been gradually introduced. This method can handle complex long-history branch patterns. The perceptron branch predictor uses a neural network model and combines branch history data to predict future branch directions, and updates the weights of the neural network with the actual results of each branch. It is suitable for complex instruction streams and has higher prediction accuracy. However, the instruction processing speed and prediction accuracy of existing perceptron branch prediction algorithms in complex branch patterns need to be improved. Summary of the invention

[0006] In view of the problems existing in the above-mentioned background technology, the purpose of the present invention is to provide a single-layer perceptron branch prediction method and system in an asynchronous superscalar processor, which can reduce the impact of misprediction on the instruction flow in complex branch modes, effectively improve the instruction processing speed and prediction accuracy, and reduce power consumption.

[0007] In order to achieve the above object, the present invention adopts the following technical solution: A single-layer perceptron branch prediction method in an asynchronous superscalar processor includes the following steps: In an asynchronous superscalar processor architecture, when a branch prediction top-level control module is in a prediction state, after sending a prediction request signal and a corresponding data packet through an instruction fetch module, the branch prediction top-level control module controls the data to be sent to a perceptron branch prediction module for prediction. The perceptron branch prediction module loads the historical data of branch instructions before the instruction is executed, stores the branch instruction information as a number of historical bits, and uses the branch instruction information for weighted calculation. If the predicted weighted result meets a specific threshold, the branch instruction is predicted to jump, otherwise the branch instruction is predicted not to jump. At the same time, the perceptron branch prediction module dynamically updates the historical record and weight of the branch instruction information according to the change of branch behavior, and returns the prediction information to the branch prediction top-level control module, which then sends data to the instruction fetch module for bidirectional instruction fetching. When the instruction fetch module receives a full round of instructions, the branch prediction top-level control module switches its state to a correction state. When the branch prediction top-level control module is in the correction state, after sending the prediction correction request signal and the corresponding data packet through the out-of-band module, the branch prediction top-level control module sends data to the perceptron branch prediction module, and the perceptron branch prediction module performs correction operations on the branch instruction, including modifying the historical records and weights of the branch instruction information. When the out-of-band module sends a correction end signal, the branch prediction top-level control module sends the base address of the next round of instruction fetching to the instruction fetch module, and at the same time, the branch prediction top-level control module switches its state to the prediction state.

[0008] Furthermore, the branch prediction top-level control module selects the instruction fetch data branch prediction path to send data to the perceptron branch prediction module to perform branch prediction on the branch instruction. The branch prediction top-level control module selects different out-of-order instruction correction slots to send data to the perceptron branch prediction module to perform correction operations on the branch instruction. When the out-of-order end event and data occur, the branch prediction top-level control module ends the correction operation by selecting the out-of-order data correction end path and converts the correction state to the prediction state.

[0009] Furthermore, a counter is set in the branch prediction top-level control module, and the conversion between the prediction state and the correction state is controlled by the counter.

[0010] Furthermore, the branch instruction information includes an instruction number, an instruction type, an original PC value, a next instruction PC value, and a jump PC value.

[0011] The present invention further provides a system for implementing a single-layer perceptron branch prediction method in an asynchronous superscalar processor, comprising a branch prediction top-level control module, a perceptron branch prediction module, an instruction fetch module and an exit module, wherein: Branch prediction top-level control module: used to receive the prediction request signal and the corresponding data packet sent by the instruction fetch module, or receive the prediction correction request signal and the corresponding data packet sent by the exit module, and send data to the perceptron branch prediction module; Perceptron branch prediction module: includes a prediction submodule and a correction submodule, wherein the prediction submodule includes a prediction data unpacking module, a B-type prediction module, a Jalr-type prediction module, a Call-type prediction module, and a Ret-type prediction module; the correction submodule includes a correction data unpacking module, a B-type correction module, and a Jalr-type correction module; The prediction data unpacking module is used to find the first jump instruction from the prediction data packet received by the perception machine branch prediction module, and record the branch instruction information of the jump instruction. The prediction data unpacking module detects whether the data packet contains the jump instruction according to the instruction type code; the data packet to be branch predicted enters the corresponding prediction submodule according to the branch instruction type code after being processed by the prediction data unpacking module, predicts the corresponding jump instruction and outputs the prediction result; The correction data unpacking module is used to split the instructions in the prediction correction data packet received by the perception machine branch prediction module, and send them to the corresponding correction submodule according to the branch instruction type code to correct the branch instruction.

[0012] Furthermore, the type B prediction module adopts a dynamic branch prediction model implemented by a single-layer perceptron, including a history record table submodule, a weight table submodule and a prediction logic submodule. A global history register and a counter are set inside the history record table submodule, and the global history register records the prediction results of each type B branch instruction; the weight table submodule adopts a 256*72 SRAM, and the lower 8 bits of the PC of each type B instruction store a 72-bit weight value table, and the 72 bits are divided into 9 8-bit weights for predicting type B jump instructions; the 72-bit weight value table is taken out from the weight table submodule through the lower 8 bits of the input type B instruction PC, and is sent to the prediction logic submodule together with the lower 8 bits of the global history register in the history record table submodule, and the prediction logic submodule divides the 72-bit weight value table into 9 8-bit weight registers, and sets a summation register to predict type B jump instructions.

[0013] Furthermore, a 16*37-bit two-dimensional history record table is set inside the Jalr type prediction module to record the PC value and number of correct jump addresses of each Jalr type instruction.

[0014] Furthermore, the Call type prediction module manages the Call type instructions and the Ret type prediction module manages the Ret type instructions using a simulated stack. When a Call type instruction appears, the next instruction of the original instruction is pushed onto the stack and the value of the original Call type jump instruction PC is output. When a Ret type instruction appears, an instruction is popped from the top of the stack and output as a predicted jump instruction.

[0015] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects: (1) Improving the accuracy of branch prediction: The present invention introduces a dynamic branch prediction method based on a perceptron. After each prediction is completed, the perceptron model updates the weight vector according to the actual jump situation of the branch instruction, so that the predictor can improve the instruction prediction accuracy in complex and dynamic branch modes; (2) Reducing the cost caused by misprediction: In the perceptron branch prediction design of the present invention, the number of misprediction occurrences is effectively reduced through weighted calculation and weight adjustment mechanism, which reduces the impact of misprediction on the pipeline. This not only improves the processor throughput and instruction processing speed in complex branch modes, but also reduces the waste of computing resources caused by correction operations and re-instruction fetching due to misprediction. (3) The single-layer perceptron branch prediction system in the asynchronous superscalar processor of the present invention is simpler in structure, has lower power consumption, better performance, and can adapt to the needs of complex instruction flow environments, enabling the processor to have significant advantages in high-performance, low-power application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the internal mechanism of the branch prediction top-level control module provided by an embodiment of the present invention; Figure 2 Schematic diagram of the internal mechanism of the perceptron branch prediction module provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of the instruction encoding provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0018] Branch prediction plays an important role in improving the continuity of instruction execution in processor architecture, especially in superscalar architecture, by predicting the execution path of branch instructions in advance, thereby reducing pipeline pauses caused by branch instructions. The present invention proposes a single-layer perceptron branch prediction method in an asynchronous superscalar processor, which determines whether the branch instruction to be executed will jump based on the branch behavior characteristics and historical information of the instruction, and determines the acquisition address of the next instruction accordingly. The specific method is as follows: In the asynchronous superscalar processor architecture, when the branch prediction top-level control module is in the prediction state, after sending the prediction request signal and the corresponding data packet through the instruction fetch module, the branch prediction top-level control module controls the data to be sent to the perceptron branch prediction module for prediction. In order to improve the accuracy of the prediction, the perceptron branch prediction module loads the historical data of the branch instruction before the instruction is executed to identify and learn the laws of branch behavior. In this process, the perceptron branch prediction module stores the branch instruction information as a number of historical bits. The branch instruction information includes the instruction sequence number, instruction type, original PC value, next instruction PC value, and jump PC value, and uses these branch instruction information for weighted calculation. If the predicted weighted result meets a specific threshold, the branch instruction is predicted to jump, otherwise the branch instruction is predicted not to jump. At the same time, the perceptron branch prediction module dynamically updates the historical records and weights of the branch instruction information according to the changes in branch behavior to adapt to the changes in branch behavior. The perceptron branch prediction module returns the prediction information to the branch prediction top-level control module, and then the branch prediction top-level control module sends data to the instruction fetch module for bidirectional instruction fetching. When the instruction fetch module receives a full round of instructions, the branch prediction top-level control module switches its state to the correction state; When the branch prediction top-level control module is in the correction state, after sending the prediction correction request signal and the corresponding data packet through the outgoing module, the branch prediction top-level control module selects different outgoing instruction correction slots to send data to the perceptron branch prediction module. The perceptron branch prediction module performs correction operations on the branch instruction, including modifying the historical records and weights of the branch instruction information. When the outgoing module sends a correction end signal, the branch prediction top-level control module sends the base address of the next round of instruction fetching to the instruction fetch module to start the next round of instruction fetching operations. At the same time, the branch prediction top-level control module switches its state to the prediction state.

[0019] The system for implementing a single-layer perceptron branch prediction method in an asynchronous superscalar processor comprises a branch prediction top-level control module, a perceptron branch prediction module, an instruction fetch module and an exit module.

[0020] The internal mechanism of the branch prediction top-level control module is as follows Figure 1 As shown, the branch prediction top-level control module has two states: prediction state and correction state.

[0021] In the prediction state, the branch prediction top-level control module only interacts with the instruction fetch module. When the branch prediction top-level control module receives a data packet from the instruction fetch module, it selects the instruction fetch data branch prediction path Fetch_rou to send the data to the perceptron branch prediction module for branch prediction. After the prediction is completed, the result is sent to the instruction fetch module. According to the highest bit of the received instruction fetch data packet, it is judged whether the instruction fetch module has an exception. If an exception occurs, the event and data are not sent to the perceptron branch prediction module, but the perceptron branch prediction module is bypassed and an all-zero data packet is directly sent to the instruction fetch module. The instruction fetch module is designed with 4 16-depth instruction slots for bidirectional instruction fetching. During initialization, the branch prediction top-level control module is in the prediction state, and the counter is initialized to 0. Because the asynchronous superscalar processor pipeline is completely empty after initialization, the module switches to the correction state to process the outgoing events and data after the instruction fetch module receives three rounds of 64 instructions. Therefore, a counter is set to control the conversion of the prediction and correction states.

[0022] In the correction state, the branch prediction top-level control module obtains events and data from the outgoing module and the exception handling module (which will only interact after an exception occurs). After processing, it sends the next round of instruction fetch address to the instruction fetch module and switches to the prediction state. Each outgoing instruction correction slot (Correchtion_rou1~Correchtion_rou4) corresponds to a 1-way interface. After switching to the correction state, it will receive at least one event and data from one of the four outgoing instruction correction slots, as well as the event and data of the end of the outgoing instruction. The strategy of four-instruction slot correction allows the processor to accurately predict the jump direction of branch instructions within one cycle, thereby taking out more instructions from the instruction cache, thereby improving instruction throughput. After receiving the events and data of the outgoing instruction correction slot, they are sent to the perceptron branch prediction module through the asynchronous control chain for correction. At the same time, the correct address in the data brought by each outgoing instruction correction slot is recorded. Because the data given by the outgoing instruction contains the base address of the instruction fetched from the outgoing instruction correction slot, and the order of outgoing instruction must follow the path sequence of Correchtion_rou1~Correchtion_rou4, the last recorded base address must be the base address of the next round of instruction fetch (except for abnormal situations). Figure 1 The event link line of the retirement termination path_rou5 of the outgoing data correction termination path is carried out, and the correction state is converted to the prediction state. The path is selected through the exception signal to control whether the recorded base address is not sent.

[0023] The internal mechanism of the perceptron branch prediction module is as follows Figure 2As shown, it includes a prediction submodule and a correction submodule. The prediction submodule includes a prediction data unpacking module (Data_Unpacking), a B-type prediction module (B_type), a Jalr-type prediction module (Jalr_type), a Call-type prediction module (Call_type) and a Ret-type prediction module (Ret_type). The correction submodule includes a correction data unpacking module (Data_Unpacking), a B-type correction module (B_correction) and a Jalr-type correction module (Jalr_correction). When the branch prediction top-level control module sends a prediction request signal and a data packet (Inst_Buffer), the perceptron branch prediction module will choose to enter the prediction unit (Prediction_Unit) to perform the prediction process; when the branch prediction top-level control module sends a prediction correction request signal and a data packet (C_Data), the perceptron branch prediction module will choose to enter the correction unit (Prediction_Unit).

[0024] The prediction data unpacking module is used to find the first jump instruction from the data packet to be predicted by the branch prediction module of the sensor, and record the branch instruction information of the jump instruction, including the instruction number (index), instruction type (o_type), original PC (o_pc) value, next instruction PC (o_next_pc) value, and jump PC (o_addr) value. The prediction data unpacking module detects whether the data packet contains a jump instruction according to the instruction type code. The specific instruction code table is as follows: Figure 3 As shown, the detection method is to detect whether the 3-bit instruction code of each instruction is one of 000, 001, 010, 011, 100, and 111. After the data packet to be branch predicted is processed by the prediction data unpacking module, it enters the corresponding prediction submodule according to the branch instruction type code, predicts the corresponding jump instruction, and outputs the prediction result.

[0025] The B-type prediction module adopts a dynamic branch prediction model implemented by a single-layer perceptron, including a history record table submodule, a weight table submodule and a prediction logic submodule. A 20-bit global history register and a counter are set inside the history record table submodule. The global history register records the prediction results of each B-type branch instruction; the weight table submodule adopts a 256*72 SRAM, and the lower 8 bits of the PC of each B-type instruction store a 72-bit weight value table. The 72 bits are divided into 9 8-bit weights for predicting B-type jump instructions; the 72-bit weight value table is taken out from the weight table submodule through the lower 8 bits of the PC of the input B-type instruction, and is sent to the prediction logic submodule together with the lower 8 bits of the global history register in the history record table submodule. The prediction logic submodule divides the 72-bit weight value table into 9 8-bit weight registers and sets a sum register to predict B-type jump instructions.

[0026] A 16*37-bit two-dimensional history record table is set inside the Jalr type prediction module to record the PC value and number of correct jump addresses of each Jalr type instruction (37 bits = 32-bit PC + 5-bit number of times).

[0027] The Call type prediction module manages Call type instructions and the Ret type prediction module manages Ret type instructions using a simulated stack. Call type instructions and Ret type instructions normally appear in pairs. When a Call type instruction appears, the next instruction of the original instruction is pushed onto the stack, and the value of the PC of the original Call type jump instruction is output. When a Ret type instruction appears, an instruction is popped from the top of the stack and output as a predicted jump instruction.

[0028] The correction data unpacking module is used to split the instructions in the prediction correction data packet received by the perceptron branch prediction module, and send them to the corresponding correction submodule according to the branch instruction type code to correct the branch instruction.

[0029] The B-type correction module first takes out the 72-bit weight value table and the lower 8 bits of the global history register from the weight table and the history table and sends them to the B-type correction module, and then divides the 72-bit global history register value into 9 8-bit registers. Traverse the history registers, update the register values, and store the updated weight table in the weight table submodule. The history table submodule judges based on the B-type prediction result given by the outgoing instruction. If the B-type prediction is correct, then the counter is subtracted by 1. If the B-type prediction given by the outgoing instruction is wrong, then the global history register is right-shifted by the number of bits of the counter value to restore it to the value corresponding to the B-type instruction prediction, and the counter is reset to zero.

[0030] The Jalr type correction module first uses the 16 entries of the history weight table to find the one with the smallest five bits, and records the number of times and the item number. 16 flag registers are set to indicate whether the corrected jump address already exists in each item in the history table.

[0031] The single-layer perceptron branch prediction system in the asynchronous superscalar processor of the present invention is implemented by a two-phase single-rail self-timed event-driven circuit based on the bounded data binding (BBD) handshake protocol, namely, a BBD-type asynchronous circuit. Its implementation mechanism is based on the Click controller family in the asynchronous circuit, which can effectively realize clock-free control and optimize timing management in a local range. The BBD-type asynchronous circuit is a technology that divides the design structure of the circuit into two parts, the data path and the control path, by decomposing the timing dependency problem, so as to ensure stable data transmission and operation at different stages.

[0032] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A single-layer perceptron branch prediction method in an asynchronous superscalar processor, characterized in that: The steps include: In an asynchronous superscalar processor architecture, when a branch prediction top-level control module is in a prediction state, after sending a prediction request signal and a corresponding data packet through an instruction fetch module, the branch prediction top-level control module controls the data to be sent to a perceptron branch prediction module for prediction. The perceptron branch prediction module loads the historical data of branch instructions before the instruction is executed, stores the branch instruction information as a number of historical bits, and uses the branch instruction information for weighted calculation. If the predicted weighted result meets a specific threshold, the branch instruction is predicted to jump, otherwise the branch instruction is predicted not to jump. At the same time, the perceptron branch prediction module dynamically updates the historical record and weight of the branch instruction information according to the change of branch behavior, and returns the prediction information to the branch prediction top-level control module, which then sends data to the instruction fetch module for bidirectional instruction fetching. When the instruction fetch module receives a full round of instructions, the branch prediction top-level control module switches its state to a correction state. When the branch prediction top-level control module is in the correction state, after sending the prediction correction request signal and the corresponding data packet through the out-of-band module, the branch prediction top-level control module sends data to the perceptron branch prediction module, and the perceptron branch prediction module performs correction operations on the branch instruction, including modifying the historical records and weights of the branch instruction information. When the out-of-band module sends a correction end signal, the branch prediction top-level control module sends the base address of the next round of instruction fetching to the instruction fetch module, and at the same time, the branch prediction top-level control module switches its state to the prediction state.

2. The single-layer perceptron branch prediction method in an asynchronous superscalar processor according to claim 1, characterized in that: The branch prediction top-level control module selects the instruction fetch data branch prediction path to send data to the perceptron branch prediction module to perform branch prediction on the branch instruction. The branch prediction top-level control module selects different out-of-order instruction correction slots to send data to the perceptron branch prediction module to perform correction operations on the branch instruction. When the out-of-order end event and data occur, the branch prediction top-level control module ends the correction operation by selecting the out-of-order data correction end path and converts the correction state to the prediction state.

3. The single-layer perceptron branch prediction method in an asynchronous superscalar processor according to claim 2, characterized in that: A counter is set in the branch prediction top-level control module, and the conversion between the prediction state and the correction state is controlled by the counter.

4. The single-layer perceptron branch prediction method in an asynchronous superscalar processor according to claim 1, characterized in that: The branch instruction information includes instruction number, instruction type, original PC value, next instruction PC value, and jump PC value.

5. A single-layer perceptron branch prediction system in an asynchronous superscalar processor that implements the single-layer perceptron branch prediction method in an asynchronous superscalar processor according to any one of claims 1 to 4, characterized in that: It includes a branch prediction top-level control module, a perceptron branch prediction module, an instruction fetch module, and an exit module, among which: Branch prediction top-level control module: used to receive the prediction request signal and the corresponding data packet sent by the instruction fetch module, or receive the prediction correction request signal and the corresponding data packet sent by the exit module, and send data to the perceptron branch prediction module; Perceptron branch prediction module: includes a prediction submodule and a correction submodule, wherein the prediction submodule includes a prediction data unpacking module, a B-type prediction module, a Jalr-type prediction module, a Call-type prediction module, and a Ret-type prediction module; the correction submodule includes a correction data unpacking module, a B-type correction module, and a Jalr-type correction module; The prediction data unpacking module is used to find the first jump instruction from the prediction data packet received by the perception machine branch prediction module, and record the branch instruction information of the jump instruction. The prediction data unpacking module detects whether the data packet contains the jump instruction according to the instruction type code; the data packet to be branch predicted enters the corresponding prediction submodule according to the branch instruction type code after being processed by the prediction data unpacking module, predicts the corresponding jump instruction and outputs the prediction result; The correction data unpacking module is used to split the instructions in the prediction correction data packet received by the perception machine branch prediction module, and send them to the corresponding correction submodule according to the branch instruction type code to correct the branch instruction.

6. The single-layer perceptron branch prediction system in an asynchronous superscalar processor according to claim 5, characterized in that: The type B prediction module adopts a dynamic branch prediction model implemented by a single-layer perceptron, including a history record table submodule, a weight table submodule and a prediction logic submodule. A global history register and a counter are set inside the history record table submodule, and the global history register records the prediction results of each type B branch instruction; the weight table submodule adopts a 256*72 SRAM, and the lower 8 bits of the PC of each type B instruction store a 72-bit weight value table, and the 72 bits are divided into 9 8-bit weights for predicting type B jump instructions; the 72-bit weight value table is taken out from the weight table submodule through the lower 8 bits of the PC of the input type B instruction, and is sent to the prediction logic submodule together with the lower 8 bits of the global history register in the history record table submodule, and the prediction logic submodule divides the 72-bit weight value table into 9 8-bit weight registers, and sets a summation register to predict type B jump instructions.

7. The single-layer perceptron branch prediction system in an asynchronous superscalar processor according to claim 5, characterized in that: A 16*37-bit two-dimensional history record table is set inside the Jalr type prediction module to record the PC value and number of correct jump addresses of each Jalr type instruction.

8. The single-layer perceptron branch prediction system in an asynchronous superscalar processor according to claim 5, characterized in that: The Call type prediction module manages the Call type instructions and the Ret type prediction module manages the Ret type instructions using a simulated stack. When a Call type instruction appears, the next instruction of the original instruction is pushed onto the stack and the value of the PC of the original Call type jump instruction is output. When a Ret type instruction appears, an instruction is popped from the top of the stack and output as a predicted jump instruction.

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