Instruction stream generation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an instruction stream generation method and device, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that an operation code is selected from an operation code set to serve as a first operation code; selecting an operation code from a subsequent operation code set corresponding to the first operation code as a second operation code to obtain a dependent operation code pair formed by the first operation code and the second operation code; acquiring a next dependent operation code pair from the operation code set based on an inclusion relationship between the second operation code and the preorder operation code set until all dependent operation code pairs corresponding to a preset dependency relationship are obtained; and obtaining target instructions generated for the operation codes in the dependent operation code pairs, and obtaining an instruction stream formed by the target instructions. All dependency operation code pairs under the preset dependency relationship can be efficiently generated, and the accuracy of testing a CPU through an instruction stream can be improved. And the efficiency of testing the CPU through the instruction stream can be improved to a certain extent.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to an instruction stream generation method, device, electronic device and storage medium. Background Art

[0002] At present, with the continuous development of computer technology, the design of the central processing unit (CPU) is becoming more and more complex. How to verify the CPU during the design and development process is becoming more and more important in the CPU development process.

[0003] Usually, an instruction generator is used to randomly generate a continuous stream of instructions to input into the simulated CPU core or CPU physical core, and the CPU is tested by observing its processing and response to these instruction streams. These instruction streams need to contain not only instructions with different opcodes, but also instruction pairs consisting of opcode pairs with dependencies, so as to test whether the CPU can correctly process different instructions and instruction combinations.

[0004] However, by randomly selecting opcodes and randomly generating instruction streams for testing, in order to include as many opcode combinations with dependencies as possible in the instruction stream, it is usually necessary to generate a large amount of instruction streams for testing, and even if a large amount of instruction streams are generated, there may still be missed combinations, resulting in poor efficiency and accuracy when the instruction stream generated by the above method is used for CPU testing. Summary of the invention

[0005] The embodiments of the present invention provide an instruction stream generation method, device, electronic device and storage medium, which can generate an instruction stream with high test efficiency and test accuracy, and improve the efficiency and accuracy of testing a CPU through the instruction stream.

[0006] In order to solve the above problem, an embodiment of the present invention discloses an instruction stream generation method, the method comprising: Select an opcode from the opcode set as a first opcode; wherein the first opcode belongs to a preceding opcode set, and the preceding opcode set is determined from the opcode set based on a preset dependency relationship; Selecting an opcode from a post-order opcode set corresponding to the first opcode as a second opcode, and obtaining a dependent opcode pair consisting of the first opcode and the second opcode; wherein the post-order opcode set is determined from the opcode set based on the preset dependency relationship; Based on the inclusion relationship between the second opcode and the preceding opcode set, obtaining a next dependent opcode pair from the opcode set until all dependent opcode pairs corresponding to the preset dependency relationship are obtained; Obtain target instructions generated for each opcode in each dependent opcode pair, and obtain an instruction stream consisting of each target instruction; wherein the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit.

[0007] Optionally, the method further includes: Based on the preset dependency relationship, obtaining a dependent register encoding from a target instruction corresponding to a previous opcode in a dependent opcode pair; Based on the preset dependency relationship and the dependent register encoding, a target instruction corresponding to a latter opcode in the dependent opcode pair is determined.

[0008] Optionally, the method further includes: Randomly generate a target instruction corresponding to a previous opcode and a target instruction corresponding to a subsequent opcode in the dependent opcode pair; When the target instruction corresponding to the subsequent opcode and the target instruction corresponding to the previous opcode have the same dependent register encoding corresponding to the preset dependency relationship, the subsequent opcode is deleted from the subsequent opcode set corresponding to the first opcode.

[0009] Optionally, the method further includes: After obtaining any dependent opcode pair, the subsequent opcode of the dependent opcode pair is deleted from the subsequent opcode set corresponding to the previous opcode of the dependent opcode pair.

[0010] Optionally, the method further includes: After deleting an opcode from any subsequent opcode set, detecting whether the subsequent opcode set is empty; When it is detected that the post-order operation code set is empty, deleting the operation code corresponding to the post-order operation code set from the pre-order operation code set; When it is detected that the preceding operation code set is empty, all dependent operation code pairs corresponding to the preset dependency relationship are determined.

[0011] Optionally, the method further includes: The target instruction stream is obtained by splicing the instruction streams corresponding to the plurality of preset dependencies respectively; or, between the dependency instruction pairs of the instruction streams corresponding to the preset dependencies, the dependency instruction pairs of the instruction streams corresponding to other preset dependencies are inserted to obtain the target instruction stream.

[0012] Optionally, selecting an operation code from the operation code set as the first operation code includes: Select an operation code from the operation code set, and determine the inclusion relationship between the operation code and the preceding operation code set; When the inclusion relationship is inclusion, the operation code is used as the first operation code; When the inclusion relationship is non-inclusion, the opcode is used as an independent opcode, and an opcode is reselected from the opcode set as the first opcode; wherein the independent opcode is used to generate an independent opcode included in the instruction stream.

[0013] Optionally, the preset dependency relationship includes a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship.

[0014] On the other hand, an embodiment of the present invention discloses an instruction stream generating device, the device comprising: A first operation code module, configured to select an operation code from the operation code set as a first operation code; wherein the first operation code belongs to a preceding operation code set, and the preceding operation code set is determined from the operation code set based on a preset dependency relationship; a second operation code module, configured to select an operation code from a post-order operation code set corresponding to the first operation code as a second operation code, and obtain a dependent operation code pair consisting of the first operation code and the second operation code; wherein the post-order operation code set is determined from the operation code set based on the preset dependency relationship; A dependent opcode pair module, configured to obtain a next dependent opcode pair from the opcode set based on an inclusion relationship between the second opcode and the preceding opcode set, until all dependent opcode pairs corresponding to the preset dependency relationship are obtained; The instruction stream module is used to obtain the target instructions generated for each opcode in each dependent opcode pair, and obtain an instruction stream composed of each target instruction; wherein the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit.

[0015] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the aforementioned method.

[0016] The embodiment of the present invention further discloses a computer-readable storage medium on which instructions are stored. When executed by one or more processors, the processors execute the method as described above.

[0017] The embodiment of the present invention includes the following advantages: in the instruction stream generation method provided in the embodiment of the present invention, an operation code is selected from the operation code set as the first operation code; wherein the first operation code belongs to the pre-order operation code set, and the pre-order operation code set is determined from the operation code set based on the preset dependency relationship; an operation code is selected from the post-order operation code set corresponding to the first operation code as the second operation code, and a dependent operation code pair consisting of the first operation code and the second operation code is obtained; wherein the post-order operation code set is determined from the operation code set based on the preset dependency relationship; based on the inclusion relationship between the second operation code and the pre-order operation code set, the next dependent operation code pair is obtained from the operation code set until all dependent operation code pairs corresponding to the preset dependency relationship are obtained; the target instruction generated for each operation code in each dependent operation code pair is obtained, and an instruction stream consisting of each target instruction is obtained; wherein the target instruction corresponding to the operation code in the same dependent operation code pair has the same register encoding, and the instruction stream is used to test the central processing unit. In this way, all dependent operation code pairs under the preset dependency relationship can be efficiently generated, and the instruction stream generated according to these dependent operation code pairs can include all possible instruction combinations with the preset dependency relationship, which helps to improve the accuracy of testing the CPU through the instruction stream. And because the opcodes can be specifically selected from the post-opcode set of the opcode to form dependent opcode pairs, the efficiency of selecting dependent opcode pairs can be improved to a certain extent, which helps to improve the density of instructions with dependencies in the generated instruction stream, thereby reducing the length of the instruction stream required to test the CPU and improving the efficiency of the instruction stream in testing the CPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0019] Figure 1 is a flowchart of a method for generating an instruction stream provided by an embodiment of the present invention; Figure 2 This is an operation code selection flow chart provided by an embodiment of the present invention; Figure 3 is a block diagram of an instruction stream generating device provided by an embodiment of the present invention; Figure 4 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] Reference Figure 1 , shows a flow chart of the steps of an instruction stream generation method provided by an embodiment of the present invention, such as Figure 1 As shown, the method may specifically include the following steps: Step 101: Select an opcode from an opcode set as a first opcode; wherein the first opcode belongs to a preceding opcode set, and the preceding opcode set is determined from the opcode set based on a preset dependency relationship.

[0022] In an embodiment of the present invention, an opcode (Opcode) represents a part of a computer instruction, which is used to represent a specific operation or task. Each instruction usually consists of an opcode and an operand. The opcode defines the operation that the CPU should perform, and the operand defines the data location of the operation and / or the storage location of the operation result. The opcode can also be called the instruction name. An opcode set represents a set of all opcodes that need to be tested for the CPU or CPU core to be tested when the CPU is verified in the core. A pre-order opcode set represents an opcode in the opcode set whose running result can be used as the running condition of a post-order opcode, that is, there is a preset dependency relationship between a pre-order opcode and a post-order opcode of the pre-order opcode.

[0023] In an embodiment of the present invention, there may be multiple preset dependencies, and according to each dependency, a corresponding set of preceding opcodes may be determined from an opcode set. The preset dependencies may include but are not limited to read-after-write dependencies, write-after-write dependencies, read-after-write dependencies, and read-after-read dependencies. Among them, the read-after-write dependency relationship indicates that the register written by the previous opcode when the next opcode is executed can be read when the next opcode is executed, that is, the source register of the instruction generated by the next opcode can be the same as the destination register of the instruction generated by the previous opcode; the write-after-write dependency relationship indicates that the register written by the previous opcode when the next opcode is executed can be written when the next opcode is executed, that is, the destination register of the instruction generated by the next opcode can be the same as the destination register of the instruction generated by the previous opcode; the write-after-read dependency relationship indicates that the register read by the previous opcode when the next opcode is executed can be written when the next opcode is executed, that is, the destination register of the instruction generated by the next opcode can be the same as the source register of the instruction generated by the previous opcode; the read-after-read dependency relationship indicates that the register read by the previous opcode when the next opcode is executed can be read when the next opcode is executed, that is, the source register of the instruction generated by the next opcode can be the same as the source register of the instruction generated by the previous opcode.

[0024] Exemplarily, if an opcode set is [ADD, LUI, ORI, BEQ], ADD is used to perform addition operations on the values ​​of two registers and store the result in a destination register; LUI is used to add an immediate value to a register; ORI is used to perform addition operations on the value of a register and an immediate value and store the result in a destination register; BEQ is used to jump to the specified instruction address to continue execution when the values ​​of the two registers are equal. Since the above opcodes ADD, LUI and ORI need to write to registers during execution, for the read-after-write dependency, it can be determined that ADD, LUI, ORI in the above opcode set can constitute a preamble opcode set corresponding to the read-after-write dependency, or a preamble opcode set corresponding to the write-after-write dependency.

[0025] In the embodiment of the present invention, an operation code is selected from the operation code set. If the operation code belongs to one of the preceding operation code sets corresponding to the preset dependency relationship, the operation code can be used as the first operation code. Specifically, the selection method may include but is not limited to random selection, sequential selection, reverse selection, alternating selection, etc., which is not specifically limited in the embodiment of the present invention.

[0026] It should be noted that, in an embodiment of the present invention, an opcode can be selected from an opcode set and recorded. If the selected opcode does not belong to a preceding opcode set, the opcode continues to be selected from the opcode set until an opcode belonging to the preceding opcode set is selected and used as the first opcode. Alternatively, an opcode can be directly selected from the preceding opcode set corresponding to the opcode set as the first opcode.

[0027] Step 102: Select an opcode from the post-opcode set corresponding to the first opcode as the second opcode, and obtain a dependent opcode pair consisting of the first opcode and the second opcode; wherein the post-opcode set is determined from the opcode set based on the preset dependency relationship.

[0028] In an embodiment of the present invention, each preamble operation code in the preamble operation code set may correspond to a postamble operation code set, and the postamble operation code set corresponding to the preamble operation code includes a subsequent operation code having a corresponding preset dependency relationship with the preamble operation code.

[0029] For example, if an opcode set is [ADD, LUI, ORI, BEQ], the preceding opcode set corresponding to the read-after-write dependency is [ADD, LUI, ORI]. Since ADD, ORI, and BEQ in the opcode set need to read registers when executed, the following opcode set ADD_SET corresponding to ADD in the preceding opcode set is [ADD, ORI, BEQ], the following opcode set LUI_SET corresponding to LUI is [ADD, ORI, BEQ], and the following opcode set ORI_SET corresponding to ORI is [ADD, ORI, BEQ].

[0030] In the embodiment of the present invention, an operation code may be selected from the set of subsequent operation codes corresponding to the first operation code selected as the second operation code corresponding to the first operation code. The method of selecting the operation code may include but is not limited to random selection, sequential selection, reverse selection, alternating selection, etc., which is not specifically limited in the embodiment of the present invention.

[0031] Since the first opcode and the second opcode selected above are respectively selected from the preceding opcode and the succeeding opcode corresponding to the preset dependency relationship, the selected first opcode and the corresponding second opcode can constitute a dependent opcode pair that conforms to the preset dependency relationship, that is, the dependent opcode pair represents a group of opcodes that conform to the preset dependency relationship.

[0032] Exemplarily, if the preceding opcode set corresponding to the read-after-write dependency is [ADD, LUI, ORI], the selected first opcode is ADD, and the subsequent opcode set ADD_SET corresponding to ADD = [ADD, ORI, BEQ], then an opcode (for example, ORI) can be selected from the set ADD_SET as the second opcode corresponding to the first opcode ADD, then ADD and ORI constitute a dependent opcode pair (ADD, ORI) corresponding to the read-after-write dependency.

[0033] Step 103: Based on the inclusion relationship between the second opcode and the preceding opcode set, obtain the next dependent opcode pair from the opcode set until all dependent opcode pairs corresponding to the preset dependency relationship are obtained.

[0034] In an embodiment of the present invention, the next dependent opcode pair can be continuously obtained from the opcode set according to the inclusion relationship between the second opcode and the preceding opcode set. Specifically, if the second opcode belongs to the preceding opcode set, the second opcode can be used as the next preceding opcode, and the next subsequent opcode can be obtained from the subsequent opcode set corresponding to the next preceding opcode, and the next preceding opcode and the next subsequent opcode can constitute the next dependent opcode pair; if the second opcode does not belong to the preceding opcode set, an opcode belonging to the preceding opcode set can be reselected from the opcode set as the next preceding opcode, and the next subsequent opcode can be obtained from the subsequent opcode set corresponding to the next preceding opcode, and the next preceding opcode and the next subsequent opcode can constitute the next dependent opcode pair.

[0035] Exemplarily, if the pre-order opcode set corresponding to the read-after-write dependency relationship is [ADD, LUI, ORI], the first opcode selected is ADD, and the post-order opcode set ADD_SET corresponding to ADD is [ADD, ORI, BEQ], after obtaining a dependent opcode pair (ADD1, ORI2) corresponding to a read-after-write dependency relationship formed by ADD and ORI, it can be determined whether ORI2 belongs to the pre-order opcode set. After determining that the inclusion relationship between ORI2 and the pre-order opcode set is that it belongs, an opcode (for example, BEQ) can be selected from the post-order opcode set ORI_SET=[ADD, ORI, BEQ] corresponding to the next pre-order opcode ORI2 as the next post-order opcode, and the next dependent opcode pair (ORI2, BEQ3) is obtained. Afterwards, we can continue to determine whether BEQ3 belongs to the preceding opcode set. After determining that the inclusion relationship between BEQ3 and the preceding opcode set is not, we can continue to select an opcode belonging to the preceding opcode set (such as LUI) from the opcode set as the third preceding opcode, and select the third subsequent opcode (such as ORI) from the subsequent opcode set LUI_SET=[ADD, ORI, BEQ] corresponding to LUI. Then the third dependent opcode pair is (LUI4, ORI5).

[0036] In the embodiment of the present invention, the above process can be repeated until all dependent opcode pairs corresponding to the preset dependency relationship are obtained, that is, all dependent opcode pairs that can be formed by combining all opcodes in the opcode set under the preset dependency relationship are obtained.

[0037] Step 104, obtaining the target instructions generated for each opcode in each dependent opcode pair, and obtaining an instruction stream composed of each target instruction; wherein, the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit.

[0038] In an embodiment of the present invention, for each dependent opcode pair obtained, a target instruction corresponding to each opcode can be generated. The target instruction can be composed of an opcode and an operand. The opcode in the target instruction is used to indicate the type of operation performed by the instruction, and the operand in the target instruction is used to indicate the data of the operation and / or the data storage location, and the operand may include but is not limited to the source register code, the destination register code, the immediate number, etc. The target instruction generated for the opcode in the same dependent opcode pair may have at least one pair of identical register codes.

[0039] Specifically, the opcodes in all dependent opcode pairs selected in the above steps can be arranged in the order of selection to form an opcode sequence, and the target instructions generated based on each opcode in the opcode sequence can constitute the above instruction stream. Furthermore, in addition to the opcodes in each dependent opcode pair, the above opcode sequence can also include independent opcodes selected from the opcode set that fail to form a dependent opcode pair. These independent opcodes and the opcodes in the dependent opcode pairs can be arranged in the opcode sequence in the order of selection, so that the instruction stream composed of the target instructions generated based on each opcode in the opcode sequence can contain richer opcodes, which helps to increase the complexity of the instruction stream and improve the test effect of the processor core test through the instruction stream.

[0040] Exemplarily, if three dependent opcode pairs are obtained for the read-after-write dependency, including (ADD1, ORI2), (ORI2, BEQ3) and (LUI4, ORI5), then the first dependent opcode pair (ADD1, ORI2) corresponds to two target instructions ADD1 and ORI2; the second dependent opcode pair (ORI2, BEQ3) corresponds to two target instructions ORI2 and BEQ3; the first dependent opcode pair (LUI, ORI) corresponds to two target instructions LUI4 and ORI5. Then the above dependent opcode pairs can form an opcode sequence [ADD1, ORI2, BEQ3, LUI4, ORI5]. Among them, a source register encoding of the ORI2 instruction can be the same as the destination register encoding of the ADD1 instruction, a source register encoding of the BEQ3 instruction can be the same as the destination register encoding of the ORI2 instruction, and a source register encoding of the ORI5 instruction can be the same as the destination register encoding of the LUI4 instruction. That is to say, a source register code of the ORI2 instruction can be directly determined according to the destination register code of the ADD1 instruction, a source register code of the BEQ3 instruction can be directly determined according to the destination register code of the ORI2 instruction, and so on. It should be noted that the register code in each target instruction does not need to be determined according to the register code of the previous target instruction, and can be selected from the register code set that can be used, and the selection method can include but is not limited to random selection, sequential selection, reverse selection, alternating selection, etc., which is not specifically limited in the embodiment of the present invention.

[0041] In summary, in an instruction stream generation method provided by an embodiment of the present invention, an operation code is selected from an operation code set as a first operation code; wherein the first operation code belongs to a pre-order operation code set, and the pre-order operation code set is determined from the operation code set based on a preset dependency relationship; an operation code is selected from a post-order operation code set corresponding to the first operation code as a second operation code, and a dependent operation code pair consisting of the first operation code and the second operation code is obtained; wherein the post-order operation code set is determined from the operation code set based on a preset dependency relationship; based on the inclusion relationship between the second operation code and the pre-order operation code set, the next dependent operation code pair is obtained from the operation code set until all dependent operation code pairs corresponding to the preset dependency relationship are obtained; the target instructions generated for each operation code in each dependent operation code pair are obtained, and an instruction stream consisting of each target instruction is obtained; wherein the target instructions corresponding to the operation codes in the same dependent operation code pair have the same register encoding, and the instruction stream is used to test the central processing unit. In this way, all dependent operation code pairs under the preset dependency relationship can be efficiently generated, and the instruction stream generated according to these dependent operation code pairs can include all possible instruction combinations with preset dependencies, which helps to improve the accuracy of testing the CPU through the instruction stream. And because the opcodes can be specifically selected from the post-opcode set of the opcode to form dependent opcode pairs, the efficiency of selecting dependent opcode pairs can be improved to a certain extent, which helps to improve the density of instructions with dependencies in the generated instruction stream, thereby reducing the length of the instruction stream required to test the CPU and improving the efficiency of the instruction stream in testing the CPU.

[0042] Optionally, in some embodiments, the instruction stream further includes an independent instruction generated based on the independent opcode, and the step of selecting an opcode from the opcode set as the first opcode may specifically include: Step 1011, select an operation code from the operation code set, and determine the inclusion relationship between the operation code and the preceding operation code set.

[0043] In an embodiment of the present invention, not only can dependent opcode pairs be selected from an opcode set, but independent opcodes that cannot form dependent opcode pairs with other opcodes can also be selected, so that the instruction stream generated based on the selected opcodes can include not only target instructions with dependent relationships, but also independent instructions, thereby helping to increase the complexity of the instruction stream and improve the accuracy and test effect of processor core testing based on the instruction stream.

[0044] Specifically, you can first determine the preceding opcode set corresponding to the preset dependency from the opcode set, then start selecting opcodes from the preceding opcode set, and determine the inclusion relationship between the selected opcode and the preceding opcode set, that is, determine whether the preceding opcode set contains the opcode, and the inclusion relationship may include inclusion and non-inclusion.

[0045] Reference Figure 2 , Figure 2 FIG. 2 shows a flowchart of an operation code selection provided by an embodiment of the present invention. Figure 2 As shown, the preceding opcode set can be first determined according to the preset dependency relationship, and the following opcode set corresponding to each opcode in the preceding opcode set can be determined, and then the first opcode can be selected. When selecting the opcode, it is determined whether the opcode currently to be selected is the first opcode. If the opcode currently to be selected is the first opcode, an opcode is selected from the opcode set, and the corresponding instruction is randomly generated, and then the second opcode is selected. Since the opcode currently to be selected is not the first opcode at this time, it is determined whether the previous opcode belongs to the preceding opcode set, that is, it is determined whether the first opcode selected above is in the preceding opcode set to obtain the judgment result. It should be noted that the above-mentioned random generation of corresponding instructions means randomly determining the source register encoding and / or the destination register encoding to obtain the corresponding instructions.

[0046] For example, if the instruction set architecture of a processor to be tested contains a total of 4 opcodes, namely ADD, LUI, ORI, and BEQ. For the read-after-write dependency, the corresponding pre-order opcode set INST_SET=[ADD, LUI, ORI], the post-order opcode set ADD_SET=[ADD, ORI, BEQ] corresponding to ADD, the post-order opcode set LUI_SET=[ADD, ORI, BEQ] corresponding to LUI, and the post-order opcode set ORI_SET=[ADD, ORI, BEQ] corresponding to ORI can be determined. If the first opcode ADD is randomly selected from the opcode set, and its registers are randomly encoded: the destination register rd=16, one source register rs1=3, and the other source register rs2=9, then the instruction corresponding to the first opcode ADD can be obtained as "ADD rd=16rs1=3 rs2=9".

[0047] Step 1012: When the inclusion relationship is inclusion, use the operation code as the first operation code.

[0048] In an embodiment of the present invention, if the inclusion relationship between an opcode selected from an opcode set and a preceding opcode set is inclusion, the opcode belongs to the preceding opcode set, and the opcode can be determined as the first opcode. Then, an opcode is selected from the subsequent opcode set corresponding to the first opcode as the second opcode, forming a dependent opcode pair.

[0049] like Figure 2As shown, when the second opcode is selected, it can be determined whether the previous opcode belongs to the previous opcode set, that is, the inclusion relationship between the first opcode selected above and the previous opcode set is determined. If the judgment result is yes, the first opcode selected above is used as the first opcode, and a subsequent opcode is selected from the subsequent opcode set corresponding to the previous opcode, that is, a second opcode is selected from the subsequent opcode set corresponding to the first opcode, that is, the second opcode. The second opcode can form a dependent opcode pair with the first opcode. For the second opcode, the target instruction of the subsequent opcode can be generated according to the target instruction of the previous opcode, that is, according to the preset dependency relationship and the dependent register encoding corresponding to the previous opcode in the dependent opcode pair, the corresponding target instruction is generated.

[0050] Continuing with the above example, since the first opcode selected belongs to the preceding opcode set INST_SET, the first ADD opcode can be used as the first opcode, and an opcode is selected from the following opcode set ADD_SET=[ADD, ORI, BEQ] as the second opcode (for example, BEQ), i.e., the second opcode. The destination register code 16 in the target instruction corresponding to the first opcode is used as a source register code of the second opcode BEQ. The remaining register codes of the second opcode BEQ can be randomly generated, and its target instruction can be "BEQ rs1=16 rs2=23".

[0051] Step 1013, when the inclusion relationship is non-inclusion, the opcode is used as an independent opcode, and an opcode is reselected from the opcode set as the first opcode; wherein the independent opcode is used to generate an independent opcode included in the instruction stream.

[0052] In an embodiment of the present invention, if the inclusion relationship between an opcode selected from an opcode set and a preceding opcode set is non-inclusion, then the opcode does not belong to the preceding opcode set, and the opcode can be used as an independent opcode, and an independent instruction randomly generated based on the independent opcode is stored in the instruction stream, and the opcode continues to be selected from the opcode set, and the inclusion relationship between the selected opcode and the preceding opcode set is continued to be determined, and the above process is repeated until the selected opcode belongs to the preceding opcode set, and the most recently selected opcode is used as the first opcode.

[0053] like Figure 2As shown, when selecting an opcode, it can be determined whether the previous opcode belongs to the pre-order opcode set. For example, when selecting the second opcode, it can be determined whether the first opcode belongs to the pre-order opcode set. If the judgment result is no, it means that the opcode currently required to be selected cannot form a dependent opcode pair with the previous opcode. In one embodiment, an opcode can be selected from the pre-order opcode set / opcode set, and the corresponding instruction can be randomly generated. In another embodiment, an opcode can also be selected from the opcode set, and the corresponding instruction can be randomly generated. Exemplarily, if the first and second opcodes selected do not belong to the pre-order opcode set, when selecting the third opcode, an opcode can be selected from the pre-order opcode set / opcode set to obtain the third opcode, and continue to determine whether the third opcode belongs to the pre-order opcode set, until the nth opcode belonging to the pre-order opcode set is selected as the first opcode. Then, a second opcode is selected from the subsequent opcode set corresponding to the first opcode, that is, the n+1th opcode. The second opcode can form a dependent opcode pair with the first opcode. For the n+1th opcode, its corresponding target instruction can be generated according to the preset dependency relationship and the dependent register encoding corresponding to the previous opcode in the dependent opcode pair, and the instruction generated according to the nth opcode is the target instruction.

[0054] Continuing with the above example, if the first opcode selected is BEQ, since the first opcode selected does not belong to the previous opcode set INST_SET, it can be determined that the first opcode is an independent opcode, and the second opcode can be selected from the opcode set or the previous opcode set INST_SET. If the second opcode selected is ADD, since the second opcode selected belongs to the previous opcode set INST_SET, the second opcode ADD can be used as the first opcode, and an opcode (for example, BEQ) is selected from the post-opcode set ADD_SET=[ADD, ORI, BEQ] as the second opcode, that is, the third opcode. Then the first opcode is used as an independent opcode, and the second opcode and the third opcode constitute a dependent opcode pair. The independent instruction of the first opcode and the target instruction corresponding to the second opcode can be randomly generated, and the target instruction corresponding to the third opcode can be generated according to the target instruction corresponding to the second opcode.

[0055] In the embodiment of the present invention, an opcode can be selected from the opcode set, and the inclusion relationship between the opcode and the preceding opcode set can be determined; if the inclusion relationship is inclusion, the opcode is used as the first opcode; if the inclusion relationship is non-inclusion, the opcode is used as an independent opcode, and an opcode is reselected from the opcode set as the first opcode. This helps to improve the complexity and randomness of the instruction stream obtained later, and helps to improve the accuracy of the in-core test through the instruction stream.

[0056] Optionally, in some embodiments, the target instruction may be determined by the following steps: Step A1, based on the preset dependency relationship, obtain the dependent register code from the target instruction corresponding to the previous opcode in the dependent opcode pair.

[0057] In an embodiment of the present invention, the target instruction corresponding to the opcode in each dependent opcode pair can be generated according to the selection order. For the latter opcode in each dependent opcode pair, its target instruction can be determined according to the target instruction corresponding to the previous opcode in the dependent opcode pair to which it belongs; for the previous opcode in each dependent opcode pair, its target instruction can be randomly generated. It should be noted that since the previous opcode of the dependent opcode may belong to the next opcode of the previous dependent opcode pair, in this case, the corresponding target instruction is generated for the dependent opcode as the next opcode of the previous dependent opcode pair.

[0058] In an embodiment of the present invention, the dependent register encoding indicates the encoding of the register whose previous opcode needs to be consistent with the next opcode in the dependent opcode pair under a preset dependency relationship. For example, under a read-after-write dependency relationship, the destination register of the previous opcode serves as the dependent register; under a write-after-read dependency relationship, a source register of the previous opcode serves as the dependent register.

[0059] Step A2: determining a target instruction corresponding to a latter opcode in the dependent opcode pair based on the preset dependency relationship and the dependent register encoding.

[0060] In the embodiment of the present invention, the target instruction corresponding to the latter opcode in the dependent opcode pair may be determined based on the preset dependency relationship and the dependent register code corresponding to the former opcode in the dependent opcode pair.

[0061] Continuing with the above example, if the first extracted opcode is ADD and the second opcode is BEQ, then the target instruction corresponding to the first opcode ADD can be randomly generated, for example, "ADD rd=16 rs1=3 rs2=9", and 16 can be used as a source register code of the target instruction corresponding to the second opcode BEQ, and other register codes can be randomly generated, for example, "BEQrs1=16 rs2=23" can be obtained.

[0062] In an embodiment of the present invention, based on a preset dependency relationship, a dependent register code can be obtained from the target instruction corresponding to the previous opcode in the dependent opcode pair; based on the preset dependency relationship and the dependent register code, the target instruction corresponding to the latter opcode in the dependent opcode pair is determined, so that the target instructions generated by the dependent opcode pair can have corresponding register codes, which helps to improve the efficiency and accuracy of the subsequent generated instruction stream.

[0063] Optionally, in some embodiments, the target instruction may also be determined by the following steps: Step B1, randomly generate a target instruction corresponding to the previous opcode and a target instruction corresponding to the next opcode in the dependent opcode pair.

[0064] In the embodiment of the present invention, the same dependent opcode pair may appear multiple times during the selection process, and for each selected dependent opcode pair, corresponding target instructions may be randomly generated for both the previous opcode and the next opcode in the dependent opcode pair. The same dependent opcode pair refers to a dependent opcode pair in which the previous opcode and the next opcode are the same.

[0065] For example, if a sequence of 4 opcodes is obtained after selection: [opcode 1, opcode 2, opcode 3, opcode 4], opcode 1 may be the same as opcode 3, opcode 2 may be the same as opcode 4, opcodes 1 and 2 may form a dependent opcode pair, and opcodes 3 and 4 may form another dependent opcode pair, then these two dependent opcode pairs belong to the same dependent opcode pair.

[0066] Step B2, when the target instruction corresponding to the subsequent opcode and the target instruction corresponding to the previous opcode have the same dependent register encoding corresponding to the preset dependency relationship, delete the subsequent opcode from the subsequent opcode set corresponding to the first opcode.

[0067] In the embodiment of the present invention, since the target instruction corresponding to the latter opcode in the dependent opcode pair and the target instruction corresponding to the former opcode can be randomly generated, the dependent register encodings of the two target instructions may be the same or different, that is, the two target instructions may have the same dependent register encoding corresponding to the preset dependency relationship, or may not have the same dependent register encoding corresponding to the preset dependency relationship. Exemplarily, in the case where the preset dependency relationship is a read-after-write dependency relationship, if the target instruction corresponding to the latter opcode ADD in a dependent opcode pair is ADD14 17 54, and the target instruction corresponding to the former opcode SUB is SUB 17 34 38, then the destination register encoding 17 of the target instruction of the former opcode SUB is the same as the source register encoding 17 of the target instruction of the latter opcode ADD, and the two target instructions have the same dependent register encoding 17 corresponding to the preset dependency relationship.

[0068] If the target instruction corresponding to the latter opcode in a dependent opcode pair and the target instruction corresponding to the previous opcode do not contain the same dependent register code, the latter opcode will continue to be retained in the post-order opcode set corresponding to the previous opcode, so that the dependent opcode pair can still be selected in the post-order selection process to continue to randomly generate the corresponding target instruction. If the target instruction corresponding to the latter opcode in a dependent opcode pair and the target instruction corresponding to the previous opcode contain the same dependent register code, it means that the dependent instruction pair corresponding to the dependent opcode has been generated, and the latter opcode can be deleted in the post-order opcode set corresponding to the previous opcode, so that the dependent opcode pair will no longer be generated in the post-order selection process.

[0069] In the embodiment of the present invention, by randomly generating a target instruction corresponding to the previous opcode and a target instruction corresponding to the next opcode in a dependent opcode pair; when the target instruction corresponding to the next opcode and the target instruction corresponding to the previous opcode have the same dependent register encoding corresponding to a preset dependency relationship, the next opcode is deleted from the subsequent opcode set corresponding to the first opcode. It is possible to generate multiple groups of different instructions for a dependent opcode pair, and ensure that one group of instructions belongs to the dependent instruction pair of the dependent opcode pair, avoid repeatedly generating multiple dependent instruction pairs of the same dependent opcode pair, and improve the instruction generation efficiency.

[0070] Optionally, in some embodiments, after obtaining any dependent opcode pair, the subsequent opcode of the dependent opcode pair is deleted from a subsequent opcode set corresponding to the previous opcode of the dependent opcode pair.

[0071] Exemplarily, a first opcode can be selected, and an opcode can be selected as the second opcode from the post-order opcode set corresponding to the first opcode, to obtain a dependent opcode pair consisting of the first opcode and the second opcode, and then the second opcode can be deleted from the post-order opcode set corresponding to the first opcode. This avoids repeatedly obtaining the same dependent opcode pair consisting of the first opcode and the second opcode in the post-order selection process, thereby improving the efficiency of obtaining all dependent opcode pairs. Correspondingly, after selecting any dependent opcode pair, the latter opcode in the dependent opcode pair can be deleted from the post-order opcode set corresponding to the previous opcode in the dependent opcode pair.

[0072] Optionally, in some embodiments, after deleting an opcode from any subsequent opcode set, the following steps may also be included: Step C1, detecting whether the post-order operation code set is empty.

[0073] In the embodiment of the present invention, after an operation code in any subsequent operation code set is deleted, the subsequent operation code set may be checked to determine whether the subsequent operation code set is empty.

[0074] Step C2: when it is detected that the post-order operation code set is empty, deleting the operation code corresponding to the post-order operation code set from the pre-order operation code set.

[0075] In the embodiment of the present invention, if it is detected that a post-order opcode set is empty, it means that the post-order opcode set no longer contains any opcode, that is, all dependent opcode pairs that can be formed between the post-order opcode set and its corresponding opcodes have been selected, and the opcode corresponding to the post-order opcode set can be directly deleted from the pre-order opcode set. If it is detected that the post-order opcode set is not empty, it means that the post-order opcode set still contains opcodes, and the post-order opcode set can be retained to continue to select dependent opcode pairs.

[0076] Step C3, when it is detected that the preceding operation code set is empty, all dependent operation code pairs corresponding to the preset dependency relationship are determined.

[0077] In the embodiment of the present invention, after deleting the operation code from the preceding operation code set, the preceding operation code set can be detected to determine whether the preceding operation code set is empty. When it is detected that the preceding operation code set is empty, it can be explained that all dependent operation code pairs of the corresponding preset dependency relationship have been selected and generated, and all dependent operation code pairs corresponding to the preset dependency relationship can be determined.

[0078] In the embodiment of the present invention, after deleting an opcode from any post-order opcode set, it is detected whether the post-order opcode set is empty; when it is detected that the post-order opcode set is empty, the opcode corresponding to the post-order opcode set is deleted from the pre-order opcode set; when it is detected that the pre-order opcode set is empty, it is determined to obtain all dependent opcode pairs corresponding to the preset dependency relationship. The opcodes that have formed dependent opcode pairs can be removed from the post-order opcode set in a timely manner, and the opcodes that have formed all possible dependent opcode pairs can be removed from the pre-order opcode in a timely manner, which can avoid repeated generation of dependent opcode pairs and improve the efficiency of traversing all dependent opcode pairs of the preset dependency relationship.

[0079] like Figure 2As shown, after generating the target instruction of the subsequent opcode according to the target instruction of the previous opcode, the subsequent opcode can be removed from the subsequent opcode set corresponding to the previous opcode, and then it is determined whether the subsequent opcode set corresponding to the previous opcode is empty. If the determination result is no, the next opcode is selected. If the determination result is yes, the previous opcode is removed from the preceding opcode set, and then it is determined whether the preceding opcode set is empty. If the determination result is no, the next opcode is selected. If the determination result is yes, the selection is stopped to obtain the required instruction stream.

[0080] For example, if the instruction set architecture of a processor to be tested contains a total of 4 opcodes, namely ADD, LUI, ORI, and BEQ. For the read-after-write dependency, the corresponding pre-order opcode set INST_SET=[ADD, LUI, ORI], the post-order opcode set ADD_SET=[ADD, ORI, BEQ] corresponding to ADD, the post-order opcode set LUI_SET=[ADD, ORI, BEQ] corresponding to LUI, and the post-order opcode set ORI_SET=[ADD, ORI, BEQ] corresponding to ORI can be determined. If the first opcode ADD is randomly selected from the opcode set, and its registers are randomly encoded: the destination register rd=16, one source register rs1=3, and the other source register rs2=9, then the target instruction corresponding to the first opcode ADD can be obtained as "ADD rd=16 rs1=3 rs2=9". Since the first opcode ADD belongs to the preceding opcode set INST_SET, the second opcode BEQ can be randomly selected from the succeeding opcode set ADD_SET corresponding to ADD, and under the condition that a source register code corresponding to the second opcode BEQ is the same as the destination register code (16) of the target instruction corresponding to the first opcode ADD, the target instruction corresponding to the second opcode BEQ is randomly generated as "BEQ rs1=16 rs2=23", and the opcode BEQ can be removed from the succeeding opcode set ADD_SET corresponding to ADD to obtain the updated ADD_SET=[ADD, ORI]. Since BEQ does not belong to the preceding opcode set INST_SET, the third opcode LUI can be randomly selected from the preceding opcode set INST_SET, and its corresponding target instruction is randomly generated as "LUI rd=4". Since LUI belongs to the preceding opcode set INST_SET, the fourth opcode ADD can be randomly selected from the subsequent opcode set LUI_SET=[ADD, ORI, BEQ] corresponding to the opcode LUI, and form a dependent opcode pair with the third opcode LUI. Based on the third opcode LUI, 4 is used as the source register encoding, and the target instruction "ADD rd=19 rs1=4 rs2=30" is randomly generated. The opcode ADD is deleted from the subsequent opcode set LUI_SET to obtain the updated subsequent opcode set ORI_SET=[ORI, BEQ].Since ADD belongs to the pre-order opcode set, the 5th opcode ADD is randomly selected from the post-order opcode set ADD_SET to form a dependent opcode pair with the 4th opcode ADD. Based on the 5th opcode ADD and the source register code 19, the target instruction corresponding to the 5th opcode ADD is randomly generated as "ADD rd=17 rs1=12 rs2=19", and the opcode ADD is deleted from the post-order opcode set ADD_SET. The updated ADD_SET=[ORI].

[0081] Since ADD belongs to the pre-order opcode set, the 6th opcode is randomly selected from the post-order opcode set ADD_SET as ORI, and forms a dependent opcode pair with the 5th opcode ADD. Based on the 6th opcode being ORI and the source register code 17, the target instruction corresponding to the 6th opcode ORI is randomly generated as "ORI rs1=17", and the opcode ORI is deleted from the post-order opcode set ADD_SET. The updated ADD_SET=[]. Since the post-order opcode set ADD_SET is empty, the corresponding opcode ADD is deleted from the pre-order opcode set. The updated pre-order opcode set INST_SET=[LUI, ORI]. By analogy, the 7th to 14th opcodes can be BEQ, ORI, ADD, LUI, ORI, ORI, LUI, BEQ respectively. The target instructions generated by the 1st to 14th opcodes, and the corresponding opcodes and operands can be shown in Table 1 below: Table 1

[0082] Since after the 14th opcode BEQ is selected above, the opcode BEQ is deleted from LUI_SET, and the updated LUI_SET is empty, then after the opcode LUI is deleted from the preceding opcode set INST_SET, the preceding opcode set INST_SET is updated to empty. At this time, it can be determined that all possible dependent opcode pairs under all write-after-read dependencies have been obtained.

[0083] Optionally, in some embodiments, after the step of obtaining the instruction stream composed of various target instructions, the instruction streams corresponding to multiple preset dependencies can be spliced ​​together to obtain the target instruction stream; or, between the dependency instruction pairs of the instruction streams corresponding to the preset dependencies, the dependency instruction pairs of the instruction streams corresponding to other preset dependencies can be inserted to obtain the target instruction stream.

[0084] In the embodiment of the present invention, in order to improve the test efficiency, the above instruction stream generation method can be used to generate instruction streams corresponding to different preset dependencies respectively, and then the instruction streams corresponding to different preset dependencies are combined to obtain a target instruction stream containing dependent instruction pairs with different preset dependencies. Thus, a target instruction stream can be used to test instruction combinations with multiple dependencies, which helps to further improve the efficiency of testing the CPU through the instruction stream.

[0085] Specifically, in one embodiment, the instruction streams corresponding to the plurality of preset dependencies can be directly spliced ​​head to tail to obtain a target instruction stream. In another embodiment, the dependent instruction pairs of the instruction streams corresponding to the preset dependencies can be inserted between the dependent instruction pairs of the instruction streams corresponding to the preset dependencies to obtain the target instruction stream. The dependent instruction pair represents a pair of instructions with the same dependent register encoding generated for the dependent opcode pair, and the above-mentioned insertion method may include but is not limited to random insertion, sequential insertion, reverse insertion, etc., which are not specifically limited in the embodiments of the present invention.

[0086] Reference Figure 3 , shows a block diagram of an instruction stream generating device provided by an embodiment of the present invention, such as Figure 3 As shown, the device may specifically include: A first operation code module 301 is used to select an operation code from the operation code set as a first operation code; wherein the first operation code belongs to a preceding operation code set, and the preceding operation code set is determined from the operation code set based on a preset dependency relationship; A second operation code module 302 is configured to select an operation code from a post-order operation code set corresponding to the first operation code as a second operation code, and obtain a dependent operation code pair consisting of the first operation code and the second operation code; wherein the post-order operation code set is determined from the operation code set based on the preset dependency relationship; A dependent opcode pair module 303, configured to obtain a next dependent opcode pair from the opcode set based on the inclusion relationship between the second opcode and the preceding opcode set, until all dependent opcode pairs corresponding to the preset dependency relationship are obtained; The instruction stream module 304 is used to obtain the target instructions generated for each opcode in each dependent opcode pair, and obtain an instruction stream composed of each target instruction; wherein, the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit.

[0087] Optionally, the device further comprises: A dependent register encoding module, configured to obtain a dependent register encoding from a target instruction corresponding to a previous opcode in a dependent opcode pair based on the preset dependency relationship; The first target instruction module is used to determine the target instruction corresponding to the latter opcode in the dependent opcode pair based on the preset dependency relationship and the dependent register encoding.

[0088] Optionally, the device further comprises: A second target instruction module, used for randomly generating a target instruction corresponding to a preceding opcode and a target instruction corresponding to a succeeding opcode in the dependent opcode pair; The first deletion module is used to delete the subsequent opcode from the subsequent opcode set corresponding to the first opcode when the target instruction corresponding to the subsequent opcode and the target instruction corresponding to the previous opcode have the same dependent register encoding corresponding to the preset dependency relationship.

[0089] Optionally, the device further comprises: The second deletion module is used to delete the subsequent operation code of any dependent operation code pair from the subsequent operation code set corresponding to the previous operation code of the dependent operation code pair after obtaining the dependent operation code pair.

[0090] Optionally, the device further comprises: A detection submodule, configured to detect whether the subsequent operation code set is empty after deleting an operation code from any subsequent operation code set; A pre-order operation code set deletion submodule, configured to delete the operation code corresponding to the post-order operation code set from the pre-order operation code set when detecting that the post-order operation code set is empty; The determination submodule is used to determine all dependent operation code pairs corresponding to the preset dependency relationship when it is detected that the preceding operation code set is empty.

[0091] Optionally, the device further comprises: The target instruction stream module is used to splice the instruction streams corresponding to multiple preset dependencies to obtain the target instruction stream; or, between the dependency instruction pairs of the instruction streams corresponding to the preset dependencies, the dependency instruction pairs of the instruction streams corresponding to other preset dependencies are inserted to obtain the target instruction stream.

[0092] Optionally, the first operation code module includes: A relation submodule, configured to select an operation code from the operation code set and determine an inclusion relation between the operation code and the preceding operation code set; A first selection submodule, configured to use the operation code as a first operation code when the inclusion relationship is inclusion; The second selection submodule is used to use the operation code as an independent operation code when the inclusion relationship is non-inclusion, and reselect an operation code from the operation code set as the first operation code; wherein the independent operation code is used to generate the independent operation code included in the instruction stream.

[0093] Optionally, the preset dependency relationship includes a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship.

[0094] In summary, in the instruction stream generation device provided by the embodiment of the present invention, an operation code is selected from the operation code set as the first operation code; wherein the first operation code belongs to the pre-order operation code set, and the pre-order operation code set is determined from the operation code set based on the preset dependency relationship; an operation code is selected from the post-order operation code set corresponding to the first operation code as the second operation code, and a dependent operation code pair consisting of the first operation code and the second operation code is obtained; wherein the post-order operation code set is determined from the operation code set based on the preset dependency relationship; based on the inclusion relationship between the second operation code and the pre-order operation code set, the next dependent operation code pair is obtained from the operation code set until all dependent operation code pairs corresponding to the preset dependency relationship are obtained; the target instructions generated for each operation code in each dependent operation code pair are obtained, and an instruction stream consisting of each target instruction is obtained; wherein the target instructions corresponding to the operation codes in the same dependent operation code pair have the same register encoding, and the instruction stream is used to test the central processing unit. In this way, all dependent operation code pairs under the preset dependency relationship can be efficiently generated, and the instruction stream generated according to these dependent operation code pairs can include all possible instruction combinations with preset dependencies, which helps to improve the accuracy of testing the CPU through the instruction stream. And because the opcodes can be specifically selected from the post-opcode set of the opcode to form dependent opcode pairs, the efficiency of selecting dependent opcode pairs can be improved to a certain extent, which helps to improve the density of instructions with dependencies in the generated instruction stream, thereby reducing the length of the instruction stream required to test the CPU and improving the efficiency of the instruction stream in testing the CPU.

[0095] Reference Figure 4 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the instruction stream generation method of the above embodiment. The executable instructions can form a program.

[0096] An embodiment of the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the instruction stream generation method of the aforementioned embodiment.

[0097] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0098] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. It should be noted that all actions of acquiring signals, information or data in the present invention are carried out under the premise of complying with the corresponding data protection laws and policies of the country of residence and with the authorization given by the owner of the corresponding device. The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0099] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0100] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0101] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0102] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0103] The above is a detailed introduction to an instruction stream generation method, an instruction stream generation device, an electronic device and a storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for generating an instruction stream, characterized in that: The method comprises: Select an opcode from the opcode set as a first opcode; wherein the first opcode belongs to a preceding opcode set, and the preceding opcode set is determined from the opcode set based on a preset dependency relationship; Selecting an opcode from a post-order opcode set corresponding to the first opcode as a second opcode, and obtaining a dependent opcode pair consisting of the first opcode and the second opcode; wherein the post-order opcode set is determined from the opcode set based on the preset dependency relationship; Based on the inclusion relationship between the second opcode and the preceding opcode set, obtaining a next dependent opcode pair from the opcode set until all dependent opcode pairs corresponding to the preset dependency relationship are obtained; Obtain target instructions generated for each opcode in each dependent opcode pair, and obtain an instruction stream composed of each target instruction; wherein, the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit.

2. The instruction stream generation method according to claim 1, characterized in that: The method further comprises: Based on the preset dependency relationship, obtaining a dependent register encoding from a target instruction corresponding to a previous opcode in a dependent opcode pair; Based on the preset dependency relationship and the dependent register encoding, a target instruction corresponding to a latter opcode in the dependent opcode pair is determined.

3. The instruction stream generation method according to claim 1, characterized in that: The method further comprises: After obtaining any dependent opcode pair, the subsequent opcode of the dependent opcode pair is deleted from the subsequent opcode set corresponding to the previous opcode of the dependent opcode pair.

4. The instruction stream generation method according to claim 3, characterized in that: The method further comprises: After deleting an opcode from any subsequent opcode set, detecting whether the subsequent opcode set is empty; When it is detected that the post-order operation code set is empty, deleting the operation code corresponding to the post-order operation code set from the pre-order operation code set; When it is detected that the preceding operation code set is empty, all dependent operation code pairs corresponding to the preset dependency relationship are determined.

5. The instruction stream generation method according to claim 1, characterized in that: The method further comprises: Randomly generate a target instruction corresponding to a previous opcode and a target instruction corresponding to a subsequent opcode in the dependent opcode pair; When the target instruction corresponding to the subsequent opcode and the target instruction corresponding to the previous opcode have the same dependent register encoding corresponding to the preset dependency relationship, the subsequent opcode is deleted from the subsequent opcode set corresponding to the first opcode.

6. The instruction stream generation method according to claim 1, characterized in that: The method further comprises: The target instruction stream is obtained by splicing the instruction streams corresponding to the plurality of preset dependencies respectively; or, between the dependency instruction pairs of the instruction streams corresponding to the preset dependencies, the dependency instruction pairs of the instruction streams corresponding to other preset dependencies are inserted to obtain the target instruction stream.

7. The instruction stream generation method according to claim 1, characterized in that: The step of selecting an operation code from the operation code set as the first operation code comprises: Select an operation code from the operation code set, and determine the inclusion relationship between the operation code and the preceding operation code set; When the inclusion relationship is inclusion, the operation code is used as the first operation code; When the inclusion relationship is non-inclusion, the opcode is used as an independent opcode, and an opcode is reselected from the opcode set as the first opcode; wherein the independent opcode is used to generate an independent opcode included in the instruction stream.

8. The instruction stream generation method according to claim 1, characterized in that: The preset dependency relationship includes a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship.

9. An instruction stream generating device, characterized in that: The device comprises: A first operation code module, configured to select an operation code from the operation code set as a first operation code; wherein the first operation code belongs to a preceding operation code set, and the preceding operation code set is determined from the operation code set based on a preset dependency relationship; a second operation code module, configured to select an operation code from a post-order operation code set corresponding to the first operation code as a second operation code, and obtain a dependent operation code pair consisting of the first operation code and the second operation code; wherein the post-order operation code set is determined from the operation code set based on the preset dependency relationship; A dependent opcode pair module, configured to obtain a next dependent opcode pair from the opcode set based on an inclusion relationship between the second opcode and the preceding opcode set, until all dependent opcode pairs corresponding to the preset dependency relationship are obtained; The instruction stream module is used to obtain the target instructions generated for each opcode in each dependent opcode pair, and obtain an instruction stream composed of each target instruction; wherein the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit.

10. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the instruction stream generation method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: Instructions are stored thereon, and when executed by one or more processors, the processors are caused to execute the instruction stream generation method according to any one of claims 1 to 8.

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