Storage device for managing mapping information provided to host and operating method thereof

Abstract

The present disclosure provides a storage device for managing mapping information provided to a host and a method of operating the same to enable efficient management of a host mapping table. The storage device may include a memory device and a memory controller configured to generate mapping information in which a physical address of the memory device is mapped to a logical address provided from a host, provide a first mapping segment among a plurality of mapping segments included in the mapping information to the host, and provide a second mapping segment among the plurality of mapping segments to the host. And generate mapping change information when the first mapping segment changes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0135219 filed on October 11, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to a semiconductor device, and more particularly, to a storage device for managing mapping information provided to a host and a method of operating the storage device. Background Art

[0004] The storage device may include a memory device that stores data, and the operation of the memory device may be controlled in response to a request received from a host.

[0005] An operation performed in response to a request received from a host or an internal operation independently generated in a storage device may be performed by the storage device to convert a logical address (LA) provided from the host into a physical address (PA) of the storage device. In this case, a mapping table including an address mapping relationship between a logical address and a physical address, i.e., a logical to physical (L2P) mapping table, is used.

[0006] On the other hand, as the capacity of the memory device becomes larger and larger, the size of the mapping table will inevitably increase, and the time required for the memory device to search the mapping table will also increase, resulting in a decrease in the operation speed of the memory device. In order to solve this problem, multiple host mapping tables can be set in the host, and the mapping table of the memory device can be synchronized with the multiple host mapping tables, so that the address conversion operation can be performed preferentially in the host. This operation can be called a "host performance booster (HPB) operation". Summary of the invention

[0007] Various embodiments of the present disclosure are directed to a storage device capable of effectively managing a host mapping table and a method of operating the storage device.

[0008] Embodiments of the present disclosure may provide a storage device. The storage device may include a memory device and a memory controller, the memory controller being configured to generate mapping information that maps a physical address of the memory device to a logical address provided from a host, provide a first mapping segment among a plurality of mapping segments included in the mapping information to the host, and generate mapping change information when the first mapping segment changes.

[0009] An embodiment of the present disclosure may provide a method for operating a storage device. The method may include: generating a first mapping segment, the first mapping segment including multiple address mapping relationships between multiple logical addresses and multiple physical addresses; providing the first mapping segment to a host; calculating the number of changed address mapping relationships among the multiple address mapping relationships; determining whether the first mapping segment is valid based on the number of changed address mapping relationships; receiving an operation request from the host and the address mapping relationship associated with the logical address included in the first mapping segment; and determining a storage area for performing an operation corresponding to the operation request based on whether the first mapping segment is valid. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram illustrating a mapping segment according to an embodiment of the present disclosure.

[0012] Figure 3 is a diagram illustrating mapping change information according to an embodiment of the present disclosure.

[0013] Figure 4 is a diagram illustrating a changed map segment according to an embodiment of the present disclosure.

[0014] Figure 5 is a diagram illustrating an example in which a mapping segment is changed according to a write operation according to an embodiment of the present disclosure.

[0015] Fig. 6A is a diagram illustrating an example of performing a read operation corresponding to a read request according to an embodiment of the present disclosure.

[0016] Figure 6B is a diagram illustrating an example of performing a read operation corresponding to a read request according to an embodiment of the present disclosure.

[0017] Figure 6C is a diagram illustrating an example of performing a read operation corresponding to a read request according to an embodiment of the present disclosure.

[0018] Fig.6D is a diagram illustrating an example of performing a read operation corresponding to a read request according to an embodiment of the present disclosure.

[0019] Figure 7 is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0020] Figure 8is a flowchart illustrating an example of recommending mapping segments according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The specific structure or function description in the embodiments of the present disclosure introduced in this specification or application is provided only as an example to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be practiced in various forms and should not be understood as being limited to the embodiments described in the specification or application.

[0022] Figure 1 is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , the computing system 10 may include a storage device 100 and a host 200 .

[0024] In an embodiment, the storage device 100 may be a device that stores data under the control of the host 200 .

[0025] The storage device 100 may be manufactured as any of various types of storage devices, such as a solid state drive (SSD) and a universal flash memory (UFS), according to a host interface as a scheme for communicating with the host 200. In addition, the storage device 100 may be manufactured as any of various types of packaging forms, such as a system on chip (SOC).

[0026] The memory device 100 may include a memory device 110 , a buffer memory 120 , and a memory controller 130 .

[0027] The memory device 110 may be a non-volatile memory.

[0028] The memory device 110 may include a memory cell array including a plurality of memory cells storing data.

[0029] The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, each page may be a unit for storing data in the memory device 110 in a programming operation (write operation), or may be a unit for reading data stored in the memory device 110 in a read operation. A memory block may be a unit for erasing data in an erase operation.

[0030] The memory device 110 may receive a command and an address from the memory controller 130 , and may perform an operation indicated by the command on a region selected by the address in a memory cell array.

[0031] In an embodiment, the memory device 110 may store mapping information 111 .

[0032] In an embodiment, mapping information 111 may be information that maps a physical address of memory device 110 to a logical address provided from host 200. In the present application, a logical address and a "logical block address" may be used interchangeably. In the present application, a physical address and a "physical block address" may be used interchangeably.

[0033] The mapping information 111 may include a plurality of mapping segments 111a to 111n. Each mapping segment may include mapping information corresponding to a logical address region including a plurality of logical addresses. Each mapping segment may include a plurality of address mapping relationships between a plurality of logical addresses and a plurality of physical addresses mapped to the plurality of logical addresses.

[0034] In an embodiment, the first mapping segment among the plurality of mapping segments 111a to 111n may be provided to the host 200. Here, the first mapping segment may include a plurality of first mapping segments. For example, the plurality of first mapping segments may indicate the ath mapping segment 111a to the cth mapping segment 111c among the plurality of mapping segments 111a to 111n.

[0035] The buffer memory 120 may be a volatile memory.

[0036] The buffer memory 120 may store various types of information required for the operation of the memory controller 130 in the form of firmware (FW).

[0037] In an embodiment, the buffer memory 120 may store mapping change information 121 and change map segments 122 .

[0038] In an embodiment, the mapping change information 121 and the change mapping segment 122 may be stored in the memory device 110 .

[0039] When the plurality of first mapping segments 111 a to 111 c provided to the host 200 are changed according to the operation of the memory device 110 , the mapping change information 121 may be information indicating whether the corresponding first mapping segments 111 a to 111 c have been changed.

[0040] The changed mapping section 122 may be information indicating a changed address mapping relationship among a plurality of address mapping relationships included in the first mapping sections 111a to 111c when the first mapping sections 111a to 111c provided to the host 200 are changed.

[0041] In an embodiment, the buffer memory 120 may store some of the plurality of mapping segments 111a to 111n. Here, the mapping segments stored in the buffer memory 120 may be the first mapping segments 111a to 111c provided to the host 200, or frequently accessed mapping segments.

[0042] The memory controller 130 may control overall operations of the memory device 100 .

[0043] In an embodiment, the memory controller 130 may include a processor capable of running firmware, a host interface capable of communicating with the host 200, a memory interface capable of communicating with the memory device 110 and the buffer memory 120, and an error correction circuit capable of correcting errors in data.

[0044] When power is applied to the memory device 100, the memory controller 130 may execute the firmware stored in the buffer memory 120. When the memory device 110 is a flash memory device, the firmware may include a host interface layer (HIL) that controls communication with the host 200, a flash translation layer (FTL) that controls communication between the host 200 and the memory device 110, and a flash interface layer (FIL) that controls communication with the memory device 110.

[0045] The memory controller 130 may provide a command, an address, or data related to a corresponding operation to the memory device 110 in response to a request of the host 200 , thereby performing a program / write operation, a read operation, or an erase operation.

[0046] In an embodiment, the memory controller 130 may independently generate commands, addresses, and data without a request from the host 200, and may send them to the memory device 110. For example, the memory controller 130 may provide the memory device 110 with commands, addresses, and data required to perform background operations related to internal operations such as wear leveling, read reclamation, and garbage collection operations.

[0047] In an embodiment, the memory controller 130 may be coupled to a plurality of memory devices through a channel. The memory controller 130 may control the plurality of memory devices according to an interleaving scheme to improve operation performance. The interleaving scheme may be a scheme for controlling the memory devices 110 so that operations of at least two memory devices 110 overlap with each other.

[0048] In an embodiment, the memory controller 130 may update the mapping information 111 during a write operation. For example, the memory controller 130 may receive data, a write request, and a logical address from the host 200. The logical address may be converted into a physical address by a flash translation layer (FTL), which indicates an address of a memory cell in the memory device 110 where data is to be stored. Here, an address mapping relationship between the logical address converted by the FTL and the physical address may be added to the mapping information 111.

[0049] In an embodiment, the memory controller 130 may need an address mapping relationship associated with the read data during a read operation. When the address mapping relationship corresponding to the read data is stored in the buffer memory 120, the memory controller 130 may generate a read command corresponding to the received read request and transmit the read command to the memory device 110. When the address mapping relationship corresponding to the read data is not stored in the buffer memory 120, the memory controller 130 may first transmit a read command for the address mapping relationship to the memory device 110. When the memory device 110 reads the address mapping relationship and transmits it to the memory controller 130, the memory controller 130 may transmit the read command for the read data together with the physical address corresponding to the received address mapping relationship to the memory device 110.

[0050] The capacity of the buffer memory 120 may be smaller than that of the host memory 210, and there may not be enough space to store the mapping segment. According to the host performance booster (HPB) operation, all or part of the mapping information 111 in the memory device 110 may be retained in the host memory 210 to improve the cache performance of the mapping information 111. In this case, the host 200 may provide the storage device 100 with an address mapping relationship among the multiple mapping information 111 included in the host memory 210 when generating a read request, and the address mapping relationship indicates the area where the data to be read is located. Compared with the case where the mapping segment is stored only in the buffer memory 120, the cache hit probability of the mapping information 111 can be increased. Therefore, the data reading speed between the host 200 and the storage device 100 can be improved.

[0051] In an embodiment, the memory controller 130 may select some mapping segments, such as first mapping segments 111a to 111c, from among the plurality of mapping segments 111a to 111n included in the mapping information 111. The memory controller 130 may select a mapping segment corresponding to a logical address region having a large number of cache hits from the memory device 110 to the buffer memory 120 or a large number of read requests received from the host 200. The memory controller 130 may provide the selected first mapping segments 111a to 111c to the host 200. In addition, the memory controller 130 may store the selected first mapping segments 111a to 111c in the buffer memory 120.

[0052] In an embodiment, when the first mapping segments 111a to 111c provided to the host 200 are changed according to the operation of the memory device 110, the memory controller 130 may generate mapping change information 121 and changed mapping segments 122 related to the first mapping segments 111a to 111c. Here, the operation of the memory device may include not only an operation corresponding to a request of the host 200 but also an internal operation independently performed by the memory device 100. The memory controller 130 may control an operation requested by the host 200 or determine a time point at which a mapping segment provided to the host 200 is recommended based on the mapping change information 121 and the changed mapping segments 122.

[0053] In an embodiment, the host 200 may communicate with the storage device 100 using at least one of various communication methods such as: Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0054] In an embodiment, the host 200 may include a host memory 210 and a host controller 220 .

[0055] The host memory 210 may be used as a main memory, a working memory, a buffer memory, or a cache memory of the host 200. The host memory 210 may include a volatile memory such as a DRAM or an SRAM.

[0056] In an embodiment, the host memory 210 may store the first mapping segments 111 a to 111 c provided from the storage device 100 .

[0057] The host controller 220 may execute an application program, an operating system (OS), etc. for controlling the computing system 10. For example, the host controller 220 may include a processor, an interface, a graphic engine, etc. that execute the application program, the operating system, etc.

[0058] When transmitting a read request to the storage device 100, the host controller 220 may transmit the address mapping relationship received from the host memory 210 together with the read request to the storage device 100. For example, when the host memory 210 stores an address mapping relationship having a logical address of data corresponding to the read request to be transmitted to the storage device 100, the host controller 220 may transmit the corresponding address mapping relationship together with the read request to the storage device 100. Different from this, when the host memory 210 does not store an address mapping relationship including a logical address of data corresponding to the read request to be transmitted to the storage device 100, the host controller 220 may only transmit the read request to the storage device 100.

[0059] Figure 2 is a diagram illustrating a mapping segment according to an embodiment of the present disclosure.

[0060] Although in Figure 2 For the sake of convenience, the description is based on mapping segment A 111a, but the same method as mapping segment A 111a is also applicable to other mapping segments.

[0061] Reference Figure 2 , the mapping segment A 111a may include a plurality of address mapping relationships between a plurality of logical addresses LA_1 to LA_100 and a plurality of physical addresses PA_101 to PA_200 mapped to the plurality of logical addresses LA_1 to LA_100. Here, the plurality of logical addresses LA_1 to LA_100 may be included in one logical address region LA REGION.

[0062] In an embodiment, the mapping segment A 111a may be mapping information corresponding to one logical address region LA REGION.

[0063] Although in Figure 2 , it is described that one logical address region LA REGION includes 100 logical addresses, but the present disclosure is not limited thereto, and the number of logical addresses may be less than or greater than 100 according to an embodiment.

[0064] Figure 3 is a diagram illustrating mapping change information according to an embodiment of the present disclosure.

[0065] Reference Figure 3 The mapping change information 121 may include mapping identification information MAP ID of each mapping segment 111a to 111c provided to the host 200, the number UPDATE COUNT of changed address mapping relationships among the multiple address mapping relationships included in each of the mapping segments 111a to 111c, and status information CONDITION of each mapping segment.

[0066] In an embodiment, the address mapping relationships associated with the logical addresses LA_11, LA_12, LA_15, LA_16, and LA_17 may change in the mapping segment A 111a-1 stored in the buffer memory 120. In this case, since five address mapping relationships are changed, the number of changed address mapping relationships UPDATE COUNT of the mapping segment A 111a-1 may be 5.

[0067] In an embodiment, the state information CONDITION may indicate the state of each mapping segment 111 a to 111 c according to the number UPDATE COUNT of changing address mapping relationships.

[0068] In an embodiment, the state information CONDITION may include at least one of the following states: a "clean" state, in which there is no change in the address mapping relationship; a "partially dirty" state, in which the number of changes in the address mapping relationship UPDATECOUNT is less than a preset number; and a "completely dirty" state, in which the number of changes in the address mapping relationship UPDATE COUNT is equal to or greater than a preset number. Among them, the "clean" state may correspond to a valid state, the "partially dirty" state may correspond to a partially valid state, and the "completely dirty" state may correspond to an invalid state.

[0069] In an embodiment, since mapping segment C 111c has not changed the address mapping relationship, it may be in a "clean" state.

[0070] In an embodiment, when the preset number is 10, since the number of changed address mapping relationships UPDATE COUNT is 5, which is less than the preset number, the mapping segment A 111a may be in a "partially dirty" state.

[0071] In an embodiment, when the preset number is 10, since the number of changed address mapping relationships UPDATE COUNT is 15, which is greater than the preset number, the mapping segment B 111b may be in a "completely dirty" state.

[0072] Figure 4 is a diagram illustrating changing a mapping segment according to an embodiment of the present disclosure.

[0073] Reference Figure 4 When the respective mapping segments 111a to 111c provided to the host 200 correspond to the "partially dirty" state, the memory controller 130 may generate a change mapping segment 122. In an embodiment, the change mapping segment 122 may include a new address mapping relationship having a logical address included in each change address mapping relationship.

[0074] For example, due to Figure 3As shown, the address mapping relationship associated with the logical addresses LA_11, LA_12, LA_15, LA_16, and LA_17 in the mapping segment A 111a-1 has changed, and therefore, the memory controller 130 may generate a changed mapping segment 122 including a new address mapping relationship of the logical addresses LA_11, LA_12, LA_15, LA_16, and LA_17.

[0075] In an embodiment, when each of the mapping segments 111 a to 111 c provided to the host 200 corresponds to a “completely dirty” state, the memory controller 130 may remove the changed mapping segment 122 of the corresponding mapping segment.

[0076] For example, since mapping segment B 111 b corresponds to a “completely dirty” state, the changed mapping segment 122 of mapping segment B 111 b may be removed from the buffer memory 120 .

[0077] Figure 5 is a diagram illustrating an example in which a mapping segment is changed according to a write operation according to an embodiment of the present disclosure.

[0078] Reference Figure 5 , the memory controller 130 may receive data DATA, a write request REQ_WRITE, and a logical address LA_2 corresponding to the write request REQ_WRITE from the host 200. The memory controller 130 may map the physical address PA_1000 to the logical address LA_2. The memory controller 130 may generate a write command CMD_WRITE, and may provide the data DATA, the write command CMD_WRITE, and the physical address PA_1000 to the memory device 110.

[0079] In an embodiment, the memory controller 130 may update the change mapping segment 122 according to whether the mapping segment A 111a - 2 includes an address mapping relationship associated with the logical address LA_2 .

[0080] For example, since the mapping segment A 111 a - 2 includes an address mapping relationship associated with the logical address LA_2, the memory controller 130 may update the changed mapping segment 122 of the mapping segment A 111 a - 2.

[0081] In an embodiment, the memory controller 130 may increase the number UPDATE COUNT of changed address mapping relationships of the mapping segment A 111 a provided to the host 200 in the mapping change information 121 .

[0082] In an embodiment, the memory controller 130 may include the address mapping relationship between the logical address LA_2 and the physical address PA_1000 in the change map segment 122 .

[0083] On the other hand, Figure 5 Different from the example shown, when the mapping segment A 111 a - 2 does not include a logical address corresponding to the write request REQ_WRITE, the physical address may be mapped to the logical address and a new address mapping relationship may be updated in the mapping information 111 .

[0084] Fig. 6A is a diagram showing an example of performing a read operation corresponding to a read request according to an embodiment of the present disclosure. Specifically, Fig. 6A is a diagram for explaining an example of performing a read operation when a mapping segment corresponds to a “clean” state in which an address mapping relationship is not changed.

[0085] Reference Fig. 6A , the memory controller 130 may receive a read request REQ_READ and an address mapping relationship L2P_201 associated with the logical address LA_201 included in the mapping segment C111c from the host 200 .

[0086] In an embodiment, the memory controller 130 may determine a region of the memory device 110 where a read operation corresponding to the read request REQ_READ is to be performed based on the state information CONDITION.

[0087] For example, when the mapping segment C 111c corresponds to the "clean" state, the memory controller 130 may obtain the physical address PA_301 based on the address mapping relationship L2P_201 associated with the logical address LA_201 received from the host 200. The memory controller 130 may control the memory device 110 to read data from the area corresponding to the obtained physical address PA_301. In this case, the memory controller 130 may generate a read command CMD_READ, and may provide the read command CMD_READ and the physical address PA_301 to the memory device 110.

[0088] Figure 6B is a diagram showing an example of performing a read operation corresponding to a read request according to an embodiment of the present disclosure. Specifically, Figure 6B is a diagram for explaining an example of performing a read operation when a mapping segment corresponds to a “partially dirty” state in which the number of changed address mapping relationships is less than a preset number.

[0089] Reference Figure 6B , the memory controller 130 may receive a read request REQ_READ and an address mapping relationship L2P_1 associated with the logical address LA_1 included in the mapping segment A111a from the host 200 .

[0090] In an embodiment, when the mapping segment A 111a corresponds to the “partially dirty” state and the change mapping segment 122 does not include the address mapping relationship associated with the logical address LA_1, the memory controller 130 may obtain the physical address PA_101 based on the address mapping relationship L2P_1 associated with the logical address LA_1 received from the host 200. The memory controller 130 may control the memory device 110 to read data from the area corresponding to the obtained physical address PA_101.

[0091] In this case, the memory controller 130 may generate a read command CMD_READ and may provide the read command CMD_READ and the physical address PA_101 to the memory device 110 .

[0092] Figure 6C is a diagram showing an example of performing a read operation corresponding to a read request according to an embodiment of the present disclosure. Specifically, Figure 6C is a diagram for explaining an example of performing a read operation when a mapping segment corresponds to a “partially dirty” state in which the number of changed address mapping relationships is less than a preset number.

[0093] Reference Figure 6C , the memory controller 130 may receive a read request REQ_READ and an address mapping relationship L2P_2 associated with the logical address LA_2 included in the mapping segment A111a from the host 200 .

[0094] In an embodiment, when the mapping segment A 111a corresponds to the "partially dirty" state and the change mapping segment 122 includes an address mapping relationship associated with the logical address LA_2, the memory controller 130 may obtain the physical address PA_1000 mapped to the logical address LA_2 based on the change mapping segment 122. The memory controller 130 may control the memory device 110 to read data from the area corresponding to the physical address PA_1000.

[0095] In this case, the memory controller 130 may generate a read command CMD_READ and may provide the read command CMD_READ and the physical address PA_1000 to the memory device 110 .

[0096] Fig.6D is a diagram showing an example of performing a read operation corresponding to a read request according to an embodiment of the present disclosure. Specifically, Fig.6D is a diagram for explaining an example of performing a read operation when a mapping segment corresponds to a “completely dirty” state in which the number of changed address mapping relationships is equal to or greater than a preset number.

[0097] Reference Fig.6D, the memory controller 130 may receive a read request REQ_READ and an address mapping relationship L2P_101 associated with a logical address LA_101 from the host 200 .

[0098] In an embodiment, when the mapping segment B 111b corresponds to the "completely dirty" state, the memory controller 130 may obtain the physical address mapped to the logical address LA_101 based on the mapping information 111 of the memory device. For example, the mapping information 111 of the memory device may include the updated mapping segment B 111b-1. The memory controller 130 may obtain the physical address PA_701 mapped to the logical address LA_101 based on the updated mapping segment B 111b-1. The memory controller 130 may control the memory device 110 to read data from the area corresponding to the physical address PA_701.

[0099] In this case, the memory controller 130 may generate a read command CMD_READ and may provide the read command CMD_READ and the physical address PA_701 to the memory device 110 .

[0100] On the other hand, the updated mapping segment B 111b-1 may include a new address mapping relationship generated by the update, but may also include an existing address mapping relationship that has not been updated.

[0101] Figure 7 is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0102] Figure 7 The method shown can be performed, for example, by Figure 1 The storage device 100 shown performs.

[0103] In step S701 , the storage device 100 may generate a first mapping segment, where the first mapping segment includes a plurality of address mapping relationships between a plurality of logical addresses and a plurality of physical addresses.

[0104] In step S703 , the storage device 100 may provide the first mapping segment to the host 200 .

[0105] In step S705, the storage device 100 may calculate the number of changed address mapping relationships according to the set operation among the plurality of address mapping relationships (i.e., UPDATE COUNT). Here, the set operation may include a read operation, a write (program) operation, or an erase operation corresponding to a request of the host 200, and internal background operations such as wear leveling, read recycling, and garbage collection operations.

[0106] In step S707 , the storage device 100 may determine whether the first mapping segment provided to the host is valid based on the number of changed address mapping relationships.

[0107] In an example, when there is no change in the address mapping relationship (or before there is a change in the address mapping relationship), the storage device 100 may determine the state of the first mapping segment as a valid (clean) state.

[0108] In an example, when the number of changed address mapping relationships is less than a preset number (after one or more of the multiple address mapping relationships are changed), the storage device 100 may determine the state of the first mapping segment as a partially dirty (partially valid) state.

[0109] In an example, when the number of changed address mapping relationships is equal to or greater than a preset number (after one or more of the multiple address mapping relationships are changed), the storage device 100 may determine the state of the first mapping segment as a completely dirty (invalid) state.

[0110] In step S709 , the storage device 100 may receive a read request and an address mapping relationship associated with the logical address included in the first mapping segment from the host 200 .

[0111] In step S711 , the storage device 100 may determine a storage area in which a read operation corresponding to a read request is to be performed based on whether the first mapping segment is valid.

[0112] In the example, when the state of the first mapping segment is a valid state, the storage device 100 can obtain a physical address based on an address mapping relationship associated with the logical address received from the host 200, and can determine the storage area corresponding to the obtained physical address as the storage area for the read operation to be performed.

[0113] In the example, when the state of the first mapping segment is a partially valid state, the storage device 100 can determine the storage area corresponding to the physical address newly mapped to the logical address received from the host 200 as the storage area for the read operation to be performed in response to a change in the address mapping relationship associated with the logical address received from the host 200.

[0114] In the example, when the state of the first mapping segment is a partially valid state, the storage device 100 can obtain a physical address based on the address mapping relationship associated with the logical address received from the host 200 in response to the fact that the address mapping relationship associated with the logical address received from the host 200 has not changed, and determine the storage area corresponding to the obtained physical address as the storage area on which the read operation is to be performed.

[0115] In the example, when the state of the first mapping segment is an invalid state, the storage device 100 can obtain a physical address mapped to a logical address received from the host 200 based on mapping information stored in the storage device 100, and can determine a storage area corresponding to the obtained physical address as a storage area on which a read operation is to be performed.

[0116] Figure 8 is a flowchart illustrating an example of recommending mapping segments according to an embodiment of the present disclosure.

[0117] Figure 8 The method shown can be performed, for example, by Figure 1 The storage device 100 shown performs.

[0118] In step S801 , the storage device 100 may generate a first mapping segment, where the first mapping segment includes a plurality of address mapping relationships between a plurality of logical addresses and a plurality of physical addresses.

[0119] In step S803 , the storage device 100 may provide the first mapping segment to the host 200 .

[0120] In step S805, the storage device 100 may calculate the number of changed address mapping relationships based on the set operation among the plurality of address mapping relationships. Here, the set operation may include a read / write operation or an erase operation of the storage device corresponding to a request of the host 200, and internal operations such as wear leveling, read recovery, and garbage collection operations.

[0121] In step S807 , the storage device 100 may determine whether the first mapping segment provided to the host is valid based on the number of changed address mapping relationships.

[0122] In step S809 , the storage device 100 may determine whether the first mapping segment is in an invalid state.

[0123] When it is determined in step S809 that the first mapping segment is in an invalid state, the storage device 100 may provide recommendation information for recommending the mapping segment to the host 200 in step S811. Here, the recommended mapping segment may be an updated mapping segment, which includes a changed address mapping relationship corresponding to a plurality of logical addresses included in the first mapping segment before the change. The updated mapping segment may be stored in the buffer memory 120, or may be included in the mapping information 111 of the memory device 110. That is, the storage device 100 may recommend the updated mapping segment to the host 200, and the host 200 may request the updated mapping segment from the storage device in response to the recommendation information. The storage device 100 may provide the updated mapping segment in response to the request of the host 200.

[0124] According to the present disclosure, a storage device capable of effectively managing a host mapping table and a method of operating the storage device are provided.

Claims

1. A storage device, comprising: Memory device; as well as A memory controller generates mapping information that maps a physical address of the memory device to a logical address provided from a host, provides a first mapping segment among a plurality of mapping segments included in the mapping information to the host, and generates mapping change information when the first mapping segment changes.

2. The storage device according to claim 1, wherein: The first mapping segment includes a plurality of address mapping relationships between a plurality of logical addresses and a plurality of physical addresses mapped to the plurality of logical addresses.

3. The storage device according to claim 2, wherein: The mapping change information includes the number of changed address mapping relationships among the plurality of address mapping relationships, and state information indicating a state of the first mapping segment based on the number of changed address mapping relationships.

4. The storage device according to claim 3, wherein: The state information includes: a first state, the changed address mapping relationship does not exist; a second state, the number of the changed address mapping relationships is less than a preset number; and a third state, the number of the changed address mapping relationships is equal to or greater than the preset number.

5. The storage device according to claim 2, wherein: When the number of the changed address mapping relationships in the first mapping segment is less than a preset number, the memory controller generates a second mapping segment, the second mapping segment including a new address mapping relationship, the new address mapping relationship having a logical address included in the changed address mapping relationship.

6. The storage device according to claim 5, wherein: When the number of the changed address mapping relationships in the first mapping segment is equal to or greater than the preset number, the memory controller removes the second mapping segment.

7. The storage device according to claim 5, wherein: The memory controller receives a write request and a first logical address corresponding to the write request from the host, maps a first physical address to the first logical address, and updates the second mapping segment based on whether the first mapping segment includes an address mapping relationship associated with the first logical address.

8. The storage device according to claim 7, wherein: When the first mapping segment includes an address mapping relationship associated with the first logical address, the memory controller includes an address mapping relationship between the first logical address and the first physical address in the second mapping segment.

9. The storage device according to claim 7, wherein: When the first mapping segment includes an address mapping relationship associated with the first logical address, the memory controller changes the number of the changed address mapping relationships in the mapping change information.

10. The storage device according to claim 3, wherein: The memory controller receives a read request from the host and an address mapping relationship associated with a second logical address included in the first mapping segment, and determines an area in the memory device where a read operation corresponding to the read request is to be performed based on the state information.

11. The storage device according to claim 10, wherein: When the changed address mapping relationship does not exist in the first mapping segment, the memory controller obtains a second physical address based on the address mapping relationship associated with the second logical address received from the host, and controls the memory device to read data from an area corresponding to the second physical address.

12. The storage device according to claim 10, wherein: When the number of changed address mapping relationships in the first mapping segment is less than a preset number and the second mapping segment does not include an address mapping relationship associated with the second logical address, the memory controller obtains a second physical address based on the address mapping relationship associated with the second logical address received from the host, and controls the memory device to read data from an area corresponding to the second physical address, wherein the second mapping segment includes a new address mapping relationship, and the new address mapping relationship has a logical address included in the changed address mapping relationship.

13. The storage device according to claim 10, wherein: When the number of changed address mapping relationships in the first mapping segment is less than a preset number and the second mapping segment includes an address mapping relationship associated with the second logical address, the memory controller obtains a third physical address mapped to the second logical address based on the second mapping segment, and controls the memory device to read data from an area corresponding to the third physical address, wherein the second mapping segment includes a new address mapping relationship, and the new address mapping relationship has a logical address included in the changed address mapping relationship.

14. The storage device according to claim 10, wherein: When the number of changed address mapping relationships in the first mapping segment is equal to or greater than a preset number, the memory controller obtains a fourth physical address mapped to the second logical address based on the mapping information, and controls the memory device to read data from an area corresponding to the fourth physical address.

15. The storage device according to claim 2, wherein: When the number of changed address mapping relationships in the first mapping segment is equal to or greater than a preset number, the memory controller provides recommendation information to the host, wherein the recommendation information is used to recommend an updated mapping segment, and the updated mapping segment includes the changed address mapping relationships according to the multiple logical addresses.

16. A method of operating a storage device, comprising: generating a first mapping segment, wherein the first mapping segment includes a plurality of address mapping relationships between a plurality of logical addresses and a plurality of physical addresses; providing the first mapping segment to a host; Calculating the number of changed address mapping relationships among the plurality of address mapping relationships; Determining whether the first mapping segment is valid based on the number of changed address mapping relationships; receiving an operation request and an address mapping relationship associated with a logical address included in the first mapping segment from the host; as well as A storage area in which an operation corresponding to the operation request is to be performed is determined based on whether the first mapping segment is valid.

17. The method of claim 16, wherein: Determining whether the first mapping segment is valid includes: In response to the absence of the change in the address mapping relationship, determining the state of the first mapping segment as valid, and Determining the storage area includes: Acquire a physical address based on an address mapping relationship associated with the logical address received from the host; and The acquired physical address is determined as the storage area.

18. The method according to claim 16, wherein: Determining whether the first mapping segment is valid includes: In response to the situation that the number of changed address mapping relationships is less than a preset number, the state of the first mapping segment is determined to be partially valid.

19. The method according to claim 18, wherein: Determining the storage area includes: The physical address newly mapped to the logical address is determined as the storage area.

20. The method according to claim 16, wherein: Determining whether the first mapping segment is valid includes: In response to the number of address mapping relationships being changed being greater than or equal to a preset number, determining the state of the first mapping segment to be invalid, and Determining the storage area includes: A physical address mapped to the logical address is acquired based on the mapping information, and the acquired physical address is determined as the storage area.

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