Communication method and device between chips, medium and equipment

Abstract

The embodiment of the invention discloses an inter-chip communication method and device, a medium and equipment, and the method comprises the steps: determining the first identification information of a to-be-communicated target chip; determining first chip information of the target chip based on the first identification information and a pre-configured chip information mapping relation; establishing a communication link with the target chip based on the first chip information; and communicating with the target chip through the established communication link. According to the embodiment of the invention, the user operation complexity can be reduced, and the user experience is improved.

Description

Technical Field

[0001] The present disclosure relates to communication technology, and in particular to a method, device, medium and equipment for communication between chips. Background Art

[0002] In the fields of smart driving and smart cockpits, there are usually multiple SOCs (System on Chip, system on chip or system-level chip, referred to as chips) that are interconnected and communicated through the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) bus. Each SOC acts as a bus device connected to the PCIe bus. Any bus device can be an RC (Root-Complex) device or an EP (Endpoint) device. In the related technology, the user needs to execute a specified command (such as the lspci command) on the RC device to view the EP device connected to the bus for communication between bus devices. The operation is highly complex and the user experience is poor. Summary of the invention

[0003] The embodiments of the present disclosure provide a method, apparatus, medium and device for communication between chips, which can reduce the complexity of user operations and improve user experience.

[0004] A first aspect of an embodiment of the present disclosure provides a method for communication between chips, comprising: determining first identification information of a target chip to be communicated with; determining first chip information of the target chip based on the first identification information and a preconfigured chip information mapping relationship; establishing a communication link with the target chip based on the first chip information; and communicating with the target chip through the established communication link.

[0005] According to a second aspect of an embodiment of the present disclosure, a chip-to-chip communication device is provided, comprising: a first processing module, used to determine first identification information of a target chip to be communicated; a second processing module, used to determine first chip information of the target chip based on the first identification information and a preconfigured chip information mapping relationship; a third processing module, used to establish a communication link with the target chip based on the first chip information; and a fourth processing module, used to communicate with the target chip through the established communication link.

[0006] According to a third aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the inter-chip communication method described in any of the above embodiments of the present disclosure.

[0007] According to a fourth aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: a processor; a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the instructions to implement the inter-chip communication method described in any of the above embodiments of the present disclosure.

[0008] A fifth aspect of the embodiments of the present disclosure provides a computer program product. When instructions in the computer program product are executed by a processor, the inter-chip communication method provided by any of the above embodiments of the present disclosure is executed.

[0009] Based on the inter-chip communication method, apparatus, medium and equipment provided by the above-mentioned embodiments of the present disclosure, when it is necessary to communicate with the target chip, the first chip information of the target chip can be automatically and quickly determined through the pre-configured chip information mapping relationship, and then a communication link can be established with the target chip. By communicating with the target chip through the established communication link, the user can avoid viewing the chip information of the target chip by executing commands, thereby reducing the complexity of user operations and improving user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is an exemplary application scenario of the inter-chip communication method provided by the present disclosure;

[0011] Figure 2 is a flow chart of a method for communication between chips provided by an exemplary embodiment of the present disclosure;

[0012] Figure 3 is a flow chart of a communication method between chips provided by another exemplary embodiment of the present disclosure;

[0013] Figure 4 is a flowchart of a communication method between chips provided by another exemplary embodiment of the present disclosure;

[0014] Figure 5 is a flowchart of a communication method between chips provided by another exemplary embodiment of the present disclosure;

[0015] Figure 6 is a flowchart of a communication method between chips provided by another exemplary embodiment of the present disclosure;

[0016] Figure 7 is a schematic diagram of chip logic relationships provided by an exemplary embodiment of the present disclosure;

[0017] Figure 8 is a schematic diagram of the structure of an inter-chip communication device provided by an exemplary embodiment of the present disclosure;

[0018] Fig. 9is a schematic diagram of the structure of an inter-chip communication device provided by another exemplary embodiment of the present disclosure;

[0019] Fig.10 is a schematic diagram of the structure of an inter-chip communication device provided by yet another exemplary embodiment of the present disclosure;

[0020] Fig.11 is a schematic structural diagram of an inter-chip communication device provided by another exemplary embodiment of the present disclosure;

[0021] Fig.12 It is a structural diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0023] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0024] SUMMARY OF THE DISCLOSURE

[0025] In the process of implementing the present disclosure, the inventors found that in the fields of intelligent driving, intelligent cockpits, etc., there are usually multiple SOCs (System on Chip, system on chip or system-level chip, referred to as chips) that are interconnected and communicated through the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) bus. Each SOC acts as a bus device connected to the PCIe bus. Any bus device can be used as an RC (Root-Complex) device or an EP (Endpoint) device. In the related art, the user needs to view the EP device connected to the bus by executing a specified command (such as the lspci command) on the RC device for communication between bus devices (chips), which has high operation complexity and poor user experience.

[0026] Exemplary Overview

[0027] Figure 1 This is an exemplary application scenario of the inter-chip communication method provided by the present disclosure. Figure 1As shown, in the intelligent driving system 10, n (n is a positive integer) chips (including chip 11, chip 12, ..., chip 1n) are connected to the preset bus B, and each chip is interconnected and communicated through the preset bus B. The chip may include a storage chip, a network chip, various processing chips, etc. The processing chip may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) chip, etc. The processing chip can be used to realize the perception, positioning, planning and control functions of the intelligent driving system. For any chip (which can be called the current chip), if it is necessary to communicate with other chips, the current chip can determine the first identification information of the target chip to be communicated; based on the first identification information and the pre-configured chip information mapping relationship, determine the chip information of the target chip (called the first chip information); and then establish a communication link with the target chip based on the first chip information; communicate with the target chip through the established communication link. Through the preconfigured chip information mapping relationship, the first chip information of the target chip can be automatically and quickly determined, and then a communication link can be established with the target chip. By communicating with the target chip through the established communication link, the user can avoid viewing the chip information of the target chip by executing commands, thereby reducing the complexity of user operations and improving user experience. Figure 1 Only one preset bus is used as an example for explanation. In actual applications, the system may include one or more buses, and each bus may be connected to one or more chips.

[0028] It should be noted that the inter-chip communication method disclosed in the present invention is not limited to applications in the fields of intelligent driving, smart cockpits, etc., and the inter-chip communication method disclosed in the present invention can be used in any other fields or scenarios that require inter-chip communication through a preset bus such as PCIe.

[0029] Exemplary Methods

[0030] Figure 2 FIG. 1 is a flow chart of a method for inter-chip communication provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to electronic devices, such as a vehicle-mounted computing platform, such as Figure 2 As shown, the method of the embodiment of the present disclosure may include the following steps:

[0031] Step 210: determine first identification information of a target chip to be communicated with.

[0032] The first identification information of the target chip may be the name, number (ID) or other information of the target chip that can uniquely identify the chip.

[0033] In some optional embodiments, the first identification information of the target chip to be communicated can be obtained from the application (or software) running on the current chip. The application may include, for example, a data acquisition application, a perception application, a planning and control application, and other applications that need to communicate with other chips for data transmission. That is, the user can specify the first identification information of the target chip to be communicated in the application. For example, the current chip runs a data acquisition application, and the collected sensor data needs to be transmitted to the target chip running the perception application. After the current chip collects the sensor data, it executes the data transmission instruction to obtain the first identification information of the target chip to be communicated. For another example, the current chip runs a perception application, and the obtained perception application needs to be transmitted to the chip running the planning and control application. In this case, the chip running the planning and control application can be used as the target chip to be communicated, and the first identification information of the target chip can be obtained.

[0034] In some optional embodiments, the first identification information of the target chip to be communicated can be obtained from the storage controller or other hardware of the current chip. For example, if the storage controller of the current chip needs to be connected to a storage chip, the storage chip is used as the target chip to be communicated, and the storage controller obtains the first identification information of the target chip to be communicated according to the configuration information. The configuration information can be pre-configured by the user, and the configuration information includes the identification information of the storage chip. The specific method of determining the first identification information of the target chip to be communicated is determined according to the actual function of the current chip, and the embodiments of the present disclosure are not limited thereto.

[0035] Step 220: Determine first chip information of the target chip based on the first identification information and the preconfigured chip information mapping relationship.

[0036] The chip information mapping relationship is a mapping relationship between the chip identification information and the chip information.

[0037] In some optional embodiments, the chip information mapping relationship may include a mapping relationship between identification information of each chip connected to a preset bus and corresponding chip information.

[0038] In some optional embodiments, the chip information mapping relationship may include a mapping relationship between identification information of each chip and storage address information of corresponding chip information. The mapping method of the specific chip information mapping relationship is not limited, as long as the chip information of the chip can be obtained through the chip information mapping relationship.

[0039] In some optional embodiments, the chip information includes specific description information (or attribute information) of the chip, and the specific description information may include, for example, at least one of the following information: platform architecture information, working mode information, domain information, bus identification information, chip identification information, function identification information, and the number of direct memory access (DMA) channels supported by the chip. According to the mapping relationship between the first identification information and the preconfigured chip information, the first chip information of the target chip may be determined, so that the current chip can obtain the information required to establish a communication link with the target chip from the first chip information, such as the platform architecture information, working mode information, domain information, bus identification information, and the number of DMA channels supported by the target chip, for establishing a communication link.

[0040] In some optional embodiments, the chip information mapping relationship can be pre-established by the current chip and configured to the designated storage space of the current chip, or the chip information mapping relationship can be pre-established by other chips and configured to the designated storage space of the current chip, or the chip information mapping relationship can be pre-established by the host computer and configured to the designated storage space of the current chip. The specific configuration method is not limited.

[0041] Step 230: Establish a communication link with the target chip based on the first chip information.

[0042] Among them, the first chip information includes specific description information required to establish a communication link with the target chip, so a communication link can be established with the target chip based on the first chip information. Specifically, the current chip can transmit the first chip information of the target chip to the underlying driver of the current chip, and establish a communication link with the target chip through the underlying driver. The communication link between the current chip and the target chip may include at least one transmission link, and each transmission link may include one or more channels (Lane). For example, the number of channels that each transmission link may include may be 1, 2, 4, 6, 8, 16, 32, and so on. Each channel includes a send (Tx) link and a receive (Rx) link. The process of establishing a communication link (referred to as link building) with the target chip through the underlying driver is not described in detail.

[0043] Step 240, communicating with the target chip via the established communication link.

[0044] After the current chip establishes a communication link with the target chip, the current chip can communicate with the target chip through the established communication link, for example, the current chip transmits data to the target chip, the current chip reads data from the target chip, and so on.

[0045] The inter-chip communication method provided in this embodiment can automatically and quickly determine the first chip information of the target chip through a pre-configured chip information mapping relationship, and then establish a communication link with the target chip. By communicating with the target chip through the established communication link, the user can avoid viewing the chip information of the target chip by executing commands. The user only needs to obtain the chip identification information and reference the chip identification information in the application or hardware to achieve inter-chip communication, thereby reducing the complexity of user operations and improving user experience.

[0046] Figure 3 It is a flowchart of a communication method between chips provided by another exemplary embodiment of the present disclosure.

[0047] In some optional embodiments, the chip information mapping relationship includes identification information corresponding to each chip connected to the preset bus, and position relationship information of the chip information.

[0048] Among them, the preset bus can be a PCIe bus or other buses. The chips connected to the preset bus may include, for example, memory chips, network chips, central processing units, graphics processing units, field programmable gate arrays and / or application-specific integrated circuits. Each chip has corresponding unique identification information. The position relationship information of the chip information refers to the relationship information of the storage position of the chip information of each chip. Specifically, the chip information of each chip may have a certain data structure and be stored in a certain storage method. For example, the storage is performed in a bidirectional linked list, an array, a table, etc. The position relationship information may refer to the predecessor and successor of the chip information in the bidirectional linked list, or the array subscript of the chip information in the array, or the number of the chip information in the table, etc.

[0049] In some optional embodiments, in the above Figure 2 Based on the embodiment shown, Figure 3 As shown, step 220 of determining the first chip information of the target chip based on the first identification information and the preconfigured chip information mapping relationship may include the following steps:

[0050] Step 2210: Based on the first identification information, determine the position relationship information of the chip information corresponding to the first identification information from the chip information mapping relationship.

[0051] Among them, the position relationship information of the chip information corresponding to the first identification information (i.e., the first chip information) refers to the information of the storage position relationship of the first chip information. For example, the predecessor and successor of the first chip information in the bidirectional linked list, the array subscript of the first chip information in the array, the number of the first chip information in the table, and other information representing the storage position relationship of the first chip information. The predecessor and successor of the first chip information in the bidirectional linked list may refer to the identification information of the chip information pointed to by the predecessor pointer and the successor pointer of the first chip information, respectively. The array subscript of the first chip information in the array may refer to the element position subscript of the first chip information in the array. The number of the first chip information in the table may refer to the row and column number of the first chip information in the table.

[0052] In some optional embodiments, the chip information mapping relationship includes a mapping relationship between the identification information of each chip and the position relationship information of the corresponding chip information. The first identification information can be matched with the identification information in the chip information mapping relationship to determine the target identification information that matches the first identification information. The position relationship information of the chip information corresponding to the target identification information is the position relationship information of the chip information corresponding to the first identification information.

[0053] Step 2220: Determine first chip information of the target chip based on the position relationship information of the chip information corresponding to the first identification information.

[0054] After obtaining the position relationship information of the chip information corresponding to the first identification information, the chip information corresponding to the first identification information can be obtained from the corresponding position according to the position relationship information as the first chip information of the target chip.

[0055] In some optional embodiments, the chip information of each chip may be represented by a structure, or may be represented by a table field, or may be represented by other methods, and the specific representation method is not limited.

[0056] In the embodiment of the present disclosure, by pre-configuring identification information and positional relationship information of chip information corresponding to each chip connected to a preset bus, when any current chip needs to communicate with any target chip, the positional relationship information of the chip information corresponding to the first identification information can be accurately determined from the chip information mapping relationship according to the first identification information of the target chip, and then the first chip information of the target chip can be accurately obtained, thereby providing accurate and effective chip information for establishing a communication link with the target chip.

[0057] In some optional embodiments, determining the first chip information of the target chip based on the position relationship information of the chip information corresponding to the first identification information in step 2220 may include:

[0058] Based on the position relationship information of the chip information corresponding to the first identification information, the storage address information of the first chip information is determined; based on the storage address information, the first chip information is acquired.

[0059] Among them, the position relationship information of the chip information corresponding to the first identification information represents the storage location of the first chip information. Therefore, based on the position relationship information of the chip information corresponding to the first identification information, the storage address information of the first chip information can be determined, and based on the storage address information, the first chip information can be read from the storage space corresponding to the storage address information.

[0060] In some optional embodiments, the chip information of each chip can be stored in a specified storage space in a specified order, and the first address of the storage space can be recorded. Based on the position relationship information of the chip information of any chip, the relative storage position of the chip information with respect to the first address can be determined. Combined with the first address, the storage address information of the chip information can be determined. Based on this, the storage address information of the first chip information can be determined based on the position relationship information of the chip information corresponding to the first identification information.

[0061] In the embodiment of the present disclosure, the storage address information of the first chip information corresponding to the first identification information can be accurately obtained through the positional relationship information of the chip information corresponding to the first identification information, so that the first chip information can be obtained from the corresponding storage space according to the storage address information, providing accurate and effective chip information for establishing a communication link with the target chip.

[0062] Figure 4 It is a flowchart of a communication method between chips provided by yet another exemplary embodiment of the present disclosure.

[0063] In some optional embodiments, the chip information mapping relationship includes identification information and structure information corresponding to each chip connected to the preset bus, and the structure corresponding to the structure information records the chip information of the corresponding chip.

[0064] Among them, the chip information is represented by a structure, and the structure information may include the position relationship information of the structure. For example, the predecessor and successor of the structure in a bidirectional linked list, the subscript of the structure in an array, the number of the structure in a table, etc. The structure is a structured data composed of a batch of data, each of which is called sub-data of the structured data. In the embodiment of the present disclosure, the sub-data of the structure is various chip information of the chip, such as the above-mentioned platform architecture information, working mode information, etc.

[0065] In some optional embodiments, based on any of the above embodiments, determining the first chip information of the target chip based on the first identification information and the preconfigured chip information mapping relationship in step 220 may include:

[0066] Step 22a0: Based on the first identification information, determine the first structure information corresponding to the first identification information from the chip information mapping relationship.

[0067] The first structure information includes the positional relationship information of the structure corresponding to the first identification information, such as the positional relationship information of the predecessor and successor of the structure, the number of the structure, etc. The first identification information can be matched with the chip information mapping relationship, and the target identification information matching (or identical) with the first identification information can be determined from the chip information mapping relationship. The structure information corresponding to the target identification information is the first structure information corresponding to the first identification information.

[0068] Step 22b0: Determine first chip information of the target chip based on the first structure information.

[0069] The first structure information includes storage position relationship information of the structure corresponding to the first identification information. Based on the first structure information, the storage position relationship between the structure corresponding to the first identification information and other structures can be determined. For example, the storage address of the first structure or the first address of the overall storage space of the structure can be recorded. According to the storage position relationship of the structure corresponding to the first identification information relative to the storage address of the first structure, and the storage address of the first structure (or the first address of the storage space), the storage address information of the first structure corresponding to the first identification information can be determined, and then the first structure can be obtained from the corresponding storage space according to the storage address information, and the first chip information of the target chip can be obtained from the first structure. The specific method of determining the first chip information of the target chip according to the first structure information is not limited.

[0070] In the disclosed embodiment, a structure is used to represent chip information, so that the chip information is structured, which facilitates parsing various properties of the target chip required for establishing a communication link from the structure according to the specific structure of the structure in subsequent applications.

[0071] Figure 5 It is a flowchart of a communication method between chips provided by another exemplary embodiment of the present disclosure.

[0072] In some optional embodiments, based on any of the above embodiments, Figure 5 As shown, before determining the first chip information of the target chip based on the first identification information and the preconfigured chip information mapping relationship in step 220, the method of the embodiment of the present disclosure further includes:

[0073] Step 310: Obtain a hardware configuration description file of a chip connected to a preset bus.

[0074] The hardware configuration description file is a file that describes the hardware configuration of the chip connected to the preset bus. The hardware configuration description file can be a configuration file written by relevant R&D personnel in a certain programming language (such as a high-level programming language or other programming language) according to the chip connected to the preset bus in the actual scenario.

[0075] In some optional embodiments, the hardware configuration description file may include hardware configuration description information of each chip connected to the preset bus. For example, the hardware configuration description file may include at least one of the information such as the ID of each defined chip, the chip name, the platform architecture information of the chip, the working mode information of the chip, the domain information of the chip, the bus number of the chip (bus identification information), the device number of the chip (i.e., chip identification information), and the function number of the chip (i.e., function identification information). For a chip connected to the preset bus as an RC (Root-Complex) device (which may be referred to as an RC chip), the hardware configuration description file may include the ID, name, platform architecture information, working mode information, and / or domain information of the RC chip. For a chip connected to the preset bus as an EP (Endpoint) device (which may be referred to as an EP chip), the hardware configuration description file may include the ID, name, platform architecture information, working mode information, domain information, bus number, device number, function number, etc. of the EP chip.

[0076] Step 320: Determine the chip information mapping relationship based on the hardware configuration description file.

[0077] The hardware configuration description file may be parsed to obtain chip information of each chip, and a chip information mapping relationship may be established based on the chip information of each chip for subsequent establishment of communication links between chips.

[0078] The disclosed embodiment establishes a chip information mapping relationship through a hardware configuration description file, provides effective mapping relationship reference information for subsequent automatic acquisition of chip information based on chip identification information, simplifies user operations, and improves user experience.

[0079] In some optional embodiments, a programmable interface may be provided for the user, so that the user can design a hardware configuration description file according to the application scenario, and automatically convert the hardware configuration description file into a chip information mapping relationship through the method of the embodiment of the present disclosure.

[0080] Figure 6 It is a flowchart of a communication method between chips provided by yet another exemplary embodiment of the present disclosure.

[0081] In some optional embodiments, determining the chip information mapping relationship based on the hardware configuration description file in step 320 may include:

[0082] Step 3210: Parse the hardware configuration description file based on preset parsing rules to obtain field information of preset fields corresponding to each chip.

[0083] Among them, the preset fields include the chip identification information field and the chip information field. The preset parsing rules can be set according to the description format of the chip information in the hardware configuration description file. The identification information field is the field corresponding to the chip identification information, and the field information of the identification information field is the chip identification information. The chip information field is the field corresponding to the chip information of the chip. The number of chip information fields can be 1 or more. The field information of each chip information field records a kind of attribute information of the chip. For example, the field information of the platform architecture field records the platform architecture information of the chip, the field information of the working mode field records the working mode of the chip, and so on.

[0084] Step 3220: Determine chip information corresponding to each chip based on field information of a preset field corresponding to the chip.

[0085] Among them, the field information of the preset field includes the field information of the chip information field. Therefore, based on the field information of the preset field corresponding to each chip, the chip information corresponding to the chip, such as platform architecture information, working mode information, etc., can be obtained.

[0086] Step 3230, store the chip information corresponding to each chip, and obtain the storage address information corresponding to each chip.

[0087] The chip information corresponding to each chip can be stored in a designated storage space in a certain data structure to obtain storage address information corresponding to each chip (ie, storage address information of the chip information corresponding to each chip).

[0088] In some optional embodiments, the chip information corresponding to each chip can be stored in a specified storage space in a specified order.

[0089] Step 3240: Establish chip information mapping relationship according to storage address information corresponding to each chip.

[0090] In some optional embodiments, a mapping relationship between identification information and storage address information corresponding to each chip may be established as a chip information mapping relationship.

[0091] In some optional embodiments, the chip information corresponding to each chip can be connected to establish a certain connection relationship according to the order of storage address information, for example, a bidirectional linked list, array, table, etc. Take a bidirectional linked list as an example, the bidirectional pointers of the chip information of each chip in the bidirectional linked list point to the predecessor and successor of the chip information respectively, which is used to characterize the storage order relationship between the chip information of each chip. In this way, the storage address information of the chip information can be obtained through the first address of the storage space of the chip information and the position relationship information of any chip information, and then the chip information can be obtained according to the storage address information.

[0092] In the disclosed embodiment, by parsing the hardware configuration description file to obtain the field information of the preset fields of each chip connected to the preset bus, the complete chip information of the chip can be automatically obtained, and then the chip information of each chip can be stored in a designated storage space, and the storage address information of the chip information of each chip can be obtained. Based on the storage address information, the chip information mapping relationship can be effectively established, so that when any chip needs to communicate with a target chip, the chip information of the target chip can be accurately obtained according to the chip information mapping relationship, so that the current chip can be accurately matched to the target chip and a communication link can be established with the target chip.

[0093] In some optional embodiments, based on any of the above embodiments, the first chip information includes at least one of the platform architecture information, working mode information, domain information, bus identification information, chip identification information, function identification information, and the number of direct memory access channels supported by the target chip.

[0094] Among them, the platform architecture information refers to the platform architecture type of the chip, and the platform architecture type may include, for example, ARM (Advanced Reduced Instruction Set Computer Machines or Advanced RISC Machines, Advanced Reduced Instruction Set Computer Architecture) type, INTEL (Intel) type, etc. The working mode information refers to the working mode type of the chip in the current preset bus system, and the working mode type may include RC mode and EP mode. Optionally, the RC mode can be represented as 1, the EP mode can be represented as 0, or the RC mode is represented as 0, and the EP mode is represented as 1. The RC mode refers to the chip as an RC chip, and the EP mode refers to the chip as an EP chip. The chip in RC mode, for example but not limited to, refers to a host or a root endpoint. The root endpoint is the starting point on the preset bus, which is responsible for initiating bus transactions and managing all chips connected to the preset bus. For example, the bus controller inside the CPU can be used as a root endpoint. The chip in EP mode is responsible for receiving requests from the root endpoint or other chips, and performing data transmission accordingly. For example, the EP chip responds to bus events from the RC chip or other EP chips, and performs corresponding read, write or configuration operations. Domain information refers to the functional area information of the chip. A chip can include one or more controllers, each of which corresponds to a functional domain. Bus identification information refers to the bus number of the chip (which can be called a primary identification), which is the communication bus number assigned by the RC chip to the EP chip. Chip identification information is the device number of the chip (which can be called a secondary identification). Functional identification information is the function number of the chip (which can be called a tertiary identification). A chip can implement one or more functions, and each function corresponds to a function number. For example, a USB (Universal Serial Bus) hub chip can implement network port function and card reader function. The network port function corresponds to the network port function number, and the card reader function corresponds to the card reader function number. The number of direct memory access (DMA) channels (Lane) supported by the target chip refers to the number of DMA hardware resources possessed by the target chip, that is, the number of channels that can be used for communication links at the same time.

[0095] After obtaining the first chip information of the target chip, the target chip can be located from each chip connected to the preset bus according to the first chip information, and the device number, channel number, etc. of the target chip can be obtained, and the device number, channel number, etc. of the target chip can be transmitted to the underlying driver. The underlying driver opens the corresponding number of channels with the target chip according to the device number, channel number, etc. of the target chip, and establishes a communication link with the target chip. Specifically, the bus system of the current scene can include one or more buses (such as multiple PCIe buses), each bus can connect a group of chips (one or more chips), and each chip can implement one or more functions. The chip instruction sets of different platform architectures are different. According to the platform architecture information of the target chip, the instructions that can be supported by the communication with the target chip can be determined, and the domain information of the target chip represents the functional domain corresponding to the target chip. The bus identification information determines the bus number assigned by the RC chip to the target chip, the chip identification information determines the device number of the target chip, the function identification information determines the function that the target chip needs to implement in the functional domain, and the number of DMA channels supported by the target chip determines the number of channels to establish a communication link with the target chip. Therefore, based on the first chip information, the target chip can be located, and a communication link corresponding to the number of channels can be established with the target chip to communicate with the target chip through instructions supported by the target chip, so that the target chip can respond to the request of the current chip through the specified function. The specific establishment of the communication link and the communication process are conventional technologies in the relevant technical field and will not be described in detail here.

[0096] In some optional embodiments, Figure 7 FIG. 1 is a schematic diagram of a chip logic relationship provided by an exemplary embodiment of the present disclosure. Figure 7 As shown, by combining the chip information mapping relationship and the data structure of the chip information, the following can be formed: Figure 7 The chip structure relationship shown. System S0 may refer to systems such as intelligent driving systems and intelligent cockpit systems. System S0 may include two platform (plat) architectures P1 and P2, and platlist represents the platform list. System S0 may include two domains (domain D0 and domain D1), and domainlist represents the domain list. Among them, the chip list (chiplist) of domain D0 includes RC0 chip, EP00 chip, EP01 chip and EP02 chip, and the platform to which each chip of domain D0 belongs is P2. The chip list of domain D1 includes RC1 chip, EP10 chip, EP11 chip, EP12, RC0 chip, EP00 chip, EP01 chip and EP02 chip. In chiplist, next and arrows represent the positional relationship information of chip information. For example, in a bidirectional linked list, the predecessor of EP10 is RC1, and the successor of EP10 is EP11. Figure 7This is only an exemplary schematic diagram and is not intended to limit the embodiments of the present disclosure. In actual applications, the number of platforms, platform types, number of domains, and chip lists corresponding to each domain included in the system S0 can be set according to actual application scenarios. Each chip can be integrated on the same circuit board (Board), or can be separately or partially integrated on different boards, without specific limitation.

[0097] The disclosed embodiments, by establishing a system-level chip information mapping relationship, can conveniently expand system functions, such as replacing chips of other platform architectures, increasing the number of chips, etc. The application layer does not need to pay attention to the detailed information of the underlying hardware connection, but only needs to pay attention to the identification information set for the chip in the mapping relationship, which effectively abstracts the system organization relationship and effectively reduces the operation complexity of application layer users. And through the chip information mapping relationship, when each bus-connected chip communicates, the relevant properties of the target chip to be communicated, such as DMA channel configuration, can be automatically identified, so that a communication link can be established with the target chip quickly and accurately. In addition, after replacing the target chip, there is no need to modify other codes, because the hardware details are hidden, and the application layer only needs to specify the identification information such as the ID or name of the target chip.

[0098] The above-mentioned embodiments of the present disclosure may be implemented separately or in any combination without conflict. The specific configuration may be based on actual needs and the present disclosure does not limit this.

[0099] Any inter-chip communication method provided in the embodiments of the present disclosure may be executed by any appropriate electronic device with data processing capabilities, including but not limited to: electronic devices such as terminal devices and servers. Alternatively, any inter-chip communication method provided in the embodiments of the present disclosure may be executed by a processor, such as a processor executing any inter-chip communication method mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in a memory. This will not be described in detail below.

[0100] Exemplary Devices

[0101] Figure 8 is a schematic diagram of the structure of an inter-chip communication device provided by an exemplary embodiment of the present disclosure. The device of this embodiment can be used to implement the corresponding method embodiment of the present disclosure, such as Figure 8 The apparatus shown may include:

[0102] The first processing module 51 is used to determine first identification information of a target chip to be communicated.

[0103] The second processing module 52 is used to determine the first chip information of the target chip based on the first identification information and the preconfigured chip information mapping relationship.

[0104] The third processing module 53 is used to establish a communication link with the target chip based on the first chip information.

[0105] The fourth processing module 54 is used to communicate with the target chip through the established communication link.

[0106] Fig. 9 It is a schematic diagram of the structure of an inter-chip communication device provided by another exemplary embodiment of the present disclosure.

[0107] In some optional embodiments, the chip information mapping relationship includes identification information corresponding to each chip connected to the preset bus, and position relationship information of the chip information.

[0108] In some optional embodiments, in the above Figure 8 Based on the embodiment shown, Fig. 9 As shown, the second processing module 52 may include: a first processing unit 521 and a second processing unit 522 .

[0109] The first processing unit 521 is configured to determine, based on the first identification information, from the chip information mapping relationship the position relationship information of the chip information corresponding to the first identification information.

[0110] The second processing unit 522 is configured to determine first chip information of the target chip based on the position relationship information of the chip information corresponding to the first identification information.

[0111] In some optional embodiments, the second processing unit 522 may be specifically configured to:

[0112] Based on the position relationship information of the chip information corresponding to the first identification information, the storage address information of the first chip information is determined; based on the storage address information, the first chip information is acquired.

[0113] In some optional embodiments, the chip information mapping relationship includes identification information and structure information corresponding to each chip connected to the preset bus, and the structure corresponding to the structure information records the chip information of the corresponding chip.

[0114] In some optional embodiments, based on any of the above embodiments, see Fig. 9 The second processing module 52 may include: a first processing unit 521 and a second processing unit 522 .

[0115] The first processing unit 521 may be configured to determine, based on the first identification information, first structure information corresponding to the first identification information from the chip information mapping relationship.

[0116] The second processing unit 522 may be configured to determine first chip information of the target chip based on the first structure information.

[0117] Fig.10 4 is a schematic diagram of the structure of an inter-chip communication device provided by yet another exemplary embodiment of the present disclosure.

[0118] In some optional embodiments, based on any of the above embodiments, Fig.10 As shown, the device of the embodiment of the present disclosure further includes: an acquisition module 61 and a fifth processing module 62

[0119] The acquisition module 61 is used to acquire a hardware configuration description file of a chip connected to a preset bus.

[0120] The fifth processing module 62 is used to determine the chip information mapping relationship based on the hardware configuration description file.

[0121] Fig.11 It is a schematic diagram of the structure of an inter-chip communication device provided by yet another exemplary embodiment of the present disclosure.

[0122] In some optional embodiments, the fifth processing module 62 may include:

[0123] The parsing unit 621 is used to parse the hardware configuration description file based on preset parsing rules to obtain field information of preset fields corresponding to each chip.

[0124] The preset fields include a chip identification information field and a chip information field.

[0125] The third processing unit 622 is used to determine chip information corresponding to each chip based on field information of a preset field corresponding to the chip.

[0126] The fourth processing unit 623 is used to store the chip information corresponding to each chip and obtain the storage address information corresponding to each chip.

[0127] The fifth processing unit 624 establishes a chip information mapping relationship according to the storage address information corresponding to each chip.

[0128] In some optional embodiments, based on any of the above embodiments, the first chip information includes at least one of the platform architecture information, working mode information, domain information, bus identification information, chip identification information, function identification information, and the number of direct memory access channels supported by the target chip.

[0129] The above-mentioned embodiments of the present disclosure may be implemented separately or in any combination without conflict. The specific configuration may be based on actual needs and the present disclosure does not limit this.

[0130] The beneficial technical effects corresponding to the exemplary embodiment of the present device can be found in the corresponding beneficial technical effects of the above exemplary method section, which will not be repeated here.

[0131] Exemplary Electronic Devices

[0132] Fig.12 It is a structural diagram of an electronic device provided by an embodiment of the present disclosure, including at least one processor 91 and a memory 92.

[0133] The processor 91 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 90 to perform desired functions.

[0134] The memory 92 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 91 may execute one or more computer program instructions to implement the methods and / or other desired functions of the various embodiments of the present disclosure described above.

[0135] In one example, the electronic device 90 may further include: an input device 93 and an output device 94 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0136] The input device 93 may also include, for example, a touch screen, a microphone, various sensors, and the like. Sensors may include, for example, image sensors (such as cameras, cameras, etc.), laser radars, millimeter-wave radars, ultrasonic radars, positioning sensors, pressure sensors, air quality sensors, temperature sensors, and the like. Image sensors, laser radars, millimeter-wave radars, ultrasonic radars, and the like may be used to sense the surrounding environment, that is, to detect dynamic and static objects in the surrounding environment. Dynamic and static objects may include, for example, static objects such as lane lines, curbs, arrows, signs, trees, and buildings, as well as dynamic objects such as surrounding vehicles, pedestrians, and cyclists. Positioning sensors are used to realize the positioning of movable devices (such as self-vehicles, robots, etc.) where electronic devices are located. Positioning sensors may include, for example, inertial measurement units (Inertial Measurement Unit, referred to as: IMU), global positioning systems (Global Positioning System, referred to as: GPS), and the like. Pressure sensors may be used to detect seat pressure. Temperature sensors may be used to detect the temperature in the vehicle cabin. Air quality sensors may be used to detect the air quality in the vehicle cabin.

[0137] The output device 94 can output various information to the outside, and may include, for example, a display, a speaker, a communication network and a remote output device connected thereto, and the like.

[0138] Of course, to simplify, Fig.12 Only some of the components related to the present disclosure in the electronic device 90 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 90 may also include any other appropriate components.

[0139] Exemplary computer program products and computer-readable storage media

[0140] In addition to the above methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the methods of various embodiments of the present disclosure described in the above “Exemplary Methods” section.

[0141] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0142] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps in the method of various embodiments of the present disclosure described in the above “Exemplary Method” section.

[0143] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or device including electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0144] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0145] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A communication method between chips, comprising: Determine first identification information of a target chip to be communicated; Determine first chip information of the target chip based on the first identification information and a preconfigured chip information mapping relationship; Establishing a communication link with the target chip based on the first chip information; Communication is performed with the target chip via the established communication link.

2. The method according to claim 1, wherein: The chip information mapping relationship includes identification information corresponding to each chip connected to the preset bus, and position relationship information of the chip information; The determining the first chip information of the target chip based on the first identification information and the preconfigured chip information mapping relationship includes: Based on the first identification information, determining position relationship information of the chip information corresponding to the first identification information from the chip information mapping relationship; The first chip information of the target chip is determined based on the position relationship information of the chip information corresponding to the first identification information.

3. The method according to claim 2, wherein: The determining the first chip information of the target chip based on the position relationship information of the chip information corresponding to the first identification information includes: Determine storage address information of the first chip information based on position relationship information of the chip information corresponding to the first identification information; Based on the storage address information, the first chip information is acquired.

4. The method according to claim 1, wherein: The chip information mapping relationship includes identification information and structure information corresponding to each chip connected to the preset bus, and the structure corresponding to the structure information records the chip information of the corresponding chip; The determining the first chip information of the target chip based on the first identification information and the preconfigured chip information mapping relationship includes: Based on the first identification information, determining first structure information corresponding to the first identification information from the chip information mapping relationship; Based on the first structure information, the first chip information of the target chip is determined.

5. The method according to any one of claims 1 to 4, wherein: Before determining the first chip information of the target chip based on the first identification information and the preconfigured chip information mapping relationship, the method further includes: Obtain a hardware configuration description file of a chip connected to a preset bus; Based on the hardware configuration description file, the chip information mapping relationship is determined.

6. The method according to claim 5, wherein: The determining the chip information mapping relationship based on the hardware configuration description file includes: Parsing the hardware configuration description file based on preset parsing rules to obtain field information of preset fields corresponding to each chip; the preset fields include an identification information field and a chip information field of the chip; Based on the field information of the preset field corresponding to each chip, determine the chip information corresponding to the chip; The chip information corresponding to each of the chips is stored to obtain storage address information corresponding to each of the chips; The chip information mapping relationship is established according to the storage address information corresponding to each of the chips.

7. The method according to any one of claims 1 to 4, wherein: The first chip information includes at least one of platform architecture information, working mode information, domain information, bus identification information, chip identification information, function identification information of the target chip, and the number of direct memory access channels supported by the target chip.

8. A chip-to-chip communication device, comprising: A first processing module, used to determine first identification information of a target chip to be communicated; A second processing module, configured to determine first chip information of the target chip based on the first identification information and a preconfigured chip information mapping relationship; A third processing module, configured to establish a communication link with the target chip based on the first chip information; The fourth processing module is used to communicate with the target chip through the established communication link.

9. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the method according to any one of claims 1 to 7.

10. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the method described in any one of claims 1 to 7.

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