Communication system

Abstract

The invention relates to the technical field of communication, and provides a communication system. The communication system comprises a host and at least one slave which is in communication connection with the host through a master I2C bus and an auxiliary I2C bus, and the two I2C buses share the same clock line; the host sends a start signal through the auxiliary I2C bus; when the slave detects a start signal on the auxiliary I2C bus through the I2C control circuit, a first register associated with the main I2C bus and a second register associated with the auxiliary I2C bus are reset; the host sends an operation instruction through the auxiliary I2C bus; the slave receives the operation instruction through the auxiliary I2C bus and executes corresponding operation according to the operation instruction; the host sends a stop signal through the auxiliary I2C bus; and when the slave detects a stop signal on the auxiliary I2C bus through the I2C control circuit, the first register and the second register are reset. Equipment addressing and register addressing are not needed, the period needed by one-time communication transmission is shortened, and the communication rate is increased.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a communication system. Background Art

[0002] IIC (Inter-Integrated Circuit) is also called I2C, which is one of the most widely used serial communication protocols today. Compared with the strict timing requirements of single-wire serial interfaces and more cable requirements such as SPI (Serial Peripheral Interface), I2C can perform bidirectional communication between multiple masters and multiple slaves using only two cables. It is compact, flexible and convenient, and can meet the communication needs between different devices.

[0003] The I2C bus consists of SDA (Serial Data) and SCL (Serial Clock) as communication lines. It can be used to send and receive data. The SDA and SCL pin output drivers of all devices on the I2C bus are open-drain (OD) structures, and the line-and-logic relationship of the SDA and SCL signals of all nodes on the bus is realized through external pull-up resistors. The I2C protocol has strict timing requirements, including the start signal, stop signal, and response bit, which must be sent at precise time intervals. The controller must accurately generate clock pulses (SCL line) and control the level changes on the data line (SDA line). Any deviation may cause communication errors. In addition, each I2C communication requires a certain handshake process, which takes a certain amount of time. For example, a write data frame includes a start bit, a device address, a response bit, the address of the write register, write data, and a stop bit. It takes 26 SCL clock cycles to complete a frame of write operation. According to the I2C fast mode + (Fast-Plus) rate, it takes 26 microseconds. However, in some fields, such as optical fiber communication, signal encoding must be calculated in real time based on the light flux. Modulating laser load changes requires software to respond immediately to enable current drive devices. If the communication is carried out according to the conventional I2C protocol, the system response speed will be limited by the I2C communication speed. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a communication system.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a communication system, the communication system comprising a host and at least one slave, the slave being communicatively connected to the host via a main I2C bus and an auxiliary I2C bus, the main I2C bus and the auxiliary I2C bus sharing a same clock line, the slave comprising an I2C control circuit, a first register associated with the main I2C bus, and a second register associated with the auxiliary I2C bus;

[0007] The host sends a start signal via the auxiliary I2C bus;

[0008] When the slave detects a start signal on the auxiliary I2C bus through the I2C control circuit, the first register and the second register are reset;

[0009] The host sends an operation instruction via the auxiliary I2C bus;

[0010] The slave receives the operation instruction through the auxiliary I2C bus, and performs a corresponding operation according to the operation instruction;

[0011] The host sends a stop signal via the auxiliary I2C bus;

[0012] When the slave detects a stop signal on the auxiliary I2C bus through the I2C control circuit, the first register and the second register are reset.

[0013] In an optional implementation, when only one slave in the communication system is communicatively connected to the host via the auxiliary I2C bus, the slave obtains the operation type and the data to be processed according to the operation instruction, and performs a corresponding operation based on the operation type and the data to be processed.

[0014] In an optional implementation, when there are multiple slaves in the communication system that are communicatively connected to the host via the auxiliary I2C bus, the slave obtains the device identification, operation type and data to be processed according to the operation instruction, and when the device identification represents itself, performs a corresponding operation based on the operation type and the data to be processed.

[0015] In an optional embodiment, when the auxiliary I2C bus is composed of a shared clock line and a bidirectional serial data line, the I2C control circuit includes an electrically connected detection module and a reset module, and the reset module is electrically connected to the first register and the second register;

[0016] The detection module is used for transmitting a first reset signal to the reset module when detecting a start signal or a stop signal on the main I2C bus;

[0017] The reset module is used for resetting the first register when receiving the first reset signal;

[0018] The detection module is further configured to transmit a second reset signal to the reset module when a start signal or a stop signal on the auxiliary I2C bus is detected;

[0019] The reset module is further configured to reset the first register and the second register when receiving the second reset signal.

[0020] In an optional implementation, when the auxiliary I2C bus is composed of a shared clock line and a multiplexed IO data line, the I2C control circuit includes a control register, a multiplexer, a detection module, and a reset module; the control register is electrically connected to the multiplexer, the multiplexer is electrically connected to the detection module, the detection module is electrically connected to the reset module, and the reset module is electrically connected to the first register and the second register;

[0021] The control register is used to control the multiplexer to connect the multiplexed IO data line with the detection module in an enabled state;

[0022] The detection module is used for transmitting a first reset signal to the reset module when detecting a start signal or a stop signal on the main I2C bus;

[0023] The reset module is used for resetting the first register when receiving the first reset signal;

[0024] The detection module is further configured to transmit a second reset signal to the reset module when a start signal or a stop signal on the auxiliary I2C bus is detected;

[0025] The reset module is further configured to reset the first register and the second register when receiving the second reset signal.

[0026] In an optional embodiment, the detection module includes a first detection module and a second detection module, and the reset module includes a first reset module and a second reset module; the first detection module is electrically connected to the first reset module, the second detection module is electrically connected to the first reset module and the second reset module, the first reset module is electrically connected to the first register, and the second reset module is electrically connected to the second register;

[0027] The first detection module is used for transmitting a first reset signal to the first reset module when detecting a start signal or a stop signal on the main I2C bus;

[0028] The first reset module is used for resetting the first register when receiving the first reset signal;

[0029] The second detection module is used for transmitting a second reset signal to the first reset module and the second reset module when detecting a start signal or a stop signal on the auxiliary I2C bus;

[0030] The first reset module is further configured to reset the first register upon receiving the second reset signal;

[0031] The second reset module is used for resetting the second register when receiving the second reset signal.

[0032] In an optional embodiment, the first detection module includes a first start condition detection unit and a first stop condition detection unit, and the first start condition detection unit and the first stop condition detection unit are both electrically connected to the first reset module;

[0033] The first start condition detection unit is used for transmitting a first reset signal to the first reset module when detecting a start signal on the main I2C bus;

[0034] The first stop condition detection unit is used to transmit a first reset signal to the first reset module when a stop signal on the main I2C bus is detected.

[0035] In an optional embodiment, the second detection module includes a second start condition detection unit and a second stop condition detection unit, the second start condition detection unit is electrically connected to the first reset module and the second reset module, and the second stop condition detection unit is electrically connected to the first reset module and the second reset module;

[0036] The second start condition detection unit is used for transmitting a second reset signal to the first reset module and the second reset module when detecting a start signal on the auxiliary I2C bus;

[0037] The second stop condition detection unit is used for transmitting a second reset signal to the first reset module and the second reset module when a stop signal on the auxiliary I2C bus is detected.

[0038] In an optional embodiment, the first reset module includes a first NOR gate and a first AND gate; the first input end of the first NOR gate is electrically connected to the first start condition detection unit, the second input end of the first NOR gate is electrically connected to the first stop condition detection unit, the third input end of the first NOR gate is electrically connected to the second start condition detection unit, the fourth input end of the first NOR gate is electrically connected to the second stop condition detection unit, the output end of the first NOR gate is electrically connected to the first input end of the first AND gate, the output end of the first AND gate is electrically connected to the first register, and the second input end of the first AND gate is used to receive a power-on reset signal.

[0039] In an optional embodiment, the second reset module includes a second NOR gate and a second AND gate; the first input end of the second NOR gate is electrically connected to the second start condition detection unit, the second input end of the second NOR gate is electrically connected to the second stop condition detection unit, the output end of the second NOR gate is electrically connected to the first input end of the second AND gate, the output end of the second AND gate is electrically connected to the second register, and the second input end of the second AND gate is used to receive a power-on reset signal.

[0040] The present invention provides a communication system, which includes a host and at least one slave, the slave is connected to the host through a main I2C bus and an auxiliary I2C bus, the main I2C bus and the auxiliary I2C bus share the same clock line, and the slave includes an I2C control circuit, a first register associated with the main I2C bus, and a second register associated with the auxiliary I2C bus. The host sends a start signal through the auxiliary I2C bus; when the slave detects the start signal on the auxiliary I2C bus through the I2C control circuit, the first register and the second register are reset; the host sends an operation instruction through the auxiliary I2C bus; the slave receives the operation instruction through the auxiliary I2C bus and performs the corresponding operation according to the operation instruction; the host sends a stop signal through the auxiliary I2C bus; when the slave detects the stop signal on the auxiliary I2C bus through the I2C control circuit, the first register and the second register are reset. Compared with the existing I2C bus communication process, the present invention does not need to perform device addressing and register addressing, thereby reducing the cycle required for a communication transmission and improving the communication rate.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 One of the schematic diagrams of a communication system provided by an embodiment of the present invention is shown;

[0044] Figure 2 A second schematic diagram of a communication system provided by an embodiment of the present invention is shown;

[0045] Figure 3 One of the schematic diagrams of the I2C control circuit provided by the embodiment of the present invention is shown;

[0046] Figure 4 A second schematic diagram of an I2C control circuit provided by an embodiment of the present invention is shown;

[0047] Figure 5 The third schematic diagram of the I2C control circuit provided by the embodiment of the present invention is shown;

[0048] Figure 6 A fourth schematic diagram of an I2C control circuit provided by an embodiment of the present invention is shown;

[0049] Figure 7 A fifth schematic diagram of an I2C control circuit provided in an embodiment of the present invention is shown;

[0050] Figure 8 FIG6 shows a sixth schematic diagram of an I2C control circuit provided by an embodiment of the present invention.

[0051] Icon: 10-I2C control circuit; 20-first register; 30-second register. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0053] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0054] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0055] See also Figure 1 and Figure 2 , is a schematic diagram of two communication systems provided by an embodiment of the present invention. Among them, Figure 1 The communication system shown includes a host and a slave, and the slave is communicatively connected to the host via a main I2C bus and an auxiliary I2C bus. Figure 2 The communication system shown includes a host and multiple slaves, and the multiple slaves are all communicatively connected to the host via a main I2C bus and an auxiliary I2C bus.

[0056] It should be noted that the main IC2 bus is a conventional general I2C bus, which includes an SCL line and an SDA line; the auxiliary I2C bus is composed of the SCL line and other data lines, namely the AUX_SDA line. That is, the main I2C bus and the auxiliary I2C bus share the same clock line. In addition, each slave includes an I2C control circuit 10, a first register 20 and a second register 30. Among them, the first register 20 is used to store control information related to the main I2C bus; the second register 30 is used to store control information related to the auxiliary I2C bus.

[0057] It is understandable that based on Figure 1 and Figure 2 The communication system shown in the figure may also include one or more common slaves that are connected to the host through the main I2C bus. That is, the number of the host, slaves and conventional slaves in the communication system provided by the embodiment of the present invention can be set according to actual conditions, and the embodiment of the present invention does not limit this.

[0058] The following will be based on Figure 1 and Figure 2 The communication system shown in FIG. 1 introduces the process of the master and the slave communicating through the auxiliary I2C bus.

[0059] First, the host sends a start signal through the auxiliary I2C bus, that is, when the SCL line is at a high level, the host pulls the AUX_SDA line from a high level to a low level to generate a start signal, and this start signal indicates the start of a communication. When the slave detects the start signal on the auxiliary I2C bus through the I2C control circuit 10, it resets its first register 20 and second register 30.

[0060] Then, the host sends the operation instruction through the auxiliary I2C bus, that is, when the SCL line is kept at a low level, the host controls the level change of the AUX_SDA line to send a string of operation codes (OP codes) of no more than 8 bits within 8 cycles. It can be understood that the operation code is used to indicate the operation of a specific device in the slave, such as the register of an optical module.

[0061] In the case where only one slave is connected to the host through the auxiliary I2C bus in the communication system, the slave will perform the corresponding operation according to the operation instruction after receiving the operation instruction through the auxiliary I2C bus. In the case where multiple slaves are connected to the host through the auxiliary I2C bus in the communication system, each slave will identify the operation instruction after receiving it through the auxiliary I2C bus. If the identification fails, the operation instruction is discarded; if the identification succeeds, the corresponding operation is performed according to the operation instruction.

[0062] Finally, the host sends a stop signal through the auxiliary I2C bus, that is, when the SCL line is at a high level, the host pulls the AUX_SDA line from a low level to a high level to generate a stop signal, and this stop signal indicates the end of a communication. When the slave detects the stop signal on the auxiliary I2C bus through the I2C control circuit 10, it resets its first register 20 and second register 30.

[0063] In the above communication process, when the slave detects a start signal or a stop signal on the auxiliary I2C bus, it resets its own second register 30 in order to restore the registers related to the auxiliary I2C bus to the initial state to ensure correct data transmission.

[0064] Furthermore, the slave resets its first register 20 to avoid affecting the communication on the main I2C bus. That is, the communication on the auxiliary I2C bus may cause the communication process on the main I2C bus to be interrupted, which will cause the registers related to the main I2C bus to be in an unknown state, thereby affecting the communication on the main I2C bus. Therefore, the implementation of the present invention is to reset the first register 20 to restore it to a clear initial state, thereby ensuring that the main I2C bus can communicate normally in the future.

[0065] It can be understood that the embodiment of the present invention realizes communication between the master and slave machines by sending a start signal, an operation instruction, and a stop signal via an auxiliary I2C bus. Compared with the existing I2C bus communication process, the present invention does not need to perform device addressing and register addressing, thereby reducing the cycle required for a communication transmission and improving the communication rate.

[0066] Optionally, in the case where only one slave in the communication system is connected to the host through the auxiliary I2C bus, since the host will only communicate with one slave through the auxiliary I2C bus, in this case, the operation instruction may include the operation type and the data to be processed. Then, after receiving the operation instruction sent by the host, the slave may obtain the operation type and the data to be processed carried therein, and perform the corresponding operation based on the operation type and the data to be processed.

[0067] For example, assuming the operation instruction is an 8-bit opcode, it can be set to 100+ADDR+IDAC3_Fast_EN+IDAC2_Fast_EN+IDAC1_Fast_EN+

[0068] IDAC0_Fast_EN. 100 indicates the operation type such as write operation, ADDR indicates the register identifier, and IDAC3_Fast_EN, IDAC2_Fast_EN, IDAC1_Fast_EN, and IDAC0_Fast_EN indicate the data to be processed.

[0069] It should be understood that the length of the opcode can be less than 8 bits, and the number of bits and bit positions used to indicate the operation type, and the number of bits and bit positions used to indicate the data to be processed can be set according to actual conditions, and the embodiments of the present invention do not limit this.

[0070] It can be understood that in the case where there is only one slave connected to the host through the auxiliary I2C bus in the communication system, the host will only send operation instructions to the slave. Therefore, there is no need to perform device addressing when the master and slave communicate through the auxiliary I2C bus, and since the operation instruction is to operate on a specific register, there is no need to perform register addressing, thereby reducing the cycle required for a communication transmission and improving the communication rate.

[0071] Optionally, in the case where there are multiple slaves in the communication system that are connected to the host through an auxiliary I2C bus, since the host can communicate with multiple slaves through the auxiliary I2C bus, in this case, in order to distinguish which slave the host sends the operation instruction to, the operation instruction may include a device identification, an operation type, and data to be processed.

[0072] After receiving the operation instruction sent by the host, the slave will identify the operation instruction. If the slave fails to identify, that is, it does not identify the identifier representing itself, it means that the slave does not need to execute the operation instruction, and the operation instruction is discarded. If the slave successfully identifies, that is, it identifies the identifier representing itself, it means that the slave needs to execute the operation instruction, then the operation type and the data to be processed carried by the operation instruction are obtained, and the corresponding operation is performed based on the operation type and the data to be processed.

[0073] For example, if there are two slaves in the communication system connected to the master through the auxiliary I2C bus, and the operation instruction is a string of 8-bit operation codes, it can be set to 1+10+ADDR+IDAC3_Fast_EN+IDAC2_Fast_EN+IDAC1_Fast_EN+

[0074] IDAC0_Fast_EN. 1 indicates the device identification, such as the identification of the first slave, 10 indicates the operation type, such as a write operation, ADDR indicates the register identification, and IDAC3_Fast_EN, IDAC2_Fast_EN, IDAC1_Fast_EN, and IDAC0_Fast_EN indicate the data to be processed.

[0075] It should be understood that the length of the opcode can be less than 8 bits, and the number of bits and bit positions used to represent the device identification, the number of bits and bit positions used to represent the operation type, and the number of bits and bit positions used to represent the data to be processed can be set according to actual conditions, and the embodiments of the present invention do not limit this.

[0076] It can be understood that in a communication system where multiple slaves are connected to the host through an auxiliary I2C bus, the host will send an operation instruction carrying a device identifier, and the slave will determine whether it needs to process and execute the operation instruction based on the device identifier in the operation instruction. Therefore, the master and slave do not need to perform device addressing when communicating through the auxiliary I2C bus, and since the operation instruction is to operate on a specific register, there is no need to perform register addressing, thereby reducing the cycle required for a communication transmission and improving the communication rate.

[0077] Optionally, the AUX_SDA line can be a bidirectional serial data line, and the auxiliary I2C bus is composed of a common SCL line and the bidirectional serial data line. In this case, the embodiment of the present invention provides a schematic diagram of an I2C control circuit 10, see Figure 3 .

[0078] The I2C control circuit 10 includes a detection module and a reset module which are electrically connected, and the reset module is electrically connected to the first register 20 and the second register 30 .

[0079] In this embodiment, when the detection module detects the start signal on the main I2C bus, that is, when the SCL line is detected to be at a high level and the SDA line changes from a high level to a low level, the detection module transmits a first reset signal to the reset module. Then, the reset module receives the first reset signal and resets the first register 20.

[0080] When the detection module detects the stop signal on the main I2C bus, that is, when the SCL line is detected to be high and the SDA line changes from low level to high level, the detection module transmits a first reset signal to the reset module. Then the reset module receives the first reset signal and resets the first register 20.

[0081] When the detection module detects the start signal on the auxiliary I2C bus, that is, when the SCL line is detected to be at a high level and the bidirectional serial data line changes from a high level to a low level, the detection module transmits a second reset signal to the reset module. Then the reset module receives the second reset signal and resets the first register 20 and the second register 30.

[0082] When the detection module detects the stop signal on the auxiliary I2C bus, that is, when the SCL line is detected to be at a high level and the bidirectional serial data line changes from a low level to a high level, the detection module transmits a second reset signal to the reset module. Then the reset module receives the second reset signal and resets the first register 20 and the second register 30.

[0083] Optionally, since the above-mentioned method of using a bidirectional serial data line as the AUX_SDA line will occupy a single port, in order to save ports and reduce the area of ​​the slave chip. The following provides a method of multiplexing the IO data line as the AUX_SDA line, and the auxiliary I2C bus is composed of a shared SCL line and the multiplexed IO data line. In this case, the embodiment of the present invention provides another schematic diagram of the I2C control circuit 10, please refer to Figure 4 .

[0084] The control register is electrically connected to the multiplexer, the multiplexer is electrically connected to the detection module, the detection module is electrically connected to the reset module, and the reset module is electrically connected to the first register 20 and the second register 30 .

[0085] In this embodiment, when the host needs to communicate with the slave through the auxiliary I2C bus, it first communicates with the slave through the main I2C bus to set the control register to an enabled state. When the control register is in the enabled state, the control multiplexer connects the multiplexed IO data line to the detection module.

[0086] When the detection module detects the start signal on the main I2C bus, that is, when the SCL line is detected to be high and the SDA line changes from high level to low level, the detection module transmits a first reset signal to the reset module. Then the reset module receives the first reset signal and resets the first register 20.

[0087] When the detection module detects the stop signal on the main I2C bus, that is, when the SCL line is detected to be high and the SDA line changes from low level to high level, the detection module transmits a first reset signal to the reset module. Then the reset module receives the first reset signal and resets the first register 20.

[0088] When the detection module detects the start signal on the auxiliary I2C bus, that is, when the SCL line is detected to be at a high level and the multiplexed IO data line changes from a high level to a low level, the detection module transmits a second reset signal to the reset module. Then the reset module receives the second reset signal and resets the first register 20 and the second register 30.

[0089] When the detection module detects the stop signal on the auxiliary I2C bus, that is, when the SCL line is detected to be at a high level and the multiplexed IO data line changes from a low level to a high level, the detection module transmits a second reset signal to the reset module. Then the reset module receives the second reset signal and resets the first register 20 and the second register 30.

[0090] Optionally, based on the above Figure 3 The I2C control circuit 10 shown in FIG. 1 is a schematic diagram of another I2C control circuit 10 provided in the embodiment of the present invention. Figure 5 .

[0091] The detection module includes a first detection module and a second detection module, and the reset module includes a first reset module and a second reset module. The first detection module is electrically connected to the first reset module, the second detection module is electrically connected to the first reset module and the second reset module, the first reset module is electrically connected to the first register 20, and the second reset module is electrically connected to the second register 30.

[0092] In this embodiment, when the first detection module detects the start signal on the main I2C bus, that is, when the SCL line is detected to be at a high level and the SDA line changes from a high level to a low level, the first detection module transmits a first reset signal to the first reset module. Then, the first reset module receives the first reset signal and resets the first register 20.

[0093] When the first detection module detects a stop signal on the main I2C bus, that is, when the SCL line is detected to be high and the SDA line changes from low level to high level, the first detection module transmits a first reset signal to the first reset module. Then the first reset module receives the first reset signal and resets the first register 20.

[0094] When the second detection module detects the start signal on the auxiliary I2C bus, that is, detects that the SCL line is at a high level and the bidirectional serial data line changes from a high level to a low level, the second detection module transmits a second reset signal to the first reset module and the second reset module. Then the first reset module receives the second reset signal and resets the first register 20. At the same time, the second reset module receives the second reset signal and resets the second register 30.

[0095] When the second detection module detects the stop signal on the auxiliary I2C bus, that is, when the SCL line is detected to be at a high level and the bidirectional serial data line changes from a low level to a high level, the second detection module transmits a second reset signal to the first reset module and the second reset module. Then the first reset module receives the second reset signal and resets the first register 20. At the same time, the second reset module receives the second reset signal and resets the second register 30.

[0096] Optionally, based on the above Figure 4 The I2C control circuit 10 shown in FIG. 1 is a schematic diagram of another I2C control circuit 10 provided in the embodiment of the present invention. Figure 6 .

[0097] The detection module includes a first detection module and a second detection module, and the reset module includes a first reset module and a second reset module. The first detection module is electrically connected to the first reset module, the second detection module is electrically connected to the first reset module and the second reset module, the first reset module is electrically connected to the first register 20, and the second reset module is electrically connected to the second register 30. The multiplexer is electrically connected to the second detection module.

[0098] In this embodiment, when the host needs to communicate with the slave through the auxiliary I2C bus, it first communicates with the slave through the main I2C bus to set the control register to an enabled state. When the control register is in the enabled state, the multiplexer is controlled to connect the multiplexed IO data line to the second detection module.

[0099] When the first detection module detects the start signal on the main I2C bus, that is, when the SCL line is detected to be high and the SDA line changes from high to low, the first detection module transmits a first reset signal to the first reset module. Then the first reset module receives the first reset signal and resets the first register 20.

[0100] When the first detection module detects a stop signal on the main I2C bus, that is, when the SCL line is detected to be high and the SDA line changes from low level to high level, the first detection module transmits a first reset signal to the first reset module. Then the first reset module receives the first reset signal and resets the first register 20.

[0101] When the second detection module detects the start signal on the auxiliary I2C bus, that is, when the SCL line is detected to be at a high level and the multiplexed IO data line changes from a high level to a low level, the second detection module transmits a second reset signal to the first reset module and the second reset module. Then the first reset module receives the second reset signal and resets the first register 20. At the same time, the second reset module receives the second reset signal and resets the second register 30.

[0102] When the second detection module detects the stop signal on the auxiliary I2C bus, that is, when the SCL line is detected to be at a high level and the multiplexed IO data line changes from a low level to a high level, the second detection module transmits a second reset signal to the first reset module and the second reset module. Then the first reset module receives the second reset signal and resets the first register 20. At the same time, the second reset module receives the second reset signal and resets the second register 30.

[0103] Optionally, based on the above Figure 5 The I2C control circuit 10 shown in FIG. 1 is a schematic diagram of another I2C control circuit 10 provided in the embodiment of the present invention. Figure 7 .

[0104] The first detection module includes a first start condition detection unit and a first stop condition detection unit. The first start condition detection unit and the first stop condition detection unit are both electrically connected to the first reset module.

[0105] The second detection module includes a second start condition detection unit and a second stop condition detection unit. The second start condition detection unit is electrically connected to the first reset module and the second reset module, and the second stop condition detection unit is electrically connected to the first reset module and the second reset module.

[0106] The first reset module includes a first NOR gate and a first AND gate. The first input terminal a1 of the first NOR gate is electrically connected to the first start condition detection unit, the second input terminal a2 of the first NOR gate is electrically connected to the first stop condition detection unit, the third input terminal a3 of the first NOR gate is electrically connected to the second start condition detection unit, the fourth input terminal a4 of the first NOR gate is electrically connected to the second stop condition detection unit, the output terminal a5 of the first NOR gate is electrically connected to the first input terminal b1 of the first AND gate, the second input terminal b2 of the first AND gate is used to receive a power-on reset signal, and the output terminal b3 of the first AND gate is electrically connected to the first register 20.

[0107] The second reset module includes a second NOR gate and a second AND gate. The first input terminal c1 of the second NOR gate is electrically connected to the second start condition detection unit, the second input terminal c2 of the second NOR gate is electrically connected to the second stop condition detection unit, the output terminal c3 of the second NOR gate is electrically connected to the first input terminal d1 of the second AND gate, the second input terminal d2 of the second AND gate is used to receive a power-on reset signal, and the output terminal d3 of the second AND gate is electrically connected to the second register 30.

[0108] In this embodiment, it is assumed that when the slave is in an order placing state, the power-on reset signal, por_rst_n, is at a low level, ie, 0; when the slave is in a power-on state, the power-on reset signal, por_rst_n, always maintains a high level 1.

[0109] When the first start condition detection unit detects the start signal on the main I2C bus, that is, when the SCL line is detected to be at a high level and the SDA line changes from a high level to a low level, it outputs a high level 1. Then the first NOR gate performs a NOR operation based on the level signals of the four input terminals, namely a1 to a4, and since its first input terminal a1 is at a high level 1, it outputs a low level 0. Then the first AND gate performs an AND operation based on the level signals of the two input terminals, namely b1 and b2, and since its first input terminal b1 is at a low level 0 and the second input terminal b2 is at a high level 1, it outputs a low level 0 and controls the first register 20 to reset.

[0110] When the first stop condition detection unit detects the stop signal on the main I2C bus, that is, when the SCL line is detected to be at a high level and the SDA line changes from a low level to a high level, it outputs a high level 1. Then the first NOR gate performs a NOR operation based on the level signals of the four input terminals, namely a1 to a4, and since its second input terminal a2 is at a high level 1, it outputs a low level 0. Then the first AND gate performs an AND operation based on the level signals of the two input terminals, namely b1 and b2, and since its first input terminal b1 is at a low level 0 and the second input terminal b2 is at a high level 1, it outputs a low level 0 and controls the first register 20 to be reset.

[0111] When the second start condition detection unit detects the start signal on the auxiliary I2C bus, that is, when it detects that the SCL line is at a high level and the bidirectional serial data line changes from a high level to a low level, it outputs a high level 1. Then the first NOR gate performs an NOR operation based on the level signals of the four input terminals, a1 to a4, and since its third input terminal a3 is at a high level 1, it outputs a low level 0. Then the first AND gate performs an AND operation based on the level signals of the two input terminals, b1 and b2, and since its first input terminal b1 is at a low level 0 and the second input terminal b2 is at a high level 1, it outputs a low level 0 and controls the first register 20 to reset. At the same time, the second NOR gate performs an NOR operation based on the level signals of the two input terminals, c1 and c2, and since its first input terminal c1 is at a high level 1, it outputs a low level 0. Then the second AND gate performs an AND operation based on the level signals of the two input terminals, d1 and d2, and since its first input terminal d1 is at a low level 0 and the second input terminal d2 is at a high level 1, it outputs a low level 0 and controls the second register 30 to reset.

[0112] When the second stop condition detection unit detects the stop signal on the auxiliary I2C bus, that is, when it detects that the SCL line is at a high level and the bidirectional serial data line changes from a low level to a high level, it outputs a high level 1. Then the first NOR gate performs an NOR operation based on the level signals of the four input terminals, a1 to a4, and since its fourth input terminal a4 is at a high level 1, it outputs a low level 0. Then the first AND gate performs an AND operation based on the level signals of the two input terminals, b1 and b2, and since its first input terminal b1 is at a low level 0 and the second input terminal b2 is at a high level 1, it outputs a low level 0 and controls the first register 20 to reset. At the same time, the second NOR gate performs an NOR operation based on the level signals of the two input terminals, c1 and c2, and since its second input terminal c2 is at a high level 1, it outputs a low level 0. Then the second AND gate performs an AND operation based on the level signals of the two input terminals, d1 and d2, and since its first input terminal d1 is at a low level 0 and the second input terminal d2 is at a high level 1, it outputs a low level 0 and controls the second register 30 to reset.

[0113] Optionally, based on the above Figure 6 The I2C control circuit 10 shown in FIG. 1 is a schematic diagram of another I2C control circuit 10 provided in the embodiment of the present invention. Figure 8 .

[0114] The first detection module includes a first start condition detection unit and a first stop condition detection unit. The first start condition detection unit and the first stop condition detection unit are both electrically connected to the first reset module.

[0115] The second detection module includes a second start condition detection unit and a second stop condition detection unit. The second start condition detection unit is electrically connected to the first reset module and the second reset module, and the second stop condition detection unit is electrically connected to the first reset module and the second reset module. The second start condition detection unit and the second stop condition detection unit are both electrically connected to the multiplexer.

[0116] The first reset module includes a first NOR gate and a first AND gate. The first input terminal a1 of the first NOR gate is electrically connected to the first start condition detection unit, the second input terminal a2 of the first NOR gate is electrically connected to the first stop condition detection unit, the third input terminal a3 of the first NOR gate is electrically connected to the second start condition detection unit, the fourth input terminal a4 of the first NOR gate is electrically connected to the second stop condition detection unit, the output terminal a5 of the first NOR gate is electrically connected to the first input terminal b1 of the first AND gate, the second input terminal b2 of the first AND gate is used to receive a power-on reset signal, and the output terminal b3 of the first AND gate is electrically connected to the first register 20.

[0117] The second reset module includes a second NOR gate and a second AND gate. The first input terminal c1 of the second NOR gate is electrically connected to the second start condition detection unit, the second input terminal c2 of the second NOR gate is electrically connected to the second stop condition detection unit, the output terminal c3 of the second NOR gate is electrically connected to the first input terminal d1 of the second AND gate, the second input terminal d2 of the second AND gate is used to receive a power-on reset signal, and the output terminal d3 of the second AND gate is electrically connected to the second register 30.

[0118] In this embodiment, it is assumed that when the slave is in an order placing state, the power-on reset signal, por_rst_n, is at a low level, ie, 0; when the slave is in a power-on state, the power-on reset signal, por_rst_n, always maintains a high level 1.

[0119] When the host needs to communicate with the slave through the auxiliary I2C bus, it first communicates with the slave through the main I2C bus to set the control register to an enabled state. When the control register is in the enabled state, the multiplexer is controlled to connect the multiplexed IO data line to the second start condition detection unit and the second stop condition detection unit.

[0120] When the first start condition detection unit detects the start signal on the main I2C bus, that is, when the SCL line is detected to be at a high level and the SDA line changes from a high level to a low level, it outputs a high level 1. Then the first NOR gate performs a NOR operation based on the level signals of the four input terminals, namely a1 to a4, and since its first input terminal a1 is at a high level 1, it outputs a low level 0. Then the first AND gate performs an AND operation based on the level signals of the two input terminals, namely b1 and b2, and since its first input terminal b1 is at a low level 0 and the second input terminal b2 is at a high level 1, it outputs a low level 0 and controls the first register 20 to reset.

[0121] When the first stop condition detection unit detects the stop signal on the main I2C bus, that is, when the SCL line is detected to be at a high level and the SDA line changes from a low level to a high level, it outputs a high level 1. Then the first NOR gate performs a NOR operation based on the level signals of the four input terminals, namely a1 to a4, and since its second input terminal a2 is at a high level 1, it outputs a low level 0. Then the first AND gate performs an AND operation based on the level signals of the two input terminals, namely b1 and b2, and since its first input terminal b1 is at a low level 0 and the second input terminal b2 is at a high level 1, it outputs a low level 0 and controls the first register 20 to be reset.

[0122] When the second start condition detection unit detects the start signal on the auxiliary I2C bus, that is, when it detects that the SCL line is at a high level and the multiplexed IO data line changes from a high level to a low level, it outputs a high level 1. Then the first NOR gate performs an NOR operation based on the level signals of the four input terminals, a1 to a4, and since its third input terminal a3 is at a high level 1, it outputs a low level 0. Then the first AND gate performs an AND operation based on the level signals of the two input terminals, b1 and b2, and since its first input terminal b1 is at a low level 0 and the second input terminal b2 is at a high level 1, it outputs a low level 0 and controls the first register 20 to reset. At the same time, the second NOR gate performs an NOR operation based on the level signals of the two input terminals, c1 and c2, and since its first input terminal c1 is at a high level 1, it outputs a low level 0. Then the second AND gate performs an AND operation based on the level signals of the two input terminals, d1 and d2, and since its first input terminal d1 is at a low level 0 and the second input terminal d2 is at a high level 1, it outputs a low level 0 and controls the second register 30 to reset.

[0123] When the second stop condition detection unit detects the stop signal on the auxiliary I2C bus, that is, when it detects that the SCL line is at a high level and the multiplexed IO data line changes from a low level to a high level, it outputs a high level 1. Then the first NOR gate performs an NOR operation based on the level signals of the four input terminals, a1 to a4, and since its fourth input terminal a4 is at a high level 1, it outputs a low level 0. Then the first AND gate performs an AND operation based on the level signals of the two input terminals, b1 and b2, and since its first input terminal b1 is at a low level 0 and the second input terminal b2 is at a high level 1, it outputs a low level 0 and controls the first register 20 to reset. At the same time, the second NOR gate performs an NOR operation based on the level signals of the two input terminals, c1 and c2, and since its second input terminal c2 is at a high level 1, it outputs a low level 0. Then the second AND gate performs an AND operation based on the level signals of the two input terminals, d1 and d2, and since its first input terminal d1 is at a low level 0 and the second input terminal d2 is at a high level 1, it outputs a low level 0 and controls the second register 30 to reset.

[0124] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0125] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A communication system, characterized in that: The communication system comprises a host and at least one slave, wherein the slave is communicatively connected to the host via a main I2C bus and an auxiliary I2C bus, wherein the main I2C bus and the auxiliary I2C bus share a same clock line, and the slave comprises an I2C control circuit, a first register associated with the main I2C bus, and a second register associated with the auxiliary I2C bus; The host sends a start signal via the auxiliary I2C bus; When the slave detects a start signal on the auxiliary I2C bus through the I2C control circuit, the first register and the second register are reset; The host sends an operation instruction via the auxiliary I2C bus; The slave receives the operation instruction through the auxiliary I2C bus, and performs a corresponding operation according to the operation instruction; The host sends a stop signal via the auxiliary I2C bus; When the slave detects a stop signal on the auxiliary I2C bus through the I2C control circuit, the first register and the second register are reset.

2. The communication system according to claim 1, characterized in that In the case that only one slave in the communication system is connected to the host through the auxiliary I2C bus, the slave obtains the operation type and the data to be processed according to the operation instruction, and performs a corresponding operation based on the operation type and the data to be processed.

3. The communication system according to claim 1, characterized in that: In the case where there are multiple slaves in the communication system that are connected to the host through the auxiliary I2C bus, the slave obtains the device identification, operation type and data to be processed according to the operation instruction, and when the device identification represents itself, performs a corresponding operation based on the operation type and the data to be processed.

4. The communication system according to claim 1, characterized in that: In the case where the auxiliary I2C bus is composed of a shared clock line and a bidirectional serial data line, the I2C control circuit includes an electrically connected detection module and a reset module, and the reset module is electrically connected to the first register and the second register; The detection module is used for transmitting a first reset signal to the reset module when detecting a start signal or a stop signal on the main I2C bus; The reset module is used for resetting the first register when receiving the first reset signal; The detection module is further configured to transmit a second reset signal to the reset module when a start signal or a stop signal on the auxiliary I2C bus is detected; The reset module is further configured to reset the first register and the second register when receiving the second reset signal.

5. The communication system according to claim 1, characterized in that: In the case where the auxiliary I2C bus is composed of a shared clock line and a multiplexed IO data line, the I2C control circuit includes a control register, a multiplexer, a detection module and a reset module; the control register is electrically connected to the multiplexer, the multiplexer is electrically connected to the detection module, the detection module is electrically connected to the reset module, and the reset module is electrically connected to the first register and the second register; The control register is used to control the multiplexer to connect the multiplexed IO data line with the detection module in an enabled state; The detection module is used for transmitting a first reset signal to the reset module when detecting a start signal or a stop signal on the main I2C bus; The reset module is used for resetting the first register when receiving the first reset signal; The detection module is further configured to transmit a second reset signal to the reset module when a start signal or a stop signal on the auxiliary I2C bus is detected; The reset module is further configured to reset the first register and the second register when receiving the second reset signal.

6. The communication system according to claim 4 or 5, characterized in that: The detection module includes a first detection module and a second detection module, and the reset module includes a first reset module and a second reset module; the first detection module is electrically connected to the first reset module, the second detection module is electrically connected to the first reset module and the second reset module, the first reset module is electrically connected to the first register, and the second reset module is electrically connected to the second register; The first detection module is used for transmitting a first reset signal to the first reset module when detecting a start signal or a stop signal on the main I2C bus; The first reset module is used for resetting the first register when receiving the first reset signal; The second detection module is used for transmitting a second reset signal to the first reset module and the second reset module when detecting a start signal or a stop signal on the auxiliary I2C bus; The first reset module is further configured to reset the first register upon receiving the second reset signal; The second reset module is used for resetting the second register when receiving the second reset signal.

7. The communication system according to claim 6, characterized in that: The first detection module includes a first start condition detection unit and a first stop condition detection unit, and the first start condition detection unit and the first stop condition detection unit are both electrically connected to the first reset module; The first start condition detection unit is used for transmitting a first reset signal to the first reset module when detecting a start signal on the main I2C bus; The first stop condition detection unit is used to transmit a first reset signal to the first reset module when a stop signal on the main I2C bus is detected.

8. The communication system according to claim 7, characterized in that: The second detection module includes a second start condition detection unit and a second stop condition detection unit, the second start condition detection unit is electrically connected to the first reset module and the second reset module, and the second stop condition detection unit is electrically connected to the first reset module and the second reset module; The second start condition detection unit is used for transmitting a second reset signal to the first reset module and the second reset module when detecting a start signal on the auxiliary I2C bus; The second stop condition detection unit is used for transmitting a second reset signal to the first reset module and the second reset module when a stop signal on the auxiliary I2C bus is detected.

9. The communication system according to claim 8, characterized in that: The first reset module includes a first NOR gate and a first AND gate; the first input end of the first NOR gate is electrically connected to the first start condition detection unit, the second input end of the first NOR gate is electrically connected to the first stop condition detection unit, the third input end of the first NOR gate is electrically connected to the second start condition detection unit, the fourth input end of the first NOR gate is electrically connected to the second stop condition detection unit, the output end of the first NOR gate is electrically connected to the first input end of the first AND gate, the output end of the first AND gate is electrically connected to the first register, and the second input end of the first AND gate is used to receive a power-on reset signal.

10. The communication system according to claim 9, characterized in that: The second reset module includes a second NOR gate and a second AND gate; the first input end of the second NOR gate is electrically connected to the second start condition detection unit, the second input end of the second NOR gate is electrically connected to the second stop condition detection unit, the output end of the second NOR gate is electrically connected to the first input end of the second AND gate, the output end of the second AND gate is electrically connected to the second register, and the second input end of the second AND gate is used to receive a power-on reset signal.

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