PCIe retimer, PCIe system and electronic equipment

Abstract

According to the PCIe retimer, the PCIe system and the electronic equipment, a decoding and descrambling module carries out decoding and descrambling processing on output code streams of upstream equipment and outputs the code streams backwards, and when a low-delay triggering condition is met, a control module modifies second-class code streams in the decoding and descrambling code streams into first-class code streams and outputs the first-class code streams backwards; the de-skew module performs de-skew processing on the received code stream and outputs the code stream backwards; the coding and scrambling module carries out coding and scrambling processing on the received code stream and backwards outputs the code stream subjected to coding and scrambling processing; and the control module controls the low-delay access to serve as the current working access after determining that the low-delay access is aligned with the main access. According to the embodiment of the invention, the state machine of the downstream device does not perform state hopping due to receiving the preset number of second type code streams, so that the state jump time of the upstream device and the downstream device can be dragged, the purpose of dragging the state machine is achieved, and the PCIe retimer has more time to perform path switching without error codes.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a PCIe retimer, a PCIe system and an electronic device. Background Art

[0002] After PCIe4.0, the retimer specification was proposed, which can solve the signal integrity and transmission distance problems in the link. The retimer can also ensure that data will not be erroneous during high-speed transmission, and the retimer can participate in the management of PCIe links and other functions.

[0003] Although adding a retimer to the PCIe system brings the above advantages, it also has some disadvantages: for example, the retimer will increase the system latency during the process of signal retiming, data scrambling and descrambling, data encoding and decoding, and equalization. In some specific scenarios, the link needs to be switched to a low-latency path. How to ensure the smooth completion of the switching process has become a difficult problem that technicians in this field are concerned about. Summary of the invention

[0004] The object of the present invention is to provide a PCIe retimer, a PCIe system and an electronic device to improve the above problems.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows: In a first aspect, an embodiment of the present invention provides a PCIe retimer, the PCIe retimer comprising: a de-skew module, a control module, a decoding and descrambling module, a coding and scrambling module, and a low-latency path; The input end of the decoding and descrambling module and the input end of the low-latency path are used to connect to the output end of the upstream device, the output end of the decoding and descrambling module, the input end of the de-skew module and the low-latency path control end are connected to the control module, the output end of the de-skew module is connected to the coding and scrambling module, and the output end of the coding and scrambling module and the output end of the low-latency path are used to connect to the downstream device; The decoding and descrambling module is used to decode and descramble the output code stream of the upstream device, and output the decoded and descrambled code stream to the control module; The control module is used to determine whether the low-latency trigger condition is met according to the decoded and descrambled code stream, and if so, modify the second type of code stream in the decoded and descrambled code stream to the first type of code stream, and transmit the modified code stream to the de-skew module, wherein the second type of code stream is a trigger code stream for the downstream device to perform a state jump; The de-skew module is used to perform de-skew processing on the received code stream and transmit the de-skewed code stream to the coding and scrambling module; The coding and scrambling module is used to perform coding and scrambling processing on the received code stream, and transmit the coded and scrambled code stream to the downstream device; The control module is further configured to control the low-latency path as a current working path after determining that the low-latency path is aligned with a main path, wherein the main path is a path passing through a de-skew module.

[0006] The PCIe retimer can modify the second type of code stream in the decoded and descrambled code stream to the first type of code stream. The state machine of the downstream device will not change state due to receiving a preset number of second type code streams, thereby delaying the time for the state machine of the upstream device and the state machine of the downstream device to jump from the receiving end configuration recovery state to the idle state (Recovery.Idle), thereby achieving the purpose of delaying the state machine, so that the PCIe retimer has more time to switch the channel without bit errors.

[0007] Optionally, the control module includes a main control unit and a path switching module, the output end of the decoding and descrambling module and the input end of the de-skew module are connected to the main control unit, the low-latency path control end is connected to the path switching module, and the path switching module is connected to the main control unit; The main control unit is used to determine that the low latency trigger condition is met when the downstream device and the upstream device are both in a receiving end configuration recovery state, the rate of the output code stream of the upstream device is greater than a preset rate threshold, and a code stream that meets the second type of code stream judgment condition is received; The second type of code stream judgment condition includes that the target symbol corresponding to the code stream matches its corresponding target content; The main control unit is used for modifying the second type of code stream in the decoded descrambled code stream into the first type of code stream when the low latency trigger condition is met, and transmitting the modified code stream to the de-skew module; The path switching module is used to control the low-latency path as the current working path after determining that the low-latency path is aligned with the main path, and send a stop modification instruction to the main control unit so that the main control unit stops modifying the decoded descrambled code stream.

[0008] Through the above-mentioned second type of code stream judgment conditions, it is possible to accurately identify whether the low-latency trigger conditions are met, so that the decoding and descrambling code stream can be modified in real time to achieve the purpose of holding up the state machine, so that the PCIe retimer has more time to switch channels without bit errors.

[0009] Optionally, the main control unit is further configured to determine that an abnormal signal is received when the abnormal monitoring symbol corresponding to the received code stream does not match the target content corresponding to it; The main control unit is further used to send an exit instruction to the path switching module when receiving an abnormal signal, so that the path switching module stops determining whether the low-latency path is aligned with the main path; The main control unit is further configured to stop modifying the decoded and descrambled code stream when receiving an abnormal signal, or to keep modifying the decoded and descrambled code stream and stop modifying the decoded and descrambled code stream after a preset time length.

[0010] The main control unit is further configured to determine that an abnormal signal is received when monitoring that the rate of the output code stream of the upstream device is less than a preset rate threshold; The main control unit is further configured to determine that an abnormal signal is received when monitoring that the state machine of the upstream device or the state machine of the downstream device meets a state transition condition; The state transition condition is a condition that the state machine jumps from the recovery state to the abnormal state by the receiving end configuration, or the state transition condition is a condition that the state machine jumps from the idle state to the loopback state, the disabled state or the hot reset state.

[0011] By monitoring abnormal conditions of equipment operation and exiting low-latency mode upon receiving abnormal signals, downtime can be avoided.

[0012] Optionally, the decoding and descrambling module is used to provide a storage start signal to the main control unit when detecting the terminal characteristics of the decoded and descrambled code stream; The decoding and descrambling module is used to provide a high-level valid flag signal to the main control unit when detecting that the decoded and descrambled code stream is valid data; The main control unit is used to determine whether the category identifier of the received code stream matches the corresponding target content after receiving the storage start signal and when the valid flag signal is in a high level state, and if so, determine that the current code stream is the first category code stream and store the current code stream; The main control unit is used to replace the second type of code stream in the decoding and descrambling code stream with the latest stored first type of code stream, so as to complete the modification of the decoding and descrambling code stream.

[0013] The problem of garbled codes is avoided by replacing the second type of code stream in the decoded descrambled code stream with the latest stored first type of code stream.

[0014] Optionally, the path switching module is used to monitor the output code stream of the de-skew module in the main path, and when the number of electrical idle exit sequences (EIE) output by the de-skew module is greater than a monitoring threshold, determine that the low-latency path is aligned with the main path.

[0015] By accurately judging whether the low-latency path 15 is aligned with the main path, the timeliness of link switching is guaranteed.

[0016] In a second aspect, an embodiment of the present invention provides a PCIe system, the PCIe system comprising an upstream device, a downstream device and the above-mentioned PCIe retimer.

[0017] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the above-mentioned PCIe system.

[0018] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of the structure of a PCIe retimer provided in an embodiment of the present invention.

[0021] Figure 2 A schematic diagram of the structure of a control module provided in an embodiment of the present invention.

[0022] Figure 3 A signal timing diagram provided for an embodiment of the present invention.

[0023] In the figure: 11-decoding and descrambling module; 12-control module; 13-deskewing module; 14-coding and scrambling module; 15-low-latency path; 20-upstream device; 30-downstream device; 121-main control unit; 122-path switching module. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0027] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus.

[0028] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0029] The embodiment of the present invention provides a PCIe retimer, which can control the state machine of the upstream device and the state machine of the downstream device to enter the hovering state, and can delay the time for the state machine of the upstream device and the state machine of the downstream device to jump from the receiving end configuration recovery state to the idle state (Recovery.Idle). The PCIe retimer can modify the second type of code stream (TS2 code stream) in the decoded descrambled code stream to the first type of code stream (TS1 code stream), so as to avoid the state jump of the downstream device when receiving 8 second type code streams (TS2 code streams), thereby achieving the purpose of delaying the state machine. This allows the PCIe retimer to have more time to switch the channel without bit errors.

[0030] It should be noted that when the upstream device of the PCIe retimer is the root complex (RC), the downstream device of the PCIe retimer is the end point device (EP); when the upstream device of the PCIe retimer is the end point device, the downstream device of the PCIe retimer is the root complex.

[0031] For the specific structure of the PCIe retimer, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 1 , Figure 1A schematic diagram of the structure of a PCIe retimer provided in an embodiment of the present invention.

[0032] The PCIe retimer includes: a de-skew module 13 , a control module 12 , a decoding and descrambling module 11 , an encoding and scrambling module 14 and a low-latency path 15 .

[0033] The input end of the decoding and descrambling module 11 and the input end of the low-latency path 15 are used to connect to the output end of the upstream device 20, the output end of the decoding and descrambling module 11, the input end of the de-skew module 13 and the control end of the low-latency path 15 are connected to the control module 12, the output end of the de-skew module 13 is connected to the coding and scrambling module 14, and the output end of the coding and scrambling module 14 and the output end of the low-latency path 15 are used to connect to the downstream device 30.

[0034] The decoding and descrambling module 11 is used to perform decoding and descrambling processing on the output code stream of the upstream device 20 , and output the decoded and descrambled code stream to the control module 12 .

[0035] The control module 12 is used to determine whether the low-latency trigger condition is met based on the decoded and descrambled code stream. If so, the second type of code stream (TS2 code stream) in the decoded and descrambled code stream is modified to the first type of code stream (TS1 code stream), and the modified code stream is transmitted to the de-skew module 13. The second type of code stream is the trigger code stream for the state jump of the downstream device 30.

[0036] When the downstream device 30 receives a preset number of second-type code streams, it will jump from the current state corresponding to the low-latency trigger condition (receiving end configuration recovery state) to the next state, which is the idle state (Recovery.Idle).

[0037] The de-skew module 13 is used to perform de-skew processing on the received code stream and transmit the de-skewed code stream to the coding and scrambling module 14 .

[0038] The coding and scrambling module 14 is used to perform coding and scrambling processing on the received code stream, and transmit the coded and scrambled code stream to the downstream device 30.

[0039] The control module 12 is further configured to control the low-latency path 15 to serve as the current working path after determining that the low-latency path 15 is aligned with the main path, wherein the main path is the path passing through the de-skew module 13 .

[0040] Optionally, the main path passes through the decoding and descrambling module 11, the control module 12, the de-skew module 13 and the coding and scrambling module 14. It should be noted that the low-latency path 15 does not need to be decoded and descrambled, de-skewed and scrambled, and the delay of the low-latency path 15 is lower than the delay of the main path. The low-latency path 15 can be a direct link.

[0041] The PCIe retimer provided in the embodiment of the present invention can modify the second type of code stream (TS2 code stream) in the decoded descrambled code stream to the first type of code stream (TS1 code stream), and the state machine of the downstream device will not change state due to receiving a preset number of second type code streams, thereby delaying the time for the state machine of the upstream device and the state machine of the downstream device to jump from the receiving end configuration recovery state to the idle state (Recovery.Idle), thereby achieving the purpose of delaying the state machine, so that the PCIe retimer has more time to switch the channel without bit errors.

[0042] Optionally, after the low-latency path 15 is aligned with the main path, the control module 12 stops modifying the decoded descrambled code stream.

[0043] exist Figure 1 Based on the specific structure of the control module, the present invention also provides an optional implementation method, please refer to Figure 2 , Figure 2 A schematic diagram of the structure of a control module provided in an embodiment of the present invention.

[0044] The control module 12 includes a main control unit 121 and a path switching module 122. The output end of the decoding and descrambling module 11 and the input end of the de-skew module 13 are connected to the main control unit 121. The control end of the low-latency path 15 is connected to the path switching module 122. The path switching module 122 is connected to the main control unit 121.

[0045] The main control unit 121 is used to determine that the low latency trigger condition is met when both the downstream device 30 and the upstream device 20 are in the receiving end configuration recovery state (also called Recovery.RcvrCfg), the rate of the output code stream of the upstream device 20 is greater than a preset rate threshold, and a code stream that meets the second type of code stream judgment condition is received.

[0046] The second type of code stream judgment condition includes that the target symbol corresponding to the code stream matches the target content corresponding to the code stream.

[0047] Optionally, the code stream includes 16 symbols, and the target symbols can be symbol0, the speed_change field of symbol4, symbol7, and the hot-reset / disable field in symbol5. The target content corresponding to symbol0 is 8'h2d, the target content corresponding to the speed_change field of symbol4 is 0: the speed_change field is 0, the target content corresponding to Symbol7 is 8'h45, and the target content corresponding to the hot-reset / disable field is 0.

[0048] Optionally, the rate threshold may be configured through a register module (not shown in the figure). By adjusting the rate threshold, it is possible to support entering a low latency mode at different output code stream rates.

[0049] After the PCIe retimer is powered on, when the rate of the output bitstream of the upstream device 20 is less than or equal to the preset rate threshold, because the low latency trigger condition is not met, the main control unit 121 will be in an idle state (L1_Idle), and will not perform any processing on the received bitstream, and will directly forward the bitstream to the back-end de-skew module 13.

[0050] In an optional implementation, the rates of the output code stream of the upstream device 20 may be gen1, gen2, gen3, gen4 and gen5, where gen1, gen2, gen3, gen4 and gen5 increase in sequence. The rate threshold may be, but is not limited to, set to gen2.

[0051] The main control unit 121 is used to modify the second type of code stream (TS2 code stream) in the decoded descrambled code stream into the first type of code stream (TS1 code stream) when the low latency trigger condition is met, and transmit the modified code stream to the de-skew module 13.

[0052] It should be noted that the PCIe retimer may have multiple main paths, one main path corresponds to one data path, and the direction of the data path may be different. Each data path corresponds to an independent modified bitstream. In addition, when modifying the decoding and descrambling bitstream of a main path, only the second type of bitstream (TS2 bitstream) is modified, and other bitstreams (such as SKP bitstream, EIEOS bitstream, and EIOS bitstream, etc.) are not modified. Modifying the bitstream can be seamless, and any bit in any bitstream and any symbol data (symbol data) cannot be destroyed.

[0053] The path switching module 122 is used to control the low-latency path 15 as the current working path after determining that the low-latency path 15 is aligned with the main path, and send a stop modification instruction to the main control unit 121 to make the main control unit 121 stop modifying the decoded descrambled code stream.

[0054] Through the above-mentioned second type of code stream judgment conditions, it is possible to accurately identify whether the low-latency trigger conditions are met, so that the decoding and descrambling code stream can be modified in real time to achieve the purpose of holding up the state machine, so that the PCIe retimer has more time to switch channels without bit errors.

[0055] exist Figure 2 On this basis, regarding how to deal with abnormal conditions in the operation of the device to avoid downtime, the embodiment of the present invention also provides an optional implementation method, please refer to the following.

[0056] The main control unit 121 is further configured to determine that an abnormal signal is received when the abnormal monitoring symbol corresponding to the received code stream does not match the corresponding target content.

[0057] Optionally, the abnormal monitoring symbol may be the speed_change field of symbol4 and symbol7, and the target content corresponding to the speed_change field of symbol4 is 0: the speed_change field is 0, and the target content corresponding to Symbol7 is 8'h45.

[0058] When the target content corresponding to the speed_change field of symbol4 is 1, it means that the PCIe system may need to cut speed, so it is necessary to exit the low-latency mode; when the target content corresponding to Symbol7 is not 8'h45, it means that the PCIe system may re-equalize (EQ), so it is necessary to exit the low-latency mode.

[0059] The main control unit 121 is further configured to send an exit instruction to the path switching module 122 when receiving an abnormal signal, so that the path switching module 122 stops determining whether the low-latency path 15 is aligned with the main path.

[0060] The main control unit 121 is also used to stop modifying the decoding and descrambling code stream when receiving an abnormal signal, or to keep modifying the decoding and descrambling code stream and stop modifying the decoding and descrambling code stream after a preset time length. It is flexible to wait for the two end devices to time out and enter the abnormal state (Exit to Detect), so that the rate mismatch caused by the abnormality of the entire system will not occur, resulting in the inability to re-establish the link.

[0061] The main control unit 121 is further configured to determine that an abnormal signal is received when it is detected that the rate of the output code stream of the upstream device 20 is less than a preset rate threshold.

[0062] The main control unit 121 is further configured to determine that an abnormal signal is received when it is detected that the state machine of the upstream device 20 or the state machine of the downstream device 30 meets a state transition condition.

[0063] The state transition condition is the condition that the state machine jumps from the receiving end configuration recovery state to the abnormal state (Exit to Detect), indicating that the current PCIe system needs to restart the link establishment, or the state transition condition is the state machine jumps from the idle state (Recovery.Idle) to the loopback state (Exit to Loopback), the disabled state (Exit to Disable) or the hot reset state (Exit to Hot Reset), indicating that the current PCIe system needs to enter some test modes, and therefore also needs to exit the low latency mode.

[0064] In an optional implementation, when the low latency trigger condition is met, the main control unit 121 may pull up the datapath_modify_enh signal, so that the main control unit 121 jumps to the L1_NORMAL_MODIF state, indicating that the low latency mode is entered, and the decoding and descrambling code stream is modified, that is, the second type of code stream (TS2 code stream) in the decoding and descrambling code stream is modified to the first type of code stream (TS1 code stream).

[0065] After the main control unit 121 jumps to the L1_NORMAL_MODIF state, the main control unit 121 starts to monitor whether an abnormal signal is received. If the main control unit 121 receives an abnormal signal, the main control unit 121 jumps to the NO_L2_STOP_MODIF state. At this time, the main control unit 121 continues to modify the decoded and descrambled code streams. After a preset time length, the main control unit 121 stops modifying the decoded and descrambled code streams, and the main control unit 121 jumps to the exit state (L1_EXIT), indicating exiting the low latency mode.

[0066] In an optional embodiment, after determining that the low-latency path 15 is aligned with the main path, the path switching module 122 sends a stop modification instruction to the main control unit 121 as a continuous high-level signal. When the main control unit 121 detects the rising edge of the stop modification instruction pair, the main control unit 121 jumps to the L2_STOP_MODIF state, at which time the decoding and descrambling code stream is stopped from being modified, but the main control unit 121 will still monitor the abnormal signal. If the main control unit 121 receives an abnormal signal before the main control unit 121 detects the falling edge of the stop modification instruction pair, the main control unit 121 jumps to the L2_UNOR_MODIF state, re-modifies the decoding and descrambling code stream, and stops modifying the decoding and descrambling code stream after a preset time length, and the main control unit 121 jumps to the exit state (L1_EXIT).

[0067] When the main control unit 121 is in the exit state (L1_EXIT), if the downstream device 30 and the upstream device 20 are both in the receiving end configuration recovery state, and the rate of the output code stream of the upstream device 20 is greater than the preset rate threshold, and when a code stream that meets the second type of code stream judgment condition is received, it is determined that the low latency trigger condition is met, and the main control unit 121 jumps to the L1_NORMAL_MODIF state again.

[0068] In an optional implementation, the preset time length may be configured via a register module.

[0069] On the basis of the foregoing, regarding how to modify the decoding and descrambling code stream, the embodiment of the present invention further provides an optional implementation method to replace the second type of code stream (TS2 code stream) in the decoding and descrambling code stream with the latest stored first type of code stream (TS1 code stream), thereby avoiding the problem of garbled code. Please refer to the following for details.

[0070] The decoding and descrambling module 11 is used to provide a storage start signal (k_start_block) to the main control unit 121 when detecting the terminal feature of the decoded and descrambled code stream.

[0071] The decoding and descrambling module 11 is used to provide a high-level valid flag signal (k_valid) to the main control unit 121 when detecting that the decoded and descrambled code stream is valid data.

[0072] The main control unit 121 is used to determine whether the category identifier of the received code stream matches its corresponding target content after receiving the storage start signal and the valid flag signal is in a high level state. If it matches, it determines that the current code stream is the first type of code stream (TS1 code stream) and stores the current code stream.

[0073] The category identifier symbol may be symbol0, and the target content corresponding to symbol0 is 8'h1e. When the two match, it indicates that the identified code stream is the first category code stream (TS1 code stream).

[0074] In an optional implementation, the main control unit 121 stores the current code stream only when the rate of the output code stream of the upstream device 20 is greater than a preset rate threshold.

[0075] The main control unit 121 is used to replace the second type of code stream (TS2 code stream) in the decoding and descrambling code stream with the latest stored first type of code stream (TS1 code stream) to complete the modification of the decoding and descrambling code stream.

[0076] Please refer to Figure 3 , Figure 3A signal timing diagram provided for an embodiment of the present invention. Since the PIPE interface of the PCIe retimer uses 4 symbols for transmission, four beats (cycles) are required to store a complete first-class code stream (TS1 code stream). When the rate (gen3 / 4 / 5) of the output code stream of the upstream device 20 is greater than the preset rate threshold, the upstream device 20 adopts the 128b / 130b encoding method. Therefore, during normal data transmission, the synchronization header (syncheader) will be compensated. Therefore, the main control unit 121 will only store the current code stream when the valid flag signal (k_valid) is pulled high. The storage starts when the storage start signal (k_start_block) is pulled high, the valid flag signal (k_valid) is at a high level, and the category identifier symbol matches the corresponding target content. That is, the first-class code stream in the T period in the figure is stored.

[0077] On the basis of the foregoing, regarding how to accurately determine whether the low-latency path 15 is aligned with the main path, so as to ensure the timeliness of link switching, the embodiment of the present invention also provides an optional implementation method, please refer to the following.

[0078] The path switching module 122 is used to monitor the output code stream of the de-skew module 13 in the main path, and when the number of electrical idle exit sequences (EIE) output by the de-skew module 13 is greater than the monitoring threshold, determine that the low latency path 15 is aligned with the main path.

[0079] Regarding how to further monitor the operating status of the PCIe system to ensure the accuracy of system operation and the operating effect, the embodiment of the present invention also provides an optional implementation method, please refer to the following.

[0080] The main control unit 121 is further used to count the number of times the main path enters or exits the low-latency mode, where the number of times includes the number of times the main path enters the low-latency mode and the number of times the main path exits the low-latency mode.

[0081] The main control unit 121 is also used to compare the frequency data of the main channel with the frequency data of the opposite channel corresponding to the main channel to determine whether there is any abnormality in the operation.

[0082] Optionally, the upstream device of the main passage is the downstream device of the opposite passage, and the downstream device of the main passage is the upstream device of the opposite passage.

[0083] In an optional implementation, a low-latency enable signal can be configured through a register module. When the low-latency enable signal is not configured, the control module 12 only forwards the received code stream and does not need to perform other processing. When the low-latency enable signal is configured, the control module 12 performs the above functions.

[0084] An embodiment of the present invention further provides a PCIe system, which includes an upstream device, a downstream device and the above-mentioned PCIe retimer.

[0085] An embodiment of the present invention further provides an electronic device, which includes the above-mentioned PCIe system.

[0086] In summary, the embodiments of the present invention provide a PCIe retimer, a PCIe system and an electronic device, wherein the decoding and descrambling module decodes and descrambles the output code stream of the upstream device, and outputs the decoded and descrambled code stream to the control module. When the low-latency trigger condition is met, the control module modifies the second type of code stream (TS2 code stream) in the decoded and descrambled code stream into the first type of code stream (TS1 code stream), and transmits the modified code stream to the de-skew module. The de-skew module de-skews the received code stream and transmits the de-skewed code stream to the coding and scrambling module; the coding and scrambling module performs coding and scrambling on the received code stream and transmits the scrambled code stream to the downstream device; after determining that the low-latency path is aligned with the main path, the control module controls the low-latency path as the current working path. The state machine of the downstream device will not change state due to receiving a preset number of second-type code streams, thereby delaying the state jump time of the upstream and downstream devices, achieving the purpose of delaying the state machine, so that the PCIe retimer has more time to switch paths without bit errors.

[0087] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0088] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A PCIe retimer, characterized in that: The PCIe retimer includes: a de-skew module, a control module, a decoding and descrambling module, a coding and scrambling module, and a low-latency path; The input end of the decoding and descrambling module and the input end of the low-latency path are used to connect to the output end of the upstream device, the output end of the decoding and descrambling module, the input end of the de-skew module and the low-latency path control end are connected to the control module, the output end of the de-skew module is connected to the coding and scrambling module, and the output end of the coding and scrambling module and the output end of the low-latency path are used to connect to the downstream device; The decoding and descrambling module is used to decode and descramble the output code stream of the upstream device, and output the decoded and descrambled code stream to the control module; The control module is used to determine whether the low-latency trigger condition is met according to the decoded and descrambled code stream, and if so, modify the second type of code stream in the decoded and descrambled code stream to the first type of code stream, and transmit the modified code stream to the de-skew module, wherein the second type of code stream is a trigger code stream for the downstream device to perform a state jump; The de-skew module is used to perform de-skew processing on the received code stream and transmit the de-skewed code stream to the coding and scrambling module; The coding and scrambling module is used to perform coding and scrambling processing on the received code stream, and transmit the coded and scrambled code stream to the downstream device; The control module is further configured to control the low-latency path as a current working path after determining that the low-latency path is aligned with a main path, wherein the main path is a path passing through a de-skew module.

2. The PCIe retimer of claim 1, wherein: After the low-latency path is aligned with the main path, the control module stops modifying the decoded descrambled code stream.

3. The PCIe retimer of claim 1, wherein: The control module includes a main control unit and a path switching module, the output end of the decoding and descrambling module and the input end of the de-skew module are connected to the main control unit, the low-latency path control end is connected to the path switching module, and the path switching module is connected to the main control unit; The main control unit is used to determine that the low latency trigger condition is met when the downstream device and the upstream device are both in a receiving end configuration recovery state, the rate of the output code stream of the upstream device is greater than a preset rate threshold, and a code stream that meets the second type of code stream judgment condition is received; The second type of code stream judgment condition includes that the target symbol corresponding to the code stream matches its corresponding target content; The main control unit is used for modifying the second type of code stream in the decoded descrambled code stream into the first type of code stream when the low latency trigger condition is met, and transmitting the modified code stream to the de-skew module; The path switching module is used to control the low-latency path as the current working path after determining that the low-latency path is aligned with the main path, and send a stop modification instruction to the main control unit so that the main control unit stops modifying the decoded descrambled code stream.

4. The PCIe retimer of claim 3, wherein: The main control unit is also used to determine that an abnormal signal is received when the abnormal monitoring symbol corresponding to the received code stream does not match the target content corresponding to it; The main control unit is further used to send an exit instruction to the path switching module when receiving an abnormal signal, so that the path switching module stops determining whether the low-latency path is aligned with the main path; The main control unit is further configured to stop modifying the decoded and descrambled code stream when receiving an abnormal signal, or to keep modifying the decoded and descrambled code stream and stop modifying the decoded and descrambled code stream after a preset time length.

5. The PCIe retimer of claim 4, wherein: The main control unit is further configured to determine that an abnormal signal is received when monitoring that the rate of the output code stream of the upstream device is less than a preset rate threshold; The main control unit is further configured to determine that an abnormal signal is received when monitoring that the state machine of the upstream device or the state machine of the downstream device meets a state transition condition; The state transition condition is a condition that the state machine jumps from the recovery state to the abnormal state by the receiving end configuration, or the state transition condition is a condition that the state machine jumps from the idle state to the loopback state, the disabled state or the hot reset state.

6. The PCIe retimer of claim 3, wherein: The decoding and descrambling module is used to provide a storage start signal to the main control unit when detecting the terminal characteristics of the decoding and descrambling code stream; The decoding and descrambling module is used to provide a high-level valid flag signal to the main control unit when detecting that the decoded and descrambled code stream is valid data; The main control unit is used to determine whether the category identifier of the received code stream matches the corresponding target content after receiving the storage start signal and when the valid flag signal is in a high level state, and if so, determine that the current code stream is the first category code stream and store the current code stream; The main control unit is used to replace the second type of code stream in the decoding and descrambling code stream with the latest stored first type of code stream, so as to complete the modification of the decoding and descrambling code stream.

7. The PCIe retimer of claim 3, wherein: The path switching module is used to monitor the output code stream of the de-skew module in the main path, and determine that the low-latency path is aligned with the main path when the number of electrical idle exit sequences output by the de-skew module is greater than a monitoring threshold.

8. The PCIe retimer of claim 3, wherein: The main control unit is further used to count the number of times the main path enters or exits the low-latency mode, wherein the number of times includes the number of times the main path enters the low-latency mode and the number of times the main path exits the low-latency mode; The main control unit is also used to compare the frequency data of the main channel with the frequency data of the opposite channel corresponding to the main channel to determine whether there is any abnormality in the operation.

9. A PCIe system, characterized in that: The PCIe system includes an upstream device, a downstream device, and the PCIe retimer according to any one of claims 1 to 8.

10. An electronic device, characterized in that: Includes the PCIe system as described in claim 9.

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