A reliable loading method for DSP and FPGA in a distributed heterogeneous system

Abstract

This invention discloses a reliable loading method for DSP and FPGA in a distributed heterogeneous system, relating to the field of industrial control technology. The method includes an MSU module, FPGA, DSP, and related buses and storage units. The key feature is that the MSU module is connected to the FPGA via a SelectMAP bus or to the DSP via an EMIF bus. This reliable loading method for DSP and FPGA in a distributed heterogeneous system adds an MSU module to the FPGA+DSP scheme, breaking the limitation of device-bound algorithm components. The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network control port. Then, the algorithm components are remotely loaded to the FPGA or DSP via the FPGA SelectMAP bus or the DSP EMIF bus, realizing dynamic remote loading of algorithm components. In this way, this invention overcomes the limitation of device-bound algorithm components, thereby reducing equipment maintenance costs, improving equipment reliability and stability, and simplifying the complexity of system design.

Description

Technical Field

[0001] This invention relates to the field of industrial control technology, specifically to a reliable loading method for DSP and FPGA in a distributed heterogeneous system. Background Technology

[0002] In aerospace, industrial control, radar, and other fields, the combination design of Field Programmable Gate Array (FPGA) + Digital Signal Processor (DSP) has been widely used due to its advantages in signal processing. For example, in radar signal processing, FPGA can perform high-speed data acquisition and preprocessing, while DSP is used for complex algorithm calculations.

[0003] Based on the requirements of industrial radio control scenarios, it is necessary to load and unload algorithm components running on FPGAs and DSPs. However, current equipment has many limitations in this regard. Taking updating algorithm components via the JTAG interface as an example, updating one algorithm component takes several minutes on average, and only one algorithm component can run on a single device. When there are multiple devices in the system, this update method is not only time-consuming and labor-intensive, but also cannot meet the requirements for rapid switching and loading of algorithm components with different frequency bands and modulation methods. This leads to a lack of reliability in device updates, which is detrimental to equipment maintenance and management. Therefore, a reliable loading method for DSPs and FPGAs in a distributed heterogeneous system is proposed to solve the above problems. Summary of the Invention

[0004] This invention provides a reliable loading method for DSPs and FPGAs in a distributed heterogeneous system to solve the problems in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a reliable loading method for DSP and FPGA in a distributed heterogeneous system, comprising an MSU module, an FPGA, a DSP, related buses, and storage units, characterized in that: the MSU module is connected to the FPGA via a SelectMAP bus or to the DSP via an EMIF bus, comprising the following steps:

[0006] The S1 and MSU modules select the remote loading mode of the SelectMAP bus via the chip select signal; the generation of the chip select signal is based on the loading of the IP core that calls the internal program, ensuring accurate selection of the loading mode;

[0007] S2. Since the MSU module data bus is a multiplexed pin, the program control of the SelectMAP or EMIF signal must utilize the CPLD's internal BYPASS logic. The CPLD internally selects and implements the selectMAP signal link between the FPGA and the MSU module by detecting the high and low levels of the bus chip select GPIO signal pin.

[0008] The S3 and MSU module control programs read the algorithm components from the eMMC and write them into the DDR. The algorithm components transmit data from the PS side to the PL side via the AXI-GP protocol. After receiving the GP protocol data, the PL side remotely loads the FPGA according to the selectMAP timing sequence.

[0009] Furthermore, the MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network control port for storing the algorithm components. The MSU module can realize remote loading of the FPGA.

[0010] Furthermore, the MSU module enables remote loading of the DSP, or the specific steps are as follows:

[0011] The S1 and MSU modules select the remote loading mode of the SelectMAP bus via the chip select signal; the generation of the chip select signal is based on the loading of the IP core that calls the internal program, ensuring accurate selection of the loading mode;

[0012] S2. Because the MSU module data bus is a multiplexed pin, the program control of the SelectMAP or EMIF signal must utilize the CPLD's internal BYPASS logic. The CPLD internally selects and implements the selectMAP signal link between the FPGA and the MSU module by detecting the high and low levels of the bus chip select GPIO signal pin.

[0013] S3: The MSU module control program reads the algorithm component from the eMMC and writes it into the DDR; the algorithm component transmits data from the PS side to the PL side through the AXI-GP protocol. After receiving the GP protocol data, the PL side remotely loads the DSP according to the EMIF timing sequence.

[0014] Furthermore, the eMMC storage unit is an embedded storage structure, comprising an MMC packaging interface and a main controller containing a control chip.

[0015] Furthermore, during DDSP loading operations, the convolution formula used for filtering and denoising in signal processing is as follows:

[0016]

[0017] in: It is the input signal; It is the impulse response of the filter; through calculation, the output signal can be obtained. .

[0018] Furthermore, the update process of the MSU module includes reading algorithm components from the eMMC storage unit and loading them onto the FPGA or DSP via a relevant bus.

[0019] Furthermore, the hardware implementation process of the MSU module for remote loading of the FPGA includes chip select signal selection, logic switching, data reading and writing, and loading according to timing sequence.

[0020] Furthermore, the hardware implementation process of the MSU module for remote loading of the DSP includes chip select signal selection, logic switching, data reading and writing, and loading according to timing sequence.

[0021] Furthermore, it also includes a loading failure handling module. If the first remote loading fails, the FPGA or DSP can be remotely reset via the MSU module before remote loading can be performed again. The reset pins on the FPGA and DSP chips are connected to the MSU module. The MSU module can use the network window control program to call the underlying driver to pull low and release the FPGA and DSP reset function, thereby achieving remote reset.

[0022] Furthermore, the eMMC storage unit stores at least two algorithm components, and the stored algorithm components are remotely loaded onto the FPGA or DSP via the FPGASelectMAP bus or DSPEMIF bus.

[0023] Compared with existing technologies, this invention provides a reliable loading method for DSPs and FPGAs in a distributed heterogeneous system, which has the following advantages:

[0024] This method for reliable loading of DSP and FPGA in a distributed heterogeneous system adds an MSU module to the FPGA+DSP scheme, breaking the limitation of device-bound algorithm components. The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network port, and then remotely loads the algorithm components to the FPGA or DSP via the FPGASelectMAP bus or DSPEMIF bus, realizing dynamic remote loading of algorithm components. In this way, the present invention breaks through the limitation of device-bound algorithm components, thereby reducing equipment maintenance costs, improving equipment reliability and stability, and simplifying the complexity of system design. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a block diagram of the module support unit design for a reliable loading method for DSP and FPGA in a distributed heterogeneous system according to the present invention.

[0027] Figure 2 This is a schematic diagram of the MSU module update process for a reliable loading method for DSP and FPGA in a distributed heterogeneous system according to the present invention.

[0028] Figure 3 This is a flowchart of the hardware implementation of remote loading of FPGA by the MSU module in a distributed heterogeneous system according to the present invention, which is a reliable loading method for DSP and FPGA in a distributed heterogeneous system.

[0029] Figure 4 This is a flowchart illustrating the hardware implementation of remote loading of the DSP by the MSU module in a distributed heterogeneous system, which is a reliable loading method for DSP and FPGA in this invention. Detailed Implementation

[0030] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0031] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0032] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0033] This invention aims to address the problems existing in the prior art by proposing an MSU module as a module support unit. By adding an MSU module to an FPGA + DSP solution, the limitation of device-bound algorithm components is broken. The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or via its network port. Multiple algorithm components are stored in the eMMC storage unit. The stored algorithm components are remotely loaded onto the FPGA or DSP via the FPGASelectMAP bus or DSPEMIF bus, realizing dynamic remote loading of algorithm components. In this way, this invention overcomes the limitation of device-bound algorithm components, thereby reducing equipment maintenance costs, improving equipment reliability and stability, and simplifying the complexity of system design.

[0034] The innovation of this invention lies in its hardware design scheme for remote loading of DSP and FPGA based on an MSU module. Since the device needs to remotely load both the FPGA and DSP, the MSU module pin multiplexing allows for separate remote loading of SelectMAP and EMIF during the overall hardware architecture design. This MSU module design simplifies system design complexity and significantly improves device reliability and stability. Remote loading and unloading of the FPGA or DSP can be performed in real time via the control bus. The design also considers scenarios where the first remote loading attempt fails, allowing for remote reset of the FPGA or DSP via the MSU before resuming remote loading.

[0035] Please see Figure 1-4 This invention discloses a reliable loading method for DSP and FPGA in a distributed heterogeneous system.

[0036] Overall Hardware Architecture: The innovation of this invention lies in the hardware design scheme for remote loading of DSP and FPGA based on MSU module. The overall hardware architecture includes MSU module, FPGA, DSP, and related buses and storage units; MSU module is connected to FPGA via SelectMAP bus or to DSP via EMIF bus; at the same time, MSU module integrates eMMC storage component for storing algorithm components.

[0037] The pin multiplexing of the SelectMAP and EMIF buses is a key feature of this design. This multiplexing reduces the number of hardware pins, lowers hardware costs, and simultaneously meets the remote loading requirements of the FPGA and DSP.

[0038] Remote loading process: Through the hardware architecture described above, the MSU module can remotely load the FPGA, including the following steps:

[0039] The S1 and MSU modules select the remote loading mode of the SelectMAP bus via the chip select signal; the generation of the chip select signal is based on the loading of the IP core that calls the internal program, ensuring accurate selection of the loading mode;

[0040] S2. Since the MSU module data bus is a multiplexed pin, the program control of the SelectMAP or EMIF signal must utilize the CPLD's internal BYPASS logic. The CPLD internally selects and implements the selectMAP signal link between the FPGA and the MSU module by detecting the high and low levels of the bus chip select GPIO signal pin.

[0041] The S3 and MSU module control programs read the algorithm components from the eMMC and write them into the DDR. The algorithm components transmit data from the PS side to the PL side via the AXI-GP protocol. After receiving the GP protocol data, the PL side remotely loads the FPGA according to the selectMAP timing sequence.

[0042] Specifically, the MSU module enables remote loading of the DSP, or the specific steps are as follows:

[0043] The S1 and MSU modules select the remote loading mode of the SelectMAP bus via the chip select signal; the generation of the chip select signal is based on the loading of the IP core that calls the internal program, ensuring accurate selection of the loading mode;

[0044] S2. Because the MSU module data bus is a multiplexed pin, the program control of the SelectMAP or EMIF signal must utilize the CPLD's internal BYPASS logic. The CPLD internally selects and implements the selectMAP signal link between the FPGA and the MSU module by detecting the high and low levels of the bus chip select GPIO signal pin.

[0045] S3: The MSU module control program reads the algorithm component from the eMMC and writes it into the DDR; the algorithm component transmits data from the PS side to the PL side through the AXI-GP protocol. After receiving the GP protocol data, the PL side remotely loads the DSP according to the EMIF timing sequence.

[0046] Loading failure handling: It also includes a loading failure handling module. If the first remote loading fails, the FPGA or DSP can be remotely reset through the MSU module before remote loading can be performed again. The reset pins on the FPGA and DSP chips are connected to the MSU module. The MSU module can call the underlying driver through the network window control program to pull low to release the FPGA and DSP reset function, thereby realizing remote reset.

[0047] This method for reliable loading of DSP and FPGA in a distributed heterogeneous system adds an MSU module to the FPGA+DSP scheme, breaking the limitation of device-bound algorithm components. The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network port, and then remotely loads the algorithm components to the FPGA or DSP via the FPGASelectMAP bus or DSPEMIF bus, realizing dynamic remote loading of algorithm components. In this way, the present invention breaks through the limitation of device-bound algorithm components, thereby reducing equipment maintenance costs, improving equipment reliability and stability, and simplifying the complexity of system design.

[0048] Specifically, the MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network control port for storing the algorithm components. The MSU module can realize remote loading of the FPGA.

[0049] Specifically, the eMMC storage unit is an embedded storage structure, consisting of an MMC packaging interface and a main controller containing a control chip.

[0050] Specifically, during DDSP loading and computation, the convolution formula used for filtering and denoising in signal processing is as follows:

[0051]

[0052] in: It is the input signal; It is the impulse response of the filter; through calculation, the output signal can be obtained. .

[0053] refer to Figure 2 As shown, the update process of the MSU module includes reading the algorithm components from the eMMC storage unit and loading them onto the FPGA or DSP via the relevant bus.

[0054] refer to Figure 3 As shown, the hardware implementation process of the MSU module for remote loading of the FPGA includes chip select signal selection, logic switching, data reading and writing, and loading according to timing sequence.

[0055] refer to Figure 4 As shown, the hardware implementation process of the MSU module for remote loading of the DSP includes chip select signal selection, logic switching, data reading and writing, and loading according to timing sequence.

[0056] In digital signal processing (DSP) and field-programmable gate array (FPGA) systems, remote loading technology enables flexible software and hardware updates without physical access to devices, which is especially important in distributed control systems, communication devices, and embedded systems.

[0057] The algorithms for remote loading applications of DSP and FPGA are as follows:

[0058] Remote loading consists of three main phases: data transfer, verification, and configuration. The algorithm needs to meet the following requirements:

[0059] Reliability: The integrity and correctness of transmitted data.

[0060] Security: Prevents unauthorized updates and malicious tampering.

[0061] Efficiency: Minimize the time required for updates.

[0062] Flexibility: Compatible with different protocols and hardware.

[0063] Step 1: System Initialization

[0064] The algorithm steps are as follows:

[0065] 1. Check the network connection status to ensure normal communication with the remote server.

[0066] 2. Alternatively, initialize the communication protocol stack (e.g., TCP / IP, UDP, CAN, RS-485), and store the algorithm components to be loaded in the eMMC storage unit through the network control port.

[0067] 3. Check the current system running status to confirm whether the update operation can be performed:

[0068] oDSP is in idle mode.

[0069] Alternatively, the oFPGA is in an erasable / rewritable state (ensure it is not locked).

[0070] pseudocode:

[0071] pseudo

[0072] Copy code

[0073] if CheckNetworkConnection() == false:

[0074] Abort("Network connection unavailable")

[0075] InitProtocolStack(protocol="TCP / IP")

[0076] if CheckSystemIdle(DSP) == false or CheckFPGAWriteReady() == false:

[0077] Abort("System not ready for update")

[0078] Step 2: Data transmission

[0079] Core requirements:

[0080] 1. Data chunking: Prevents memory overflow caused by transferring too large a amount of data at once.

[0081] 2. Reliable transmission protocol: Ensures data is received correctly (e.g., using TCP).

[0082] 3. Encryption and Authentication: AES encryption and SHA verification are used to prevent data tampering.

[0083] The algorithm steps are as follows:

[0084] 1. Request an update package from the server to obtain metadata (such as size, version, checksum).

[0085] 2. Download data in blocks, each block being N bytes in size.

[0086] 3. Each data block is checked using CRC; if the check fails, a retransmission is requested.

[0087] After the data download is complete, perform SHA-256 verification on the entire data packet.

[0088] pseudocode

[0089] pseudo

[0090] Copy code

[0091] metadata = RequestUpdateMetadata(server_url)

[0092] total_size = metadata["size"]

[0093] checksum = metadata["SHA256"]

[0094] buffer = []

[0095] for offset in range(0, total_size, N):

[0096] chunk = DownloadChunk(server_url, offset, N)

[0097] if CRC32(chunk) != metadata["chunk_crc"][offset / / N]:

[0098] RequestRetransmission(offset)

[0099] else:

[0100] buffer.append(chunk)

[0101] if SHA256(buffer) != checksum:

[0102] Abort("Data integrity check failed")

[0103] Step 3: Load configuration

[0104] Core requirements:

[0105] 1. Ensure that the DSP and FPGA configuration processes do not interfere with each other.

[0106] 2. Ensure configuration security and success rate.

[0107] 3. Automatic rollback mechanism after update (to prevent system malfunction due to update failure).

[0108] The algorithm steps are as follows:

[0109] 1. Utilize the internal logic of the CPLD to select an appropriate bus for data transmission, and implement the loading operation of the FPGA / DSP on the PL side through the AXI-GP protocol.

[0110] 2. Send an erase / write command to the FPGA to ensure that the old configuration is cleared.

[0111] 3. Load the new configuration to the FPGA block by block.

[0112] 4. The DSP restarts and loads a new program.

[0113] pseudocode

[0114] pseudo

[0115] Copy code

[0116] StopDSP()

[0117] if EraseFPGA() == false:

[0118] Abort("FPGA erase failed")

[0119] for chunk in buffer:

[0120] if WriteToFPGA(chunk) == false:

[0121] Abort("FPGA write failed")

[0122] if VerifyFPGAConfiguration() == false:

[0123] RollbackFPGA()

[0124] Abort("FPGA verification failed")

[0125] Step 4: Fault Recovery Mechanism

[0126] Design considerations:

[0127] 1. Use a dual-partition mechanism: the current partition saves the old configuration, and the new partition saves the new configuration.

[0128] 2. If verification fails or an error occurs, switch back to the old partition.

[0129] pseudocode

[0130] pseudo

[0131] Copy code

[0132] ActivateNewPartition()

[0133] if TestSystemHealth() == false:

[0134] SwitchToOldPartition()

[0135] Abort("Rollback to stable configuration")

[0136] The eMMC storage unit stores at least two algorithm components, and the stored algorithm components are remotely loaded onto the FPGA or DSP via the FPGASelectMAP bus or DSPEMIF bus.

[0137] DSP is an abbreviation for Digital Signal Processing. A digital signal processor represents signals in digital form and uses a computer or signal processing device to acquire, transform, filter, compress, enhance, and identify signals to extract useful components and forms. A DSP (Digital Signal Processor) is a programmable chip specifically designed for digital signal processing. Its main characteristics include: high real-time performance with predictable runtime; Harvard architecture with separate instruction and data buses; RISC instruction set for predictable instruction timing; a special architecture suitable for computationally intensive applications; an internal hardware multiplier for short and fast multiplication operations; high integration with multiple memory interfaces and I / O interconnect interfaces; and a commonly included DMA channel controller to ensure parallel data transfer and computation processing.

[0138] The biggest advantage of the DSP+FPGA architecture is its flexibility and versatility, making it suitable for modular design and thus improving algorithm efficiency. It also boasts a short development cycle, easy system maintenance and expansion, making it ideal for real-time signal processing. In real-time signal processing systems, lower-level signal preprocessing algorithms handle large amounts of data and require high processing speeds, but their computational structures are relatively simple, making them suitable for hardware implementation using FPGAs, thus balancing speed and flexibility. Higher-level processing algorithms, on the other hand, process less data than lower-level algorithms but have more complex control structures, making them suitable for implementation using DSP chips with high processing speeds, flexible addressing modes, and robust communication mechanisms.

[0139] This application proposes an MSU module-based design scheme to achieve remote loading of FPGA and DSP, simplifying hardware design and improving system reliability and stability. By multiplexing the pins of the MSU module, this application controls the CPLD to achieve time-division multiplexing of SelectMAP and EMIF, thereby simultaneously supporting the remote loading requirements of FPGA and DSP.

[0140] Usage: First, the user needs to store the file containing the FPGA / DSP loading data in the eMMC device of the MSU module; second, the user controls the MSU module interface through the program to complete the reading and transmission of data to the FPGA or DSP; the user controls the use of the BYPASS logic and CPLD inside the MSU module to realize the shared use of SelectMAP and EMIF, so as to complete the remote loading task of FPGA and DSP.

[0141] Working process: First, select the FPGA remote loading mode, at which point the SelectMAP bus is activated; second, the CPLD detects and selects the correct bus connection path; third, the program in the eMMC reads the loading data from the DDR and transmits it via the AXI-GP protocol; finally, remote loading is achieved according to the FPGA's SelectMAP timing.

[0142] When a user remotely sends a loading command, the relevant chips and logic circuits in the MSU module become active and begin to process data transmission, verification, loading, and other tasks in sequence. The process is equivalent to the gradual implementation of the D / A conversion task.

[0143] The technical solution of this application is a system based on MSU module design that can load FPGA and DSP operating programs in a remote environment. The system adopts pin multiplexing technology, that is, one interface supports Alternate functions at the same time, such as switching between SelectMAP and EMIF, so that the same module can have no less than two completely different interfaces and realize no less than two loading tasks with different heights.

[0144] This application mainly includes MSU modules, FPGAs, DSPs, CPLDs (programmable logic devices), eMMC storage devices, and related buses and storage units, among which:

[0145] MSU module: As the core control unit, it implements gating logic, interface multiplexing, and reset control.

[0146] FPGA: Field Programmable Gate Array that the user needs to load.

[0147] DSP: Digital Signal Processor, which also requires loading new programs later.

[0148] CPLD: Configures logic devices and selects bus connection paths by detecting GPIO signals.

[0149] eMMC: A storage device that holds the algorithm components required for loading.

[0150] Bus and storage units: responsible for data transmission and caching operations.

[0151] Technical benefits: Simplifies design, improves hardware flexibility and reliability, simplifies design by utilizing pin multiplexing technology of MSU modules, optimizes hardware interfaces, reduces costs, and enables remote loading of FPGA and DSP by processing control gating logic through CPLD.

[0152] The algorithm components are stored in the eMMC storage device of the MSU module. The appropriate bus is selected for data transmission using the internal logic of the CPLD. The loading operation of the FPGA and DSP is realized on the PL side through the AXI-GP protocol. Remote loading is achieved efficiently using the SelectMAP and EMIF buses, while maintaining the system's response speed and accuracy. In case of loading failure, the FPGA or DSP is remotely reset through the MSU module to ensure that the loading task can be completed smoothly, thereby enhancing the system's stability.

[0153] In summary, this reliable loading method for DSP and FPGA in a distributed heterogeneous system adds an MSU module to the FPGA+DSP scheme, breaking the limitation of device-bound algorithm components. The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network port, and then remotely loads the algorithm components to the FPGA or DSP via the FPGASelectMAP bus or DSPEMIF bus, realizing dynamic remote loading of algorithm components. In this way, the present invention breaks through the limitation of device-bound algorithm components, thereby reducing equipment maintenance costs, improving equipment reliability and stability, and simplifying the complexity of system design.

[0154] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0155] More specific examples (a non-exhaustive list) of computer-readable media include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0156] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0157] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for reliable loading of DSP and FPGA in a distributed heterogeneous system, comprising an MSU module, an FPGA, a DSP, and related buses and storage units, characterized in that: The MSU module is connected to the FPGA via the SelectMAP bus or to the DSP via the EMIF bus, including the following steps: The S1 and MSU modules select the remote loading mode of the SelectMAP bus via the chip select signal; the generation of the chip select signal is based on the loading of the IP core that calls the internal program, ensuring accurate selection of the loading mode; S2. Since the MSU module data bus is a multiplexed pin, the program control of the SelectMAP or EMIF signal must utilize the CPLD's internal BYPASS logic. The CPLD internally selects and implements the selectMAP signal link between the FPGA and the MSU module by detecting the high and low levels of the bus chip select GPIO signal pin. The S3 and MSU module control programs read the algorithm components from the eMMC and write them into the DDR. The algorithm components transmit data from the PS side to the PL side via the AXI-GP protocol. After receiving the GP protocol data, the PL side implements remote loading of the FPGA according to the selectMAP timing sequence. The MSU module enables remote loading of the DSP. The specific steps are as follows: The S1 and MSU modules select the remote loading mode of the SelectMAP bus via the chip select signal; the generation of the chip select signal is based on the loading of the IP core that calls the internal program, ensuring accurate selection of the loading mode; S2. Because the MSU module data bus is a multiplexed pin, the program control of the SelectMAP or EMIF signal must utilize the CPLD's internal BYPASS logic. The CPLD internally selects and implements the selectMAP signal link between the FPGA and the MSU module by detecting the high and low levels of the bus chip select GPIO signal pin. S3: The MSU module control program reads the algorithm component from the eMMC and writes it into the DDR; the algorithm component transmits data from the PS side to the PL side through the AXI-GP protocol. After receiving the GP protocol data, the PL side remotely loads the DSP according to the EMIF timing sequence. When the DSP loads and performs operations, it is used for filtering and denoising in signal processing. The convolution formula used is as follows: wherein: is an input signal; is an impulse response of the filter; by operating, an output signal is obtained.

2. The method of claim 1, wherein the method comprises: The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network control port for storing the algorithm components. The MSU module can realize remote loading of FPGA.

3. The method of claim 2, wherein the method comprises: The eMMC storage unit is an embedded storage structure, consisting of an MMC packaging interface and a main controller containing a control chip.

4. The method of claim 1, wherein the method comprises: The update process of the MSU module includes reading algorithm components from the eMMC storage unit and loading them onto the FPGA or DSP via a relevant bus.

5. The method of claim 1, wherein the method comprises: The hardware implementation process of the MSU module for remote loading of the FPGA includes chip select signal selection, logic switching, data reading and writing, and loading according to timing sequence.

6. The reliable loading method for DSP and FPGA in a distributed heterogeneous system according to claim 1, characterized in that: The hardware implementation process of the MSU module for remote loading of the DSP includes chip select signal selection, logic switching, data reading and writing, and loading according to timing sequence.

7. The reliable loading method for DSP and FPGA in a distributed heterogeneous system according to claim 1, characterized in that: It also includes a loading failure handling module. If the first remote loading fails, the FPGA or DSP can be remotely reset via the MSU module before remote loading can be performed again. The reset pins on the FPGA and DSP chips are connected to the MSU module. The MSU module can call the underlying driver through the network window control program to pull low and release the FPGA and DSP reset function, thereby realizing remote reset.

8. A reliable loading method for DSP and FPGA in a distributed heterogeneous system according to claim 2, characterized in that: The eMMC storage unit stores at least two algorithm components, and the stored algorithm components are remotely loaded onto the FPGA or DSP via the FPGASelectMAP bus or DSPEMIF bus.

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