Generalized inverse matrix solving circuit based on block matrix and working method

Abstract

The invention provides a generalized inverse matrix solving circuit based on a block matrix and a working method, and belongs to the field of semiconductors, analog computation and integrated circuits. Small-scale matrixes obtained after an original matrix is partitioned are mapped to resistive memory arrays of two small-scale generalized inverse matrix solving circuits respectively, and the generalized inverse matrix solving operation of the partitioned matrixes is completed in two steps by adjusting a circuit analog switch arranged between circuit devices. In the implementation process, only one set of analog computing system is needed, hardware resource consumption is reduced through an array multiplexing mode, the number of needed array devices is consistent with the mode of directly mapping matrix elements, but the scale of a matrix solved by an actual circuit is reduced, and therefore the solving performance and the circuit construction feasibility are improved; the implementation of the simulation in-memory calculation in a large-scale calculation scene is improved, and the advantages of the simulation in-memory calculation technology can be further developed.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor, analog computing and integrated circuit, and relates to a method for realizing the solution of the generalized inverse matrix of a block matrix in an analog computing circuit, and specifically relates to an analog circuit design method and working method for solving the generalized inverse matrix of a block matrix suitable for resistive memory (such as resistive memory, phase change memory, magnetic memory, ferroelectric memory, etc.), including its working principle and operation method. Background Art

[0002] With the surge in data volume and the increase in computing demand, traditional digital computers are limited by serial digital algorithms and storage-computation separation architectures, facing the dual challenges of efficiency and energy consumption when processing large-scale matrix operations, making it difficult to cope with today's large and complex computing tasks. In order to improve computing efficiency and reduce energy consumption, the development of new computing paradigms has gradually become a research hotspot. Analog computing circuits based on resistive memory arrays can perform in-situ matrix operations, such as matrix-vector multiplication, matrix inversion, matrix generalized inverse, and matrix eigenvectors. Benefiting from the extremely high parallelism of the analog computing paradigm, this method provides a strong guarantee for improving computing efficiency and has been widely studied and applied as artificial intelligence reasoning and training accelerators.

[0003] In the field of modern computing, generalized inverse matrix solution is a key computing component in the fields of scientific computing, artificial intelligence, and regression problem solving. However, in the actual computing environment, the extremely large matrix scale will make it difficult for the generalized inverse solution circuit based on the analog computing paradigm to write matrix elements and map and construct circuits, resulting in greater circuit operation complexity; at the same time, the larger matrix scale will increase circuit noise, causing serious loss of solution accuracy and error; in addition, the solution of analog computing circuits is highly dependent on the loop stability characteristics based on operational amplifiers, and the larger solution matrix scale is not conducive to circuit stability. All of the above problems will seriously limit the application of generalized inverse solution circuits, and reduce or even offset the advantages of low power consumption and high efficiency brought by analog computing. Therefore, a generalized inverse matrix solution method that can effectively reduce the size of the solution matrix needs to be developed urgently. Summary of the invention

[0004] The purpose of the present invention is to develop a generalized inverse matrix solving circuit based on a block matrix based on a resistive memory array, reduce the scale of the resistive memory array by a block method, and reuse the resistive memory array through the working method developed by the present invention to complete the generalized inverse matrix solving, thereby improving the circuit solving performance and reducing hardware resource consumption.

[0005] The problem of solving the generalized inverse matrix of a partitioned matrix addressed by the present invention is described as follows:

[0006] For an overdetermined linear system of equations \(y = Ax\), where \(A\) is a matrix of size \(m\times n\) with \(m>n\), \(y\) is a known vector of size \(m\times1\), and \(x\) is an unknown vector of size \(n\times1\) to be solved. There is no exact solution \(x\) for the overdetermined problem such that \(y - Ax=0\). However, there exists a specific vector \(x\) that minimizes the Euclidean distance \(\|y - Ax\|_2\) between \(Ax\) and \(y\). At this time, \(x = A\) + \(^+y\), where \(A^+\) + \(=(A^TA)^{-1}A^T\) T \) is called the left inverse matrix of \(A\). Partition \(A\) by columns, i.e., \(A = [B\ C]\), where the size of matrix \(B\) is \(m\times p\), the size of matrix \(C\) is \(m\times q\), and \(p + q=n\). Based on the Sherman - Morrison - Woodbury formula, we have: -1 \(A^+=[(I - B(B^TB)^{-1}B^T)\ 0][(I - C(C^TC)^{-1}C^T)\ 0]\) T where \(P_1\)

[0007]

[0008] and \(P_2\) B1 and \(P_2\) C1 are respectively expressed as \(P_1 = I - B(B^TB)^{-1}B^T\) B1 and \(P_2 = I - C(C^TC)^{-1}C^T\) T \). -1 \) and \(P_2\) T \(=I - C(C^TC)^{-1}C^T\) C1 \) and \(P_2\) T \(=I - C(C^TC)^{-1}C^T\) -1 \). T .

[0009] For an underdetermined linear system of equations \(y = Ax\), where \(A\) is a matrix of size \(m\times n\) with \(m < n\), \(y\) is a known vector of size \(m\times1\), and \(x\) is an unknown vector of size \(n\times1\) to be solved. If there are no additional constraints on the solution of the underdetermined system of equations, then there are infinitely many vectors \(x\) that satisfy \(y = Ax\). If the solution vector \(x\) is restricted to minimize the \(L_2\) norm, i.e., \(\min(\|x\|_2)\), then at this time \(x = A^+\) + \(^+y\), where \(A^+\) + \(=A^T(AA^T)^{-1}\) T \) is called the right inverse matrix of \(A\). Partition \(A\) by rows, i.e., \(A=\begin{bmatrix}B\\C\end{bmatrix}\), where the size of matrix \(B\) is \(p\times n\), the size of matrix \(C\) is \(q\times n\), and \(p + q=m\). Partition \(y\) by rows, i.e., \(y=\begin{bmatrix}y_1\\y_2\end{bmatrix}\) T \). -1 \), where the size of matrix \(B\) is \(p\times n\), the size of matrix \(C\) is \(q\times n\), and \(p + q=m\). Partition \(y\) by rows, i.e., \(y = [y_1\) T \ C\) T T , \(y_1\) T and \(y_2\) T T ​​, the size of y1 vector is p×1, and the size of y2 vector is q×1. Based on the Sherman-Morrison-Woodbury formula, we can get:

[0010]

[0011] Among them, P B2 and P C2 Respectively represented as P B2 =IB T (BB T ) -1 B and P C2 =IC T (CC T ) -1 C.

[0012] The left inverse matrix and the right inverse matrix described above are collectively referred to as generalized inverse matrices. The present invention implements the solution of the generalized inverse matrix of the block matrix, thereby reducing the size of the resistive memory array and further accelerating the operation.

[0013] The technical solution of the present invention is as follows:

[0014] A generalized inverse matrix solving circuit based on a block matrix is ​​used for solving the generalized inverse matrices M and N of the column block matrices of a target real number matrix A (the size is m×n and m>n), A=[MN] (the size of the matrix M is m×p, the size of the matrix N is m×q, and p+q=n), characterized in that the circuit is composed of two circuits connected by two groups of analog switches, one of which is used to map and process the block matrix M, and the other circuit is used to map and process the block matrix N;

[0015] Let matrix M be expressed as M=M (+) -M (-) , where M (+) =(M+|M|) / 2, M (-) =(|M|-M) / 2, M (+) and M (-) are the actual mapped matrix values, representing the positive and negative elements of the original matrix respectively; the matrix N is represented as N = N (+) -N (-) , where N (+) =(N+|N|) / 2, N (-) =(|N|-N) / 2, N (+) and N (-) are the actual mapped matrix values, representing the positive and negative elements of the original matrix respectively;

[0016] The circuit of the mapping matrix M comprises 4 groups of resistive memory arrays, multiple analog inverters (INV), multiple transimpedance amplifiers (TIA), multiple operational amplifiers (OPA), multiple input reference resistors, multiple analog switches and 8 input and output ports; the 4 groups of resistive memory arrays are arranged in a grid, and the first two groups of resistive memory arrays map M respectively. (+) and M (-) , the latter two groups map M (-) and M (+) , the mapping M in the first two groups (+) The column lines of the array are connected to the mapping M through analog inverters (-) The column lines of the array are connected to the row lines of the two arrays, and M (-) The array rows are connected to the input of the transimpedance amplifier through analog switches, and the output of the transimpedance amplifier is connected to the mapping M in the latter two arrays through analog switches. (+) The row lines of the array are then connected through analog inverters to map the two arrays into M (-) The row lines of the array of the first two groups are connected, and the column lines of the second two groups of arrays are connected and connected to the positive input terminal of the operational amplifier through an analog switch. The reverse input terminal of the operational amplifier is grounded, and the output terminal is connected to the column lines of the first two groups of arrays through an analog switch; the input and output ports are connected through the input reference resistor G0 in the common row lines of the first two groups of arrays and the common column lines of the second two groups of arrays, respectively, and M is mapped in the first two groups of arrays. (+) The column lines of the array and the last two arrays are mapped in M (+) The row lines of the array are directly connected to the input and output ports to complete the calculation operation; at the same time, in the layout, the circuit of the mapping matrix M is vertically flipped, where the mapping matrix is ​​the corresponding vertical flip matrix, and the matrix M after the vertical flip operation f , which is the same size as M, but the order of rows is reversed;

[0017] The topological structure of the circuit of the mapping matrix N is completely consistent with that of the circuit of the mapping matrix M. The difference lies in the difference in the number of columns of the resistive memory array. The first two groups of resistive memory arrays map N (-) and N (+) , the latter two groups map N (+) and N (-) ;

[0018] The circuit of the mapping matrix M and the circuit of the mapping matrix N are connected through two groups of analog switches, one group of analog switches is used to control the row lines connecting the first two groups of arrays in the two circuits, and the other group of analog switches is used to control the row lines connecting the last two groups of arrays in the two circuits.

[0019] Furthermore, the size of the resistive memory array of the circuit of the mapping processing matrix M is m×p, the size of the resistive memory array of the circuit of the mapping processing matrix N is m×q, and m>(p+q) is satisfied.

[0020] The present invention also proposes a left inverse matrix solving method based on a generalized inverse matrix solving circuit of a block matrix. For a target solving matrix A, the left inverse matrix vector product A is solved. + y, A + =(A T A) -1 A T , the matrix after column and row block is B, C, the problem to be solved is converted to A + y=[(P C1 B) + y(P B1 C) + y] T , where P B1 =IB(B T B) -1 B T , P C1 =IC(C T C) - 1 C T , characterized in that it comprises the following steps:

[0021] The first step is to map the block matrices B and C to the generalized inverse of the block matrix to solve the resistive memory array of the circuit, adjust the analog switches of the circuit, and solve the matrix P C1 B and matrix P B1 All element values ​​of C;

[0022] The second step is to map the matrix P C1 B and P B1 C to block matrix generalized inverse matrix solver circuit resistive memory array, adjust circuit analog switch, solve vector value (P C1 B) + y and (P B1 C) + y.

[0023] Furthermore, the first step of the step maps the block matrix, specifically, the positive and negative matrix values ​​of the B matrix are mapped to (+) , B (-) The resistive memory array in the circuit mapped to the mapping processing matrix M converts the positive and negative values ​​of the C matrix into the matrix value C (+) , C (-) A resistive memory array in a circuit mapped to a mapping processing matrix N;

[0024] The second step of the step is to map the matrix, specifically, map P C1 The positive and negative value matrix of the B matrix (P C1 B) (+) ,(P C1 B) (-) To the first step of mapping the B matrix in the resistive memory array, map P B1 The positive and negative value matrix of the C matrix (P B1 C) (+) ,(P B1 C) (-) To the resistive memory array of the first step mapping C matrix.

[0025] Furthermore, in the first step, the circuit analog switch is adjusted to solve the matrix P C1 B and matrix P B1 C, specifically, turning off all analog switches of the circuit of mapping processing matrix B and the analog switches between the row lines of the last two groups of arrays of the two circuits, connecting all analog switches of the circuit of mapping processing matrix C and the analog switches between the row lines of the first two groups of arrays of the two circuits; mapping B in the first two groups of arrays of the circuit of mapping processing matrix B (+) The input and output ports on the column lines of the array sequentially input the voltage signals in the form of one-hot codes, and after each input, the mapping matrix C is mapped in the last two arrays of the circuit of the mapping matrix C. (+) The voltage output by the input and output ports on the row lines of the array is scaled by coefficients, and finally the matrix P is obtained. C1 Each column vector of B; in completing the matrix P C1 After calculating B, all analog switches of the circuit of the mapping processing matrix C and the analog switches between the row lines of the last two groups of arrays of the two circuits are turned off, and all analog switches of the circuit of the mapping processing matrix B and the analog switches between the row lines of the first two groups of arrays of the two circuits are turned on; in the first two groups of arrays of the circuit of the mapping processing matrix C, mapping C is (+) The input and output ports on the column lines of the array sequentially input the voltage signals in the form of one-hot codes, and after each input, the mapping matrix B is mapped in the last two arrays of the circuit of the mapping processing matrix B. (+) The voltage output by the input and output ports on the row lines of the array is scaled by coefficients, and finally the matrix P is obtained. B1 The column vectors of C.

[0026] Furthermore, in the second step, the circuit analog switch is adjusted to solve the vector value, specifically, the analog switches between the row lines of the first two groups of arrays of the two circuits and the analog switches between the row lines of the last two groups of arrays are turned off, and the mapping processing matrix P is connected. C1 B's circuit and mapping processing matrix P B1 All analog switches of the circuit of C; respectively to the mapping processing matrix P C1B's circuit and mapping processing matrix P B1 The input and output ports on the common row lines of the first two arrays of the circuit of C input the known vector y through the input reference resistor, then the voltage output by the input and output ports on the row lines of the arrays with positive values ​​in the mapping matrix of the first two arrays of the two circuits are respectively expressed as (P C1 B) + y and (P B1 C) + y, and then the final left inverse matrix calculation result is A + y=[(P C1 B) + y(P B1 C) + y] T .

[0027] On the other hand, the present invention proposes a right inverse matrix solving method based on a generalized inverse matrix solving circuit of a block matrix, for a target solving matrix A, solving its right inverse matrix vector product A + y, A + =A T (AA T ) -1 , after the rows are divided into blocks, they are represented as A=[B T C T ] T , the y vector row is divided into blocks y = [y1 T y2 T ] T , solve the problem and convert it into A + y=[(BP C2 ) + y1(CP B2 ) + y2] T , where P B2 =IB T (BB T ) -1 B.P C2 =IC T (CC T ) -1 C, characterized in that it comprises the following steps:

[0028] The first step is to transform the matrix B T and C T They are mapped to the resistive memory array of the block matrix generalized inverse matrix solving circuit to solve the matrix BP C2 and CP B2 ;

[0029] The second step is mapping (BP C2 ) T and (CPB2 ) T Matrix to block matrix generalized inverse matrix solver circuit resistive memory array, solve vector (BP C2 ) + y and (CP B2 ) + y.

[0030] Furthermore, the first step of the step maps the block matrix, specifically, B T The positive and negative values ​​of the matrix matrix value B T (+) , B T (-) The resistive memory array in the circuit mapped to the mapping processing matrix M is mapped to C T The positive and negative values ​​of the matrix matrix value C T (+) , C T (-) The resistive memory array in the circuit mapped to the mapping processing matrix N; the second step of the step is to map the matrix, specifically, mapping (BP C2 ) T The positive and negative values ​​of the matrix matrix value (BP C2 ) T (+) , (BP C2 ) T (-) To the first step mapping B T In the resistive memory array of the matrix, the mapping (CP B2 ) T The positive and negative values ​​of the matrix (CP B2 ) T (+) , (CP B2 ) T (-) To the first step mapping C T In a resistive memory array of a matrix.

[0031] Further, the first step of the step is to adjust the circuit analog switch, specifically, to turn off the mapping processing matrix B T All analog switches of the circuit and the analog switches between the rows of the first two groups of arrays of the two circuits are connected to the mapping processing matrix C T All analog switches of the circuit and the analog switches between the row lines of the two groups of arrays after the two circuits; in the mapping processing matrix C T The input and output ports on the common row lines of the first two arrays of the circuit sequentially input the voltage signals in the form of one-hot codes through the input reference resistors, and after each input, the mapping processing matrix B TThe input and output ports on the common column lines in the last two arrays of the circuit are scaled by the output voltage obtained by the reference resistor to obtain the matrix BP C2 Each column vector of the completed matrix BP C2 After calculation, the mapping matrix C is turned off. T All analog switches of the circuit and the analog switches between the rows of the first two groups of arrays of the two circuits are connected to the mapping processing matrix B T All analog switches of the circuit and the analog switches between the row lines of the two groups of arrays after the two circuits; in the mapping processing matrix B T The input and output ports on the common row lines of the first two arrays of the circuit sequentially input the voltage signals in the form of one-hot codes through the input reference resistors. After each input, the mapping processing matrix C T The input and output ports on the common column lines in the last two arrays of the circuit are scaled by the output voltage obtained by the reference resistor to obtain the matrix CP B2 The column vectors of .

[0032] Furthermore, the second step of the step adjusts the circuit analog switch to solve the vector value, specifically, turns off the analog switches between the row lines of the first two groups of arrays of the two circuits and the analog switches between the row lines of the last two groups of arrays, and connects the mapping processing matrix P C1 B's circuit and mapping processing matrix P B1 All analog switches of the circuit of C; respectively to the mapping processing matrix P C1 B's circuit and mapping processing matrix P B1 The input and output ports on the common column lines of the last two arrays of the circuit of C input the known vectors y1 and y2 through the reference resistor. Then the voltage output by the input and output ports on the row lines of the arrays with positive values ​​in the mapping matrix of the last two arrays of the two circuits are respectively expressed as (BP C2 ) + y1 and (CP B2 ) + y2, and then the final right inverse matrix calculation result is A + y=(BP C2 ) + y1+(CP B2 ) + y2.

[0033] The technical effects of the present invention are as follows:

[0034] The present invention provides an analog computing circuit implementation scheme for solving the generalized inverse matrix of a block matrix, which can solve the generalized inverse solution task of a large-scale matrix in the form of a block matrix. Different from the traditional generalized inverse matrix solution circuit that directly maps the target solution matrix elements to the resistive memory array, the scheme provided by the present invention is to map the small-scale matrices after the original matrix is ​​divided into blocks to the resistive memory arrays of two small-scale generalized inverse matrix solution circuits, and complete the generalized inverse matrix solution operation of the block matrix in two steps by adjusting the circuit simulation switch set between the circuit devices. This design scheme not only reduces the target matrix scale of the actual circuit solution, but also improves the circuit loop stability and reduces the output noise, thereby improving the solution accuracy. At the same time, the scheme only requires one set of analog computing systems during the implementation process, and reduces the consumption of hardware resources by multiplexing the array. The number of array devices required is consistent with the method of directly mapping the matrix elements, but the scale of the matrix solved by the actual circuit is reduced, thereby improving the solution performance and the feasibility of circuit construction. The scheme of the present invention improves the feasibility of analog in-memory computing in large-scale computing scenarios, which helps to further give play to the advantages of analog in-memory computing technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of a generalized inverse matrix solving circuit based on a block matrix provided in an embodiment of the present invention;

[0036] Figure 2 It is a flow chart of a left inverse matrix solving working method of a generalized inverse matrix solving circuit based on a block matrix provided in an embodiment of the present invention;

[0037] Figure 3 It is a flow chart of a working method for solving a right inverse matrix of a generalized inverse matrix solving circuit based on a block matrix provided by an embodiment of the present invention;

[0038] Figure 4 It is a schematic diagram of a specific implementation method of the first step of the left inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided in an embodiment of the present invention;

[0039] Figure 5 It is a schematic diagram of a specific implementation method of the second step of the left inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided in an embodiment of the present invention;

[0040] Figure 6 It is a schematic diagram of a specific implementation method of the first step of the right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided in an embodiment of the present invention;

[0041] Figure 7It is a schematic diagram of a specific implementation method of the second step of the right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention will be further clearly and completely described below through specific embodiments in conjunction with the accompanying drawings.

[0043] Figure 1 Schematic diagram of a generalized inverse matrix solving circuit based on a block matrix provided by an embodiment of the present invention. The circuit is composed of two similar circuits connected by two sets of analog switches. The two circuits respectively map and process the matrices M and N (m>p+q) of size m×p and m×q after the blocks are respectively completed. For a resistive memory array, the actual mapped matrix element value is a ij =G ij / G0, where G ij is the device conductance value of the resistive memory array at the corresponding position, and G0 is the conductance value of the reference resistor. For the circuit of the mapping matrix M, it includes 4 groups of variable resistor cross arrays with m rows and p columns, m+p analog inverters (INV), m transimpedance amplifiers (TIA, with a transimpedance of 1 / cG0), p operational amplifiers (OPA), m+p input reference resistors, and 2(m+p) analog switches. For the real number matrix M, since the actual circuit conductance can only map positive values, the matrix M is represented as M=M (+) -M (-) , where M (+) =(M+|M|) / 2, M (-) =(|M|-M) / 2, M (+) and M (-) is the actual mapped matrix element value, and the positive and negative elements of the original matrix are expressed by connecting analog inverters (i.e. Figure 1 The mapping M (+) and M (-) Between arrays, mapping N (+) and N (-) In the circuit structure of the mapping matrix M (i.e. Figure 1 The first two groups of resistive memory arrays map M (+) and M (-) , mapping M (+) The column lines of the array are connected to the mapping M through analog inverters (-) The column lines of the array, the two array row lines are connected and connected through analog switches ( Figure 1 S1 in the figure is connected to the input of the transimpedance amplifier, and the output of the transimpedance amplifier is connected to the input of the transimpedance amplifier through an analog switch ( Figure 1 S3) is connected to the last two arrays and mapped to M (+)The row lines of the array are connected by analog inverters and then the two groups of arrays are mapped into M (-) The row lines of the array, the column lines of the latter two arrays are connected through analog switches ( Figure 1 S3 in the figure is connected to the positive input of the operational amplifier, the negative input of the operational amplifier is grounded, and the output is connected to the analog switch ( Figure 1 The common row lines of the first two arrays and the common column lines of the last two arrays are connected to the input and output ports through reference resistors, and the M is mapped in the first two arrays. (+) The column lines of the array and the last two arrays are mapped in M (+) The input and output ports are directly connected in the row lines of the array. As for the circuit structure of the mapping matrix N, it includes 4 groups of variable resistor cross arrays with m rows and q columns, m+q analog inverters (INV), m transimpedance amplifiers (TIA), q operational amplifiers (OPA), m+q input reference resistors, 2 (m+q) analog switches, and 8 ports. For the real number matrix N, the method is consistent with the mapping matrix M, and the matrix N is expressed as N=N (+) -N (-) , where N (+) =(N+|N|) / 2, N (-) =(|N|-N) / 2, N (+) and N (-) are the actual mapped matrix values, representing the positive and negative elements of the original matrix (subscript (+) and (-) Represent the above calculation operations respectively). The topological structure of the circuit of the mapping matrix N is exactly the same as that of the circuit of the mapping matrix M, except for the difference in the number of columns of the actual resistive memory array (p columns for the M matrix and q columns for the N matrix). Based on the circuits of the mapping matrix M and the mapping matrix N, m analog switches are used to control the row lines connecting the first two arrays and the row lines connecting the last two arrays in the two circuits. At the same time, in order to optimize the circuit layout and facilitate line connection, the upper half of the circuit is vertically flipped (described by the subscript f). The two parts of the circuit are connected through the analog switch groups S5 and S6. At the same time, the connection inside the circuit can be controlled by adjusting the analog switch groups S1, S2, S3, and S4 in the transimpedance amplifier and operational amplifier set inside the two parts of the circuit. In the actual process of solving the generalized inverse matrix, it is necessary to use Figure 1 The input and output ports P1, P2, P3, P4, P5, P6, P7, P8 shown in the figure, among which P3, P4, P5, P6 need to be connected to an input reference resistor (the conductance is G0).

[0044] The vertical flip operation of the mapping process M matrix is: for the original matrix M, the matrix M after the vertical flip operation f, which is the same size as M, but with the rows in reverse order. In mathematical expressions, if the elements of M are represented by m ij , then the matrix M f The element m ij,f It can be expressed as m ij,f =m (m+1-i)j , where i and j represent the row and column indices respectively.

[0045] Figure 2 The flowchart of the left inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the present invention is as follows. First, for a target solving matrix A of size m×n, to solve its left inverse matrix vector product A + y, where A + =(A T A) -1 A T First, divide it into columns, that is, A = [BC], where the size of the B matrix is ​​m×p, the size of the C matrix is ​​m×q, and p+q=n, and then map the block matrices B and C to the resistive memory in the circuit respectively. Secondly, by adjusting the circuit analog switch and inputting a specific voltage signal, the matrix P is solved respectively. C1 B and P B1 C. Then, the obtained P C1 B and P B1 The C matrix information is remapped to the resistive memory of the original circuit to realize array multiplexing. Finally, the circuit analog switch is adjusted again and the original signal y is input to complete (P C1 B) + y and (P B1 C) + The solution of y, (P C1 B) + y and (P B1 C) + y is A + The row block matrix of y, i.e. A + y=[(P C B) + y(P B C) + y] T .

[0046] Figure 3 The flowchart of the right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the present invention is as follows. First, for a target solving matrix A of size m×n, to solve its right inverse matrix vector product A + y, where A + =A T (AA T ) -1First, divide it into rows, that is, A=[B T C T ] T , where the B matrix size is p×n, the C matrix size is q×n, and p+q=m, and then the block matrix B T and C T Mapped to the resistive memory in the circuit. Secondly, by adjusting the circuit analog switch and inputting a specific voltage signal, the matrix BP is solved respectively. C2 and CP B2 Then, the obtained BP C2 and CP B2 The matrix information is remapped to the resistive memory of the original circuit to realize array reuse. Finally, the known vector y is divided into rows, that is, y = [y1 T y2 T ] T , the size of y1 vector is p×1, the size of y2 vector is q×1, and the circuit analog switch is adjusted again to input the original signals y1 and y2, thus completing (BP C2 ) + y1 and (CP B2 ) + The solution for y2 is A. + y=(BP C2 ) + y1+(CP B2 ) + y2.

[0047] Figure 4 The figure is a schematic diagram of the specific implementation of the first step of the left inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided by the embodiment of the present invention. Consider a matrix A of size m×n, where m>n, and its columns are divided into blocks and represented as A=[BC], the size of the B matrix is ​​m×p, and the size of the C matrix is ​​m×q, and the B matrix and the C matrix are mapped to the following respectively: Figure 1 The described mapping matrices M and N are arrays of two similar circuits, and p+q=n (the subscripts (+) and (-) represent positive and negative matrices, respectively, and the subscript f represents a vertical flip matrix). Figure 4 (a) and Figure 4 (b) The circuits described can solve P C1 B and P B1 C. In Figure 4 In (a), the circuit simulation switch groups S2, S4 and S5 are turned on, and the circuit simulation switch groups S1, S3 and S6 are turned off. For the circuit at this time, when the voltage vector x is input at port P1, the current output vector obtained on the common row line after passing through the array is I t =-G B x,G BThe conductivity value matrix (including positive and negative) of the mapping B matrix is ​​used to input the current vector into the subsequent circuit, and then the voltage output vector V can be obtained at port P8. out =-G0 -1 c -1 P C1 I t =c -1 P C1 Bx, where c is the ratio of the transconductance of the transimpedance amplifier to the reference conductance. Based on the above analysis, by sequentially inputting the scanning voltage in the form of one-hot code at port P1 (if the number of column lines is 3, that is, inputting the voltage signals of [001V], [01V 0], [1V 00] in sequence), for the i-th input, at this time, c can be obtained at the output port P8 -1 P C1 The vector composed of the elements in the i-th column of B can be solved by inputting voltages in sequence to obtain c - 1 P C1 All element values ​​of B can be obtained by scaling the coefficients to get the matrix P C1 B's element information. Figure 4 (b), P B1 The logic of solving C is the same as described above. The difference is that when solving P B1 C needs to select the circuit simulation switch group S1, S3 and S5, and turn off the circuit simulation switch group S2, S4 and S6. At the same time, the scan voltage needs to be input at port P2, and the final result is output by port P7.

[0048] Figure 5 This is a schematic diagram of a specific implementation method of the second step of the left inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided in an embodiment of the present invention. Figure 4 Described by P C1 B and P B1 The calculation result of C is the matrix P C1 B and P B1 C are mapped to the arrays mapped to B and C respectively (the subscripts (+) and (-) represent the positive and negative matrices respectively, and the subscript f represents the vertical flip operation), and the circuit analog switch group S1, S2, S3, S4 is turned on, and the circuit analog switch S5, S6 is turned off. At this time, the whole system is transformed into two independent small-scale matrix generalized inverse matrix solving circuits. The required calculation vector y is input into ports P5 and P6 respectively, and the output voltage vector (P) can be obtained at ports P1 and P2 respectively. C1 B) + y and (P B1 C) + y, and then the final left inverse matrix calculation result can be obtained as A + y=[(PC1 B) + y(P B1 C) + y] T For example, to solve for all elements of matrix A + the input vector y can be replaced with a one-hot encoded sweep voltage, and the voltage sweep operation demonstrated in the first step can be performed sequentially to obtain matrix A + .

[0049] Figure 6 is a schematic diagram of the specific implementation of the first step of the right inverse matrix solving method for the generalized inverse matrix solving circuit based on the block matrix provided in the embodiments of the present invention. Considering a matrix A of size m×n, where m < n, after row partitioning it is represented as A = [B T C T T , the size of matrix B is p×n, the size of matrix C is q×n, and matrices B T and C T are respectively mapped to arrays of two similar circuits of mapping matrices M and N as described in Figure 1 , and p + q = m. The known vector y is row partitioned, i.e., y = [y1 T y2 T T , the size of vector y1 is p×1, and the size of vector y2 is q×1 (subscripts (+) and (-) represent positive and negative matrices respectively, and subscript f represents the vertically flipped matrix). Figure 6 (a) and Figure 6 (b) can solve for BP C2 and CP B2 respectively. In Figure 6 (a), the circuit simulation switch groups S2, S4, and S6 are selected, and the circuit simulation switch groups S1, S3, and S5 are turned off. For the circuit at this time, when the voltage vector x is input at port P6, the voltage output vector obtained on the array row lines after passing through the lower half of the circuit is V t =-c -1 P C2 x, and this voltage vector is continuously input to the subsequent circuit, and then the voltage output vector V out =-G0 -1 G B V t =c -1 BP C2 ​​x, where c is the ratio of the transconductance of the transimpedance amplifier to the reference conductance. Based on the above analysis, by sequentially inputting the scanning voltage in the form of one-hot code at port P6 (if the number of column lines is 3, that is, inputting the voltage signals of [001V], [01V 0], [1V 00] in sequence), for the i-th input, at this time, c can be obtained at the output port P3. -1 BP C2 The vector composed of the elements in the i-th column of , by inputting the voltages in sequence, we can solve for c -1 BP C2 All element values ​​of the matrix BP can be obtained by scaling the coefficients C2 element information. Figure 6 (b), CP B2 The solution operation logic is consistent with the above description, except that in solving CP B2 When the circuit analog switch group S1, S3 and S6 need to be turned on, the circuit analog switch group S2, S4 and S5 need to be turned off. At the same time, the scan voltage needs to be input at port P5, and the final result is output by port P4.

[0050] Figure 7 This is a schematic diagram of a specific implementation method of the second step of the right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix provided in an embodiment of the present invention. Figure 6 BP described C2 and CP B2 The calculation results of the matrix (BP C2 ) T and (CP B2 ) T Map them to the previous mapping B respectively T and C T The array is in the form of (superscript T represents transposition operation, subscripts (+) and (-) represent positive and negative matrices respectively, and subscript f represents vertical flip operation), and the circuit analog switch group S1, S2, S3, S4 is turned on, and the circuit analog switch S5, S6 is turned off. At this time, the whole system is transformed into two independent small-scale matrix generalized inverse matrix solving circuits. The vectors y1 and y2 after the required calculation vector y are input into ports P3 and P4 respectively, and the output voltage vectors (BP) can be obtained at ports P7 and P8 respectively. C2 ) + y1 and (CP B2 ) + y2, and then the final right inverse matrix calculation result can be obtained as A + y=(BP C2 ) + y1+(CP B2 ) + y2. If you need to solve the matrix A +All elements of , the input vector y can be replaced with the scanning voltage in the form of a one-hot code and then input in blocks, and the voltage scanning operation demonstrated in the first step can be performed in sequence to obtain the matrix A + .

[0051] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A generalized inverse matrix solving circuit based on block matrices, used for solving the generalized inverse matrices of column block matrices M and N of a target real number matrix A, A=[MN], the size of matrix A is m×n and m>n, the size of matrix M is m×p, the size of matrix N is m×q, and p+q=n, characterized in that, The circuit is composed of two circuits connected by two sets of analog switches, one circuit is used for mapping and processing the block matrix M, and the other circuit is used for mapping and processing the block matrix N; Let matrix M be expressed as M=M (+) -M (-) , where M (+) =(M+|M|) / 2, M (-) =(|M|-M) / 2, M (+) and M (-) are the actual mapped matrix values, representing the positive and negative elements of the original matrix respectively; the matrix N is represented as N = N (+) -N (-) , where N (+) =(N+|N|) / 2, N (-) =(|N|-N) / 2, N (+) and N (-) are the actual mapped matrix values, representing the positive and negative elements of the original matrix respectively; The circuit of the mapping matrix M comprises 4 groups of resistive memory arrays, a plurality of analog inverters INV, a plurality of transimpedance amplifiers TIA, a plurality of operational amplifiers OPA, a plurality of input reference resistors, a plurality of analog switches and 8 input and output ports; the 4 groups of resistive memory arrays are arranged in a grid pattern, and the first two groups of resistive memory arrays respectively map M (+) and M (-) , the latter two groups map M (-) and M (+) , the mapping M in the first two groups (+) The column lines of the array are connected to the mapping M through analog inverters (-) The column lines of the array are connected to the row lines of the two arrays, and M (-) The array rows are connected to the input of the transimpedance amplifier through analog switches, and the output of the transimpedance amplifier is connected to the mapping M in the latter two arrays through analog switches. (+) The row lines of the array are then connected through analog inverters to map the two arrays into M (-) The row lines of the array of the first two groups are connected, and the column lines of the second two groups of arrays are connected and connected to the positive input terminal of the operational amplifier through an analog switch. The reverse input terminal of the operational amplifier is grounded, and the output terminal is connected to the column lines of the first two groups of arrays through an analog switch; the input and output ports are connected through the input reference resistor G0 in the common row lines of the first two groups of arrays and the common column lines of the second two groups of arrays, respectively, and M is mapped in the first two groups of arrays. (+) The column lines of the array and the last two arrays are mapped in M (+) The row lines of the array are directly connected to the input and output ports to complete the calculation operation; at the same time, in the layout, the circuit of the mapping matrix M is vertically flipped, where the mapping matrix is ​​the corresponding vertical flip matrix, and the matrix M after the vertical flip operation f , which has the same size as M, but the order of rows is reversed; The topological structure of the circuit of the mapping matrix N is completely consistent with that of the circuit of the mapping matrix M. The difference lies in the difference in the number of columns of the resistive memory array. The first two groups of resistive memory arrays map N (-) and N (+) , the latter two groups map N (+) and N (-) ; The circuit of the mapping matrix M and the circuit of the mapping matrix N are connected through two groups of analog switches, one group of analog switches is used to control the row lines connecting the first two groups of arrays in the two circuits, and the other group of analog switches is used to control the row lines connecting the last two groups of arrays in the two circuits.

2. The generalized inverse matrix solving circuit based on block matrix according to claim 1, characterized in that: The size of the resistive memory array of the circuit mapping the processing matrix M is m×p, the size of the resistive memory array of the circuit mapping the processing matrix N is m×q, and m>(p+q) is satisfied.

3. A method for solving the left inverse matrix of a generalized inverse matrix solving circuit based on a block matrix, for a target solving matrix A, solving its left inverse matrix vector product A + y, A + =(A T A) -1 A T , the matrix after column and row block is B, C, the problem to be solved is converted to A + y=[(P C1 B) + y(P B1 C) + y] T ,in, P B1 =IB(B T B) -1 B T , P C1 =IC(C T C) -1 C T , characterized in that it comprises the following steps: The first step is to map the block matrices B and C to the generalized inverse of the block matrix to solve the resistive memory array of the circuit, adjust the analog switches of the circuit, and solve the matrix P C1 B and matrix P B1 All element values ​​of C; The second step is to map the matrix P C1 B and P B1 C to block matrix generalized inverse matrix solver circuit resistive memory array, adjust circuit analog switch, solve vector value (P C1 B) + y and (P B1 C) + y.

4. The left inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix as claimed in claim 3, characterized in that: The first step of the step is to map the block matrix, specifically, to convert the positive and negative matrix values ​​of the B matrix into (+) , B (-) The resistive memory array in the circuit mapped to the mapping processing matrix M converts the positive and negative values ​​of the C matrix into the matrix value C (+) , C (-) A resistive memory array in a circuit mapped to a mapping processing matrix N; The second step of the step is to map the matrix, specifically, map P C1 The positive and negative value matrix of the B matrix (P C1 B) (+) ,(P C1 B) (-) To the first step of mapping the B matrix in the resistive memory array, map P B1 The positive and negative value matrix of the C matrix (P B1 C) (+) ,(P B1 C) (-) To the resistive memory array of the first step mapping C matrix.

5. The left inverse matrix solving working method of the generalized inverse matrix solving circuit based on the block matrix as claimed in claim 3, characterized in that: The first step of the step is to adjust the circuit analog switch to solve the matrix P C1 B and matrix P B1 C, specifically, turning off all analog switches of the circuit of mapping processing matrix B and the analog switches between the row lines of the last two groups of arrays of the two circuits, connecting all analog switches of the circuit of mapping processing matrix C and the analog switches between the row lines of the first two groups of arrays of the two circuits; mapping B in the first two groups of arrays of the circuit of mapping processing matrix B (+) The input and output ports on the column lines of the array sequentially input the voltage signals in the form of one-hot codes, and after each input, the mapping matrix C is mapped in the last two arrays of the circuit of the mapping matrix C. (+) The voltage output by the input and output ports on the row lines of the array is scaled by coefficients, and finally the matrix P is obtained. C1 The column vectors of B; After completing the matrix P C1 After calculating B, all analog switches of the circuit of the mapping processing matrix C and the analog switches between the row lines of the last two groups of arrays of the two circuits are turned off, and all analog switches of the circuit of the mapping processing matrix B and the analog switches between the row lines of the first two groups of arrays of the two circuits are turned on; Mapping C in the first two arrays of the circuit that maps the processing matrix C (+) The input and output ports on the column lines of the array sequentially input the voltage signals in the form of one-hot codes, and after each input, the mapping matrix B is mapped in the last two arrays of the circuit of the mapping processing matrix B. (+) The voltage output by the input and output ports on the row lines of the array is scaled by coefficients, and finally the matrix P is obtained. B1 The column vectors of C.

6. The left inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix as claimed in claim 3, characterized in that: The second step of the step is to adjust the circuit analog switch to solve the vector value, specifically, to turn off the analog switches between the row lines of the first two groups of arrays of the two circuits and the analog switches between the row lines of the last two groups of arrays, and connect the mapping processing matrix P C1 B's circuit and mapping processing matrix P B1 All analog switches of the circuit of C; respectively to the mapping processing matrix P C1 B's circuit and mapping processing matrix P B1 The input and output ports on the common row lines of the first two arrays of the circuit of C input the known vector y through the input reference resistor, then the voltage output by the input and output ports on the row lines of the arrays with positive values ​​in the mapping matrix of the first two arrays of the two circuits are respectively expressed as (P C1 B) + y and (P B1 C) + y, and then the final left inverse matrix calculation result is A + y=[(P C1 B) + y(P B1 C) + y] T .

7. A right inverse matrix solving method based on a generalized inverse matrix solving circuit of a block matrix, for a target solving matrix A, solving its right inverse matrix vector product A + y, A + =A T (AA T ) -1 , after the rows are divided into blocks, they are represented as A=[B T C T ] T , the y vector row is divided into blocks y = [y1 T y2 T ] T , solve the problem and convert it into A + y=[(BP C2 ) + y1(CP B2 ) + y2] T ,in, P B2 =IB T (BB T ) -1 B.P C2 =IC T (CC T ) -1 C, characterized in that it comprises the following steps: The first step is to transform the matrix B T and C T They are mapped to the resistive memory array of the block matrix generalized inverse matrix solving circuit to solve the matrix BP C2 and CP B2 ; The second step is mapping (BP C2 ) T and (CP B2 ) T Matrix to block matrix generalized inverse matrix solver circuit resistive memory array, solve vector (BP C2 ) + y and (CP B2 ) + y.

8. The right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix as claimed in claim 7, characterized in that: The first step of the step is to map the block matrix, specifically, B T The positive and negative values ​​of the matrix matrix value B T (+) , B T (-) The resistive memory array in the circuit mapped to the mapping processing matrix M is mapped to C T The positive and negative values ​​of the matrix matrix value C T (+) , C T (-) A resistive memory array in a circuit mapped to a mapping processing matrix N; The second step of the step is to map the matrix, specifically, mapping (BP C2 ) T The positive and negative values ​​of the matrix matrix value (BP C2 ) T (+) , (BP C2 ) T (-) To the first step mapping B T In the resistive memory array of the matrix, the mapping (CP B2 ) T The positive and negative values ​​of the matrix (CP B2 ) T (+) , (CP B2 ) T (-) To the first step mapping C T In a resistive memory array of a matrix.

9. The right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix as claimed in claim 7, characterized in that: The first step of the step is to adjust the circuit analog switch, specifically, to turn off the mapping processing matrix B T All analog switches of the circuit and the analog switches between the rows of the first two groups of arrays of the two circuits are connected to the mapping processing matrix C T All analog switches of the circuit and the analog switches between the row lines of the two groups of arrays after the two circuits; in the mapping processing matrix C T The input and output ports on the common row lines of the first two arrays of the circuit sequentially input the voltage signals in the form of one-hot codes through the input reference resistors, and after each input, the mapping processing matrix B T The input and output ports on the common column lines in the last two arrays of the circuit are scaled by the output voltage obtained by the reference resistor to obtain the matrix BP C2 The column vectors of ; In completing the matrix BP C2 After calculation, the mapping matrix C is turned off. T All analog switches of the circuit and the analog switches between the rows of the first two groups of arrays of the two circuits are connected to the mapping processing matrix B T All analog switches of the circuit and the analog switches between the row lines of the two groups of arrays after the two circuits; in the mapping processing matrix B T The input and output ports on the common row lines of the first two arrays of the circuit sequentially input the voltage signals in the form of one-hot codes through the input reference resistors. After each input, the mapping processing matrix C T The input and output ports on the common column lines in the last two arrays of the circuit are scaled by the output voltage obtained by the reference resistor to obtain the matrix CP B2 The column vectors of .

10. The right inverse matrix solving method of the generalized inverse matrix solving circuit based on the block matrix as claimed in claim 7, characterized in that: The second step of the step is to adjust the circuit analog switch to solve the vector value, specifically, to turn off the analog switches between the row lines of the first two groups of arrays of the two circuits and the analog switches between the row lines of the last two groups of arrays, and connect the mapping processing matrix P C1 B's circuit and mapping processing matrix P B1 All analog switches of the circuit of C; respectively to the mapping processing matrix P C1 B's circuit and mapping processing matrix P B1 The input and output ports on the common column lines of the last two arrays of the circuit of C input the known vectors y1 and y2 through the reference resistor. Then the voltage output by the input and output ports on the row lines of the arrays with positive values ​​in the mapping matrix of the last two arrays of the two circuits are respectively expressed as (BP C2 ) + y1 and (CP B2 ) + y2, and then the final right inverse matrix calculation result is A + y=(BP C2 ) + y1+(CP B2 ) + y2.

Images