Method for automatically pasting capacitor in electronic design software

Abstract

The invention relates to the technical field of electronic design automation, and particularly discloses a method for automatically pasting a capacitor in electronic design software, which comprises the following steps: placing a chip in a board card of EDA software, and carrying out fanout processing on each non-Dummy pin of the chip; the method comprises the following steps: inputting a chip refdes to which a capacitor needs to be automatically pasted on a user interface of an automatic tool, and segmenting a plurality of refdes by using '',''; the system automatically calls and executes related EDA programs; searching the chip in the board according to the input refdes, and reporting an error if the chip is not found; and if the chip is found, judging whether the non-Dummy pins of the chip are all fanout, and if the non-fanout pins exist, reporting an error. According to the invention, the time for manually placing the capacitor is saved, the working efficiency of electronic design is improved, and the design cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA), and in particular to a method for automatically attaching capacitors in electronic design software. Background Art

[0002] In the field of electronic design, connecting the power pin of a chip to a decoupling capacitor is a key step to ensure stable operation of the circuit. As the complexity of electronic circuits continues to increase, the number of decoupling capacitors required by chips is increasing. In the process of circuit board design, manually placing these capacitors has become an extremely tedious and time-consuming task. In some complex designs, it may even take more than a whole day to complete the placement of capacitors, which greatly reduces design efficiency and increases design costs.

[0003] At present, although most EDA design software is equipped with secondary development tools, and its built-in language can realize some design automation functions, when dealing with complex design tasks, relying solely on the built-in language for development will be limited by the EDA software itself, and it is easy to run stuck. This makes the development of efficient and stable automated capacitor attachment tools a problem that needs to be solved urgently. Up to now, there has not been a customized tool that can realize the function of automated capacitor attachment. The present invention aims to fill this gap and provide an efficient solution for electronic design work. Summary of the invention

[0004] The purpose of the present invention is to provide a method for automatically attaching capacitors in electronic design software to solve the following technical problems: Manual placement of capacitors is inefficient, and there are freezes when using the built-in language of EDA software to develop complex applications. This allows you to quickly and accurately place capacitors automatically in electronic design software, improving electronic design work efficiency.

[0005] The purpose of the present invention can be achieved through the following technical solutions: A method for automatically attaching capacitors in electronic design software comprises the following steps: Preparation steps: Place the chip in the board of the EDA software and perform fanout processing on each non-dummy pin of the chip; Steps for inputting chip identification: input the chip refdes that needs to be automatically attached to the capacitor in the user interface of the automation tool, and separate multiple refdes with ","; EDA program execution steps: The system automatically calls and executes related EDA programs; Chip search and status judgment steps: Search for the chip in the board according to the input refdes. If not found, an error is reported. If the chip is found, determine whether all non-dummy pins of the chip have fanout. If there are pins that have not fanout, an error is reported.

[0006] As a further solution of the present invention: it also includes an information extraction step, and the information extraction step includes: Find PowerNets sub-step: Find the pin information belonging to the power according to the attributes of the chip pin and store it in a temporary list; Output Power_cap_net.txt file sub-step: traverse the temporary list, find the capacitor connected to powernet, and output the Power_cap_net.txt file containing IC_name, Power_net, Cap_name, Cap_power_pin_number, and Cap_size information; Output ic_information.txt file sub-steps: Find the shape of the specified chip in the EDA software packagegeometryclass to obtain the chip package size, export the IC_neme, Via_net_name, Via_location, and Via_size information of all vias in the chip package area, and output it as an ic_information.txt file.

[0007] As a further solution of the present invention: the capacitance parameter calculation step includes: Calculate capacitor size sub-steps: According to the Via_location and Via_size information in the ic_information.txt file, simulate the via location and size, calculate the distance between vias and count them into a distance array, and determine the capacitor size that can be placed based on the distance array; Sub-steps for calculating the number of capacitors: Count the number of caps of different powernets according to Power_cap_net.txt, recorded as Q_cap; count the number and location information of vias of powernet in combination with Power_cap_net.txt and ic_information.txt, find out whether the adjacent vianet is GND, and define the vias in groups of two as Gp_via; if Q_cap≤Gp_via, the calculated number is the actual number of caps; if Q_cap>Gp_via, offset the caps to increase the number of caps.

[0008] As a further solution of the present invention: it also includes the step of generating a clip file: based on the calculated capacitor size and quantity information, a clip file that can be imported by EDA software is generated, the clip file defines the origin coordinates of the board as the location of the via in the upper left corner of the chip, capacitors of appropriate sizes are placed in the via area inside the chip, the remaining capacitors are evenly placed around the chip according to the power position, and the spacing between caps is arranged according to different sizes.

[0009] As a further solution of the present invention: it also includes a wiring connection step: importing the clip file into the board, generating flying wires between the power and ground pins of the cap and the adjacent pins of the same net, using a command to call the wiring mode, and connecting the flying wire coordinate points with cline.

[0010] As a further solution of the present invention: in the EDA program execution step, the main program is embedded in the EDA software, and starts to execute after the board card that needs automatic capacitor bonding is opened, without the need to open the specified board card additionally.

[0011] As a further solution of the present invention: in the sub-step of calculating the capacitor size, when simulating the via position and size, it is actually achieved by building a two-dimensional array instead of constructing an actual model.

[0012] As a further solution of the present invention: when the cap is offset, it is assumed that the power via coordinates are (x, y), the via spacing is D, and the offset position coordinates are (xD / 2, yD / 2).

[0013] As a further solution of the present invention: in the step of generating a clip file, usually, the size of the capacitors placed around the chip is slightly larger than the size of the capacitors placed in the via area inside the chip.

[0014] Beneficial effects of the present invention: The present invention combines the built-in development language of EDA with external development tools (such as Python) to give full play to the advantages of both, and avoids the jamming phenomenon when only using the built-in language of EDA to develop complex applications. The automatic capacitor placement method can quickly and accurately complete the capacitor placement work, greatly saving the time required for manual placement of capacitors, improving the work efficiency of electronic design, and reducing design costs. At the same time, the method has good versatility and can be applied to a variety of EDA software, providing an efficient and convenient design method for the electronic design industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will be further described below in conjunction with the accompanying drawings.

[0016] Figure 1It is a schematic diagram of the process of inputting chip information before executing the EDA program in the present invention; Figure 2 It is a schematic diagram of the process of executing the EDA program in the present invention; Figure 3 It is a schematic diagram of the flow of capacitance calculation after executing the EDA program in the present invention; Figure 4 It is a schematic diagram of the position and size of via in the present invention; Figure 5 It is a schematic diagram of the final placement of capacitors in the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] The present invention is a method for automatically attaching capacitors in electronic design software, comprising the following steps: Preparation: Before starting the operation, the designer needs to place the chip in the board of the EDA software and perform fanout processing on each non-dummy (virtual or empty) pin.

[0019] Enter chip information: Figure 1 As shown, enter the chip refdes (Reference Designator, reference identifier, which is also the unique name of the device defined in the figure) to which the capacitor needs to be automatically attached in the user interface. You can enter one or more refdes. Multiple refdes are separated by ",", such as U1, U2, U3.

[0020] Execute EDA program: Figure 2 As shown in the figure, when the refdes input is completed, the system automatically calls and executes the relevant EDA program. Since the main program is embedded in the EDA software, it starts to execute after opening the board that needs to automatically paste the capacitor, without opening the specified board.

[0021] Select the chip and determine the status: According to the refdes entered by the user, search for the corresponding chip in the board. If the chip is not found, an error window pops up prompting "Chip not found in the board"; if the chip is found, further determine whether all non-dummy pins of the chip have completed fanout. If there are pins that have not fanouted, an error window pops up, for example, "A1 pin of U1 chip has not fanouted."

[0022] Extract chip and capacitor information: When the chip is in normal state, extract chip and capacitor information.

[0023] Find Power Nets: According to the different attributes of the chip pins, determine the type of signal pins, find the pin-related information belonging to power, and store it in a temporary list.

[0024] Output Power_cap_net.txt file: Use foreach to traverse the temporary list containing power net and find the capacitor connected to it. The output Power_cap_net.txt file is as follows: IC_neme;Power_net;Cap_name;Cap_power_pin_number; Cap_size; U1; VDD_I; C1; 1; 0402; U1; VDD_I; C2; 1; 0402; U1; VDD_I; C3; 1; 0402; U1; VDD_I; C4; 1; 0402; U1; VDD_I; C5; 1; 0402; U1; VDD I; C6; 1; 0402; U1; VDD_II; C7; 1; 0402; U1; VDD II; C8; 1; 0402; U1; VDD_II; C9; 1; 0402; U1; VDD_II; C10; 1; 0402; U1; VDD_II; C11; 1; 0402; Contains information such as IC_name (Integrated Circuit Name), Power_net (PowerNetwork), Cap_name (Capacitor Name), Cap_power_pin_number (capacitor power pin number), and Cap_size (Capacitor Size). foreach is a loop structure used in programming to traverse the elements in a collection or array. Its main purpose is to simplify the traversal operation of iterable objects and make the code more concise and easy to read. The specific implementation and syntax of foreach vary in different programming languages.

[0025] Output ic_information.txt file: Since the capacitor is attached to the back of the chip, only the via (via, a hole used to achieve electrical connection between different layers in a multilayer printed circuit board (PCB)) information of the pin fan-out needs to be considered. The chip package size is obtained by finding the shape (package style) of the specified chip in the EDA software packagegeometryclass, and then the basic information of all vias in the chip package area is exported, including IC_name, Via_net_name (Via Network Name, i.e. via network name), Via_location (Via Location, i.e. via location), Via_size (via size), and the output is ic_information.txt file, as shown below: IC_neme;Via_net_name;Via_location; Via_size; U1; GND; (-42.0000 134.2244); 012PO20RND; U1;TGO_A_DSEL6;(-41.0000 134.2244); 012PO20RND; U1;TGO_A_I021;(-40.0000 134.2244); 012P020RND; U1;TGO_A_IO5;(-39.0000 134.2244); 012PO20RND; U1;TGO_A_IO23;(-38.0000 134.2244); 012PO20RND; U1; GND; (-37.0000 134.2244); 012PO2ORND; U1;TGO_A_IO25;(-36.0000 134.2244); 012PO20RND; U1;TGO_Al09;(-35.0000 134.2244); 012PO2ORND; like Figure 3 As shown, calculate the capacitor size and quantity: Calculate the capacitor size: Based on the Via_location and Via_size in the ic_information.txt file, simulate the following Figure 4 The schematic diagram of via positions and sizes shown (actually only a two-dimensional array needs to be built); According to the summarized coordinate array, from left to right and from top to bottom, the distance between each via can be calculated, and the different distances can be counted and counted into another distance array. For example, there are 1400 vias with a distance of 1mm, 200 vias with a distance of 2mm, and 30 vias with a distance of 3mm. Based on the distance array above, we can calculate the size information of the capacitors that can be placed.

[0026] Distance ≤ 0.6mm: 0201; 0.6mm<distance≤1mm:0201,0402; 1mm<distance≤1.6mm:0402,0603; 1.6mm<distance≤2mm:0402,0603,0805; Generally speaking, the size of capacitors within the chip should not be too large. Try not to use capacitors larger than 0805. If the distance is more than 2mm, try to use capacitors smaller than 0805. When the capacitors are full, consider whether there is room for capacitors larger than 0805.

[0027] Calculate the number of capacitors: First, count the number of caps (capacitors) of different power nets according to the Power_net in Power_cap_net.txt (recorded as Q_cap); Then, according to the Power_net in Power_cap_net.txt, obtain all the power nets of the required chip, and combine the Via_net_name and Via_location in ic_information.txt to count the number and location information of the vias of these power nets. Since each cap has two pins, one connected to the power net and the other connected to the ground net (ground network), it is necessary to find out whether the adjacent via net is GND (Ground, indicating grounding), and define the vias in pairs as Gp_via.

[0028] Compare the number of caps and vias: If Q_cap≤Gp_via, it means that it is sufficient to attach the cap directly to the via. In this case, the calculated number is the actual number of caps corresponding to this power net; If Q_cap>Gp_via, it means that after the cap is attached to the via, there is still a part that has no suitable via to attach to it, and the cap needs to be offset to fit. The offset method is as follows: Assuming that the coordinates of the power via are defined as (x, y), and the distance between vias is D, the position coordinates that need to be offset are (xD / 2, yD / 2). The number of caps that can be obtained by this offset method can increase the maximum number of vias on the horizontal or vertical axis of this power net; In electronic circuit design, offset placement refers to placing capacitors at a certain offset instead of in the usual neat arrangement.

[0029] Output clip file: Generate a clip file that can be imported by EDA software based on the calculated capacitor size and quantity information. The clip file needs to define the origin coordinates of the board (the location of the via in the upper left corner of the chip), place the capacitors of appropriate size in the via area inside the chip, and place the remaining capacitors evenly around the chip according to the power position, and arrange the spacing between the caps according to different sizes. Usually, the capacitors around the edges are slightly larger than those in the middle.

[0030] In EDA software, sometimes it is necessary to transfer similar information between different boards, and the file used is the clip file; For example, the same A board has many signal layers. Engineer A needs to complete the routing of sig01 layer, and Engineer B needs to complete the routing of sig02 layer. When they finish their work, they need to merge these lines together, so they use the tools provided by EDA to export these lines into clip format for merging.

[0031] Of course, not only the routing, but any designable part of the board can be imported and exported.

[0032] Route connection: After the generated clip file is imported into the board, the power and ground pins of the cap will generate flying wires with the adjacent pins of the same net. Use the command call to open the route mode, connect the coordinate points of the generated flying wires with cline (route), and complete the final placement of the capacitor, such as Figure 5 shown.

[0033] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A method for automatically attaching capacitors in electronic design software, characterized in that: The following steps are involved: Preparation steps: Place the chip in the board of the EDA software and perform fanout processing on each non-dummy pin of the chip; Steps for inputting chip identification: input the chip refdes that needs to be automatically attached with capacitors in the user interface of the automation tool, and separate multiple refdes with ","; EDA program execution steps: The system automatically calls and executes related EDA programs; Chip search and status judgment steps: Search for the chip in the board according to the input refdes. If not found, an error is reported. If the chip is found, determine whether all non-dummy pins of the chip have fanout. If there are pins that have not fanout, an error is reported.

2. A method for automatically attaching capacitors in electronic design software according to claim 1, characterized in that: The information extraction step is also included, and the information extraction step includes: Find Power Nets sub-step: Find the pin information belonging to the power according to the attributes of the chip pin and store it in a temporary list; Output Power_cap_net.txt file sub-step: traverse the temporary list, find the capacitor connected to powernet, and output the Power_cap_net.txt file containing IC_name, Power_net, Cap_name, Cap_power_pin_number, and Cap_size information; Output ic_information.txt file sub-steps: Find the shape of the specified chip in the EDA software packagegeometryclass to obtain the chip package size, export the IC_neme, Via_net_name, Via_location, and Via_size information of all vias in the chip package area, and output it as an ic_information.txt file.

3. The method for automatically attaching capacitors in electronic design software according to claim 1, characterized in that: The capacitance parameter calculation step comprises: Calculate capacitor size sub-steps: According to the Via_location and Via_size information in the ic_information.txt file, simulate the via location and size, calculate the distance between vias and count them into a distance array, and determine the capacitor size that can be placed based on the distance array; Sub-steps for calculating the number of capacitors: Count the number of caps of different powernets according to Power_cap_net.txt, recorded as Q_cap; count the number and location information of vias of powernet in combination with Power_cap_net.txt and ic_information.txt, find out whether the adjacent vianet is GND, and define the vias in groups of two as Gp_via; if Q_cap≤Gp_via, the calculated number is the actual number of caps; if Q_cap>Gp_via, offset the caps to increase the number of caps.

4. The method for automatically attaching capacitors in electronic design software according to claim 1, characterized in that: It also includes the step of generating a clip file: based on the calculated capacitor size and quantity information, a clip file that can be imported by the EDA software is generated. The clip file defines the origin coordinates of the board as the location of the via in the upper left corner of the chip. Capacitors of appropriate sizes are placed in the via area inside the chip. The remaining capacitors are evenly placed around the chip according to the power position, and the spacing between caps is arranged according to different sizes.

5. The method for automatically attaching capacitors in electronic design software according to claim 1, characterized in that: It also includes the wiring connection steps: import the clip file into the board, generate flying wires between the power and ground pins of the cap and the adjacent pins of the same net, use the command to call the wiring mode, and connect the flying wire coordinate points with cline.

6. The method for automatically attaching capacitors in electronic design software according to claim 1, characterized in that: In the EDA program execution step, the main program is embedded in the EDA software and starts to execute after the board card that needs to automatically attach capacitors is opened, without the need to open the specified board card additionally.

7. The method for automatically attaching capacitors in electronic design software according to claim 3, characterized in that: In the sub-step of calculating the capacitor size, when simulating the via position and size, it is actually achieved by building a two-dimensional array instead of constructing an actual model.

8. The method for automatically attaching capacitors in electronic design software according to claim 3, characterized in that: When the cap is offset, assuming that the power via coordinates are (x, y), the via spacing is D, the position coordinates after offset placement are (xD / 2, yD / 2).

9. The method for automatically attaching capacitors in electronic design software according to claim 4, characterized in that: In the step of generating a clip file, generally, the size of the capacitors placed around the chip is slightly larger than the size of the capacitors placed in the via area inside the chip.

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