A general circuit logic diagram layout method

Abstract

The application discloses a general circuit logic diagram layout method, comprising the following steps: S1, acquiring the relative positions of all circuit diagram nodes of a to-be-optimized circuit and the connection relationship between the circuit diagram nodes and output ports and input ports through a circuit analysis module; S2, positioning each circuit diagram node according to the connection relationship between the circuit diagram nodes and the input ports and the input ports; S3, adding virtual nodes to the to-be-optimized circuit, the virtual nodes being arranged between two circuit diagram nodes which have a direct connection relationship and whose connection paths cross at least one column; S4, positioning each column of circuit diagram nodes according to the number of virtual nodes in the predecessor nodes of the circuit diagram nodes; and S5, removing all virtual nodes and restoring the connection relationship between the circuit diagram nodes and the output ports and the input ports. The layout algorithm is not limited to specific circuits and can be universally applied to the design of analog circuits and digital circuits, thereby simplifying the layout problem in circuit design.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, and particularly relates to a general circuit logic diagram layout method. BACKGROUND

[0002] With the rapid development of electronic technology, as the core components of modern electronic devices, analog circuits and digital circuits have increasing design complexity and integration. Engineers need to frequently process circuit diagrams containing a large number of components, interconnections and logic levels in the design process, and effective circuit diagram display layout is crucial for understanding circuit working principles, circuit analysis, troubleshooting, thereby improving design efficiency and shortening product launch cycle.

[0003] The traditional circuit diagram display layout method has the limitation of contradiction between visual effect and information density: in the limited screen space, how to balance the placement density of circuit diagram nodes and the amount of information needed for design is a challenge. Too concentrated placement of circuit diagram components may lead to overall view confusion, making it difficult to quickly identify key paths and connections between components; too sparse layout may miss important details, increasing the difficulty of review and understanding. SUMMARY

[0004] In view of the problem in the prior art that the traditional circuit diagram display layout method has overall view confusion and is difficult to quickly identify key paths and connections between components, the present application provides a general circuit logic diagram layout method.

[0005] The technical scheme of the present application is to provide a general circuit logic diagram layout method, which comprises:

[0006] Step S1: obtaining the relative positions of all circuit diagram nodes of a to-be-optimized circuit and the connection relationships between the circuit diagram nodes and output ports and input ports through a circuit analysis module;

[0007] Step S2: positioning each circuit diagram node according to the connection relationships between the circuit diagram nodes and the input ports and the input ports;

[0008] Step S3: adding a virtual node to the to-be-optimized circuit, the virtual node being arranged between two circuit diagram nodes having direct connection relationship and at least crossing one column;

[0009] Step S4: positioning each column of circuit diagram nodes according to the number of virtual nodes in the predecessor nodes of the circuit diagram nodes;

[0010] Step S5: removing all virtual nodes and restoring the connection relationships between the circuit diagram nodes and the output ports and the input ports.

[0011] Furthermore, step S2 includes:

[0012] Step S201: Set the input port as the first column and the output port as the second to last column;

[0013] Step S202: Starting from any input port, sequentially search for successor nodes and set a candidate set for all successor nodes. The value of the successor node in the candidate set is the value of the previous circuit diagram node connected to it plus 1.

[0014] Step S203: The column positioning value of the circuit diagram node is set according to the value in the corresponding candidate set.

[0015] Furthermore, step S203 includes:

[0016] When the circuit diagram node has only one predecessor node, the column positioning value of the circuit diagram node is a value taken from the corresponding candidate set.

[0017] When a circuit diagram node has at least two predecessor nodes, the column positioning value of the circuit diagram node is the maximum value in the corresponding candidate set.

[0018] Furthermore, step S4 includes:

[0019] Step S401: Detect the number of virtual nodes in the predecessor nodes of the circuit diagram nodes;

[0020] Step S402: When the number of virtual nodes is 0, the row positioning value of the circuit diagram node is optimized based on the row positioning value of its predecessor node;

[0021] When the number of virtual nodes is 1, the row positioning value of the circuit diagram node is set to the row positioning value of the virtual node;

[0022] When there are at least two virtual nodes, the row positioning value of the circuit diagram node is optimized based on the row positioning values ​​of all virtual nodes.

[0023] Furthermore, the row positioning values ​​of the circuit diagram nodes satisfy the calculation model:

[0024]

[0025] Where new_row is the row positioning value of the circuit diagram node, and row i Let k be the row number of the i-th predecessor node of the circuit diagram node, and k be the number of predecessor nodes of the circuit diagram node.

[0026] Furthermore, step S4 also includes:

[0027] Step S403: For any circuit diagram node that has neither a predecessor node nor a successor node, set its column as the next column of the output port, and arrange all circuit diagram nodes that have neither a predecessor node nor a successor node in sequence under this column.

[0028] Furthermore, step S4 also includes:

[0029] Step S404: Obtain the output ports of all circuit diagram nodes in the same column, and assign values ​​to all output ports in sequence according to a preset order;

[0030] Step S405: Calculate the port weight value of the output port of each of the circuit diagram nodes;

[0031] Step S406: Obtain the connection relationship between all circuit diagram nodes in the next column and the output port, calculate the sum of the port weight values ​​of the output ports connected to them, and set the row positioning value of all circuit diagram nodes in the column according to the sum of the port weight values.

[0032] Furthermore, the calculation model for port weight values ​​is as follows:

[0033]

[0034] Among them, port_weight (p,q) (i) represents the port weight value of the output port with index i in row p and column q, and port_num represents the total number of output ports of the current circuit diagram node.

[0035] Compared with the prior art, the present invention has at least the following beneficial effects:

[0036] 1. Versatility: The layout algorithm of this invention is not limited to a specific type of circuit and can be widely applied to the design stage of analog and digital circuits, greatly simplifying the layout problem in circuit design in multiple fields to meet rapidly changing market and technological demands.

[0037] 2. Flexibility and customizability: This invention adopts a unique modular design concept, dividing the overall layout process into a basic framework and multiple independent and undependent steps. Each step can operate as a separate functional unit. The decoupling between the steps makes this layout algorithm highly flexible and scalable.

[0038] 3. More engineer-friendly design: The algorithm has a unique ability to handle nodes in circuit diagrams that have no predecessor or successor relationship. By arranging these nodes reasonably, the entire circuit diagram can look cleaner and more orderly, which is beneficial for engineers to analyze the circuit and troubleshoot faults. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is the overall control flowchart of the present invention;

[0041] Figure 2 This is a schematic diagram of the circuit diagram nodes after column positioning according to the present invention;

[0042] Figure 3 and Figure 4 The images shown are schematic diagrams and effect diagrams after adding virtual nodes in this invention.

[0043] Figure 5 This is a schematic diagram of the circuit diagram nodes after row positioning when the number of virtual nodes is 0 in this invention;

[0044] Figure 6 This is a schematic diagram showing the row positioning of the circuit diagram nodes when the number of virtual nodes is 1 in this invention.

[0045] Figure 7 This is a schematic diagram showing the row positioning of the circuit diagram nodes when there are at least two virtual nodes in this invention;

[0046] Figure 8 This is a schematic diagram of row positioning based on port weight values ​​in this invention. Detailed Implementation

[0047] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0048] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0049] The principles and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0050] Traditional circuit diagram layout methods suffer from a trade-off between visualization effectiveness and information density: balancing the density of circuit diagram nodes with the amount of information required for the design within limited screen space is a challenge. Overly concentrated circuit diagram components can lead to a cluttered overall view, making it difficult to quickly identify critical paths and relationships between components; conversely, an overly sparse layout may miss important details, increasing the difficulty of reviewing and understanding the information.

[0051] To address the above problems, this invention proposes a general circuit logic layout method, comprising:

[0052] Step S1: Using the circuit analysis module, obtain the relative positions of all circuit diagram nodes of the circuit to be optimized, as well as the connection relationships between the circuit diagram nodes and the output and input ports;

[0053] Step S2: Based on the connection relationship between the circuit diagram nodes and the input ports, perform column positioning for each circuit diagram node;

[0054] Step S3: Add a virtual node to the circuit to be optimized. The virtual node is set between two circuit diagram nodes that are directly connected and whose connection path spans at least one column.

[0055] Step S4: Based on the number of virtual nodes in the predecessor nodes of each circuit diagram node, perform row positioning for each column of circuit diagram nodes;

[0056] Step S5: Remove all virtual nodes and restore the connection relationships between the circuit diagram nodes and the output and input ports.

[0057] Please see Figure 1 In the flowchart above, "circuit analysis, obtaining circuit diagram nodes and connection relationships" is also step S1 in the general circuit logic layout method above.

[0058] The "column positioning of each circuit diagram node through connection relationship" in the above flowchart is also step S2 in the above circuit logic layout method.

[0059] In the flowchart above, "adding virtual nodes" is also step S3 in the circuit logic layout method described above.

[0060] The above flowchart includes "Optimization of the placement order of circuit diagram nodes in each column (all predecessor nodes are non-virtual nodes)", "Optimization of the placement order of circuit diagram nodes in each column (only one circuit diagram node in the predecessor node is a virtual node)", "Optimization of the placement order of circuit diagram nodes in each column (multiple virtual nodes in the predecessor node)", "Optimization of the placement order of independent nodes with neither predecessor nor successor nodes", and "Optimization of the placement order of circuit diagram nodes considering port weight values", which is also step S4 in the above circuit logic layout method.

[0061] The "remove virtual node, restore connection relationship, start wiring" in the above flowchart is also step S5 in the above circuit logic layout method;

[0062] based on Figure 1 As shown in the flowchart, this invention optimizes the placement order of circuit diagram nodes in each column by setting settings for the cases based on virtual nodes in the predecessor node, the cases with neither predecessor nor successor nodes, and the cases optimized based on port weight values. The process of optimizing the placement of circuit diagram nodes in each of the above cases is independent of each other, and each step can operate as a separate functional unit. The decoupling characteristics between the steps make this layout algorithm highly flexible and scalable.

[0063] The steps of the present invention will be described below with reference to the accompanying drawings;

[0064] Step S1: Using the circuit analysis module, obtain the relative positions of all circuit diagram nodes of the circuit to be optimized, as well as the connection relationships between the circuit diagram nodes and the output and input ports;

[0065] Step S1 here is implemented through the circuit analysis module and will not be described in detail here;

[0066] Step S2: Based on the connection relationship between the circuit diagram nodes and the input ports, perform column positioning for each circuit diagram node;

[0067] Here, step S2 above can be divided into three steps, namely:

[0068] Step S201: Set the input port to the first column and the output port to the second-to-last column;

[0069] Step S202: Starting from any input port, sequentially search for successor nodes and set a candidate set for all successor nodes. The value of a successor node in the candidate set is the value in the candidate set of the previous circuit diagram node connected to it plus 1.

[0070] Step S203: The column positioning value of the circuit diagram node is set according to the value in the corresponding candidate set.

[0071] Step S203 further has two possible scenarios based on the number of predecessor nodes:

[0072] When a circuit diagram node has only one predecessor node, the column positioning value of the circuit diagram node is taken from the corresponding candidate set.

[0073] When a graph node has at least two predecessor nodes, the column position value of the graph node is the maximum value in the corresponding candidate set.

[0074] Appendix Figure 2 The relative positions of all circuit diagram nodes of the circuit to be optimized, as well as the connection relationships between the circuit diagram nodes and the output and input ports, are obtained by the circuit analysis module. It can be seen that the circuit to be analyzed is arranged in a matrix form with n columns of circuit diagram nodes.

[0075] In this diagram, column 0 represents the input port of the circuit to be optimized, column n-1 represents the output port of the circuit to be optimized, and each rectangle in columns 1 to n-2 represents a circuit diagram node. The lines connecting the input port to the circuit diagram node, the lines connecting the output port to the circuit diagram node, and the lines between each circuit diagram node are used to represent the connection relationship between the input port, the output port, and the circuit diagram node.

[0076] In this article, a predecessor node refers to a node that is connected to the current circuit diagram node and is closer to the input port, and a successor node refers to a node that is connected to the current circuit diagram node and is closer to the output port.

[0077] If correct Figure 2 For node 4 in the circuit diagram, the connected nodes are node 3 and node 6. Here, node 3 is closer to the input port side, so node 3 is the predecessor node of node 4. Node 6 is closer to the output port side, so node 6 is the successor node of node 4.

[0078] The following describes step S201 of the present invention. Please refer to [link / reference]. Figure 2 It has n columns of circuit diagram nodes, where the 0th column is the first column in step S201, and the (n-1)th column is the second to last column in step S201;

[0079] For step S202, which is the process of setting the candidate set, the specific process is as follows: starting from column 0, the successor node is searched sequentially according to the connection relationship. For each successor node found, an element is added to the above candidate set. The value of the element is the maximum value in the candidate set of the column positioning of the predecessor node plus 1.

[0080] like Figure 2 As shown, starting from node 0 and searching backwards, the candidate set for column positioning of node 0 is set to {0}. The successor node of node 0 is node 3. Then, according to the logic in step S202, the candidate set of node 3 is set to {1}. The successor nodes are traversed backwards in turn, and the candidate sets for column positioning of node 4 are {2}, the candidate sets for column positioning of node 6 are {3}, and the candidate sets for column positioning of node 8 are {4}.

[0081] After searching for node 0 in column 0, the search continues sequentially from the next node in column 0, i.e., node 1. Since this is a new search process, the candidate set for column positioning of node 1 is set to {0}. The successor node of node 1 is node 6. Since a candidate set for column positioning of node 6 was already set in the first search process, {3}, in the second search process, the candidate set for column positioning of node 6 is {1}. At this time, the current candidate set is directly added to the candidate set of the first search, so the candidate set for column positioning of node 6 is {3, 1}. Similarly, the candidate set for column positioning of the next node 8 is {4, 2}.

[0082] After finding all the nodes using the above method, that is, after completing step S202, step S203 needs to be executed to perform column positioning for each node.

[0083] Based on the number of elements in the candidate set of each node, we can know how many predecessor nodes the node has. For example, for node 6, its candidate set is {3, 1}, so we can know that node 6 has 2 predecessor nodes. Similarly, based on the candidate set of node 3 being {1}, we can know that node 3 has 1 predecessor node.

[0084] In this invention, the first case of step S203 is the case of having only one predecessor node. In this case, the column positioning value of the circuit diagram node is set to the value of the corresponding candidate set. For example, for node 3, its subsequent set only has the element 1, so the final column positioning value of node 3 is 1. Similarly, the final column positioning value of node 0 is 0.

[0085] The second case is when there are at least two predecessor nodes. In this case, the column positioning value of the circuit diagram node is set to the maximum value in the corresponding subsequent column set. For example, for node 6, its candidate set is {3, 1}, which contains two elements, 3 and 1. The maximum value in the candidate set is 3, so the final column positioning value of node 6 is 3. Similarly, the final column positioning value of node 8 is 4.

[0086] After performing step S2 above, virtual nodes need to be added to the circuit to be optimized in order to locate the nodes in the circuit diagram. At this time, step S3 needs to be performed.

[0087] Step S3: Add a virtual node to the circuit to be optimized. The virtual node is set between two circuit diagram nodes that are directly connected and whose connection path spans at least one column.

[0088] Please see Figure 3It can be seen that the nodes with direct connections are node 0 and node 3, node 3 and node 4, node 4 and node 6, node 6 and node 8, node 1 and node 6, node 2 and node 5, and node 5 and node 7.

[0089] Further filtering by connecting two circuit diagram nodes that span at least one column yields three combinations: node 1 and node 6 spanning columns 1 and 2, node 2 and node 5 spanning column 1, and node 5 and node 7.

[0090] When adding virtual nodes, you need to add virtual nodes to the columns that are spanned as described above, such as... Figure 3 It can be seen that the added virtual nodes are 1-1, 1-2, and 2-1 respectively (here, multiple columns are actually spanned between node 5 and node 7; node 5 is in the 2nd column, and node 7 is in the (n-1)th column). Figure 3 For ease of understanding, the middle column has been omitted. Therefore, there may be more than one virtual node that needs to be added between node 5 and node 7. Figure 3 (This was not indicated in the text).

[0091] After completing the above process of adding virtual nodes, it is necessary to perform row positioning on the circuit diagram nodes, which requires step S4.

[0092] Step S4: Based on the number of virtual nodes in the predecessor nodes of each circuit diagram node, perform row positioning for each column of circuit diagram nodes;

[0093] Step S4 above includes:

[0094] Step S401: Detect the number of virtual nodes in the predecessor nodes of the circuit diagram nodes;

[0095] Step S402: When the number of virtual nodes is 0, the row positioning value of the circuit diagram node is optimized based on the row positioning value of its predecessor node;

[0096] When the number of virtual nodes is 1, the row positioning value of the circuit diagram node is set to the row positioning value of the virtual node;

[0097] When there are at least two virtual nodes, the row positioning value of the circuit diagram node is optimized based on the row positioning values ​​of all virtual nodes.

[0098] The row positioning values ​​of the above circuit diagram nodes satisfy the calculation model:

[0099]

[0100] Where new_row is the row position value of the circuit diagram node, and row i Let k be the row number of the i-th predecessor node of the circuit diagram node, and k be the number of predecessor nodes of the circuit diagram node.

[0101] The above step S402 is divided into three cases: the number of virtual nodes in the predecessor node of the circuit diagram node is 0, the number of virtual nodes in the predecessor node of the circuit diagram node is 1, and the number of virtual nodes in the predecessor node of the circuit diagram node is multiple.

[0102] In the first case, all predecessor nodes of the circuit diagram nodes are non-virtual nodes. Figure 5 Taking the case of node 6 as an example, there are three predecessor nodes: node 3, node 4 and node 5. The row positioning value of node 3 is 0, the row positioning value of node 4 is 1, and the row positioning value of node 5 is 2. Here, node 3 is set as the first predecessor node, node 4 as the second predecessor node, and node 5 as the third predecessor node.

[0103] Substituting into the above calculation model, we get: new_row = (0 + 1 + 2) / 3 = 1;

[0104] That is, after the above optimization scheme, the row positioning value of node 6 becomes 1, and the re-optimized circuit diagram is as follows: Figure 5 The right side.

[0105] In the second case, the predecessor node has only one virtual node. The row positioning value of the circuit diagram node is directly set to the row positioning value of the virtual node. Therefore, there is no need to determine the new row positioning value through the above calculation model. The row positioning value of the circuit diagram node can be determined by directly determining the row positioning value of the virtual node.

[0106] by Figure 6 Taking the following scenario as an example, node 4 is the node to be optimized, and its predecessor nodes are node 3 and node 1-2. Here, node 1-2 is a virtual node, and there is only one virtual node among the predecessor nodes of node 4. Therefore, the row positioning value of node 4 is directly set to be the same as the row positioning value of the virtual node 1-2. Here, the row positioning value of the virtual node 1-2 is 1, so the optimized row positioning value of node 4 is also set to 1. The re-optimized circuit diagram is as follows. Figure 6 The right side.

[0107] In the third case, the predecessor node of the circuit diagram node has multiple virtual nodes, so that... Figure 7 Taking the case of node 6 as an example, there are 3 predecessor nodes, namely virtual nodes 0-2, virtual nodes 1-2, and node 5. Since there are two virtual nodes among the predecessor nodes of node 6, it needs to be divided into a third case. In this case, it is necessary to optimize according to the above calculation model and based on the row positioning value of the virtual nodes.

[0108] Here, the row positioning value of virtual node 0-2 is 0, and the row positioning value of virtual node 1-2 is 1. Here, virtual node 0-2 is set as the first predecessor node, and virtual node 1-2 is set as the second predecessor node.

[0109] Substituting into the above calculation model, we get: new_row = (0 + 1) / 2 = 0.5;

[0110] The calculated row positioning value is less than 1, so it cannot be assigned to the first row. Therefore, the row positioning value of node 6 is still set to 0, and the re-optimized circuit diagram is as follows: Figure 7 The right side.

[0111] Furthermore, step S4 above also includes:

[0112] Step S403: For any circuit diagram node that has neither a predecessor node nor a successor node, set its column as the next column after the output port, and then arrange all circuit diagram nodes that have neither a predecessor node nor a successor node in that column in sequence.

[0113] Nodes in the circuit diagram where neither a predecessor nor a successor node exists are considered independent nodes and have no connection relationship. To optimize the circuit diagram layout, this invention places all independent nodes in the same column and arranges them sequentially from row 0 downwards, as follows: Figure 2 As shown, nodes 9 and 10 are independent nodes, without any predecessor or successor nodes. Therefore, nodes 9 and 10 are placed in the nth column, which is the column below the output port, and are arranged downwards starting from the 0th row. Here, node 9 is in the 0th row and node 10 is in the 1st row.

[0114] Furthermore, the present invention also includes a scheme for optimizing row positioning values ​​based on port weight values, which includes:

[0115] Step S404: Obtain the output ports of all circuit diagram nodes in the same column, and assign values ​​to all output ports in sequence according to a preset order;

[0116] Step S405: Calculate the port weight value of the output port of each circuit diagram node;

[0117] Step S406: Obtain the connection relationship between all circuit diagram nodes and output ports in the next column, calculate the sum of the port weight values ​​of the output ports connected to them, and set the row positioning value of all circuit diagram nodes in the column according to the sum of the port weight values.

[0118] Here, the calculation model for the port weight value is as follows:

[0119]

[0120] Among them, port_weighit(p,q) (i) represents the port weight value of the output port with index i in row p and column q, and port_num represents the total number of output ports of the current circuit diagram node.

[0121] by Figure 8 Taking the case of q as an example, let's explain node 1 in the 0th row of column q. This node 1 has three output ports. Here, we assign values ​​to these three output ports from top to bottom, and assign them values ​​1, 2, and 3 respectively. The assignment here is also the sequence number in the above calculation model.

[0122] Then, search downwards in sequence for node 2, which has an output port, and assign it the value 1.

[0123] For node 3, which has two output ports, assign values ​​1 and 2 respectively;

[0124] The above steps correspond to step S404. After the assignment is completed, it is necessary to calculate the port weight value of each output port, which is step S405. The calculation is performed based on the above calculation model.

[0125] For node 1, which is located in row 0 and column q, the port weight of the output port of node 1, assigned a value of 1, can be obtained according to the above calculation model as follows:

[0126]

[0127] The port weight value obtained after the above calculation is 1.25;

[0128] Based on the above calculation model, the port weight values ​​of all output ports can be calculated. The port weight values ​​of the three output ports of node 1 are 1.25, 1.5 and 1.75, respectively.

[0129] The port weight of the output port of node 2 is 2.5;

[0130] The port weights of the two output ports of node 3 are 3.33 and 3.36, respectively;

[0131] The process of calculating the port weight value is the same as step S405. After completing step S405, step S406 needs to be executed.

[0132] It first obtains the connection relationship between all circuit diagram nodes and output ports in the next column, which is also the next column. Figure 8 In the (q+1)th column, which has nodes 4, 5, and 6, we can obtain the second output port of node 4 (corresponding to the port weight value of 1.5) and the second output port of node 3 (corresponding to the port weight value of 3.66), respectively.

[0133] Node 5 is connected to the first output port of node 1 (with a corresponding port weight of 1.25) and the output port of node 2 (with a corresponding port weight of 2.5);

[0134] Node 6 is connected to the third output port of node 1 (with a corresponding port weight of 1.75) and the first output port of node 3 (with a corresponding port weight of 3.33);

[0135] Then, the row positioning value needs to be set for the circuit diagram node in the column according to the sum of the port weight values. According to the above connection relationship, the sum of the port weight values ​​corresponding to the output port connected to node 4 is 5.16, the sum of the port weight values ​​corresponding to the output port connected to node 5 is 3.75, and the sum of the port weight values ​​corresponding to the output port connected to node 6 is 5.08.

[0136] Then, based on the sum of the port weight values ​​arranged in ascending order, node 5 can be set in row 0, node 6 in row 1, and node 4 in row 2.

[0137] Similarly, the port weight values ​​can also be set based on the average value of the port weight values. According to the port weight values ​​calculated above, the average value of the port weight values ​​of node 4 is 2.58, the average value of the port weight values ​​of node 5 is 1.875, and the average value of the port weight values ​​of node 6 is 2.54. They can be arranged in the above order from smallest to largest.

[0138] The node placement and connections before optimization are as follows: Figure 8 As shown on the left, the optimized node placement and connections are... Figure 8 As shown on the right, from Figure 8 As can be seen, before the layout optimization, the total number of intersections of all the connections was 6, and after optimization, the number of intersections was reduced to 4, which means that the present invention simplifies the circuit layout.

[0139] Step S5 is to remove the virtual node and restore the connection. This can be achieved through the circuit analysis module, so it will not be described in detail here.

[0140] Based on the overall layout method described above, the present invention has the following beneficial effects:

[0141] 1. Versatility: The layout algorithm of this invention is not limited to a specific type of circuit and can be widely applied to the design stage of analog and digital circuits, greatly simplifying the layout problem in circuit design in multiple fields to meet rapidly changing market and technological demands.

[0142] 2. Flexibility and customizability: This invention adopts a unique modular design concept, dividing the overall layout process into a basic framework and multiple independent and undependent steps. Each step can operate as a separate functional unit. The decoupling between the steps makes this layout algorithm highly flexible and scalable.

[0143] 3. More engineer-friendly design: The algorithm has a unique ability to handle nodes in circuit diagrams that have no predecessor or successor relationship. By arranging these nodes reasonably, the entire circuit diagram can look cleaner and more orderly, which is beneficial for engineers to analyze the circuit and troubleshoot faults.

[0144] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A general circuit logic diagram layout method, characterized in that, include: Step S1: Using the circuit analysis module, obtain the relative positions of all circuit diagram nodes of the circuit to be optimized, as well as the connection relationships between the circuit diagram nodes and the output and input ports; Step S2: Based on the connection relationship between the circuit diagram node and the input port, perform column positioning for each circuit diagram node; Step S3: Add a virtual node to the circuit to be optimized. The virtual node is set between two circuit diagram nodes that are directly connected and whose connection path spans at least one column. Step S4: Based on the number of virtual nodes in the predecessor nodes of the circuit diagram nodes, perform row positioning for each column of the circuit diagram nodes; Step S5: Remove all the virtual nodes and restore the connection relationship between the circuit diagram nodes and the output and input ports; Step S4 includes: Step S401: Detect the number of virtual nodes in the predecessor nodes of the circuit diagram nodes; Step S402: When the number of virtual nodes is 0, the row positioning value of the circuit diagram node is optimized based on the row positioning value of its predecessor node; When the number of virtual nodes is 1, the row positioning value of the circuit diagram node is set to the row positioning value of the virtual node; When there are at least two virtual nodes, the row positioning value of the circuit diagram node is optimized based on the row positioning values ​​of all virtual nodes. The row positioning value of the circuit diagram node satisfies the calculation model: Where new_row is the row positioning value of the circuit diagram node, and row i Let k be the row number of the i-th predecessor node of the circuit diagram node, and k be the number of predecessor nodes of the circuit diagram node. Step S4 further includes: Step S403: For any circuit diagram node that has neither a predecessor node nor a successor node, set its column as the next column after the output port, and arrange all circuit diagram nodes that have neither a predecessor node nor a successor node in sequence under this column. Step S404: Obtain the output ports of all circuit diagram nodes in the same column, and assign values ​​to all output ports in sequence according to a preset order; Step S405: Calculate the port weight value of the output port of each of the circuit diagram nodes; Step S406: Obtain the connection relationship between all circuit diagram nodes in the next column and the output port, calculate the sum of the port weight values ​​of the output ports connected to them, and set the row positioning value of all circuit diagram nodes in the column according to the sum of the port weight values. The calculation model for the port weight value is as follows: Wherein, port_weight (p，q) (i) represents the port weight value of the output port with index i in row p and column q, and port_num represents the total number of output ports of the current circuit diagram node.

2. The general circuit logic diagram layout method according to claim 1, characterized in that, Step S2 includes: Step S201: Set the input port as the first column and the output port as the second to last column; Step S202: Starting from any input port, sequentially search for successor nodes and set a candidate set for all successor nodes. The value of the successor node in the candidate set is the value of the previous circuit diagram node connected to it plus 1. Step S203: The column positioning value of the circuit diagram node is set according to the value in the corresponding candidate set.

3. The general circuit logic diagram layout method according to claim 2, characterized in that, Step S203 includes: When the circuit diagram node has only one predecessor node, the column positioning value of the circuit diagram node is a value taken from the corresponding candidate set. When a circuit diagram node has at least two predecessor nodes, the column positioning value of the circuit diagram node is the maximum value in the corresponding candidate set.

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