Module connection method and system, electronic equipment and storage medium

Abstract

The invention relates to the field of digital chips, and provides a module connection method and system, electronic equipment and a storage medium. The method comprises the steps that a connection relation file, a module file and an interface file are obtained, the module file records functions of all modules, the connection relation file records connection relations among all the modules, and the interface file records interfaces of all the modules; generating a system configuration file according to the connection relation file and the interface file, wherein the system configuration file records the to-be-connected interfaces and the connection relation of the to-be-connected interfaces; according to the system configuration file, interfaces to be connected are generated in the module file, the connection relation of the interfaces to be connected is established, an updated module file is obtained, and the updated module file is used for guiding the multiple modules in the chip to conduct physical connection. According to the method, the interface of the module can be automatically generated and interface connection can be completed, the time cost and the labor cost of chip design can be reduced, and the quality of chip design can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of digital chips, and in particular to a module connection method, system, electronic device and storage medium. Background Art

[0002] With the rapid development of semiconductor process technology and the increasing demand for integrated circuit design, the scale of digital chip design and implementation is facing unprecedented new challenges. When physically designing large-scale digital chips, several components with similar functions are usually combined into one physical module, and the chip can be divided into multiple modules. Then, from the perspective of the module, the module layout, wiring, signal timing convergence, etc. are designed and optimized. After the optimization makes each module meet the requirements, the large-scale digital chip is physically implemented according to the optimized physical design.

[0003] The more complex the module function is, the more difficult it is to implement. Therefore, during design, the functions performed by a single module are limited, and the tasks that the chip needs to complete may be more complex and cannot be completed by a single module. Therefore, cross-module communication behavior will occur between modules, and some modules need to consider the connection with other modules during physical design.

[0004] Related technologies mainly rely on designers to manually complete the connection between modules. There are many interfaces between modules, and the connection workload is extremely large. Once an interface connection error or a change in the connection relationship occurs, it may also affect the connection method of other interfaces, further increasing the workload of designers, resulting in high time and labor costs for chip design, and may also bring quality risks to the chip design. Summary of the invention

[0005] In view of this, the present disclosure proposes a module connection method, system, electronic device and storage medium, which can automatically generate module interfaces and complete interface connections, thereby reducing the time and labor costs of chip design and improving the quality of chip design.

[0006] According to one aspect of the present disclosure, a module connection method is provided, the method is used to connect modules in a chip, the chip includes multiple modules, the method includes: obtaining a connection relationship file, a module file, and an interface file, the module file records the function of each module, the connection relationship file records the connection relationship between the modules, and the interface file records the interface of each module; generating a system configuration file according to the connection relationship file and the interface file, the system configuration file records the interface to be connected and the connection relationship of the interface to be connected; according to the system configuration file, generating the interface to be connected in the module file and establishing the connection relationship of the interface to be connected, to obtain an updated module file, the updated module file is used to guide the multiple modules in the chip to be physically connected.

[0007] In a possible implementation, the method also includes: generating a beat file corresponding to each interface to be connected based on the interface file and the system configuration file, the beat file being used to improve the signal transmission capability of the corresponding interface; adding the beat file to the module file, and instantiating the beat file in the module file.

[0008] In a possible implementation, before generating the interfaces to be connected in the module file and establishing the connection relationship of the interfaces to be connected, the method further includes: disconnecting the connection relationship of the existing interfaces of each module in the module file.

[0009] In one possible implementation, the type of the interface includes an integrated interface, which connects multiple wires, and generating a beat file corresponding to each interface to be connected based on the interface file and the system configuration file includes: parsing the system configuration file to determine the type of each interface to be connected, in response to the type of the interface to be currently connected being an integrated interface, parsing the interface file to determine the beat parameters of each wire connected to the interface to be currently connected, and generating a beat file corresponding to the interface to be currently connected based on the beat parameters.

[0010] In one possible implementation, the parsing of the interface file to determine the beat parameters of each wire connected to the interface currently to be connected includes: parsing the interface file to determine the length of each wire connected to the interface currently to be connected; determining the beat parameters of each wire based on the length of the wire, the beat parameters being proportional to the length of the wire; wherein the beat is performed by a register, and the beat parameter of each wire indicates the number of registers set on the wire.

[0011] In a possible implementation, the connection relationship between the modules recorded in the connection relationship file includes at least one connection path, each connection path includes at least two modules, and adjacent modules on each connection path serve as a pair of modules to be connected.

[0012] In a possible implementation manner, the connection relationship file also records the communication direction of each pair of modules to be connected.

[0013] In a possible implementation, the obtaining of the connection relationship file includes: determining at least one connection path according to a layout planning file of the chip and each pair of modules serving as endpoints of the connection path, wherein the layout planning file records the positions of each module in the chip, and each connection path includes at least two modules; determining the connection relationship between each module according to each connection path, and generating the connection relationship file, wherein adjacent modules on each connection path are regarded as a pair of modules to be connected.

[0014] In a possible implementation, when the connection relationship file records the communication direction of each module to be connected, obtaining the connection relationship file includes: determining at least one connection path according to the layout planning file of the chip and each pair of modules serving as the starting point and end point of the connection path, wherein the layout planning file records the position of each module in the chip, and each connection path includes at least two modules; determining the connection relationship between the modules and the communication direction of each module to be connected according to each connection path, and the adjacent modules on each connection path serve as a pair of modules to be connected.

[0015] In a possible implementation, generating a system configuration file based on the connection relationship file and the interface file includes: parsing the connection relationship file to determine each connection path; parsing the interface file to determine the interface to be connected on each module included in the connection path for connecting an adjacent module, and the connection relationship between the interfaces to be connected, and generating the system configuration file.

[0016] According to another aspect of the present disclosure, a module connection system is provided, the system is used to connect modules in a chip, the chip includes multiple modules, and the system includes: an acquisition unit, used to acquire a connection relationship file, a module file, and an interface file, the module file records the function of each module, the connection relationship file records the connection relationship between each module, and the interface file records the interface of each module; a first generation unit, used to generate a system configuration file according to the connection relationship file and the interface file, the system configuration file records the interface to be connected and the connection relationship of the interface to be connected; an update unit, used to generate the interface to be connected in the module file and establish the connection relationship of the interface to be connected according to the system configuration file, to obtain an updated module file, the updated module file is used to guide the multiple modules in the chip to be physically connected.

[0017] In one possible implementation, the system also includes: a second generation unit, used to generate a beat file corresponding to each interface to be connected based on the interface file and the system configuration file, and the beat file is used to improve the signal transmission capability of the corresponding interface; a file adding unit, used to add the beat file to the module file and instantiate the beat file in the module file.

[0018] In a possible implementation, the system further includes: a disconnection unit, configured to disconnect the connection relationship of existing interfaces of each module in the module file before generating the interface to be connected in the module file and establishing the connection relationship of the interface to be connected.

[0019] In one possible implementation, the type of the interface includes an integrated interface, which connects multiple wires, and generating a beat file corresponding to each interface to be connected based on the interface file and the system configuration file includes: parsing the system configuration file to determine the type of each interface to be connected, in response to the type of the interface to be currently connected being an integrated interface, parsing the interface file to determine the beat parameters of each wire connected to the interface to be currently connected, and generating a beat file corresponding to the interface to be currently connected based on the beat parameters.

[0020] In one possible implementation, the parsing of the interface file to determine the beat parameters of each wire connected to the interface currently to be connected includes: parsing the interface file to determine the length of each wire connected to the interface currently to be connected; determining the beat parameters of each wire based on the length of the wire, the beat parameters being proportional to the length of the wire; wherein the beat is performed by a register, and the beat parameter of each wire indicates the number of registers set on the wire.

[0021] In a possible implementation, the connection relationship between the modules recorded in the connection relationship file includes at least one connection path, each connection path includes at least two modules, and adjacent modules on each connection path serve as a pair of modules to be connected.

[0022] In a possible implementation manner, the connection relationship file also records the communication direction of each pair of modules to be connected.

[0023] In a possible implementation, the obtaining of the connection relationship file includes: determining at least one connection path according to a layout planning file of the chip and each pair of modules serving as endpoints of the connection path, wherein the layout planning file records the positions of each module in the chip, and each connection path includes at least two modules; determining the connection relationship between each module according to each connection path, and generating the connection relationship file, wherein adjacent modules on each connection path are regarded as a pair of modules to be connected.

[0024] In a possible implementation, when the connection relationship file records the communication direction of each module to be connected, obtaining the connection relationship file includes: determining at least one connection path according to the layout planning file of the chip and each pair of modules serving as the starting point and end point of the connection path, wherein the layout planning file records the position of each module in the chip, and each connection path includes at least two modules; determining the connection relationship between the modules and the communication direction of each module to be connected according to each connection path, and the adjacent modules on each connection path serve as a pair of modules to be connected.

[0025] In a possible implementation, generating a system configuration file based on the connection relationship file and the interface file includes: parsing the connection relationship file to determine each connection path; parsing the interface file to determine the interface to be connected on each module included in the connection path for connecting an adjacent module, and the connection relationship between the interfaces to be connected, and generating the system configuration file.

[0026] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0027] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0028] According to another aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0029] According to the module connection method of the embodiment of the present disclosure, by obtaining the connection relationship file, the module file, and the interface file, the interface to be connected and the connection relationship of the interface to be connected can be determined according to the connection relationship file and the interface file, and a system configuration file that records the interface to be connected and the connection relationship of the interface to be connected can be generated; according to the system configuration file, the interface to be connected can be generated in the module file and the connection relationship of the interface to be connected can be established to obtain an updated module file. The interface to be connected and the connection relationship of the interface to be connected already exist in the updated module file, so it can be used to guide multiple modules in the chip to be physically connected. Only the connection relationship file, the module file, and the interface file need to be prepared, which interfaces are the interfaces to be connected and the connection relationship of the interfaces can be automatically determined, and the module file can be automatically updated. If the design is correct, the code generated by compiling the updated module file will not have errors, ensuring the credibility of the updated module file, and reducing the testing workload. In summary, the module connection method of the embodiment of the present disclosure can automatically generate the interface of the module in the module file and complete the connection of the interface, which can reduce the time cost and labor cost of chip design and improve the quality of chip design.

[0030] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0032] Figure 1 Shows one way to physically connect the modules.

[0033] Figure 2 Shows another way to physically connect the modules.

[0034] Figure 3 An exemplary application scenario of the module connection method according to an embodiment of the present disclosure is shown.

[0035] Figure 4 A schematic diagram showing the flow of a module connection method according to an embodiment of the present disclosure.

[0036] Figure 5 An example of the contents recorded in the connection relationship file, module file, and interface file according to an embodiment of the present disclosure is shown.

[0037] Figure 6 An example of the content recorded in the system configuration file according to an embodiment of the present disclosure is shown.

[0038] Figure 7 An example of a portion related to module 2 in a module file updated according to an embodiment of the present disclosure is shown.

[0039] Figure 8a An example of a beat file instantiated in a module file according to an embodiment of the present application is shown.

[0040] Figure 8b An exemplary method of generating a beat file corresponding to an integrated interface according to an embodiment of the present disclosure is shown.

[0041] Fig. 9 An example of the content recorded in the module layout planning file according to an embodiment of the present disclosure is shown.

[0042] Fig.10 A schematic diagram showing the structure of a module connection system according to an embodiment of the present disclosure.

[0043] Fig.11 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0044] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0045] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0046] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0047] With the rapid development of semiconductor process technology and the increasing demand for integrated circuit design, the scale of digital chip design and implementation is facing unprecedented new challenges. When physically designing large-scale digital chips, several components with similar functions are usually combined into one physical module, and the chip can be divided into multiple modules. Then, from the perspective of the module, the module layout, wiring, signal timing convergence, etc. are designed and optimized. After the optimization makes each module meet the requirements, the large-scale digital chip is physically implemented according to the optimized physical design.

[0048] The more complex the module function is, the more difficult it is to implement. Therefore, during design, the functions performed by a single module are limited, and the tasks that the chip needs to complete may be more complex and cannot be completed by a single module. Therefore, cross-module communication behavior will occur between modules, and some modules need to consider the connection with other modules during physical design.

[0049] Figure 1 Shows one way to physically connect the modules. Figure 2 Shows another way to physically connect the modules.

[0050] like Figure 1 As shown, in the chip design stage, when designing the interface of the module, for any pair of modules to communicate, an interface for connection is generated respectively, and the generated interfaces are directly connected through virtual wires. In the physical implementation stage of the chip, a sufficiently large channel is reserved on the chip, and the routing of the interfaces of all modules is laid out in the channel. With the increase in the complexity of chip logic functions and the increase in the scale of chip wafers, the number of interfaces that modules need to connect increases. In order to avoid routing congestion, the area of ​​the channel needs to be increased, which will bring very large additional overhead in physical implementation and it is difficult to meet the needs of large-scale chip design. Therefore, the physical connection of modules in large-scale chip design is more inclined to adopt Figure 2 Connection method shown.

[0051] like Figure 2As shown in the figure, the module connection is completed by module feedthrough. In the chip design stage, for any pair of modules to communicate, the optimal communication path with the pair of modules as the starting point and the end point is first determined, and then the chip interface is designed so that after the interface is connected, every two adjacent modules on the path can be fed through step by step. In the physical implementation stage of the chip, the wires of the feedthrough interface can be routed at any position inside the module, and there is no need to reserve additional channels for routing. The routing congestion problem will be greatly improved, which can further save the area overhead caused by routing.

[0052] Figure 1 and Figure 2 The connection methods shown require the designer to manually connect the interface. Figure 2 In the scheme shown, designers need to connect from the starting point and pass through the modules of each path before connecting to the terminal module. This means that for each module in the path, two connection operations need to be performed on this module. This further increases the workload of the connection operation and makes the connection operation very complicated. In addition, in the chip design process, there are many interfaces, unstable connection relationships of interfaces, adjustments to the physical module layout, and multiple regular iterations. The occurrence of any of these situations will lead to a significant change in the module penetration method, and manually updating the chip code will greatly increase the workload of designers and the quality risk of chip design.

[0053] If an integrated interface is used when the module is passed through, the designer needs to first convert the integrated interface of the input signal into a wire net, then drive each wire through a register to enhance the signal transmitted by the wire (also called a beat), and then convert the wire net into an integrated interface of the output signal. If there are many integrated interfaces, a large number of conversion operations are required, which is quite cumbersome. And the number of registers that each wire needs to pass through (also called the number of beats or beat parameters) also needs to be set manually. The conversion of the interface and the setting of the number of registers further increase the time cost and labor cost of module connection, and the probability of module connection errors is further increased.

[0054] In view of this, the present disclosure proposes a module connection method, system, electronic device and storage medium, which can automatically generate module interfaces and complete interface connections, thereby reducing the time and labor costs of chip design and improving the quality of chip design.

[0055] Furthermore, the module connection method of the embodiment of the present disclosure can automatically determine whether the interface needs to be converted into a type and automatically determine the beat parameters of each wire, further reducing the time and labor costs of module connection and reducing the probability of module connection errors.

[0056] Figure 3 An exemplary application scenario of the module connection method according to an embodiment of the present disclosure is shown.

[0057] The module connection method disclosed in the present invention is applied to the design stage of a chip. The designer has designed which modules the chip should include, the function of each module, the location of each module, the connection relationship between modules, and the interfaces allowed to be set for each module, and has obtained a module file recording the function of each module, a connection relationship file recording the connection relationship between modules, and an interface file recording the interfaces of each module.

[0058] like Figure 3 As shown, the module connection method of the present disclosure can be executed by a module connection system, and the module connection system can be an automated script system written by a designer. The designer can import the connection relationship file, module file, and interface file into the module connection system, and the module connection system executes the module connection method of the present disclosure, and can automatically generate the interface to be connected in the module file and complete the connection of the interface, thereby realizing the connection of the module in the module file.

[0059] The updated module file can be used to guide the physical connection of multiple modules in the chip. Furthermore, the updated module file can be tested. If the test determines that the module file does not meet the requirements, it can be directly determined that the design is wrong, rather than a deviation during connection. The designer can modify at least one of the connection relationship file, module file, and interface file and re-import the modified file into the module connection system. The module connection system repeatedly executes the module connection method to update the module file, and finally obtains a module file that meets the requirements, and uses the module file that meets the requirements to guide the physical connection of multiple modules in the chip.

[0060] Figure 4 A schematic diagram showing the flow of a module connection method according to an embodiment of the present disclosure.

[0061] like Figure 4 As shown, in a possible implementation, the present disclosure proposes a module connection method, the method is used to connect modules in a chip, the chip includes multiple modules, and the method includes:

[0062] Step S41, obtaining a connection relationship file, a module file, and an interface file, wherein the module file records the function of each module, the connection relationship file records the connection relationship between each module, and the interface file records the interface of each module;

[0063] Step S42, generating a system configuration file according to the connection relationship file and the interface file, wherein the system configuration file records the interfaces to be connected and the connection relationships of the interfaces to be connected;

[0064] Step S43, according to the system configuration file, generate the interface to be connected in the module file and establish the connection relationship of the interface to be connected, to obtain an updated module file, the updated module file is used to guide the physical connection of multiple modules in the chip.

[0065] For example, a chip designed by a designer may include multiple modules, each of which may be integrated from one or more components. The module connection method disclosed in the present invention may be used to connect modules in a chip during the chip design process, specifically, an interface may be generated in a module file, and the connection of the modules may be achieved by establishing a connection of the interface in the module file.

[0066] In step S41, a connection relationship file, a module file, and an interface file may be first obtained. The module file and the interface file may be manually written by the designer, and the connection relationship file may be manually written by the designer, or may be automatically generated by the module connection system according to the layout planning file and other chip related information provided by the designer, and the present disclosure does not limit this.

[0067] Figure 5 An example of the contents recorded in the connection relationship file, module file, and interface file according to the embodiment of the present disclosure is shown. Figure 5 As shown, the module file records the codes of modules 1 to 8, so the chip may include 8 modules. The code of each module may include the logic circuit code of the module, the interface information of the logic circuit connection, etc. The interface file records the combination of interfaces included in each module and the types of interfaces (input interface / output interface, integrated interface / independent interface, etc.). The modules with connection relationships recorded in the connection relationship file are module 1 and module 2, module 2 and module 3, module 3 and module 4, module 4 and module 5. Since the connection relationship file does not record the connection relationship of other modules, it can be considered that other modules do not need to be connected temporarily.

[0068] Some interfaces may have been used. When the designer does not want to use the used interfaces for connecting modules, an identifier (not shown) may be added to the interface file to indicate whether the interfaces are allowed to be used for connecting modules.

[0069] Those skilled in the art should understand that module files, connection relationship files and interface files can also record more content related to chip design, and the embodiments of the present disclosure do not limit the specific content recorded in module files, connection relationship files and interface files.

[0070] Modules are connected to each other through interfaces, so after obtaining the connection relationship file and the interface file, step S42 can be executed to determine which interfaces of each module are to be connected and the connection relationship of the interfaces to be connected according to the connection relationship file and the interface file, and generate a system configuration file for recording the interfaces to be connected and the connection relationship of the interfaces to be connected. If the interface file further records whether the interface is allowed to be used to connect the module, when determining the interface to be connected, the interface to be connected can be determined only from the interfaces marked as allowed to connect the module.

[0071] by Figure 5 Taking module 1 and module 2 in the example as an example, according to the interface file, it can be determined that module 1 includes interface 11-interface 12, and module 2 includes interface 21-interface 24. Assume that the interface numbered with an odd number is the output interface, and the interface numbered with an even number is the input interface. Parsing the connection relationship file can determine that module 1 is connected to module 2. If the communication direction of module 1 and module 2 is not further determined, it can be determined that the interface to be connected of module 1 includes interface 11 and interface 12, and the interface to be connected of module 2 includes interface 21 and interface 22, wherein interface 11 is connected to interface 22, and interface 21 is connected to interface 12. If it is further determined that the communication direction of module 1 and module 2 is that module 2 outputs a signal to module 1, it can be determined that the interface to be connected of module 1 includes interface 12, and the interface to be connected of module 2 includes interface 21, wherein interface 12 is connected to interface 21.

[0072] The methods for determining the interfaces to be connected and the connection relationships of the interfaces of other modules to be connected are similar to those of the modules 1 and 2 to be connected, and are not described in detail here.

[0073] Figure 6 An example of the contents recorded in the system configuration file according to an embodiment of the present disclosure is shown. Figure 6 In the example, the interfaces with connection relationships recorded in the system configuration file are interface 12 and interface 21, interface 22 and interface 31, interface 32 and interface 41, interface 42 and interface 51. Among them, interface 12 is the input interface of module 1. Interface 21 is the output interface of module 2, and interface 22 is the input interface of module 2. Interface 31 is the output interface of module 3, and interface 32 is the input interface of module 3. Interface 41 is the output interface of module 4, and interface 42 is the input interface of module 4. Interface 51 is the output interface of module 5, and interface 52 is the input interface of module 5.

[0074] Those skilled in the art should understand that, since there may be multiple interfaces of the same type for each module recorded in the interface file, there may be multiple interfaces to be connected and the connection relationship of the interfaces to be connected determined according to the module connection relationship file and the interface file, and the system configuration file may record any one of them. As long as the content recorded in the system configuration file indicates that each pair of connected modules are connected through an interface, and the connection relationship of the interfaces enables each pair of connected modules to achieve unidirectional or bidirectional signal transmission, the embodiment of the present disclosure does not limit the specific content included in the system configuration file. Thereafter, step S43 may be executed to update the module file. For example, according to the system configuration file, the interfaces to be connected are generated in the module file and the connection relationship of the interfaces to be connected is established to obtain an updated module file. The updated module file is used to guide the physical connection of multiple modules in the chip. After the interfaces to be connected of each module are connected, the connection of the modules is realized.

[0075] Figure 7 An example of a portion related to module 2 in a module file updated according to an embodiment of the present disclosure is shown.

[0076] like Figure 7 As shown, before executing step S43, the part related to module 2 in the module file (module 2 code) may include logic circuit 1, logic circuit 2, interface 2m, interface 2n, interface 2p, and interface 2q. Interface 2m and interface 2p are input interfaces, interface 2n and interface 2q are output interfaces, interface 2m and interface 2n are connected to logic circuit 1, and interface 2p and interface 2q are connected to logic circuit 2.

[0077] After executing step S44, the logic circuit 1, logic circuit 2, interface 2m, interface 2n, interface 2p, and interface 2q related to module 2 remain unchanged, and interface 21 and interface 22 are newly added. Interface 21 is an output interface and is connected to input interface 12 (not shown) of module 1, and interface 22 is an input interface and is connected to output interface 31 (not shown) of module 3. Interface 21 is connected to interface 22.

[0078] The connection methods of the interfaces to be connected of other modules are similar to that of module 2 and will not be described in detail here.

[0079] According to the module connection method of the embodiment of the present disclosure, by obtaining the connection relationship file, the module file, and the interface file, the interface to be connected and the connection relationship of the interface to be connected can be determined according to the connection relationship file and the interface file, and a system configuration file that records the interface to be connected and the connection relationship of the interface to be connected can be generated; according to the system configuration file, the interface to be connected can be generated in the module file and the connection relationship of the interface to be connected can be established to obtain an updated module file. The interface to be connected and the connection relationship of the interface to be connected already exist in the updated module file, so it can be used to guide multiple modules in the chip to be physically connected. Only the connection relationship file, the module file, and the interface file need to be prepared, which interfaces are the interfaces to be connected and the connection relationship of the interfaces can be automatically determined, and the module file can be automatically updated. If the design is correct, the code generated by compiling the updated module file will not have errors, ensuring the credibility of the updated module file, and reducing the testing workload. In summary, the module connection method of the embodiment of the present disclosure can automatically generate the interface of the module in the module file and complete the connection of the interface, which can reduce the time cost and labor cost of chip design and improve the quality of chip design.

[0080] In a possible implementation, the method further includes:

[0081] Generate a beat file corresponding to each interface to be connected according to the interface file and the system configuration file, the beat file is used to improve the signal transmission capability of the corresponding interface;

[0082] Add the beat file to the module file and instantiate the beat file in the module file.

[0083] For example, when a chip is physically implemented, a wire is usually used to connect the interface. The wire transmission signal has a certain loss, and a register needs to be used to enhance the signal transmission capability of the interface. This operation can be called a beat. Therefore, after obtaining the system configuration file, a beat file corresponding to each interface to be connected can be generated according to the interface file and the system configuration file. The beat file is used to enhance the signal transmission capability of the corresponding interface. A beat file can be added to the module file, and the beat file in the module file can be instantiated. Among them, the input interface and the output interface connected on the same module correspond to the same beat file. The instantiated beat file can be implemented based on the prior art, which will not be repeated here.

[0084] Figure 8a An example of a beat file instantiated in a module file according to an embodiment of the present application is shown.

[0085] like Figure 8a As shown, in Figure 7On the basis of the module file shown, the module file may further include an instantiated beat file 1, and both the interface 21 and the interface 22 correspond to the beat file 1, and the interface 21 and the interface 22 are connected to the beat file 1 respectively.

[0086] The instantiated beat file realizes the pass-through function, and is independently defined and integrated, and is clearly divided from the original logic circuit of the module file, and will not affect the original function of the module. In addition, the addition of the beat file realizes the automatic improvement of the driving capability, and can automatically compensate for the part of the signal lost during the transmission process, avoiding manual determination of the beat when physically connecting the module, further reducing the time cost and labor cost.

[0087] In a possible implementation, before generating the interface to be connected in the module file and establishing the connection relationship of the interface to be connected, the method further includes:

[0088] In the module file, disconnect the existing interfaces of each module.

[0089] For example, since both the module file and the connection relationship file may be modified, it is possible that the connection relationship file has been modified but the module file has not been modified synchronously. For example, there is an interface in the module file that was generated when the module connection method was executed last time, and the interface is also generated when the module connection method is executed this time, but the interface to be connected to is different from the interface to be connected when the module connection method was executed last time. Or, there is an interface in the module file that was generated when the module connection method was executed last time, but the interface is not generated and does not need to be connected when the module connection method is executed this time.

[0090] In this case, the connection relationship of the existing interfaces of each module can be disconnected first, and then step S43 is performed to generate the interface to be connected in the module file and establish the connection relationship of the interface to be connected. In this way, the complexity of the connection relationship of the interface can be reduced, and the test cost of the subsequent chip can be reduced.

[0091] Those skilled in the art should understand that even if the connection relationship of the existing interface is not disconnected, after the connection of the interface is completed according to the system configuration file, the test of the interface connection relationship when executing the module connection method can be completed normally. The embodiment of the present disclosure does not limit whether the connection relationship of the existing interface must be disconnected before connecting the interface.

[0092] In a possible implementation, the type of the interface includes an integrated interface, the integrated interface connects multiple wires,

[0093] Generate the beat file corresponding to each interface to be connected according to the interface file and system configuration file, including:

[0094] Parse the system configuration file to determine the type of each interface to be connected. In response to the type of the interface to be connected being an integrated interface, parse the interface file to determine the beat parameters of each wire connected to the interface to be connected, and generate a beat file corresponding to the interface to be connected based on the beat parameters.

[0095] For example, there are two types of interfaces, an integrated interface and an independent interface. An independent interface connects only one wire, while an integrated interface can connect multiple wires. The loss of signals transmitted by different wires may be inconsistent, so the beat parameters (beat times) of different wires may also be different. The beat file can include the beat parameters of each wire.

[0096] Figure 8b An exemplary method of generating a beat file corresponding to an integrated interface according to an embodiment of the present disclosure is shown.

[0097] like Figure 8b As shown, the system configuration file can be parsed first to determine the type of the interface to be connected. In response to the type of the interface to be connected being an integrated interface, the interface file can be parsed to determine the beat parameters of each wire connected to the interface to be connected, and a beat file corresponding to the interface to be connected is generated according to the beat parameters.

[0098] When it is determined that the interface to be connected is an independent interface, the beat parameters of the wire corresponding to the interface to be connected are directly determined, and the beat file corresponding to the interface to be connected is generated according to the beat parameters.

[0099] Since the input interface and output interface connected to the same module correspond to the same beat file, once the beat file corresponding to a certain input interface (or output interface) on a certain module has been generated, there is no need to generate the beat file corresponding to the output interface (or input interface) connected to the input interface on the module.

[0100] In this way, the module connection method of the embodiment of the present disclosure can automatically generate corresponding beat files for each type of interface, further reducing the time and labor costs of module connection and reducing the probability of module connection errors.

[0101] In a possible implementation, parsing the interface file to determine the beat parameters of each wire connected to the interface to be connected currently includes:

[0102] Parse the interface file to determine the length of each wire connected to the interface to be connected;

[0103] According to the length of each wire, the beat parameter of the wire is determined, and the beat parameter is proportional to the length of the wire;

[0104] The beat is completed by registers, and the beat parameter of each wire indicates the number of registers set on the wire.

[0105] For example, the longer the wire, the greater the loss of the wire transmission signal, and the more times the beat is required. Therefore, the interface file can be parsed to determine the length of each wire connected to the interface to be connected, and the beat parameter of each wire can be determined according to the length of the wire, for example, so that the value of the beat parameter of each wire is proportional to the length of the wire. The specific proportional relationship between the value of the beat parameter and the length of the wire can be set according to the application scenario requirements, and the embodiments of the present disclosure are not limited to this.

[0106] The beat is done by registers, and the signal beats once for each level of registers added. The signal enhancement range of a beat is limited, so the number of beats required for signals output by different interfaces may be different. The beat parameter of each wire indicates the number of registers set on the wire. In this case, when the module file instructs the module to make physical connections, the number of registers that the wire will pass through can be determined based on the value of the beat parameter of the wire.

[0107] Those skilled in the art should understand that there are more ways to determine the beat parameters, as long as the degree of enhancement of the signal after beating according to the beat parameters can compensate for the loss caused by the wire transmission signal. The embodiments of the present disclosure do not limit the specific method for determining the beat parameters.

[0108] The connection relationship file can be obtained manually or by executing the module connection method. The following first introduces an exemplary method for manually obtaining the connection relationship file.

[0109] In a possible implementation, the connection relationship between modules recorded in the connection relationship file includes at least one connection path, each connection path includes at least two modules, and adjacent modules on each connection path serve as a pair of modules to be connected.

[0110] For example, when designing the connection relationship of modules, designers usually first determine the location of the modules in the chip. Optionally, a layout planning file can be used to record the location of each module in the chip. Fig. 9 An example of the content recorded in the module layout planning file according to an embodiment of the present disclosure is shown.

[0111] like Fig. 9 As shown, the chip includes 8 modules arranged in an array of 4 rows and 2 columns, with modules 1 to 4 as the first column and modules 5 to 8 as the second column.

[0112] After that, the designer can determine which two modules need to communicate and in which communication direction. For example, it can be determined that module 1 and module 5 need to communicate, and the communication direction is that module 1 outputs a signal to module 5.

[0113] Combined with the layout planning file, the designer can determine a connection path with module 1 and module 5 as endpoints, such as module 1 - module 2 - module 3 - module 4 - module 5. Then the adjacent modules on the connection path can be used as a pair of modules to be connected, that is, module 1 and module 2 are a pair of modules to be connected, module 2 and module 3 are a pair of modules to be connected, module 3 and module 4 are a pair of modules to be connected, and module 4 and module 5 are a pair of modules to be connected.

[0114] If the designer has not yet determined which of module 1 and module 5 is the starting point and which is the end point, it can be assumed that bidirectional communication is required between each pair of connected modules on each connection path, that is, in each pair of connected modules, one module has an input interface connected to the output interface of another module, and an output interface connected to the input interface of another module. In this case, the time cost and labor cost of obtaining the connection relationship file are smaller.

[0115] In a possible implementation, the connection relationship file also records the communication direction of each pair of modules to be connected.

[0116] Still taking the example of the designer determining the connection path with module 1 and module 5 as the endpoints, if the designer has determined module 1 as the starting point and module 5 as the end point, it can be considered that only one-way communication is required between each pair of modules to be connected, that is, in each pair of modules to be connected, one module has an input interface (or output interface) connected to the output interface (or input interface) of another module. In this case, the connection relationship file also records the communication direction of each pair of modules to be connected. For example, module 1 outputs a signal to module 2, module 2 outputs a signal to module 3, module 3 outputs a signal to module 4, and module 4 outputs a signal to module 5.

[0117] In this way, the subsequent data processing costs of generating interfaces and connecting interfaces in module files are reduced.

[0118] The following describes an exemplary method for executing the module connection method to obtain a connection relationship file.

[0119] In a possible implementation, obtaining a connection relationship file includes:

[0120] Determine at least one connection path according to a layout planning file of the chip and each pair of modules as endpoints of the connection path, the layout planning file records the position of each module in the chip, and each connection path includes at least two modules;

[0121] The connection relationship between the modules is determined according to each connection path, and a connection relationship file is generated. The adjacent modules on each connection path are regarded as a pair of modules to be connected.

[0122] For example, the designer only needs to prepare a layout planning file of the chip and determine each pair of modules as endpoints of the connection path. When the module connection method is executed, the connection path can be automatically determined based on the layout planning file and each pair of modules as endpoints of the connection path.

[0123] Assume that the layout plan file is Fig. 9 As shown, module 1 and module 5 are a pair of modules that serve as endpoints of a connection path, and the connection path that can be automatically determined may be, for example: module 1 - module 2 - module 3 - module 4 - module 5.

[0124] Then, the connection relationship between modules can be automatically determined according to each connection path and a connection relationship file can be generated. The adjacent modules on each connection path are regarded as a pair of modules to be connected, that is, module 1 and module 2 are regarded as a pair of modules to be connected, module 2 and module 3 are regarded as a pair of modules to be connected, module 3 and module 4 are regarded as a pair of modules to be connected, and module 4 and module 5 are regarded as a pair of modules to be connected. For an example of the generated connection relationship file, see Figure 5 .

[0125] At this time, bidirectional communication is required between each pair of modules to be connected on each connection path, that is, in each module to be connected, one module has an input interface connected to the output interface of another module, and an output interface connected to the input interface of another module. In this way, the work that designers need to complete is further reduced.

[0126] In a possible implementation, when the connection relationship file records the communication direction of each module to be connected, obtaining the connection relationship file includes:

[0127] Determine at least one connection path according to a layout planning file of the chip and each pair of modules as the starting point and the end point of the connection path, the layout planning file records the position of each module in the chip, and each connection path includes at least two modules;

[0128] The connection relationship between the modules and the communication direction of each pair of modules to be connected are determined according to each connection path, and the adjacent modules on each connection path are regarded as a pair of modules to be connected.

[0129] For example, the designer only needs to prepare the layout planning file of the chip and determine each pair of modules as the starting point and the end point of the connection path. When the module connection method is executed, the connection path can be automatically determined based on the layout planning file and each pair of modules as the starting point and the end point of the connection path.

[0130] Assume that the layout plan file is Fig. 9 As shown, module 1 and module 5 are a pair of modules that are endpoints of a connection path, wherein module 1 is the starting point and module 5 is the end point. Then the connection path that can be automatically determined may be, for example: module 1 - module 2 - module 3 - module 4 - module 5.

[0131] Afterwards, the connection relationship between the modules can be automatically determined according to each connection path and a connection relationship file can be generated. The adjacent modules on each connection path are regarded as a pair of modules to be connected, that is, module 1 and module 2 are regarded as a pair of modules to be connected, module 2 and module 3 are regarded as a pair of modules to be connected, module 3 and module 4 are regarded as a pair of modules to be connected, and module 4 and module 5 are regarded as a pair of modules to be connected.

[0132] At this time, only one-way communication is required between each pair of connected modules on each connection path, that is, in each pair of connected modules, one module has an input interface (or output interface) connected to the output interface (or input interface) of another module. In this case, the connection relationship file also records the communication direction of each pair of connected modules. For example, module 1 outputs a signal to module 2, module 2 outputs a signal to module 3, module 3 outputs a signal to module 4, and module 4 outputs a signal to module 5.

[0133] In this way, the subsequent data processing costs of generating interfaces and connecting interfaces in module files are reduced.

[0134] If module 1 and module 2 are a pair of modules that are endpoints of a connection path, the determined connection path may be, for example, module 1 — module 2. In this case, the connection path includes only two modules. Each connection path includes at least two modules, and the embodiment of the present disclosure does not limit how many modules each connection path includes.

[0135] In a possible implementation, generating a system configuration file according to the connection relationship file and the interface file includes:

[0136] Parse the connection relationship file and determine each connection path;

[0137] The interface file is parsed to determine the interfaces to be connected on each module included in the connection path and used to connect to adjacent modules, as well as the connection relationship of the interfaces to be connected, and a system configuration file is generated.

[0138] Since the connection relationship between the modules recorded in the connection relationship file includes at least one connection path, when executing step S42, the connection relationship file can be parsed first to determine each connection path. The adjacent modules included in the connection path are the modules to be connected. Continue to parse the interface file to determine the interfaces to be connected on each module included in the connection path for connecting the adjacent modules, as well as the connection relationship of the interfaces to be connected. Examples of determining the interfaces to be connected and the connection relationship of the interfaces have been described above and will not be repeated here. Finally, a system configuration file can be generated based on the determined interfaces to be connected and the connection relationship of the interfaces to be connected. The present disclosure also proposes a module connection system, Fig.10 A schematic diagram showing the structure of a module connection system according to an embodiment of the present disclosure.

[0139] like Fig.10 As shown, in a possible implementation, the system is used to connect modules in a chip, the chip includes multiple modules, and the system includes:

[0140] The acquisition unit 100 is used to acquire a connection relationship file, a module file, and an interface file. The module file records the function of each module, the connection relationship file records the connection relationship between each module, and the interface file records the interface of each module.

[0141] A first generating unit 101 is used to generate a system configuration file according to the connection relationship file and the interface file, wherein the system configuration file records the interface to be connected and the connection relationship of the interface to be connected;

[0142] The updating unit 102 is used to generate the interface to be connected in the module file and establish the connection relationship of the interface to be connected according to the system configuration file, so as to obtain an updated module file, wherein the updated module file is used to guide the physical connection of multiple modules in the chip.

[0143] In one possible implementation, the system also includes: a second generation unit, used to generate a beat file corresponding to each interface to be connected based on the interface file and the system configuration file, and the beat file is used to improve the signal transmission capability of the corresponding interface; a file adding unit, used to add the beat file to the module file and instantiate the beat file in the module file.

[0144] In a possible implementation, the system further includes: a disconnection unit, configured to disconnect the connection relationship of existing interfaces of each module in the module file before generating the interface to be connected and establishing the connection relationship of the interface to be connected in the module file.

[0145] In one possible implementation, the type of the interface includes an integrated interface, which connects multiple wires, and generating a beat file corresponding to each interface to be connected based on the interface file and the system configuration file includes: parsing the system configuration file to determine the type of each interface to be connected, in response to the type of the interface to be currently connected being an integrated interface, parsing the interface file to determine the beat parameters of each wire connected to the interface to be currently connected, and generating a beat file corresponding to the interface to be currently connected based on the beat parameters.

[0146] In one possible implementation, the parsing of the interface file to determine the beat parameters of each wire connected to the interface currently to be connected includes: parsing the interface file to determine the length of each wire connected to the interface currently to be connected; determining the beat parameters of each wire based on the length of the wire, the beat parameters being proportional to the length of the wire; wherein the beat is performed by a register, and the beat parameter of each wire indicates the number of registers set on the wire.

[0147] In a possible implementation, the connection relationship between the modules recorded in the connection relationship file includes at least one connection path, each connection path includes at least two modules, and adjacent modules on each connection path serve as a pair of modules to be connected.

[0148] In a possible implementation manner, the connection relationship file also records the communication direction of each pair of modules to be connected.

[0149] In a possible implementation, the obtaining of the connection relationship file includes: determining at least one connection path according to a layout planning file of the chip and each pair of modules serving as endpoints of the connection path, wherein the layout planning file records the positions of each module in the chip, and each connection path includes at least two modules; determining the connection relationship between each module according to each connection path, and generating the connection relationship file, wherein adjacent modules on each connection path are regarded as a pair of modules to be connected.

[0150] In a possible implementation, when the connection relationship file records the communication direction of each module to be connected, obtaining the connection relationship file includes: determining at least one connection path according to the layout planning file of the chip and each pair of modules serving as the starting point and end point of the connection path, wherein the layout planning file records the position of each module in the chip, and each connection path includes at least two modules; determining the connection relationship between the modules and the communication direction of each module to be connected according to each connection path, and the adjacent modules on each connection path serve as a pair of modules to be connected.

[0151] In a possible implementation, the parsing of the connection relationship file and the interface file to generate a system configuration file includes: parsing the connection relationship file to determine each connection path; parsing the interface file to determine the interface to be connected on each module included in the connection path for connecting an adjacent module, and the connection relationship of the interface to be connected, to generate the system configuration file.

[0152] In some embodiments, the functions or modules included in the system provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0153] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0154] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0155] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0156] Fig.11 1 is a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Fig.11 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0157] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2003.TM , Mac OS X TM , Unix TM ,Linux TM , FreeBSD TM or similar.

[0158] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0159] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0160] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0161] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0162] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0163] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0164] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0165] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0166] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0167] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A module connection method, characterized in that: The method is used to connect modules in a chip, the chip includes multiple modules, and the method includes: Obtain a connection relationship file, a module file, and an interface file, wherein the module file records the function of each module, the connection relationship file records the connection relationship between modules, and the interface file records the interface of each module; Generate a system configuration file according to the connection relationship file and the interface file, wherein the system configuration file records the interface to be connected and the connection relationship of the interface to be connected; According to the system configuration file, an interface to be connected is generated in the module file and a connection relationship of the interface to be connected is established to obtain an updated module file, and the updated module file is used to guide multiple modules in the chip to be physically connected.

2. The method according to claim 1, characterized in that The method further comprises: Generate a beat file corresponding to each interface to be connected according to the interface file and the system configuration file, wherein the beat file is used to improve the signal transmission capability of the corresponding interface; Add the beat file to the module file, and instantiate the beat file in the module file.

3. The method according to claim 1, characterized in that Before generating the interface to be connected in the module file and establishing the connection relationship of the interface to be connected, the method further includes: In the module file, the connection relationship of the existing interfaces of each module is disconnected.

4. The method according to claim 2, characterized in that: The type of the interface includes an integrated interface, wherein the integrated interface connects multiple wires. The step of generating a beat file corresponding to each interface to be connected according to the interface file and the system configuration file comprises: The system configuration file is parsed to determine the type of each interface to be connected. In response to the type of the interface to be connected being an integrated interface, the interface file is parsed to determine the beat parameters of each wire connected to the interface to be connected, and a beat file corresponding to the interface to be connected is generated according to the beat parameters.

5. The method according to claim 4, characterized in that The step of parsing the interface file and determining the beat parameters of each wire connected to the interface to be connected currently includes: Parsing the interface file to determine the length of each wire connected to the interface to be connected; Determine a beat parameter of each wire according to the length of the wire, wherein the beat parameter is proportional to the length of the wire; The beat is completed by registers, and the beat parameter of each wire indicates the number of registers set on the wire.

6. The method according to claim 1, characterized in that The connection relationship between the modules recorded in the connection relationship file includes at least one connection path, each connection path includes at least two modules, and the adjacent modules on each connection path serve as a pair of modules to be connected.

7. The method according to claim 6, characterized in that The connection relationship file also records the communication direction of each pair of modules to be connected.

8. The method according to claim 6, characterized in that The obtaining of the connection relationship file includes: Determine at least one connection path according to a layout planning file of the chip and each pair of modules as endpoints of the connection path, wherein the layout planning file records the position of each module in the chip, and each connection path includes at least two modules; The connection relationship between the modules is determined according to each connection path, and the connection relationship file is generated. The adjacent modules on each connection path are regarded as a pair of modules to be connected.

9. The method according to claim 7, characterized in that: When the connection relationship file records the communication direction of each pair of modules to be connected, the step of obtaining the connection relationship file includes: Determine at least one connection path according to a layout planning file of the chip and each pair of modules as the starting point and the end point of the connection path, wherein the layout planning file records the position of each module in the chip, and each connection path includes at least two modules; The connection relationship between the modules and the communication direction of each pair of modules to be connected are determined according to each connection path, and the adjacent modules on each connection path are regarded as a pair of modules to be connected.

10. The method according to any one of claims 6 to 9, characterized in that: The generating of the system configuration file according to the connection relationship file and the interface file comprises: Parsing the connection relationship file to determine each connection path; The interface file is parsed to determine the interfaces to be connected on each module included in the connection path and used to connect to adjacent modules, as well as the connection relationship between the interfaces to be connected, and the system configuration file is generated.

11. A module connection system, characterized in that: The system is used to connect modules in a chip, the chip includes multiple modules, and the system includes: An acquisition unit, used to acquire a connection relationship file, a module file, and an interface file, wherein the module file records the function of each module, the connection relationship file records the connection relationship between the modules, and the interface file records the interface of each module; A first generating unit, configured to generate a system configuration file according to the connection relationship file and the interface file, wherein the system configuration file records the interfaces to be connected and the connection relationship between the interfaces to be connected; An updating unit is used to generate interfaces to be connected in the module file and establish connection relationships between the interfaces to be connected according to the system configuration file, so as to obtain an updated module file, wherein the updated module file is used to guide the physical connection of multiple modules in the chip.

12. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; Wherein, the processor is configured to implement the method described in any one of claims 1 to 10 when executing the instructions stored in the memory.

13. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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