Chip design index generation model training method and device and computer equipment

Abstract

The invention relates to a chip design index generation model training method and device and computer equipment. The method comprises the following steps: acquiring a physical design parameter configuration set; respectively inputting each physical design parameter configuration into a layout analysis tool, a clock tree analysis tool and a wiring analysis tool to obtain a chip design index; generating a new physical design parameter configuration and a new physical design parameter configuration set according to the chip design indexes; returning to execute the step of respectively inputting each physical design parameter configuration into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool until the chip design index corresponding to any physical design parameter configuration meets the preset index requirement, and obtaining a target chip design index; and according to the target chip design index and the corresponding physical design parameter configuration, determining a training sample, and training a chip design index generation model by using the training sample. By adopting the method, the chip design efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a chip design indicator generation model training method, device, computer equipment, computer-readable storage medium and computer program product. Background Art

[0002] Electronic Design Automation (EDA) emerged with the advent of integrated circuits (ICs). In the early stages of EDA, the logic design (Logic Design) and physical design (Physical Design) in integrated circuits were mainly processed in parallel, using wired circuit boards to build logic designs to simulate specific physical circuits in order to verify and simulate whether the designed functions are normal before production begins. With the development of circuit simulation (Circuit Simulation) and layout verification (Layout Verification), it is no longer necessary to build logic modules using wired circuit boards, which has greatly accelerated the development of integrated circuits.

[0003] Traditional technology requires a lot of time for layout analysis, clock tree analysis, and routing analysis in the process of chip physical design for large circuits, which increases the time spent on chip design and is not conducive to improving the efficiency of obtaining chip design indicators. Summary of the invention

[0004] Based on this, it is necessary to provide a chip design indicator generation model training method, device, computer equipment, computer-readable storage medium and computer program product that can improve the efficiency of chip design in response to the above-mentioned technical problems.

[0005] In a first aspect, the present application provides a chip design indicator generation model training method, comprising:

[0006] Acquire a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents configuration parameters of a layout analysis tool, configuration parameters of a clock tree analysis tool, and configuration parameters of a routing analysis tool;

[0007] Inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool respectively, to obtain chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set;

[0008] Generate a new physical design parameter configuration according to the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set;

[0009] Return to the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool, respectively, until a chip design index corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meets a preset index requirement, and use the chip design index that meets the preset index requirement as a target chip design index;

[0010] According to the target chip design indicators and the physical design parameter configuration corresponding to the target chip design indicators, training samples are determined, and the chip design indicator generation model to be trained is trained using the training samples; the chip design indicator generation model is used to determine the chip design indicators according to the output results of the layout analysis tool.

[0011] In one embodiment, generating a new physical design parameter configuration according to the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set includes:

[0012] Determining a design indicator threshold according to a chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set;

[0013] The physical design parameter configurations in the physical design parameter configuration set are divided into a first set and a second set according to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the first set is greater than or equal to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the second set is less than the design indicator threshold;

[0014] Determine a parameter configuration search space according to each physical design parameter configuration in the physical design parameter configuration set; the parameter configuration search space represents a value range of the physical design parameter configuration;

[0015] Determine, according to the first set and the second set, an expected improvement value of each physical design parameter configuration in the parameter configuration search space, and screen out a maximum expected improvement value from the expected improvement values;

[0016] The physical design parameter configuration corresponding to the maximum expected improvement value is used as the new physical design parameter configuration.

[0017] In one embodiment, the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool to obtain a chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set includes:

[0018] Determining configuration parameters of the layout analysis tool, configuration parameters of the clock tree analysis tool, and configuration parameters of the routing analysis tool according to each physical design parameter configuration in the physical design parameter configuration set;

[0019] Applying the configuration parameters of the layout analysis tool to the layout analysis tool to obtain an output result of the layout analysis tool;

[0020] Inputting the output result of the layout analysis tool into the clock tree analysis tool, and applying the configuration parameters of the clock tree analysis tool to the clock tree analysis tool to obtain the output result of the clock tree analysis tool;

[0021] Inputting the output result of the clock tree analysis tool into the wiring analysis tool, and applying the configuration parameters of the wiring analysis tool to the wiring analysis tool to obtain the output result of the wiring analysis tool;

[0022] According to the output results of the layout analysis tool, the output results of the clock tree analysis tool and the output results of the wiring analysis tool, the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set is determined.

[0023] In one embodiment, determining the training sample according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index includes:

[0024] Determining chip layout parameters according to the physical design parameter configuration, parsing the chip layout parameters to obtain a layout image, and converting the layout image into an embedding vector;

[0025] Determining a target vector according to the physical design parameter configuration corresponding to the target chip design indicator and the embedded vector;

[0026] The target vector and the target chip design index are used as the training samples.

[0027] In one embodiment, the step of using the training samples to train a chip design indicator generation model to be trained includes:

[0028] Inputting the target vector in the training sample into the chip design index generation model to be trained to obtain a prediction index;

[0029] Determining a model loss function value according to a difference between the prediction index and a target chip design index in the training sample;

[0030] According to the model loss function value, the chip design indicator generation model to be trained is adjusted.

[0031] In one of the embodiments, the chip design indicator includes at least one of chip area, actual wiring bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin and number of rule violations.

[0032] In a second aspect, the present application also provides a chip design index generation model training device, comprising:

[0033] An acquisition module, used to acquire a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents configuration parameters of a layout analysis tool, configuration parameters of a clock tree analysis tool, and configuration parameters of a routing analysis tool;

[0034] An analysis module, used to input each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, to obtain a chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set;

[0035] A generating module, configured to generate a new physical design parameter configuration according to chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set;

[0036] an execution module, configured to return to the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool, respectively, until a chip design index corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meets a preset index requirement, and the chip design index that meets the preset index requirement is used as a target chip design index;

[0037] A training module is used to determine training samples according to the target chip design indicators and the physical design parameter configuration corresponding to the target chip design indicators, and use the training samples to train the chip design indicator generation model to be trained; the chip design indicator generation model is used to determine the chip design indicators according to the output results of the layout analysis tool.

[0038] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the above method are implemented.

[0039] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0040] In a fifth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0041] The above-mentioned chip design indicator generation model training method, device, computer equipment, computer-readable storage medium and computer program product obtain a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool and the configuration parameters of the wiring analysis tool; each physical design parameter configuration in the physical design parameter configuration set is input into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, and the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set are obtained, so as to use the analysis tool to process the initial physical design parameter configuration to obtain the corresponding chip design indicators; according to the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set, a new physical design parameter configuration is generated, and the new physical design parameter configuration is added to the physical design parameter configuration set to obtain a new physical design parameter configuration set, so as to construct a new physical design parameter configuration set in combination with the chip design indicators of the initial physical design parameter configuration; return to execute each physical design parameter configuration in the physical design parameter configuration set is input into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively until the chip design index corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meets the preset index requirement, and the chip design index that meets the preset index requirement is used as the target chip design index, so as to accurately determine the chip design index that meets the preset index requirement through iteration; according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index, determine the training sample, and use the training sample to train the chip design index generation model to be trained; the chip design index generation model is used to determine the chip design index according to the output result of the layout analysis tool, so as to use the physical design parameter configurations such as layout configuration, clock tree configuration and wiring configuration and the chip design index to accurately train the chip design index generation model, so that the chip design index generation model can quickly output the chip design index and other information of the chip, and the chip design index generation model can efficiently and portablely determine the chip design index and other information, without manually configuring the parameters of the clock tree analysis tool and the wiring analysis tool one by one in each iteration of the chip design process, but the chip design index generation model predicts the chip design index based on the output result of the layout analysis tool, thereby reducing the generation time of the chip design index, thereby improving the efficiency of chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 An application environment diagram of a chip design indicator generation model training method in an embodiment;

[0044] Figure 2 A schematic diagram of a flow chart of a chip design indicator generation model training method in one embodiment;

[0045] Figure 3 A schematic diagram of a chip physical design process in one embodiment;

[0046] Figure 4 is a schematic diagram of a layout image in one embodiment;

[0047] Figure 5 is a schematic diagram of the architecture of a layout engine adapter in one embodiment;

[0048] Figure 6 A structural block diagram of a chip design indicator generation model training device in one embodiment;

[0049] Figure 7 The figure is a diagram of the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] The chip design index generation model training method provided in the embodiment of the present application can be applied to Figure 1In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. The terminal 102 obtains a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration characterizes the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the wiring analysis tool; the terminal 102 inputs each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool, respectively, to obtain the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set; the terminal 102 generates a new physical design parameter configuration according to the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set, and adds the new physical design parameter configuration to the physical design parameter configuration set, to obtain A new physical design parameter configuration set; the terminal 102 returns to execute the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, until the chip design index corresponding to any physical design parameter configuration in the physical design parameter configuration set meets the preset index requirement, and the chip design index that meets the preset index requirement is used as the target chip design index; the terminal 102 determines the training sample according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index, and uses the training sample to train the chip design index generation model to be trained; the chip design index generation model is used to determine the chip design index according to the output result of the layout analysis tool. Among them, the terminal 102 can be but not limited to various personal computers, laptops, etc. The server 104 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services.

[0052] In an exemplary embodiment, Figure 2 As shown, a chip design index generation model training method is provided, and the method is applied to a terminal as an example for explanation, including the following steps S202 to S210. Among them:

[0053] Step S202, obtaining a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents configuration parameters of a layout analysis tool, configuration parameters of a clock tree analysis tool, and configuration parameters of a routing analysis tool.

[0054] The physical design parameter configuration set may include several physical design parameter configurations.

[0055] The physical design parameter configuration may refer to information characterizing configuration parameters of a layout analysis tool, configuration parameters of a clock tree analysis tool, and configuration parameters of a routing analysis tool.

[0056] The layout analysis tool may refer to a tool used to perform physical verification, density analysis, routability prediction, parameter extraction, etc. on a chip. The configuration parameters of the layout analysis tool may include information characterizing the location arrangement of various modules or circuit units (such as CPU cores, caches, memory controllers, etc.) inside the chip.

[0057] The clock tree analysis tool may refer to a tool for performing clock network verification, load balancing, delay matching, power consumption evaluation, etc. on a chip. The configuration parameters of the clock tree analysis tool may include information characterizing the structure of the clock tree and related parameters of the clock tree.

[0058] The wiring analysis tool may refer to a tool used to perform connectivity verification, signal integrity analysis, power integrity analysis, compliance analysis, etc. on a chip. The configuration parameters of the wiring analysis tool may include information characterizing the setting of wires, metal layers, and vias between various circuit elements.

[0059] As an example, when performing chip design, the terminal can first obtain several groups of physical design parameter configurations input by the user. Several groups of physical design parameter configurations can constitute a physical design parameter configuration set. In actual applications, each group of physical design parameter configurations can represent the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the wiring analysis tool. For example: physical design parameter configuration 1 can represent the configuration parameters A1 of the layout analysis tool, the configuration parameters B1 of the clock tree analysis tool, and the configuration parameters C1 of the wiring analysis tool. Physical design parameter configuration 2 can represent the configuration parameters A2 of the layout analysis tool, the configuration parameters B2 of the clock tree analysis tool, and the configuration parameters C2 of the wiring analysis tool.

[0060] Step S204 , inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool and the routing analysis tool respectively, to obtain chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set.

[0061] Among them, the chip design index may refer to information characterizing indicators / parameters such as chip area, actual wiring bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin, and number of rule violations.

[0062] As an example, the terminal can input each physical design parameter configuration in the physical design parameter configuration set to the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively. The layout analysis tool can perform layout analysis based on the physical design parameter configuration, the clock tree analysis tool can perform clock tree analysis based on the physical design parameter configuration, and the wiring analysis tool can perform wiring analysis based on the physical design parameter configuration. The terminal can determine the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set based on the output results of the layout analysis tool, the output results of the clock tree analysis tool and the output results of the wiring analysis tool.

[0063] Step S206, generating a new physical design parameter configuration according to the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set, and adding the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set.

[0064] As an example, each physical design parameter configuration in the physical design parameter configuration set is pre-generated / configured, and the chip design indicators obtained by the layout analysis tool, the clock tree analysis tool and the wiring analysis tool based on each physical design parameter in the physical design parameter configuration set usually cannot meet the chip design requirements. At this time, the terminal can generate a new physical design parameter configuration according to the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set. For example: the original physical design parameter configuration set includes 3 groups of physical design parameter configurations. The terminal can determine the chip design indicators of the 3 groups of physical design parameter configurations through the layout analysis tool, the clock tree analysis tool and the wiring analysis tool. After that, the terminal can generate a new physical design parameter configuration based on the chip design indicators of the 3 groups of physical design parameter configurations, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set. At this time, the new physical design parameter configuration set includes 4 groups of physical design parameter configurations.

[0065] Step S208, return to the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, until the chip design index corresponding to any physical design parameter configuration in the physical design parameter configuration set meets the preset index requirement, and the chip design index that meets the preset index requirement is used as the target chip design index.

[0066] Among them, the preset indicator requirement may refer to pre-set information used to determine whether the chip design indicator meets the chip design requirements. In actual applications, the preset indicator requirements may include but are not limited to whether the difference between the chip design indicator and the design indicator threshold is less than the preset difference threshold, or whether the chip design indicator is greater than the design indicator threshold, etc. It can be understood that the preset chip design requirements may also include information such as the functions that the chip needs to have.

[0067] As an example, after obtaining a new physical design parameter configuration set, the terminal can input each physical design parameter configuration in the new physical design parameter configuration set into a layout analysis tool, a clock tree analysis tool, and a wiring analysis tool respectively to obtain chip design indicators corresponding to each physical design parameter configuration in the new physical design parameter configuration set. Then, the terminal can compare the chip design indicators corresponding to each physical design parameter configuration in the new physical design parameter configuration set with a preset design indicator threshold (or a design indicator threshold determined based on the chip design indicators corresponding to each physical design parameter configuration in the new physical design parameter configuration set) to determine whether the chip design indicators meet the preset indicator requirements. If the chip design indicators corresponding to any of the physical design parameter configurations in the new physical design parameter configuration set meet the preset indicator requirements, the terminal can compare the chip design indicators that meet the preset indicator requirements. The chip design indicators are used as target chip design indicators. If the chip design indicators corresponding to the physical design parameter configurations in the new physical design parameter configuration set do not meet the preset indicator requirements, the terminal can generate new physical design parameter configurations again according to the chip design indicators corresponding to the physical design parameter configurations in the new physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to achieve further update / expansion of the physical design parameter configuration set. After that, the terminal can input each physical design parameter configuration in the physical design parameter configuration set at this time into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, obtain the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set at this time, and judge whether the chip design indicators meet the preset indicator requirements until the target chip design indicators are obtained.

[0068] Step S210, determine the training samples according to the target chip design indicators and the physical design parameter configuration corresponding to the target chip design indicators, and use the training samples to train the chip design indicator generation model to be trained; the chip design indicator generation model is used to determine the chip design indicators according to the output results of the layout analysis tool.

[0069] The training sample may refer to information used to train a chip design indicator generation model to be trained.

[0070] Among them, the chip design indicator generation model can refer to a model used to determine the chip design indicators based on the output results of the layout analysis tool. In practical applications, the chip design indicator generation model can replace the clock tree analysis tool and the wiring tool, and quickly generate chip design indicators and other information based on the output results of the layout analysis tool.

[0071] As an example, the terminal can determine / generate training samples based on the target chip design indicators and the physical design parameter configurations corresponding to the target chip design indicators, and use the training samples to train the chip design indicator generation model to be trained. In actual applications, the chip design indicator generation model to be trained can be used as a pre-trained chip design indicator generation model after the training is completed. When determining the chip design indicators, the terminal can first obtain several groups of physical design parameter configurations input by the user, and then the terminal can input the several groups of physical design parameter configurations input by the user into the layout analysis tool. After that, the terminal can input the output results of the layout analysis tool into the pre-trained chip design indicator generation model, and the pre-trained chip design indicator generation model can output the chip design indicators.

[0072] In the above-mentioned chip design indicator generation model training method, a physical design parameter configuration set is obtained; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool and the configuration parameters of the wiring analysis tool; each physical design parameter configuration in the physical design parameter configuration set is input into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, and the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set are obtained, so as to use the analysis tool to process the initial physical design parameter configuration to obtain the corresponding chip design indicators; according to the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set, a new physical design parameter configuration is generated, and the new physical design parameter configuration is added to the physical design parameter configuration set to obtain a new physical design parameter configuration set, so as to construct a new physical design parameter configuration set in combination with the chip design indicators of the initial physical design parameter configuration; return to execute the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, until the physical design parameter configuration is The chip design index corresponding to any physical design parameter configuration in each physical design parameter configuration in the configuration set meets the preset index requirement, and the chip design index that meets the preset index requirement is used as the target chip design index, so as to accurately determine the chip design index that meets the preset index requirement through iteration; according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index, determine the training sample, and use the training sample to train the chip design index generation model to be trained; the chip design index generation model is used to determine the chip design index according to the output result of the layout analysis tool, so as to use the physical design parameter configurations such as layout configuration, clock tree configuration and wiring configuration and the chip design index to accurately train the chip design index generation model, so that the chip design index generation model can quickly output the chip design index and other information of the chip, and the chip design index generation model efficiently and conveniently determines the chip design index and other information, without manually configuring the parameters of the clock tree analysis tool and the wiring analysis tool one by one in each iteration of the chip design process, but the chip design index generation model predicts the chip design index based on the output result of the layout analysis tool, thereby reducing the generation time of the chip design index, and then improving the efficiency of chip design.

[0073] In an exemplary embodiment, a new physical design parameter configuration is generated according to the chip design indicators corresponding to each physical design parameter configuration in a physical design parameter configuration set, including: determining a design indicator threshold according to the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set; dividing each physical design parameter configuration in the physical design parameter configuration set into a first set and a second set according to the design indicator threshold; the chip design indicators corresponding to the physical design parameter configurations in the first set are greater than or equal to the design indicator threshold; the chip design indicators corresponding to the physical design parameter configurations in the second set are less than the design indicator threshold; determining a parameter configuration search space according to each physical design parameter configuration in the physical design parameter configuration set; the parameter configuration search space represents the value range of the physical design parameter configuration; determining the expected improvement value of each physical design parameter configuration in the parameter configuration search space according to the first set and the second set, and screening out the maximum expected improvement value from the expected improvement values; and taking the physical design parameter configuration corresponding to the maximum expected improvement value as the new physical design parameter configuration.

[0074] Among them, the design indicator threshold may refer to information used to determine whether the chip design indicator meets the chip design requirements. In actual applications, the design indicator threshold may include but is not limited to the average value or median of the chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set. The design indicator threshold may also be a preset value.

[0075] As an example, the terminal may calculate the median / average and other information of the chip design index according to the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set to obtain the design index threshold, and then the terminal may divide each physical design parameter configuration in the physical design parameter configuration set into a first set and a second set according to the design index threshold, wherein the chip design index corresponding to the physical design parameter configuration in the first set is greater than or equal to the design index threshold, and the chip design index corresponding to the physical design parameter configuration in the second set is less than the design index threshold. The terminal may also analyze the value range of the physical design parameter configuration according to each physical design parameter configuration in the physical design parameter configuration set, and determine the parameter configuration search space according to the value range of the physical design parameter configuration, and then the terminal may determine the expected improvement value of each physical design parameter configuration in the parameter configuration search space according to the physical design parameter configuration in the first set and the chip design index corresponding to the physical design parameter configuration and the physical design parameter configuration in the second set and the chip design index corresponding to the physical design parameter configuration, using a preset expected improvement value calculation expression, and the terminal may also filter out the expected improvement value with the largest value from the calculated expected improvement values ​​as the maximum expected improvement value, and then the terminal may set the maximum expected improvement value as the maximum expected improvement value. The physical design parameter configuration corresponding to the expected improvement value is taken as a new physical design parameter configuration. In a specific implementation, each physical design parameter configuration in the physical design parameter configuration set can be understood as a number of isolated data points, and each physical design parameter configuration in the parameter configuration search space can be understood as a data interval containing the above data points. The terminal can combine the physical design parameter configurations in the first set and the chip design indicators corresponding to the physical design parameter configurations and the physical design parameter configurations in the second set and the chip design indicators corresponding to the physical design parameter configurations, and respectively calculate the expected improvement values ​​corresponding to each data in the above data interval. The physical design parameter configuration corresponding to the expected improvement value with the largest value can be taken as the new physical design parameter configuration.

[0076] In practical applications, the terminal can calculate the expected improvement value of each physical design parameter configuration in the parameter configuration search space based on the TPE (Tree-structured Parzen Estimator) algorithm (an algorithm for Bayesian optimization), and then the terminal can filter out the maximum value from each expected improvement value as the maximum expected improvement value. In practical applications, the maximum expected improvement value is related to the chip design indicator. For example, when the chip design indicator is chip area, the maximum expected improvement value can be the maximum value of the chip area reduction; when the chip design indicator is the actual bus length of the wiring, the maximum expected improvement value can be the maximum value of the reduction of the actual bus length of the wiring; when the chip design indicator is chip power consumption, the maximum expected improvement value can be the maximum value of the chip power consumption reduction; when the chip design indicator is clock frequency, the maximum expected improvement value can be the maximum value of the clock frequency increase; when the chip design indicator is the worst negative timing margin, the maximum expected improvement value can be the minimum value of the difference between the negative timing margin and 0; when the chip design indicator is the total negative timing margin, the maximum expected improvement value can be the minimum value of the difference between the total negative timing margin and 0; when the layout metric is the number of rule violations, the maximum expected improvement value can be the minimum value of the number of rule violations.

[0077] In this embodiment, a design indicator threshold is determined according to chip design indicators corresponding to each physical design parameter configuration in a physical design parameter configuration set; each physical design parameter configuration in the physical design parameter configuration set is divided into a first set and a second set according to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the first set is greater than or equal to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the second set is less than the design indicator threshold; a parameter configuration search space is determined according to each physical design parameter configuration in the physical design parameter configuration set; the parameter configuration search space represents the value range of the physical design parameter configuration; the period of each physical design parameter configuration in the parameter configuration search space is determined according to the first set and the second set. The method comprises the following steps: a first step is to determine the expected improvement value of each physical design parameter configuration in the parameter configuration search space determined by each physical design parameter configuration in the physical design parameter configuration set, and a second step is to determine the expected improvement value of each physical design parameter configuration in the parameter configuration search space determined by each physical design parameter configuration in the physical design parameter configuration set, and the third step is to determine the accurate physical design parameter configuration so as to accurately update the physical design parameter configuration set, improve the accuracy of the physical design parameter configuration set, and thus improve the accuracy of the chip design.

[0078] In some embodiments, each physical design parameter configuration in the physical design parameter configuration set is respectively input into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool to obtain the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set, including: determining the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool and the configuration parameters of the wiring analysis tool according to each physical design parameter configuration in the physical design parameter configuration set; applying the configuration parameters of the layout analysis tool to the layout analysis tool to obtain the output result of the layout analysis tool; inputting the output result of the layout analysis tool into the clock tree analysis tool, and applying the configuration parameters of the clock tree analysis tool to the clock tree analysis tool to obtain the output result of the clock tree analysis tool; inputting the output result of the clock tree analysis tool into the wiring analysis tool, and applying the configuration parameters of the wiring analysis tool to the wiring analysis tool to obtain the output result of the wiring analysis tool; determining the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set according to the output result of the layout analysis tool, the output result of the clock tree analysis tool and the output result of the wiring analysis tool.

[0079] As an example, the terminal can determine the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the wiring analysis tool according to each physical design parameter configuration in the physical design parameter configuration set. Then, the terminal can apply the configuration parameters of the layout analysis tool to the layout analysis tool. The layout analysis tool can perform physical verification, density analysis, routability prediction, and parameter extraction based on the configuration parameters of the layout analysis tool to obtain the output result of the layout analysis tool. Then, the terminal can input the output result of the layout analysis tool into the clock tree analysis tool, and apply the configuration parameters of the clock tree analysis tool to the clock tree analysis tool. The clock tree analysis tool can combine the output result of the layout analysis tool and the configuration parameters of the clock tree analysis tool to perform clock network verification, load balancing, delay matching, and power consumption evaluation to obtain the output result of the clock tree analysis tool. Then, the terminal can input the output result of the clock tree analysis tool into the wiring analysis tool, and apply the configuration parameters of the wiring analysis tool to the wiring analysis tool. The wiring analysis tool can combine the output result of the clock tree analysis tool and the configuration parameters of the wiring analysis tool to perform connectivity verification, signal integrity analysis, power integrity analysis, and compliance analysis to obtain the output result of the wiring analysis tool. In actual applications, the terminal can determine the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set according to the output results of the layout analysis tool, the output results of the clock tree analysis tool, and the output results of the wiring analysis tool.

[0080] In this embodiment, the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the wiring analysis tool are determined according to each physical design parameter configuration in the physical design parameter configuration set; the configuration parameters of the layout analysis tool are applied to the layout analysis tool to obtain the output result of the layout analysis tool; the output result of the layout analysis tool is input to the clock tree analysis tool, and the configuration parameters of the clock tree analysis tool are applied to the clock tree analysis tool to obtain the output result of the clock tree analysis tool; the output result of the clock tree analysis tool is input to the wiring analysis tool, and the configuration parameters of the wiring analysis tool are applied to the wiring analysis tool to obtain the output result of the wiring analysis tool; according to the output result of the layout analysis tool, the output result of the clock tree analysis tool, and the output result of the wiring analysis tool, the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set are determined, and the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool can be used to accurately and orderly perform chip design and analysis, obtain accurate chip design indicators, and improve the accuracy of the chip design indicators.

[0081] In some embodiments, training samples are determined based on target chip design indicators and physical design parameter configurations corresponding to the target chip design indicators, including: determining chip layout parameters based on the physical design parameter configuration, parsing the chip layout parameters to obtain a layout image, and converting the layout image into an embedding vector; determining a target vector based on the physical design parameter configuration and the embedding vector corresponding to the target chip design indicators; and using the target vector and the target chip design indicators as training samples.

[0082] The chip layout parameters may refer to information characterizing the layout and connection relationship of circuit elements on the chip.

[0083] The layout image can display the layout and connection relationship of circuit elements on the chip in the form of an image.

[0084] The embedded vector may refer to information obtained after converting the layout image into a preset vector space.

[0085] As an example, the physical design parameter configuration may include chip layout parameters, and the terminal may analyze the physical design parameter configuration to determine the chip layout parameters. The chip layout parameters may be used as a design netlist file that can characterize the layout and connection relationship of circuit elements on the chip. The terminal may parse the chip layout parameters / the design netlist file obtained from the chip layout parameters to determine the layout image, and then the terminal may convert the layout image into a preset space to obtain an embedding vector. The terminal may then determine the target vector based on the physical design parameter configuration and the embedding vector corresponding to the target chip design index; the target vector and the target chip design index are used as training samples. In practical applications, the physical design parameter configuration may be represented as X, the chip design index may be represented as Y, and the embedding vector may be represented as V, and the training sample may be represented as ([X, V], Y).

[0086] In this embodiment, the chip layout parameters are determined according to the physical design parameter configuration, the chip layout parameters are parsed to obtain a layout image, and the layout image is converted into an embedding vector; the target vector is determined according to the physical design parameter configuration and the embedding vector corresponding to the target chip design index; the target vector and the target chip design index are used as training samples, the layout image obtained based on the chip layout parameter determination can be converted into an embedding vector, and accurate training samples can be generated in combination with the target chip design index and the physical design parameter configuration corresponding to the target chip design index, so that the training samples can be used to subsequently train the chip design index generation model to be trained, thereby optimizing the performance of the chip design index generation model to be trained.

[0087] In some embodiments, a chip design indicator generation model to be trained is trained using training samples, including: inputting a target vector in the training sample into the chip design indicator generation model to be trained to obtain a prediction indicator; determining a model loss function value based on a difference between the prediction indicator and the target chip design indicator in the training sample; and adjusting the chip design indicator generation model to be trained based on the model loss function value.

[0088] Among them, the prediction indicator may refer to the chip design indicator output by the chip design indicator generation model based on the physical design parameter configuration represented by the target vector. In practical applications, the chip design indicator output by the chip design indicator generation model can be used as a predicted value of the chip design indicator corresponding to the physical design parameter configuration represented by the target vector input into the chip design indicator generation model. It can be understood that the chip design indicator generation model can be used to simplify / replace the steps of clock tree analysis and wiring analysis, and speed up the determination of chip design indicators.

[0089] Among them, the model loss function value can refer to information that characterizes the degree of difference between the predicted value and the true value output by the chip design indicator generation model. In practical applications, the model loss function value can be used to adjust the model parameters of the chip design indicator generation model.

[0090] As an example, the terminal can input the target vector in the training sample into the chip design indicator generation model to be trained. The chip design indicator generation model to be trained can analyze the physical design parameter configuration represented by the target vector to obtain the prediction indicator. Then the terminal can determine the model loss function value based on the difference between the prediction indicator and the target chip design indicator in the training sample. If the model loss function value meets the preset loss function value requirement, the terminal can determine that the chip design indicator generation model training is completed. If the model loss function value does not meet the preset loss function value requirement, the terminal can adjust the model parameters of the chip design indicator generation model to be trained according to the model loss function value. Then the terminal can The target vector in the training sample is input into the chip design indicator generation model again. The chip design indicator generation model can generate a new prediction indicator. Then, the terminal can determine the model loss function value again based on the difference between the new prediction indicator and the target chip design indicator in the training sample. If the model loss function value still does not meet the preset loss function value requirements, the terminal can adjust the model parameters of the chip design indicator generation model based on the model loss function value at this time, and then repeat the above steps until the chip design indicator generation model training is completed, and a trained chip design indicator generation model is obtained. The trained chip design indicator generation model can be used as a pre-trained chip design indicator generation model.

[0091] In this embodiment, the prediction index is obtained by inputting the target vector in the training sample into the chip design index generation model to be trained; the model loss function value is determined according to the difference between the prediction index and the target chip design index in the training sample; according to the model loss function value, the chip design index generation model to be trained is adjusted, so that the model loss function value can be accurately calculated based on the training sample, and the chip design index generation model can be accurately adjusted, so as to optimize the model performance of the chip design index generation model and improve the accuracy of the chip design index output by the chip design index generation model.

[0092] In some embodiments, the chip design indicator includes at least one of chip area, actual wiring bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin, and number of rule violations.

[0093] Among them, the chip area (Area) can refer to the maximum product of the dimensions from one edge of the chip to another opposite edge, that is, length times width. The chip area can include all active and passive components, interconnects, power networks and other parts that make up the chip. In practical applications, the chip area can represent the actual physical space occupied by the integrated circuit on the silicon wafer.

[0094] The actual wiring bus length (Wirelength) may refer to the sum of the lengths of each wire connecting two endpoints (such as input and output pins between logic units).

[0095] The chip power consumption (Power) may refer to the electric energy consumed by the integrated circuit in a working state.

[0096] The clock frequency may refer to the number of switching times per second of a clock signal in a digital circuit.

[0097] Among them, the worst negative slack (WNS) can refer to the timing slack of a path that violates the timing constraints most seriously among all paths. The actual arrival time of this path exceeds the specified time limit. The timing slack refers to the difference between the specified setup time (Setup Time) or hold time (Hold Time) and the actual arrival time. A positive timing slack means that the path meets the timing requirements; a negative timing slack means that there is a timing violation.

[0098] The total negative slack (TNS) may refer to the sum of absolute values ​​of the timing slack on all negative timing slack paths.

[0099] The number of rule violations may refer to the total number of errors detected by verification tools such as Design Rule Check (DRC) or Electrical Rule Check (ERC) that indicate the design does not meet specific process requirements or circuit specifications.

[0100] As an example, the terminal can analyze information such as chip layout parameters, determine the maximum size from one edge of the chip to another opposite edge (such as the length and width of the chip) and calculate the product of the maximum size to obtain the chip area. The terminal can analyze information such as chip layout parameters, determine the length of each wire connecting two endpoints (such as input and output pins between logic units), and calculate the sum of the lengths of the above wires to obtain the actual wiring bus length. The terminal can simulate the behavior of the circuit in the chip based on information such as chip layout parameters, and monitor the power consumed by the circuit in the working state to obtain the chip power consumption. The terminal can perform static timing analysis based on information such as chip layout parameters to determine the clock frequency. The terminal can perform static timing analysis based on information such as chip layout parameters to determine the difference between the specified setup time (SetupTime) or hold time (Hold Time) of each path in the chip and the actual arrival time of the path to obtain the timing margin, and use the timing margin with the largest absolute value among the negative timing margins as the worst negative timing margin. The terminal can also calculate the sum of the absolute values ​​of the negative timing margins to obtain the total negative timing margin. The terminal may also perform rule checks on information such as chip layout parameters based on design rule checks (DRC) or electrical rule checks (ERC) to determine whether information such as chip layout parameters violates regulations and determine the number of design rules violated by information such as chip layout parameters as the number of rule violations.

[0101] In this embodiment, by analyzing design indicators such as chip area, actual wiring bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin and number of rule violations, the accuracy of design indicator information can be improved so as to obtain accurate training samples, thereby improving the accuracy of the output results of the chip design indicator generation model trained using the training samples.

[0102] In some embodiments, Figure 3As shown, a schematic diagram of the process of chip physical design is provided. In order to perform full-process multi-objective optimization of chip physical design, the terminal can establish a sample set of (physical design parameter configuration X, chip design index Y). At the beginning, X and Y are both empty (that is, the sample set is initialized). The terminal can define a parameter configuration space, which includes configuration parameters of a layout analysis tool, a clock tree analysis tool, and a wiring analysis tool. During chip design, the terminal can obtain the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the wiring analysis tool from the parameter configuration space, thereby determining the physical design parameter configuration set. The terminal can determine the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the wiring analysis tool according to each physical design parameter configuration in the physical design parameter configuration set, and then the terminal can apply the configuration parameters of the layout analysis tool to the layout analysis tool to implement the layout stage parameter configuration and obtain the output result of the layout analysis tool, input the output result of the layout analysis tool to the clock tree analysis tool, and apply the configuration parameters of the clock tree analysis tool to the clock tree analysis tool to implement the clock tree analysis stage parameter configuration and obtain the output result of the clock tree analysis tool, input the output result of the clock tree analysis tool to the wiring analysis tool, and apply the configuration parameters of the wiring analysis tool to the wiring analysis tool to implement the wiring stage parameter configuration and obtain the output result of the wiring analysis tool. The terminal can use the preset layout engine adapter, combined with the output results of the layout analysis tool, the output results of the clock tree analysis tool and the output results of the wiring analysis tool, to determine the chip design indicators such as chip area (Area), actual wiring bus length (Wirelength), chip power consumption (Power), clock frequency (Frequency), worst negative timing margin (WNS), total negative timing margin (TNS) and design rule violation (DRC) corresponding to each physical design parameter configuration in the physical design parameter configuration set. The chip design indicators can be used as the final output of the physical design.

[0103] The terminal can use the expected improvement algorithm based on the chip design index to generate a physical design parameter configuration that maximizes the current expected improvement value to update the physical design parameter configuration set. In actual applications, the terminal can determine the parameter configuration search space based on each physical design parameter configuration in the physical design parameter configuration set, and determine the layout metric value (such as chip design index) y of each physical design parameter configuration x in the parameter configuration search space using a preset calculation expression. At the same time, the terminal can also set a threshold (such as design index threshold y) * , and based on the threshold y * To divide the two layout density functions l(x) and g(x), a conditional probability p(x|y) can be defined, which can be expressed as:

[0104] ,

[0105] Where l(x) refers to the number of physical design parameter configurations x where the layout metric value y is less than the threshold y. * The layout density function of the physical design parameter configuration of the physical design parameter configuration, g(x) can refer to the layout metric value y in all physical design parameter configurations x that is greater than or equal to the threshold y * The layout density function of the physical design parameter configuration of x is assumed to be less than the threshold value y. * It is expressed as p(y< y * )= , then the expected improvement value EI of the TPE algorithm is y* (x) can be expressed as:

[0106] ,

[0107] Among them, Y(X) can refer to the observation set under the existing sample X (such as physical design parameter configuration), which refers to Y, p(x) can refer to the distribution of parameters (such as physical design parameter configuration), and p(y) can refer to the distribution of observation values.

[0108] Based on the above calculation expression, the expected improvement value of each physical design parameter configuration can be determined, and the physical design parameter configuration corresponding to the largest expected improvement value among the expected improvement values ​​can be used as a new physical design parameter configuration, so as to update the physical design parameter configuration set. If the chip design index corresponding to any physical design parameter configuration in each physical design parameter configuration in the physical design parameter configuration set meets the preset index requirement, the terminal can determine that the optimization can be ended at this time.

[0109] In a specific implementation, the terminal can analyze the physical design parameter configuration, determine the chip layout parameters, convert the chip layout parameters into a design netlist file, and parse the design netlist file to obtain a layout image, such as Figure 4 As shown, a schematic diagram of a layout image is provided. The terminal can also use a Transformer network to convert the layout image into a preset vector space to obtain embedded vector information v.

[0110] The terminal can also analyze chip design indicators such as chip area (Area), actual wiring bus length (Wirelength), chip power consumption (Power), clock frequency (Frequency), worst negative timing margin (WNS), total negative timing margin (TNS) and design rule violation (DRC) based on the final output of the physical design. After that, the terminal can add the final output of the physical design (such as the physical design parameter configuration) to X, and add the chip design indicators to Y to obtain training samples. The training samples can form a sample set. At the same time, the terminal can also save the embedded vector v to V and splice V with X as additional encoding information. It can be understood that the terminal can expand the sample set by updating the physical design parameter configuration set, and the sample set can contain several training samples. The terminal can establish a regression model for ([X, V], Y), and the terminal can also use the final output of the physical design corresponding to each training sample, the chip design indicator and the embedded vector to train the chip design indicator generation model to be trained. The trained chip design indicator generation model can output information such as the layout position of circuit elements on the chip, the connection relationship between circuit elements, and chip design indicators such as chip area, actual wiring bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin and number of rule violations based on the output results of the layout analysis tool. There is no need to perform complex clock tree analysis and wiring analysis, thereby accelerating the generation speed of chip design indicators and the chip design process, and reducing chip design time.

[0111] like Figure 5 As shown, a schematic diagram of the architecture of a layout engine adapter is provided. The layout engine adapter can integrate Python and C++ operations to implement layout configuration in chip design. Specifically, the layout engine adapter can be used as a top-level module to coordinate operations at different levels. The layout engine adapter can be used as an interface-level architecture. The organization level of the layout engine adapter can include Python processes and subsystems. The operation level of the layout engine adapter includes Python Placement API, Python WL, Python Density, C++ Density, C++ WL, parameter configuration, and layout engine execution. Python is mainly used for high-level operations and API calls, while C++ is responsible for the underlying specific calculations and optimizations.

[0112] In this embodiment, by comprehensively considering the routing, clock tree analysis and layout tasks, optimization is carried out from the perspective of the entire physical design stage, and more comprehensive indicators are considered, especially the indicators after routing. In this way, the overall indicators are more referenceable and practical. At the same time, the design rule violation (DRC) is considered in the indicators, which is a particularly critical indicator. If the indicator is not 0, the next process will not be considered. This can solve the problem of slow evaluation in the physical design stage on large chips, and use a machine learning model to approximate the indicators, thereby improving the efficiency of chip design.

[0113] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0114] Based on the same inventive concept, the embodiment of the present application also provides a chip design indicator generation model training device for implementing the chip design indicator generation model training method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more chip design indicator generation model training device embodiments provided below can refer to the limitations of the chip design indicator generation model training method above, and will not be repeated here.

[0115] In an exemplary embodiment, Figure 6 As shown, a chip design index generation model training device is provided, including: an acquisition module 602, an analysis module 604, a generation module 606, an execution module 608 and a training module 610, wherein:

[0116] The acquisition module 602 is used to acquire a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool and the configuration parameters of the routing analysis tool.

[0117] The analysis module 604 is used to input each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, and obtain the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set.

[0118] The generation module 606 is used to generate a new physical design parameter configuration according to the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set.

[0119] The execution module 608 is used to return to the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, until the chip design index corresponding to any physical design parameter configuration in the physical design parameter configuration set meets the preset index requirement, and the chip design index that meets the preset index requirement is used as the target chip design index.

[0120] The training module 610 is used to determine the training samples according to the target chip design indicators and the physical design parameter configuration corresponding to the target chip design indicators, and use the training samples to train the chip design indicator generation model to be trained; the chip design indicator generation model is used to determine the chip design indicators according to the output results of the layout analysis tool.

[0121] In one of the exemplary embodiments, the generation module 606 is specifically used to determine a design indicator threshold according to the chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set; divide each physical design parameter configuration in the physical design parameter configuration set into a first set and a second set according to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the first set is greater than or equal to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the second set is less than the design indicator threshold; determine a parameter configuration search space according to each physical design parameter configuration in the physical design parameter configuration set; the parameter configuration search space represents the value range of the physical design parameter configuration; determine the expected improvement value of each physical design parameter configuration in the parameter configuration search space according to the first set and the second set, and filter out the maximum expected improvement value from the expected improvement values; and use the physical design parameter configuration corresponding to the maximum expected improvement value as the new physical design parameter configuration.

[0122] In one of the exemplary embodiments, the analysis module 604 is specifically used to determine the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the wiring analysis tool according to each physical design parameter configuration in the physical design parameter configuration set; apply the configuration parameters of the layout analysis tool to the layout analysis tool to obtain the output result of the layout analysis tool; input the output result of the layout analysis tool to the clock tree analysis tool, and apply the configuration parameters of the clock tree analysis tool to the clock tree analysis tool to obtain the output result of the clock tree analysis tool; input the output result of the clock tree analysis tool to the wiring analysis tool, and apply the configuration parameters of the wiring analysis tool to the wiring analysis tool to obtain the output result of the wiring analysis tool; determine the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set according to the output result of the layout analysis tool, the output result of the clock tree analysis tool, and the output result of the wiring analysis tool.

[0123] In one of the exemplary embodiments, the training module 610 is further specifically used to determine chip layout parameters according to the physical design parameter configuration, parse the chip layout parameters to obtain a layout image, and convert the layout image into an embedding vector; determine a target vector according to the physical design parameter configuration corresponding to the target chip design indicator and the embedding vector; and use the target vector and the target chip design indicator as the training samples.

[0124] In one of the exemplary embodiments, the training module 610 is specifically used to input the target vector in the training sample into the chip design indicator generation model to be trained to obtain a prediction indicator; determine the model loss function value based on the difference between the prediction indicator and the target chip design indicator in the training sample; and adjust the chip design indicator generation model to be trained based on the model loss function value.

[0125] In one of the exemplary embodiments, the chip design indicators include at least one of chip area, actual wiring bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin and number of rule violations.

[0126] Each module in the above-mentioned chip design index generation model training device can be implemented in whole or in part by software, hardware and their combination. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0127] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 7 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (Near Field Communication, NFC) or other technologies. When the computer program is executed by the processor, a chip design indicator generation model training method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0128] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0129] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0130] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0131] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0132] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0133] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0134] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0135] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip design index generation model training method, characterized in that: The method comprises: Acquire a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents configuration parameters of a layout analysis tool, configuration parameters of a clock tree analysis tool, and configuration parameters of a routing analysis tool; Inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool respectively, to obtain chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set; Generate a new physical design parameter configuration according to the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set; Return to the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool, respectively, until a chip design index corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meets a preset index requirement, and use the chip design index that meets the preset index requirement as a target chip design index; According to the target chip design indicators and the physical design parameter configuration corresponding to the target chip design indicators, training samples are determined, and the chip design indicator generation model to be trained is trained using the training samples; the chip design indicator generation model is used to determine the chip design indicators according to the output results of the layout analysis tool.

2. The method according to claim 1, characterized in that The generating a new physical design parameter configuration according to the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set includes: Determine a design indicator threshold value according to a chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set; The physical design parameter configurations in the physical design parameter configuration set are divided into a first set and a second set according to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the first set is greater than or equal to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the second set is less than the design indicator threshold; Determine a parameter configuration search space according to each physical design parameter configuration in the physical design parameter configuration set; the parameter configuration search space represents a value range of the physical design parameter configuration; Determine, according to the first set and the second set, an expected improvement value of each physical design parameter configuration in the parameter configuration search space, and screen out a maximum expected improvement value from the expected improvement values; The physical design parameter configuration corresponding to the maximum expected improvement value is used as the new physical design parameter configuration.

3. The method according to claim 1, characterized in that The step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool to obtain a chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set includes: Determining configuration parameters of the layout analysis tool, configuration parameters of the clock tree analysis tool, and configuration parameters of the routing analysis tool according to each physical design parameter configuration in the physical design parameter configuration set; Applying the configuration parameters of the layout analysis tool to the layout analysis tool to obtain an output result of the layout analysis tool; Inputting the output result of the layout analysis tool into the clock tree analysis tool, and applying the configuration parameters of the clock tree analysis tool to the clock tree analysis tool to obtain the output result of the clock tree analysis tool; Inputting the output result of the clock tree analysis tool into the wiring analysis tool, and applying the configuration parameters of the wiring analysis tool to the wiring analysis tool to obtain the output result of the wiring analysis tool; According to the output results of the layout analysis tool, the output results of the clock tree analysis tool and the output results of the wiring analysis tool, the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set is determined.

4. The method according to claim 1, characterized in that: The determining of the training sample according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index includes: Determining chip layout parameters according to the physical design parameter configuration, parsing the chip layout parameters to obtain a layout image, and converting the layout image into an embedding vector; Determining a target vector according to the physical design parameter configuration corresponding to the target chip design indicator and the embedded vector; The target vector and the target chip design index are used as the training samples.

5. The method according to claim 4, characterized in that The step of using the training samples to train a chip design indicator generation model to be trained includes: Inputting the target vector in the training sample into the chip design index generation model to be trained to obtain a prediction index; Determining a model loss function value according to a difference between the prediction index and a target chip design index in the training sample; According to the model loss function value, the chip design indicator generation model to be trained is adjusted.

6. The method according to claim 1, characterized in that The chip design index includes at least one of chip area, actual wiring bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin and number of rule violations.

7. A chip design index generation model training device, characterized in that: The device comprises: An acquisition module, used to acquire a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents configuration parameters of a layout analysis tool, configuration parameters of a clock tree analysis tool, and configuration parameters of a routing analysis tool; An analysis module, used to input each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, to obtain a chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set; A generating module, configured to generate a new physical design parameter configuration according to chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set; an execution module, configured to return to the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool, respectively, until a chip design index corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meets a preset index requirement, and the chip design index that meets the preset index requirement is used as a target chip design index; A training module is used to determine training samples according to the target chip design indicators and the physical design parameter configuration corresponding to the target chip design indicators, and use the training samples to train the chip design indicator generation model to be trained; the chip design indicator generation model is used to determine the chip design indicators according to the output results of the layout analysis tool.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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