Real-time image defogging and moving target detection combined system

Abstract

The invention relates to a real-time image defogging and moving target detection combined system. The system comprises a first VDMAIP core used for receiving a first data stream and sending the first data stream to a memory for storage; the moving target detection IP core is used for receiving the first data stream output by the image defogging IP core and the first data stream read and output by the first VDMAIP core from the memory, and performing moving target detection by adopting a frame difference method to obtain a second data stream; and the second VDMAIP core is used for receiving the second data stream and sending the second data stream to the display for displaying. According to the invention, a module design is adopted to integrate image defogging and moving target detection functions into a complete system so as to realize accurate detection of moving objects in fog; meanwhile, the whole system is developed by means of a ZYNQ embedded platform, FPGA hardware resources of the system are fully utilized to accelerate algorithm processing, and the real-time performance of the system is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to a system combining real-time image defogging and moving target detection. Background Art

[0002] Computer vision technology has developed rapidly in key areas such as intelligent transportation, security monitoring, autonomous driving assistance, and drone monitoring, and has demonstrated significant influence. However, in environments with limited visibility (such as foggy days), suspended particles in the air can cause light absorption and scattering, resulting in reduced image contrast, weakened color saturation, and loss of key details, which seriously affects the effective acquisition of image information. Image defogging technology has emerged, using a variety of effective methods to eliminate the negative impact of fog on image quality, significantly enhance image contrast and clarity, and restore detail information, thereby improving the quality and accuracy of visual perception.

[0003] At the same time, in various sub-fields of computer vision, image motion target detection also plays a key role, covering machine vision, image matching, detection, target tracking and pattern recognition. This technology is based on digital image processing and integrates multiple modern technology fields such as optics, electronics, computer science and automated testing. It has built a highly integrated comprehensive system and is widely used in various industries.

[0004] Most of the current defogging algorithms and moving target detection methods are developed and implemented on the PC side. However, due to the large size of PC devices, it is difficult to meet the needs of portable image defogging systems. At the same time, the PC side usually adopts a serial data processing mode, which has low processing efficiency, especially when executing complex algorithms, which often takes a long time. This data processing method is not conducive to application scenarios with high real-time requirements, especially when deployed in mobile devices or embedded systems.

[0005] In addition, most of the existing image defogging algorithms and moving target detection algorithms are executed separately and independently of each other, lacking effective combination and integrated application of the two. This results in the inability of existing systems to simultaneously achieve collaborative processing of defogging and moving target detection in environments with limited visibility such as foggy days, limiting the ability to detect and identify moving objects in real time in complex environments. Therefore, there is an urgent need to develop a comprehensive system that combines defogging and moving target detection functions to achieve accurate detection of moving objects in fog, improve the intelligence and real-time performance of the system, and thus meet the needs of application scenarios such as intelligent transportation and unmanned driving. Summary of the invention

[0006] Based on this, it is necessary to provide a system that combines real-time image defogging and moving target detection to address the above technical problems and improve the practicality and real-time performance of the system.

[0007] In the first aspect, the present application provides a system combining real-time image defogging and moving target detection based on the ZYNQ platform. The system includes:

[0008] An image defogging IP core is used to defog the received video or image sequence using a defogging algorithm to obtain a first data stream;

[0009] A first VDMAIP core is used to receive a first data stream and send it to a memory for storage;

[0010] A moving target detection IP core is used to receive the first data stream output by the image defogging IP core and the first data stream read and output by the first VDMA IP core from the memory, perform moving target detection using a frame difference method, and obtain a second data stream;

[0011] The second VDMAIP core is used to receive the second data stream and send it to the display for display.

[0012] In one embodiment, the first data stream received by the moving object detection IP core from the first VDMA IP core is delayed by a preset number of frames compared with the first data stream received from the image defogging IP core.

[0013] In one embodiment, the first VDMA IP core and the second VDMA IP core adopt a dynamic synchronous phase locking mode.

[0014] In one embodiment, the image defogging IP core uses a 3*3 filter to filter the video or image sequence.

[0015] In one embodiment, the image dehazing IP core amplifies the dehazing algorithm by 256 times and right-shifts the data plane by 8 bits after the dehazing algorithm.

[0016] In one embodiment, the system further includes an HDMI driver IP core, which is used to convert the second data stream in RGB888 format into a third data stream in TMDS format and send it to the display for display.

[0017] In one embodiment, the system also includes an image acquisition IP core, which converts the light signal into an analog signal through the built-in photosensitive array of the image acquisition IP core, optimizes and amplifies the analog signal using an adaptive gain control mechanism, and then converts it into a digital signal through an analog-to-digital converter, and dynamically calibrates the digital signal through an integrated image signal processor to obtain a video or image sequence.

[0018] In a second aspect, the present application provides a programmable system on chip, on which a computer program is stored, and when the computer program is executed by a processor, the corresponding functions of the above-mentioned system are realized.

[0019] In a third aspect, the present application provides a ZYNQ product having a computer program stored thereon, the ZYNQ product including a processor and programmable logic, the ZYNQ product having an external memory, a display and a camera for capturing video or image sequences, and the computer program realizes the corresponding functions of the above-mentioned system when executed by the processor and the programmable logic.

[0020] The above-mentioned system combining real-time image defogging and moving target detection adopts a modular design to integrate the image defogging and moving target detection functions into a complete system to achieve accurate detection of moving objects in the fog; at the same time, the development of the entire system relies on the ZYNQ embedded platform, making full use of its FPGA hardware resources to accelerate algorithm processing, effectively improving the real-time performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A block diagram of the system structure combining real-time image defogging and moving target detection in one embodiment. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] The present application embodiment provides a system combining real-time image defogging and moving target detection, based on the ZYNQ platform, such as Figure 1 As shown, including:

[0024] An image defogging IP core is used to defog the received video or image sequence using a defogging algorithm to obtain a first data stream;

[0025] A first VDMAIP core is used to receive a first data stream and send it to a memory for storage;

[0026] A moving target detection IP core is used to receive the first data stream output by the image defogging IP core and the first data stream read and output by the first VDMA IP core from the memory, perform moving target detection using a frame difference method, and obtain a second data stream;

[0027] The second VDMAIP core is used to receive the second data stream and send it to the display for display.

[0028] In this embodiment, the image defogging IP core, namely Figure 1 The image defogging module is based on the atmospheric scattering physical model. The defogging algorithm written in Verilog language is encapsulated into an IP core and deployed in the ZYNQ core board. The defogging algorithms include dark channel prior method, adaptive multi-scale enhancement method (ACE), etc.

[0029] Moving target detection IP core, that is Figure 1 The frame difference method moving target detection module in the is to write the frame difference method algorithm in Verilog language, encapsulate it as an IP core, and deploy it in the ZYNQ core board.

[0030] VDMA (Video Direct Memory Access) is a high-performance DMA (Direct Memory Access) technology optimized for video data transmission. It is usually used in FPGA (Field-Programmable Gate Array) or SoC (System on Chip) systems to process high-bandwidth, low-latency video stream data. VDMA supports a multi-frame cache mechanism, usually 2-4 cache areas (such as double buffering, triple buffering). Multi-frame cache allows simultaneous read and write operations to improve data transmission efficiency. VDMA uses a pixel clock to control the line-by-line transmission of video data. The frequency of the pixel clock is determined according to the video resolution and frame rate (such as the pixel clock of 1080p60Hz is approximately 148.5MHz). VDMA can also achieve frame synchronization by marking the beginning and end of a frame of data to ensure that the video data is properly aligned on the display or other devices.

[0031] Integrate the image defogging IP core and the motion target detection IP core into the Block Design, and then deploy the first VDMA IP core (i.e. Figure 1 VDMA1 in the VDMA and the second VDMAIP core (i.e. Figure 1 The main function of the VDMA IP core is to transfer data between the memory and the image defogging IP core or between the memory and the motion target detection IP core. The first VDMA IP core is used to transmit the first data stream processed by the image defogging IP core, and the second VDMA IP core is used to transmit the second data stream processed by the motion target detection IP core.

[0032] The specific workflow of this embodiment is as follows: After receiving the video or image sequence, the image defogging IP core uses the defogging algorithm to perform image enhancement processing to obtain the first data stream in the image frame format. The image defogging IP core sends the first data stream to the first VDMA IP core and the moving target detection IP core in a broadcast form. After receiving the first data stream, the first VDMA IP core caches it in the memory, and then extracts the first data stream from the memory and outputs it to the moving target detection IP core in response to the instruction of the moving target detection IP core. Because it takes at least one clock cycle to read data from the memory, there is a time difference between the first data stream from the image defogging IP core received by the moving target detection IP core and the first data stream from the first VDMA IP core, so that the first data stream output from the first VDMA IP core is at least one frame slower than the first data stream directly output by the image defogging IP core, thereby achieving a frame difference effect, and then using the frame difference method to detect moving targets and obtain the second data stream. The second data stream is input into the memory for storage through the second VDMA IP core, and the result of the image after defogging and motion detection processing is displayed on the display.

[0033] In this embodiment, the defogging algorithm and target detection algorithm are reconstructed and encapsulated as IP cores using Verilog language to achieve modular integration and ensure efficient collaboration between the algorithm and the system architecture. Compared with traditional technologies, the innovative integration of these two algorithms in hardware overcomes the limitation that the existing technology can only perform defogging or target detection separately. In addition, since it is implemented on the ZYNQ platform, it has the advantages of small size and low power consumption, and is easier to use and promote with a display.

[0034] In other embodiments of the present invention, the video or image sequence is acquired through the OV5640 camera. The system disclosed in the present invention is connected to an external OV5640 camera to collect image data, and converts the optical signal into an analog signal through its built-in photosensitive array. To ensure the quality and reliability of the signal, an adaptive gain control mechanism is used to optimize and amplify the analog signal, and the analog signal is input into a high-precision 10-bit analog-to-digital converter (ADC) to achieve lossless conversion of the analog signal to the digital signal. Subsequently, an integrated image signal processor (ISP) is used to perform intelligent dynamic calibration and processing on the video stream data to ensure the output of high-quality 10-bit video stream data that meets the configuration requirements. The image acquisition module that performs the above process is encapsulated as an IP core for easy integration into the ZYNQ platform.

[0035] In other embodiments, the AXI protocol is used for data transmission between the image defogging IP core and the first VDMA IP core, between the first VDMA IP core and the memory, between the memory and the second VDMA IP core, and between the second VDMA IP core and the display. AXI (Advanced eXtensible Interface) is a bus protocol used in high-performance, high-bandwidth systems and is widely used in modern system-on-chip (SoC) designs. AXI is a high-performance bus interface standard designed to solve the multiplexing, low latency and high bandwidth problems of data transmission in complex systems. The characteristics of the AXI protocol include high performance, low latency, high bandwidth, flexibility and scalability, and are used for data transmission between components such as processors, storage controllers, DMA (direct memory access), and peripheral interfaces. Specifically, the AXI-stream protocol is used to process data streams between the image dehazing IP core and the first VDMA IP core, and between the second VDMA IP core and the display; AXI-SmartConnect is used between the first VDMA IP core and the memory, and between the memory and the second VDMA IP core to implement multi-master and single-slave memory read and write functions; in addition, AXI-stream transmission is replicated multiple times through AXIS-broadcast to implement broadcast transmission of the image dehazing IP core to the motion target detection IP core and the first VDMA IP core.

[0036] In addition, the first VDMAIP core and the second VDMAIP core are connected to the memory through the AXI HP interface. The HP interface refers to an interface for high-bandwidth data transmission, and generally refers to an interface used in high-performance computing (HPC), data centers, servers, storage systems, and consumer electronics products (such as monitors, graphics cards, etc.). The HP interface is characterized by supporting high bandwidth, low latency, and efficient data transmission, which can meet the needs of modern computing and storage systems for high-performance connections.

[0037] The memory uses DDR (Double Data Rate SDRAM, double data rate synchronous dynamic random access memory). The working mode of ordinary SDRAM memory is to trigger it on the rising edge of a clock cycle. That is to say, the memory will work once in a clock cycle. However, the DDR technology allows the memory to be triggered once on the rising edge and falling edge of each clock cycle, so that the memory can work twice in one clock cycle, so that the DDR memory can complete twice the workload of ordinary memory in the same time.

[0038] In one embodiment, the first VDMA IP core and the second VDMA IP core adopt a dynamic synchronous phase lock mode. In many video applications, the data rates of the image input end and the output end are generally mismatched, and a frame buffer is usually used to avoid problems caused by rate mismatch. In order to solve the image superposition problem caused by a single frame buffer (referring to the input of the image and the display of the image are both read and written through the same storage area), multiple frame buffer areas are allocated to save data. When the image input end writes to one of the frame buffers, the output end reads other frame buffers. At this time, the synchronous phase lock technology is needed. Dynamic synchronous phase lock includes dynamic synchronous phase lock master mode (Dynamic Genlock Master) and dynamic synchronous phase lock slave mode (Dynamic Genlock Slave). When the write channel or the read channel is configured as the dynamic synchronous phase lock master mode, the channel will skip the frame buffer that the Dynamic Genlock Slave channel is operating, and it is completed by skipping or repeating some frame buffer areas. When the write channel or the read channel is configured as the dynamic synchronous phase lock slave mode, the channel will operate the frame operated by the Dynamic Genlock Master channel in the previous cycle. Dynamic synchronous phase-lock mode is used to prevent the read and write channels from operating the frame buffer at the same time, maintaining data synchronization and ensuring high quality and stability of data streaming applications.

[0039] In one embodiment, the number of frame buffers of the first VDMAIP core and the second VDMAIP core is innovatively set to no less than 3 to ensure the robustness and continuity of the system under high-frequency data transmission. The storage and call efficiency of image data in the DD3 memory is optimized, and high bandwidth guarantee and dynamic throughput capacity are provided for the real-time processing of the overall system, so as to realize stable and reliable image stream processing in complex environments.

[0040] In one embodiment, the image defogging IP core uses a 3*3 filter to filter the video or image sequence.

[0041] In the dark channel prior defogging algorithm, the application of guided filtering is involved. Guided filtering is an algorithm for image filtering, which uses the content of the guide image to filter the target image while maintaining the edges and details of the target image. The core idea of ​​guided filtering is to assume that the guide image and the target image have similar structures in the local area, so the target image can be filtered with the help of the characteristics of the guide image. The present invention uses a 3*3 filter to filter the video or image sequence, which greatly reduces the computational complexity and resource overhead while ensuring the defogging effect.

[0042] In one embodiment, the image defogging IP core amplifies the defogging algorithm by 256 times and right-shifts the data by 8 bits after the defogging algorithm is completed.

[0043] The original dehazing algorithm has decimals, and the calculation of floating-point numbers in hardware is more troublesome, so the overall data of the algorithm is enlarged 256 times, that is, multiplied by 256, and the data is shifted right by 8 bits in the image recovery stage after the dark channel dehazing algorithm is completed. By enlarging the algorithm 256 times and then shifting it right by 8 bits at the data level, a balance between accuracy and calculation speed is achieved, so that the dehazing algorithm can still maintain efficient and stable performance in complex environments.

[0044] In one embodiment, the system further includes an HDMI driver IP core, which is used to convert the second data stream in RGB888 format into a third data stream in TMDS format and send it to the display for display.

[0045] RGB888 is a format that represents the color information of each pixel in an image. It represents each color (red, green, blue) using 8 bits. TMDS (Transition Minimized Differential Signaling) is used to transmit audio and video data between digital video sources and display devices. The design goal of TMDS is to ensure data integrity in long-distance transmission by reducing electromagnetic interference and signal attenuation of the signal.

[0046] In this embodiment, the second data stream output by the second VDMA IP core is connected to a DVI (Digital Visual Interface) through a conversion port, and the data stream sent using the DVI standard can be directly connected to a display screen of an HDMI interface for display.

[0047] The system needs to input two clock signals, one of which is the pixel clock of the video, which is used to transmit to the encoder and serializer modules of the HDMI driver IP core; the encoder module is responsible for encoding the video data, and the serializer module converts the encoded data into parallel and serial. The other clock is 5 times the frequency of the pixel clock, which is used to ensure the synchronization and stability of data transmission.

[0048] The working principle of the present invention is as follows: the OV5640 camera is used to collect images in a foggy environment in real time and store them in DDR, and the collected images are processed by a dark channel prior defogging algorithm to significantly enhance the contrast of the image and restore the details obscured by the fog. Subsequently, the defogging image data is used to detect and identify moving targets using the frame difference method, and the system can accurately select and calibrate the detected moving objects. The processed image data is transmitted to the display through the HDMI interface to achieve high-quality real-time image display and visual presentation of moving targets.

[0049] In summary, the present invention encapsulates the optimized dark channel defogging algorithm into an IP core, which can efficiently remove haze in the image, reduce system latency, significantly enhance the contrast and clarity of the image, and restore detail information obscured by fog. The moving target detection part uses the frame difference method to be encapsulated into an IP core. By performing differential operations on continuous frame images, the moving target in the image is quickly identified, and it is accurately positioned and calibrated. Then, through module optimization and parallel processing design, the robustness and response speed of the detection algorithm are improved to ensure real-time processing effects. Through the system integration design of multi-module collaboration and data transmission optimization, the data flow path is optimized, the dark channel prior algorithm is effectively combined with the frame difference method, and the data processing speed and response rate are improved by using parallel processing technology. The custom HDMI interface IP core outputs the processed image data stream to the display, realizing efficient encoding and parallel-to-serial conversion of RGB888 format video and smooth transmission of high-resolution video. The present invention can detect and identify moving objects in the fog that cannot be identified by the naked eye in real time in low visibility environments such as foggy days, thereby improving the system's target detection capability in complex environments and improving overall processing efficiency. At the same time, it also improves the system's portability and deployment flexibility, solving the problem of being unsuitable for real-time scenarios.

[0050] The innovation of the present invention is that it is the first time to propose an innovative method for combining a dark channel defogging algorithm with a moving target detection algorithm on a ZYNQ development board. Through the collaborative calculation of an ARM processor and an FPGA, the deep optimization of the algorithm and the efficient integration of hardware resources are designed. Compared with traditional technologies, this system integrates these two algorithms in hardware, overcoming the limitation that the existing technology can only perform defogging or target detection separately. At the same time, the dark channel defogging algorithm is optimized to improve the calculation accuracy and speed and reduce the complexity of the algorithm. In addition, modular design and multi-channel data flow management are adopted, and two VDMAIP cores are used to store the data after the defogging image is shunted and the data after the moving target is detected, respectively, to ensure that the data transmission is stable and efficient during the real-time processing process, and to avoid the delay problem caused by the serial processing on the traditional PC side. Therefore, through the independently developed IP core and heterogeneous acceleration design, the complex algorithm is parallelized, and the response capability of millisecond delay is achieved, which effectively solves the performance bottleneck caused by the single operation of the traditional algorithm and improves the real-time performance and processing efficiency. Its lightweight design not only meets the needs of portable scenarios, but can also adapt to complex application environments such as drones and intelligent transportation, and achieve accurate detection and calibration of moving targets under low visibility conditions.

[0051] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0052] Each module in the above-mentioned system combining real-time image defogging and moving target detection can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0053] Based on the same inventive concept, the embodiments of the present application also provide a programmable system-on-chip and a ZYNQ product for implementing the above-mentioned system combining real-time image defogging and moving target detection. The implementation solutions provided by the programmable system-on-chip and the ZYNQ product are similar to the implementation solutions recorded in the above-mentioned system, so the specific limitations in the one or more programmable system-on-chip and ZYNQ product embodiments provided below can refer to the above-mentioned limitations on the system combining real-time image defogging and moving target detection, and will not be repeated here.

[0054] In one embodiment, the present invention provides a programmable system on chip, on which a computer program is stored, and when the computer program is executed by a processor, the corresponding functions of the system combining the above-mentioned real-time image defogging and moving target detection are realized.

[0055] In one embodiment, the present invention provides a ZYNQ product having a computer program stored thereon, the ZYNQ product including a processor (PS, Processing System) and programmable logic (PL, Programmable Logic), the ZYNQ product having an external memory, a display and a camera for capturing video or image sequences.

[0056] Among them, PL includes:

[0057] An image defogging IP core is used to defog the received video or image sequence using a defogging algorithm to obtain a first data stream;

[0058] A first VDMAIP core is used to receive a first data stream and send it to a memory for storage;

[0059] A moving target detection IP core is used to receive the first data stream output by the image defogging IP core and the first data stream read and output by the first VDMA IP core from the memory, perform moving target detection using a frame difference method, and obtain a second data stream;

[0060] The second VDMAIP core is used to receive the second data stream and send it to the display for display.

[0061] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0062] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processors involved in each embodiment provided in this application may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, data processing logic devices based on quantum computing, etc., but are not limited thereto.

[0063] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A system combining real-time image defogging and moving target detection, characterized in that: Based on the ZYNQ platform, the system includes: An image defogging IP core is used to defog the received video or image sequence using a defogging algorithm to obtain a first data stream; A first VDMAIP core, configured to receive the first data stream and send it to a memory for storage; A moving target detection IP core, configured to receive the first data stream output by the image defogging IP core and the first data stream read and output by the first VDMA IP core from the memory, perform moving target detection using a frame difference method, and obtain a second data stream; The second VDMAIP core is used to receive the second data stream and send it to the display for display.

2. The system according to claim 1, characterized in that: The first data stream received by the moving target detection IP core from the first VDMA IP core is delayed by a preset number of frames compared with the first data stream received from the image defogging IP core.

3. The system according to claim 1, characterized in that The first VDMAIP core and the second VDMAIP core adopt a dynamic synchronous phase-locking mode.

4. The system according to claim 1, characterized in that: The image defogging IP core uses a 3*3 filter to filter the video or image sequence.

5. The system according to claim 1, characterized in that: The image defogging IP core amplifies the defogging algorithm by 256 times and right-shifts the data by 8 bits after the defogging algorithm.

6. The system according to claim 1, characterized in that: The system also includes an HDMI driver IP core, which is used to convert the second data stream in RGB888 format into a third data stream in TMDS format and send it to the display for display.

7. The system according to claim 1, characterized in that: The system also includes an image acquisition IP core, which converts light signals into analog signals through a built-in photosensitive array in the image acquisition IP core, optimizes and amplifies the analog signals using an adaptive gain control mechanism, and then converts them into digital signals through an analog-to-digital converter. The digital signals are dynamically calibrated by an integrated image signal processor to obtain the video or image sequence.

8. A programmable system on chip having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the system corresponding functions of any one of claims 1 to 7 are realized.

9. A ZYNQ product having a computer program stored thereon, the ZYNQ product comprising a processor and programmable logic, characterized in that: The ZYNQ product has an external memory, a display, and a camera for capturing video or image sequences. When the computer program is executed by the processor and the programmable logic, the corresponding functions of the system described in any one of claims 1 to 7 are realized.

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